Multilayer wiring board and method for manufacturing a multilayer wiring board

Abstract

To provide a low-cost, highly productive multilayer wiring board with flat surface vias. [Solution] The multilayer wiring board includes a conformal-shaped via plug VP provided on the uppermost layer of the rewiring layer 100, with a conductive layer 106 provided along the via hole V; an insulating film 102 following the upper surface of the rewiring layer 100; an opening OP provided in the insulating film 102 that exposes the upper surface of the conformal-shaped via plug VP; and a conductive plug CP inside the opening OP that fills the recess of the conformal-shaped via plug VP. The via hole V can be superimposed on the opening OP.

Description

【Technical Field】 【0001】 One embodiment of the present invention relates to a multilayer wiring board and a method for manufacturing the same. 【Background Art】 【0002】 When electrically connecting a semiconductor chip manufactured by a wafer process and a printed wiring board, a wiring board (also called an "interposer") for pitch conversion is used. In the wiring board, a via plug is formed by filling a through hole called a via hole formed in an insulating layer with a conductive member such as metal. Although a plating method is used for manufacturing the via plug, when the diameter of the via hole increases, the shape of the via plug becomes a conformal shape recessed in the inner part of the via hole, which causes a problem that it becomes difficult to connect the via plug to a conductive member such as solder used for connecting the wiring board, the semiconductor chip. In order to solve such problems, it has been proposed to dispose a plating accelerator substance in the recess or provide unevenness on the bottom surface (see, for example, Patent Documents 1 and 2). 【Prior Art Documents】 【Patent Documents】 【0003】 【Patent Document 1】 Japanese Patent Application Laid-Open No. 2005-333153 【Patent Document 2】 Japanese Patent Application Laid-Open No. 2005-294364 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 In the conventional method for flattening the upper surface of the via, it is necessary to introduce a new member or add a process, which causes problems such as an increase in manufacturing cost and a decrease in productivity. 【Means for Solving the Problems】 【0005】 A multilayer wiring board according to one embodiment of the present invention includes a via plug having a conformal shape and a conductive layer provided along the via hole, provided on the uppermost layer of the redistribution layer; an insulating film following the upper surface of the redistribution layer; an opening provided in the insulating film that exposes the upper surface of the conformal-shaped via plug; and a conductive plug inside the opening that fills the recess of the conformal-shaped via plug. 【0006】 A method for manufacturing a multilayer wiring board according to one embodiment of the present invention involves forming conformally shaped via plugs along via holes on the uppermost layer of a redistribution layer, scattering conductive beads on the upper surface of the redistribution layer, leaving the conductive beads in the recesses of the conformally shaped via plugs, providing an insulating film on the upper surface of the redistribution layer, irradiating the region where the conformally shaped via plugs are provided with laser light from the upper surface of the insulating film to form an opening that exposes the upper surface of the conformally shaped via plugs, melting the conductive beads remaining in the recesses of the conformally shaped via plugs, and forming conductive plugs in the recesses of the conformally shaped via plugs. [Brief explanation of the drawing] 【0007】 [Figure 1] This is a schematic plan view showing the structure of a multilayer wiring board according to one embodiment of the present invention. [Figure 2] This is a schematic end view showing the structure of a multilayer wiring board according to one embodiment of the present invention. [Figure 3] This is a flowchart illustrating the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. [Figure 4] This is a schematic end view showing the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. [Figure 5] This is a schematic end view showing the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. [Figure 6] This is a schematic end view showing the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. [Figure 7]This is a schematic end view showing the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. [Figure 8] This is a schematic end view showing the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. [Modes for carrying out the invention] 【0008】 Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described below. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals (or numerals followed by A, B, etc.), and detailed explanations may be omitted as appropriate. Furthermore, the letters "1st," "2nd," etc., attached to each element are convenient indicators used to distinguish each element and have no further meaning unless specifically explained. 【0009】 In this specification, when a member or region is said to be "above (or below)" another member or region, unless otherwise specified, this includes not only cases where it is directly above (or directly below) the other member or region, but also cases where it is above (or below) the other member or region, that is, cases where another component is included between them above (or below) the other member or region. 【0010】 In the embodiments described below, "via" refers to a connection region that electrically connects an upper wiring layer and a lower wiring layer in a multilayer wiring board, and "via hole" refers to a hole or hole (through hole) for forming a via. "Via plug" refers to a conductive portion in which a conductive material is provided in a through hole that penetrates the insulating layer. 【0011】 <First Embodiment> Figures 1 and 2 show an example of a multilayer wiring board 10 according to one embodiment of the present invention. Figure 1 is a schematic plan view showing the structure of a multilayer wiring board according to one embodiment of the present invention, and Figure 2 is a schematic end view showing the structure of a multilayer wiring board according to one embodiment of the present invention. Figures 1 and 2 show the configuration of vias, which are part of the multilayer wiring board 10, and the configuration of other parts is omitted. Figure 1 is a plan view of via VA shown in Figure 2. 【0012】 The multilayer wiring board 10 includes an insulating film 102, an opening OP provided in the insulating film 102, an insulating layer 104, a via hole V provided in the insulating layer 104, a via plug VP covering the via hole V, and a conductive plug CP inside the opening OP. 【0013】 The insulating layer 104 may include multiple insulating layers 104. Multiple insulating layers 104 are stacked. As shown in Figure 2, the insulating layer 104 can be constructed by stacking insulating layer 104-1, insulating layer 104-2, and insulating layer 104-3. Each insulating layer 104 is provided with a via VA. Each via VA of each insulating layer 104 may have a via hole V penetrating the insulating layer 104 and a via plug VP provided in the via hole V. The via plug VP of each insulating layer 104 can be electrically or directly connected. Multiple insulating layers 104 with vias VA can be stacked to form a rewiring layer 100. 【0014】 As shown in Figure 2, the redistribution layer 100 can consist of a first layer 100-1 composed of an insulating layer 104-1 and vias VA, a second layer 100-2 laminated on the first layer 100-1 and composed of an insulating layer 104-2 and vias VA, and an uppermost layer 100-3 laminated on the second layer 100-2 and composed of an insulating layer 104-3 and vias VA. 【0015】 Next, the vias VA of each layer constituting the redistribution layer 100 will be described. Focusing on the via VA of the uppermost layer 100-3, a conformal via plug VP3 is provided, with a conductive layer 110-3 along the via hole V. The conductive layer 110-3 has a recess that extends from the upper surface of the insulating layer 104-3 toward the insulating layer 104-2. The via plug VP3 also has a recess similar to the conductive layer 110-3. The upper surface 1101 of the via plug VP3 or conductive layer 110-3 is located on the upper surface 10431 of the insulating layer 104-3 and the via hole V3, and the upper surface 1101 of the via plug VP3 or conductive layer 110-3 located in the via hole V3 becomes a recess as shown in Figure 2. Conductive plug CP is filled into the recess of the via plug VP3 or conductive layer 110-3. The via plug VP3 filled with conductive plug CP can function as a wiring layer. A wiring layer is a conductive layer that electrically connects to or directly contacts other insulating layers, such as wiring layers or via plugs. Depending on the arbitrary three-dimensional layout of the wiring layers and via plugs, the rewiring layer can form a variety of circuits. 【0016】 The conductive plug CP can be directly connected to the via plug VP3 or the conductive layer 110-3. The conductive plug CP only needs to be in contact with at least a portion of the via plug VP3 or the conductive layer 110-3. The conductive plug CP may also be electrically connected to the via plug VP3 or the conductive layer 110-3. 【0017】 The conductive plug CP is preferably flush with the via plug VP3 or the conductive layer 110-3. As shown in FIG. 2, the conductive plug CP is preferably flush with the via plug VP3 or the conductive layer 110-3 on the insulating layer 104-3. It is preferable that the upper surface CP01 of the conductive plug CP is flush with the upper surface 1101 of the via plug VP3 or the conductive layer 110-3 located on the insulating layer 104-3. Since the conductive plug CP is a conductor for favorably connecting the via plug VP3 and a semiconductor chip 200 or the like mounted on the multilayer wiring board 10, the upper surface CP01 of the conductive plug CP may have a height sufficient to electrically connect the via plug VP3 and a semiconductor chip 200 or the like mounted on the multilayer wiring board 10, and may be lower than the upper surface 1101 of the via plug VP3 or the conductive layer 110-3. That the upper surface CP01 of the conductive plug CP is lower than the upper surface 1101 of the via plug VP3 or the conductive layer 110-3 indicates a case where the distance from the first layer 100-1 of the rewiring layer 100 to the upper surface CP01 of the conductive plug CP is shorter than the distance from the first layer 100-1 of the rewiring layer 100 to the upper surface 1101 of the via plug VP3 or the conductive layer 110-3. 【0018】 The vias VA in the first layer 100-1 and the second layer 100-2 can also have the same configuration as the via VA in the uppermost layer 100-3, and a via plug VP having a conformal shape may be formed. FIG. 2 shows an example in which the vias VA in the first layer 100-1 and the second layer 100-2 have a configuration different from that of the via VA in the uppermost layer 100-3. The vias VA in the first layer 100-1 and the second layer 100-2 form a via plug VP3 having a via fill shape. 【0019】 In the first layer 100-1, a via plug VP-1 is formed in a via hole V1 provided in the insulating layer 104-1. The via plug VP1 is formed by filling the via hole V1 with a conductive material. The filled conductive material can function as a wiring layer. When the first layer 100-1 is the bottom layer in the rewiring layer 100, the first layer 100-1 may have a conductive layer 106 as shown in FIG. 2. The conductive layer 106 can also be used as a pedestal for the via plug VP1, and the via plug VP1 can be provided on the conductive layer 106. The conductive layer 106 may be an electrode pad connected to a semiconductor chip or a printed wiring board, or may be a wiring layer provided in the multilayer wiring board 10. The conductive layer 106 is provided so as to be exposed from the insulating layer 104-1 on the lower surface 10412 of the rewiring layer 100. For example, as shown in FIG. 2, the conductive layer 106 is provided so as to be exposed from the insulating layer 104-1 on the lower surface 10412 opposite to the upper surface 10431 where the connection plug layer 150 is provided. By being exposed from the insulating layer 104-1, the conductive layer 106 can form a good connection state when making electrical connections with the front and back circuits. 【0020】 In the second layer 100-2, a via plug VP2 is formed in a via hole V2 provided in the insulating layer 104-2. The via plug VP2 is formed by filling the via hole V2 with a conductive material. The filled conductive material can function as a wiring layer. 【0021】 In FIG. 2, an example in which the rewiring layer 100 is composed of the first layer to the top layer is shown, but the number of layers constituting the rewiring layer 100 is not limited to this, and may include at least one layer which is the top layer. Alternatively, the rewiring layer 100 may be composed of three or more layers. Further, in FIG. 2, the rewiring layer 100 is shown in the form of a stacked via or a full-stack via in which a via VA or a via plug VP is superimposed from the first layer 100-1 to the top layer 100-3, but the rewiring layer 100 may be in the form of a staggered via or a combination of these and buried via holes. 【0022】 A connection plug layer 150 is provided on top of the rewiring layer 100. The connection plug layer 150 includes an insulating film 102 and an opening OP that penetrates the insulating film 102. 【0023】 The insulating film 102 is laminated on the rewiring layer 100. The insulating film 102 covers the upper surface 10431 of the rewiring layer 100. The upper surface 10431 of the rewiring layer 100 is synonymous with the upper surface of the top layer 100-3. The insulating film 102 can also cover the upper surface 1101 of the via plug VP3 and the upper surface CP01 of the conductive plug CP, which are provided on the top layer 100-3. 【0024】 The opening OP exposes the upper surface 1101 of the via plug VP3 of the uppermost layer 100-3. Specifically, the opening OP is provided to expose the upper surface 1101 of the via plug VP3 located in the via hole V3. The opening OP can expose the upper surface CP01 of the conductive plug CP. The opening OP can be superimposed on the via hole V3 of the uppermost layer 100-3. The opening OP can be superimposed on the via plug VP3 of the uppermost layer 100-3. As shown in Figure 1, the opening OP can be smaller than the outer frame of the via plug VP3 and larger than the outer frame of the conductive plug CP. 【0025】 The opening OP can expose the upper surface CP01 of the conductive plug CP. The opening OP can be superimposed on the conductive plug CP. By exposing the conductive plug CP from the insulating film 102, the opening OP enables contact between the conductive plug CP and a connecting member used when mounting a packaged circuit board such as a semiconductor chip 200 on the upper surface 1021 of the multilayer wiring board 10. 【0026】 The multilayer wiring board 10 is a substrate for forming electrical connections between circuits on its front and back sides, and can be used in semiconductor devices. For example, the multilayer wiring board 10 can be used to connect a semiconductor chip to a package substrate or printed wiring board. Connection electrodes such as bumps can be used to connect the multilayer wiring board 10 to the semiconductor chip, package substrate, or printed wiring board. 【0027】 When a semiconductor chip 200 is mounted on the upper surface 1021 of the multilayer wiring board 10, a bump E1 is provided in the opening OP to connect the multilayer wiring board 10 and the semiconductor chip 200. As shown in Figure 2, the bump E1 is positioned in the opening OP in contact with the conductive plug CP and the semiconductor chip 200. When a printed circuit board 250 is mounted on the lower surface 10412 of the multilayer wiring board 10, as shown in Figure 2, a bump E2 is positioned between the multilayer wiring board 10 and the printed circuit board 250 to electrically connect the multilayer wiring board 10 and the printed circuit board 250. The bump E2 is provided in contact with the conductive layer 106 exposed from the insulating layer 104-1. In Figure 2, an example is shown in which the conductive layer 106 is provided on the first layer 100-1, but the conductive layer 106 may not be provided on the first layer 100-1, and the bump E2 may be positioned in contact with the via plug VP1 exposed from the insulating layer 104-1. 【0028】 As described above, according to this embodiment, in the uppermost layer 100-3 of the redistribution layer 100, a conductive plug CP is formed in the recess of the conformally shaped via plug VP3, thereby forming a via with a flat surface. The multilayer wiring board 10 has a flat surface via, which improves the connection state with circuit boards such as semiconductor chips 200. 【0029】 <Second Embodiment> Figures 3 to 8 show an example of a method for manufacturing a multilayer wiring board 10 according to one embodiment of the present invention. Descriptions of configurations identical or similar to those in the first embodiment may be omitted. 【0030】 Figure 3 is a flowchart illustrating the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. Figures 4 to 8 are schematic end views showing the manufacturing process of a multilayer wiring board according to one embodiment of the present invention. 【0031】 Figure 4 shows the steps of forming via holes V3 in the insulating layer 104-3 provided on top of the redistribution layer 100, and further forming via plugs VP3 in the via holes V3. Any known method can be used to form the via plugs VP3; for example, electroplating can be used. The via plugs VP3 are formed by growing the conductive layer 110-3 along the shape of the via holes V3. The via plugs VP3 have a conformal shape with a recess in the inner portion of the via hole V3. 【0032】 When using electroplating to form the via plug VP3, a seed layer may be pre-formed along the surface 10431 of the insulating layer 104-3 and the shape of the via hole V3. The seed layer can be formed using the same material as the conductive layer 110-3 which will become the via plug VP3. For example, when the conductive layer 110-3 is formed of copper (Cu), it is preferable to form the seed layer as a thin film of copper. The seed layer has a film thickness of about 10 nm to 100 nm and can be formed by sputtering. In addition to copper, metals such as nickel (Ni), chromium (Cr), and gold (Au) can be used for the conductive layer 110-3 and the seed layer. Although not shown in the figures, a barrier metal layer of titanium nitride (TiN), tungsten-molybdenum alloy (W·Mo), etc. may be formed before forming the seed layer. 【0033】 There are no limitations on the structure of the redistribution layer 100. For example, the redistribution layer 100 has a structure similar to that shown in Figure 2. The redistribution layer 100 has a structure in which insulating layers 104-1, 104-2, and 104-3 are laminated, with a via plug VP1 provided in a via hole V1 in insulating layer 104-1, and a via plug VP2 provided in a via hole V2 in insulating layer 104-2. The insulating layers 104-1, 104-2, and 104-3 can be formed from resin material, and the via holes V1 and V2 can be formed by etching the insulating layers 104-1 and 104-2. When photosensitive resin material is used for insulating layers 104-1 and 104-2, the via holes V1 and V2 can be formed by exposure using a photomask and development. There are no limitations on the thickness of the insulating layers 104-1 and 104-2, but it is preferable to form them to a thickness of 3 μm to 10 μm, for example, 5 μm. 【0034】 The resin material used in the insulating layer 104 can be a composition containing precursors and photosensitive groups, such as phenolic resin materials, polyimide resin materials, and epoxy resin materials. By applying such a photosensitive resin composition and exposing it to light, insulating layers 104-1 and 104-2 can be formed. 【0035】 There are no limitations on the diameter of the via holes V1 and V2, but for example, via holes V1 with a diameter of about 10 to 200 μm can be formed. Via hole V1 is a hole that penetrates the insulating layer 104-1 and may be provided so that the conductive layer 106 is exposed. Via hole V2 is a hole that penetrates the insulating layer 104-2 and may be provided so that the via plug VP1 is exposed. 【0036】 The substrate 101 is a support substrate that supports the multilayer wiring board 10 during manufacturing and is separated after the multilayer wiring board 10 is manufactured. For example, a glass substrate is used for the substrate 101. There are various materials for the glass substrate, but it is preferable to use an alkali-free glass substrate. Alkali-free glass substrates can also be used as large-area glass substrates (mother glass substrates) used in the manufacture of liquid crystal displays. By using such a large-area glass substrate, it is possible to manufacture multiple multilayer wiring boards 10 on a single glass substrate, thereby increasing productivity. Note that the support substrate is not limited to a glass substrate, and semiconductor substrates such as silicon wafers, ceramic substrates, quartz substrates, etc. may also be used. 【0037】 Next, in step S11 of Figure 3, conductive beads CB are scattered onto the upper surface 10431 of the redistribution layer 100. As shown in Figure 5, the conductive beads CB are scattered onto the upper surface 10431 of the redistribution layer 100 and left to remain in the recesses of the via plugs VP3. Conductive beads CB that do not remain in the recesses of the via plugs VP3 and remain on the upper surface 10431 of the redistribution layer 100 are sifted off from the redistribution layer 100 by shaking the substrate 101, etc., and are removed from the upper surface 10431 of the redistribution layer 100. Figure 5 shows an example in which one conductive bead CB remains in one via hole V3, but multiple conductive beads CB may remain in one via hole V3. For example, if the pore diameter of the via hole V3 is 200 μm, multiple conductive beads CB can be placed in one via hole V3 if the pore diameter of the conductive beads CB is about 50 μm. It is preferable that the conductive beads CB are formed from a conductive material with a lower melting point than the metal material forming the via plugs VP2. It is preferable that the conductive beads CB be made of a different material than the via plug VP. For example, when a CO2 laser is used for the laser beam, the conductive beads CB can be made of iron or steel. Alternatively, the conductive beads CB may be made of solder material, for example. As the solder material, tin (Sn)-lead (Pb) solder, tin (Sn)-silver (Ag)-copper (Cu) solder, etc. can be used. The materials that can be used for the conductive beads CB are not limited to these, but it is preferable that they be made of a conductive material that can be melted by irradiation with laser light used in step S13 described later. 【0038】 Furthermore, in step S12 of Figure 3, the insulating film 102 is provided on the upper surface 10431 of the redistribution layer 100. The insulating film 102 may be formed of the same resin material as the insulating layer 104, or it may be formed of a different type of resin material. For example, insulating layers 104-1, 104-2, and 104-3 may be formed of the same type of resin material, and the insulating film 102 may be formed of a different resin material. As an example, insulating layers 104-1, 104-2, and 104-3 may be formed of a photosensitive resin material, and the insulating film 102 may be formed of a non-photosensitive (thermosetting) resin material. 【0039】 In addition to the materials described above, the insulating film 102 can be made from a coating-type thermosetting epoxy resin composition containing epoxy resin, an active ester compound containing a naphthalene structure, and an inorganic filler. Alternatively, the insulating film 102 may be formed by using a film-like or sheet-like intermediate material (a prepreg without glass fibers) made from a thermosetting epoxy resin material, attaching it to the redistribution layer 100, and then thermosetting it. By using the above-mentioned thermosetting resin material, the insulating film 102 can be made significantly thicker than the insulating layer 104. The increased thickness of the insulating film 102 allows for a more robust structure for the vias VA, improving the rigidity and flatness of the multilayer wiring board 10. 【0040】 Finally, in step S13 of Figure 3, laser light is irradiated from the upper surface 1021 of the insulating film 102 to the region VPA where the via plug VP3 is provided. Laser light is irradiated from the upper surface 1021 of the insulating film 102 to the region VPA where the via plug VP3 is provided, as shown in Figure 6. By irradiating the region VPA where the via plug VP3 is provided with laser light, an opening OP is formed that exposes the upper surface 1101 of the via plug VP3. In step S13, the melting of the conductive beads CB by laser light irradiation and the formation of the opening OP can be performed simultaneously. Alternatively, after the opening OP is formed by laser light irradiation, the conductive beads CB may be irradiated with laser light to melt the conductive beads CB. 【0041】 It is preferable to use a CO2 (carbon dioxide) laser beam. By irradiating with CO2 laser beam, the irradiated area can be selectively processed, preventing damage to the surrounding area. The output power and number of irradiations of the laser beam can be adjusted as appropriate, as long as an aperture OP is formed. Here, the laser beam irradiation step may be performed after scattering the conductive beads CB and before attaching the insulating film 102 to the redistribution layer 100. By performing the laser beam irradiation step before attaching the insulating film 102 to the redistribution layer 100, it becomes unnecessary to use the same type of laser beam for forming the aperture OP and melting the conductive beads CB, thereby increasing the variety of materials that can be used for the conductive beads CB. An example of a CO2 laser is given, but a suitable laser can be selected to match the wavelength that has good absorption efficiency for the material. Examples include YAG lasers, excimer lasers, fiber lasers, and semiconductor infrared lasers. 【0042】 When laser light is irradiated onto the region VPA where the via plug VP3 is provided, the conductive beads CB remaining in the recess of the via plug VP3 are melted, forming a conductive plug CP in the recess of the via plug VP3. When laser light (white dotted arrow) is irradiated onto the region VPA where the via plug VP3 is provided, as shown in Figure 7, the conductive beads CB melt, fill the recess of the via plug VP3, and form a conductive plug CP. The output and number of irradiations of the laser light can be changed as appropriate, as long as a conductive plug CP is formed. As long as a sufficient number or amount of conductive beads CB remain in the recess of the via plug VP3, the upper surface CP01 of the conductive plug CP formed by the melting of the conductive beads CB can be aligned flat with the upper surface 1101 of the via plug VP3 on the insulating layer 104-3. 【0043】 After step S13 in Figure 3, a step of removing the substrate 101 from the multilayer wiring board 10 may be performed. As a step of removing the substrate 101, as shown in Figure 8, the substrate 101 and the multilayer wiring board 10 can be separated by irradiating the substrate 101 with laser light (white dotted arrow) from the side 1012 opposite to the side on which the redistribution layer 100 is provided to cause ablation. Before forming the conductive layer 106 on the substrate 101, a sacrificial layer may be provided on the substrate 101 in advance, and the substrate 101 and the multilayer wiring board 10 can be separated by irradiating the sacrificial layer with laser light to cause ablation. The sacrificial layer can be formed using a material that evaporates when irradiated with laser light. 【0044】 Through the above process, the multilayer wiring board 10 shown in Figures 1 and 2 can be obtained. 【0045】 When the multilayer wiring board 10 is used in a semiconductor device, for example, as shown in Figure 2, bumps E1 are formed on the conductive plug CP within the opening OP, and the semiconductor chip 200 is mounted on the connecting plug layer 150. Bumps E2 are formed so as to be in contact with the conductive layer 106 or via plug VP-1 of the first layer 100-1, and a printed wiring board 250 is mounted on the first layer 100-1 to obtain a semiconductor device having the multilayer wiring board 10. The bumps may be formed from, for example, solder material. As the solder material, tin (Sn)-lead (Pb) solder, tin (Sn)-silver (Ag)-copper (Cu) solder, etc. can be used. 【0046】 As described above, according to this embodiment, even if the via plug has a conformal shape, a via with a flat top surface can be formed by melting conductive beads into the via plug and filling it with conductive material. As a result, the multilayer wiring board can form good electrical connections with circuit boards such as semiconductor chips, and the productivity of the multilayer wiring board can be improved. Furthermore, since conductive beads are used as the filling material for the via plug and the conductive plug is formed in the via plug by irradiating them with laser light, the process of forming the conductive plug is simplified, and manufacturing costs can be reduced. 【0047】 The various configurations of the multilayer wiring board exemplified as one embodiment of the present invention can be combined as appropriate, as long as they do not contradict each other. Furthermore, multilayer wiring boards disclosed in this specification and drawings, with additions, deletions, or design modifications of components, or additions, omissions, or changes in processes, as appropriate by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention. 【0048】 Any effects or benefits other than those brought about by the embodiments disclosed herein are to be understood to be brought about by the present invention if they are clear from the description herein or can be easily predicted by a person skilled in the art. 【0049】 The multilayer wiring board according to this embodiment can be applied to a panel-based fan-out package (FOPLP: Fan-Out Panel Level Package) that connects a semiconductor chip and a printed wiring board. According to the manufacturing method of the multilayer wiring board 10 according to this embodiment, a large glass substrate can be used as a support substrate, thereby increasing the productivity of the multilayer wiring board and reducing the manufacturing cost of semiconductor products using FOPLP. [Industrial applicability] 【0050】 A multilayer wiring board and a method for manufacturing a multilayer wiring board according to one embodiment of the present invention can be used as a rewiring member for a panel-level fan-out package. [Explanation of Symbols] 【0051】 10: Multilayer wiring board, 100: Redistribution layer, 100-1: First layer, 100-2: Second layer, 100-3: Top layer, 101: Substrate, 102: Insulating film, 104: Insulating layer, 104-1: Insulating layer, 104-2: Insulating layer, 104-3: Insulating layer, 106: Conductive layer, 110-3: Conductive layer, 150: Connector plug layer, 200: Semiconductor chip, 250: Printed wiring board, 1012: Surface, 1021: Top surface, 1101: Top surface, 10412: Bottom surface, 10431: Top surface, VA1~3: Via, V1~3: Via hole, VP1~3: Via plug, CP: Conductive plug, OP: Opening, E1, 2: Bump, Conductive bead: CB

Claims

[Claim 1] A via plug having a conformal shape, provided on the uppermost layer of the rewiring layer and having a conductive layer along the via hole, An insulating film covering the upper surface of the redistribution layer, An opening is provided in the insulating film that exposes the upper surface of the conformal-shaped via plug, The opening includes a conductive plug that fills the recess of the conformally shaped via plug inside the opening, Multilayer wiring board. [Claim 2] The beer hall overlaps with the opening, The multilayer wiring board according to claim 1. [Claim 3] The conductive layer comprises a first conductive material, The conductive plug includes a second conductive material different from the first conductive material. The multilayer wiring board according to claim 1. [Claim 4] The redistribution layer includes a first layer on which a first via plug is provided, and an uppermost layer laminated on the first layer. The first via plug described above is superimposed on the via plug, The multilayer wiring board according to claim 1. [Claim 5] A multilayer wiring board according to claim 1, A semiconductor chip disposed on the first surface of the multilayer wiring board, A printed circuit board is disposed on a second surface opposite to the first surface, Semiconductor equipment. [Claim 6] A via plug with a conformal shape is formed along the via hole in the uppermost layer of the rewiring layer. Conductive beads are scattered on the upper surface of the rewiring layer, and the conductive beads are left in the recesses of the conformally shaped via plugs. An insulating film is provided on the upper surface of the rewiring layer. A method for manufacturing a multilayer wiring board, comprising: irradiating a region on which the conformally shaped via plugs are provided with a laser beam from the upper surface of the insulating film to form an opening that exposes the upper surface of the conformally shaped via plugs; melting conductive beads remaining in the recesses of the conformally shaped via plugs to form conductive plugs in the recesses of the conformally shaped via plugs; and forming conductive plugs in the recesses of the conformally shaped via plugs. [Claim 7] The method for manufacturing a multilayer wiring board according to claim 6, wherein the melting of the conductive beads is performed by the laser light simultaneously with the formation of the opening. [Claim 8] The method for manufacturing a multilayer wiring board according to claim 6, wherein the melting of the conductive beads is performed by irradiation with a second laser beam after the formation of the opening.

Images