Plasma dicing method

Abstract

The present invention provides a method and related apparatus for enabling plasma dicing of workpieces having compound semiconductor substrates. [Solution] The method includes providing a workpiece having a compound semiconductor substrate; providing a mask structure on the workpiece having an upper layer containing a hard mask material and a peeling lower layer between the front side of the workpiece and the upper layer, defining one or more dicing streets; and plasma dicing the workpiece by a process that includes plasma etching the compound semiconductor substrate at least partially along the dicing streets.

Description

Technical Field

[0001] The present invention relates to a method for plasma dicing a compound semiconductor substrate and a related apparatus. The present invention also relates to a related workpiece having a compound semiconductor substrate.

Background Art

[0002] It is known that compound semiconductor substrates such as silicon carbide are extremely hard materials. Therefore, there are several problems in fabricating compound semiconductor devices from compound semiconductor substrates. Conventional means for separating a compound semiconductor substrate into individual dice include mechanical polishing such as a saw or wire impregnated with diamond particles, and laser dicing. Since compound semiconductor substrates are usually hard and brittle, these conventional separation means can cause cracks to propagate within the substrate. These cracks can result in yield reduction and / or reliability problems. Furthermore, because compound semiconductor substrates are hard, the cutting speed is relatively slow compared to conventional dicing of these substrates, and the consumption of blades and wires can be high.

[0003] In order to produce the maximum number of dice from a compound semiconductor substrate, the area and thickness of the dice can be reduced. However, this generally exacerbates the above problems. Usually, the thinner the substrate, the higher the probability of damage and crack formation. And since cracks can be formed in a relatively large portion of the dice, they can cause significant damage to the dice.

[0004] Plasma dicing can be used to address these problems. When plasma dicing silicon substrates, a mask is typically applied to the substrate before plasma etching. This ensures that only the area outside the mask is etched. This offers several advantages, such as a significant reduction in cracks and an efficient method for separating the silicon substrate into individual dies, as multiple parts of the substrate can be diced simultaneously. However, numerous challenges must be overcome before considering plasma dicing compound semiconductor substrates. For example, compound semiconductor substrates are relatively hard, requiring a more physical etching process to penetrate them compared to silicon substrates. Furthermore, because a relatively powerful etching process is needed to cut through compound semiconductor substrates, masks commonly used for silicon substrates wear out rapidly when used on compound semiconductor substrates. In addition, any masks used on compound semiconductor substrates must be able to withstand high etching rates for efficient process operation. As a result of these problems, despite significant interest in the use of plasma dicing on silicon carbide in semiconductor device manufacturing, there are currently no commercially viable processes.

[0005] In addition, it is necessary to consider what to do with the mask after the compound semiconductor substrate has been plasma diced. That is, the mask needs to be either made part of the semiconductor device or made removable. However, neither of these is ideal. If the mask is a permanent part of the semiconductor device, it may interfere with its operation, and removing the mask may result in damage and increase the complexity of fabricating these devices. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2017-085097 [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention addresses the above-mentioned problems and needs in at least some of its embodiments. In particular, the present invention provides a method and related apparatus for enabling plasma dicing of a workpiece having a compound semiconductor substrate. [Means for solving the problem]

[0008] According to a first aspect of the present invention, a method for plasma dicing a workpiece having a compound semiconductor substrate is provided. The method is as follows: A workpiece having a compound semiconductor substrate is provided, A mask structure is provided on the workpiece having an upper layer containing a hard mask material and a peeling lower layer between the front side of the workpiece and the upper layer, defining one or more dicing streets. The process includes plasma dicing a workpiece by a process that includes plasma etching a compound semiconductor substrate at least partially along a dicing street.

[0009] This enables high-speed etching, efficient use of mask materials, and easy removal of the mask without damaging the workpiece, while allowing for the individualization of workpieces with compound semiconductor substrates.

[0010] The mask structure can be provided on the front side (also referred to as the device side) or the back side of the compound semiconductor substrate.

[0011] Dicing streets can be formed on a mask structure using patterning means known in the art, such as laser beam scanning, mechanical means (e.g., blades), photolithography, etching ablation, and / or jet ablation.

[0012] Dicing streets create openings in the mask structure, allowing the compound semiconductor substrate to be etched through them.

[0013] Any suitable plasma etching process can be used for plasma etching of compound semiconductor substrates. Etching can be performed using an RF plasma etching process, or it can be achieved using an inductively coupled plasma (ICP) etching process.

[0014] A workpiece can be mounted on a carrier structure. The carrier structure may include a tape or a carrier wafer. If the carrier structure includes a tape, the tape may be supported by a frame structure known in the art. This type of carrier structure (i.e., including a tape supported by a frame structure) may be referred to as a tape / frame carrier structure.

[0015] The mask structure can be provided by attaching a release layer to the workpiece, attaching a hard mask material to the release layer, and creating dicing streets between the release layer and the hard mask material.

[0016] The mask structure can be provided by attaching a hard mask material to a release layer, attaching the release layer to a workpiece, and creating dicing streets between the release layer and the hard mask material.

[0017] The release layer may include, for example, the materials described herein, materials that can be incorporated into existing manufacturing process flows for deposition on and / or removal from a workpiece.

[0018] The release layer may include a release coating. The release layer may also be referred to as an adhesive layer.

[0019] The release layer may include a water-washable coating. The water-washable coating may include a carbon-based polymer. The water-washable coating may be a commercially available product known in the art (e.g., HogoMax (registered trademark) manufactured by Disco or DaeCoat (registered trademark) manufactured by Daetec). The water-washable coating may be provided on the workpiece and / or the mask structure by spin coating.

[0020] The release layer may include an adhesive tape. The tape may be attached using a tape supply device. The tape may be laminated at high temperature and optionally under reduced pressure.

[0021] The release layer may include polycrystalline silicon, silicon dioxide, or germanium oxide. The polycrystalline silicon release layer may be provided on the workpiece and / or the mask structure by chemical vapor deposition (CVD). The silicon dioxide release layer may be provided on the workpiece and / or the mask structure by CVD. The germanium oxide release layer may be provided on the workpiece and / or the mask structure by molecular beam deposition. The polycrystalline silicon release layer or the silicon dioxide release layer may be removed by a release etching process. The germanium oxide release layer may be removed by an aqueous process.

[0022] The release layer may have a thickness in the range of 1 to 10 μm (e.g., 1 μm, 3 μm, 5 μm, 10 μm, etc.).

[0023] The hard mask material may include a metal or a metal alloy. The metal or metal alloy may include one or more of copper, nickel, aluminum, indium, and tin.

[0024] The hard mask material may include aluminum oxide (Al2O3) and / or indium tin oxide.

[0025] The hard mask can be provided on the release layer by known means such as physical vapor deposition (PVD) or by a technique that requires the deposition of a thicker layer after the deposition of a thin seed layer. The seed layer can be deposited by PVD or electroless means.

[0026] Alternatively, a hard mask can also be provided on the release layer by supporting a metal (e.g., a metal film) with a film (e.g., an organic film) and attaching the metal to the release layer. In this case, a high-vacuum system is not required.

[0027] The mask structure can include a second release layer provided on the hard mask material. The second release layer can be provided on the side opposite to the side where the first release layer of the hard mask material is provided. The second release layer can have a thickness of 1 to 10 μm. As a result, by providing a dicing street in the mask structure, the post-cutting material that condenses on any surface close to the dicing street, such as the surface of the hard mask material, can be easily removed (e.g., by washing with deionized water). If the post-cutting material is not removed, it can cause deterioration of the etching shape, so it is advantageous to enable its removal.

[0028] The etching selectivity of the hard mask material with respect to the compound semiconductor substrate can be at least 10:1. The plasma etching of the compound semiconductor substrate can include fluorine- or chlorine-based plasma etching.

[0029] The plasma etching of the compound semiconductor substrate can include the use of an etching gas mixture containing sulfur hexafluoride and optionally oxygen. This etching gas mixture can further include an inert gas such as argon.

[0030] The method can further include removing the release layer and the hard mask material after plasma etching the compound semiconductor substrate. The release layer and the hard mask material can be removed using an aqueous solution or a release etching process.

[0031] The method may further include, after plasma etching a compound semiconductor substrate, performing a cleaning step to remove any residue in the dicing streets (e.g., those resulting from the interaction between the plasma and the delamination layer) before removing the delamination layer and hard mask material. The cleaning step may include a nitric acid etching process.

[0032] The workpiece may comprise a compound semiconductor substrate and one or more additional structures formed on the compound semiconductor substrate. The release layer may be in contact with the compound semiconductor substrate and / or at least a portion of the additional structures.

[0033] One or more additional structures may have a metal layer. Furthermore / or, one or more additional structures may include one or more materials such as silicon dioxide and polyimide. Furthermore / or, one or more additional structures may include a device structure. The device structure may include metal (e.g., a metal layer) and / or insulating components (e.g., an insulating layer). One or more additional structures may be provided on a compound semiconductor substrate.

[0034] The release layer may have multiple release coatings. The compound semiconductor substrate may be a silicon carbide substrate. The applicant has demonstrated a significant improvement in die strength in plasma-diced SiC. Alternatively, the compound semiconductor substrate may be a gallium nitride substrate.

[0035] Compound semiconductor substrates can be completely etched along dicing streets by plasma etching to achieve individual workpiece fragmentation. To achieve piece separation of the workpiece, the thickness of the compound semiconductor substrate may be reduced before completely etching the substrate along the dicing street by plasma etching. This process is generally referred to as dicing after grinding. The reduction in the thickness of the compound semiconductor substrate can be achieved using processes known in the art, such as substrate grinding.

[0036] Plasma etching can partially etch a compound semiconductor substrate along dicing streets, and then reduce the thickness of the compound semiconductor substrate to achieve piece separation of the workpiece. This process is generally referred to as a dicing before grinding process. The thickness reduction of the compound semiconductor substrate can be achieved using processes known in the art, such as substrate grinding.

[0037] According to a second aspect of the present invention, a system for plasma dicing a workpiece having a compound semiconductor substrate is provided. The system is A mask installation configuration is provided on a workpiece having a compound semiconductor substrate, comprising an upper layer containing a hard mask material and a peeling lower layer between the workpiece and the upper layer, defining one or more dicing streets, and a mask structure. The system comprises a plasma etching apparatus configured to at least partially plasma etch a compound semiconductor substrate along a dicing street, and a material removal apparatus configured to reduce the thickness of the compound semiconductor substrate to achieve pieceification of the workpiece.

[0038] The mask installation configuration may include a PVD device. The mask installation configuration may include a tape supply device. A plasma etching apparatus may include an RF plasma etching apparatus or an inductively coupled plasma etching apparatus. A plasma etching apparatus may include etching apparatus known in the art. A plasma etching apparatus may comprise a chamber, a plasma generating device configured to generate plasma in the chamber suitable for etching a compound semiconductor substrate, a work support disposed in the chamber to support a workpiece, a gas supply and pumping configuration for supplying etching gas to the chamber, and a control device configured to control the plasma etching apparatus including the gas supply and pumping configuration.

[0039] According to a third aspect of the present invention, a workpiece is provided having a compound semiconductor substrate, an upper layer containing a hard mask material, and a delamination lower layer between the workpiece and the upper layer, on which a mask structure defining one or more dicing streets is provided.

[0040] To avoid any ambiguity, wherever terms such as “having” or “including” are used herein, the present invention should be understood to also include more restrictive terms such as “consisting of” or “essentially composed of,” to the extent that they are contextually appropriate.

[0041] As described above, the present invention also encompasses any combination of the features described above or below in the description, drawings, or claims. For example, any feature disclosed in relation to a first aspect of the present invention may be appropriately combined with any feature disclosed in relation to a second aspect of the present invention, and vice versa. [Brief explanation of the drawing]

[0042] [Figure 1] (a) Silicon carbide substrate with a metal layer on the back, (b) Formation of a delamination layer, (c) Formation of a mask, (d) Generation of a dicing street, (e) Plasma etching / dicing step, (f) Removal of the mask and delamination layer. [Figure 2] Images of a substrate having a backside metallization layer (BSM), a washable coating, a copper mask, and a second washable coating, generated using a scanning electron microscope, are shown. [Modes for carrying out the invention]

[0043] Figure 1 illustrates a process for plasma dicing a workpiece having a compound semiconductor substrate containing a silicon carbide substrate. Figure 1(a) shows a workpiece having a silicon carbide substrate 10 on which a metal layer 15 is provided. The silicon carbide substrate 10, having a device structure with a metal surface and insulation, is supported by an insulating component 20, which is attached to a carrier structure 25. The carrier structure includes a carrier wafer, but those skilled in the art will understand that other carrier structures can be used, such as a tape supported by a frame structure known in the art (e.g., a tape / frame carrier structure).

[0044] Figure 1(b) shows the same workpiece as in Figure 1(a), where a release layer 30 is provided on the workpiece, in this case on the metal layer 15. The release layer 30 includes materials that can be incorporated into existing manufacturing process flows for both deposition on and removal from the workpiece, such as a water-washable coating (WWC). The WWC may include an organic film formed from a carbon-based polymer spin-coated onto the workpiece. The release layer 30 has a thickness ranging from 1 to 10 μm. The presence of a WWC provides the advantage of optimizing the release layer 30 for use with UV lasers, such as excimer lasers commonly used for laser scribing of dicing streets. After providing the release layer 30 on the workpiece, residual water solvent is removed, and the release layer is fired at 200°C to ensure stability of the release layer at high temperatures (e.g., 200°C). Standard scratch / scribe and tape tests known in the art demonstrated good adhesion of the WWC to the workpiece. Those skilled in the art will understand that the release layer 30 may be made from other materials, deposited on a workpiece using various processes described herein, and removed from the workpiece.

[0045] Figure 1(c) shows the same workpiece as Figure 1(b), where a mask 35 (described later) is provided on the release layer 30. Before attaching the mask, a degassing process was performed at 200°C under vacuum to prevent the generation of water during deposition, which could degrade the release layer 30 or adversely affect the adhesion of the mask 35 to the release layer. After the 200°C degassing process, an 8 μm copper mask 35 was attached to the WWC coating cured by physical vapor deposition (PVD) using a commercially available apparatus, specifically the SPTS Sigma fxP® system from SPTS Technologies Limited (Newport, UK, NP18 2TA). Second scratch / scribe and tape tests known in the art demonstrated good adhesion of the copper mask 35 to the release layer 30, and no peeling was observed. The mask material achieves a selectivity of at least 10:1 for silicon carbide to the mask, enabling plasma dicing with silicon carbide of various thicknesses. Those skilled in the art will understand that the mask 35 can be made from other moderately hard materials known in the art that can achieve a sufficiently high etching selectivity for the silicon carbide substrate 10, and that the mask can be applied to the release layer 30 using other techniques known in the art.

[0046] Figure 1(d) shows the same workpiece as in Figure 1(c), where dicing streets have been created in the mask 35, the exfoliation layer 30, and the metal layer 15, respectively. The dicing streets were created using laser scribing with an ultraviolet picosecond excimer laser system that projected a beam directly onto the copper mask 35. Those skilled in the art will understand that dicing streets can also be created using other known patterning methods, such as photolithography, etching ablation, jet ablation, or the use of blades.

[0047] Figure 1(e) shows the same workpiece as in Figure 1(d), where plasma 50 is generated adjacent to the silicon carbide substrate 10. The plasma 45 is used to etch the silicon carbide substrate 10 through the openings in the mask 35 (i.e., along the dicing street). Plasma dicing of the silicon carbide substrate 10 is performed until the silicon carbide substrate is completely removed along the vertical path 50 passing through the silicon carbide substrate. This results in the fragmentation of the workpiece, i.e., individual dies 55 are manufactured. The plasma dicing step is performed using any suitable etching process. For example, SF6RF plasma can be used (the entire content is incorporated herein by reference, by Yasuhisa Sano et al., Materials Science Forum, submitted September 8, 2023, ISSN: 1662-9752, Vol. 1124, pp. 51-55). Alternatively, plasma dicing may be performed using ICP etching with SF6, oxygen, and optionally an inert gas (see, for example, U.S. Patent Publication No. 11037793, the entire content of which is incorporated herein by reference). A cleaning step is then performed by performing nitric acid etching to remove any residue in the dicing street.

[0048] Figure 1(f) shows the same workpiece as Figure 1(e), where the mask 35 and release layer 30 have been removed. The release layer 30 and mask 35 are removed using an aqueous solution. The die 55 remaining on the carrier structure 25 is cleaned using a standard process known in the art. The die 55 is then removed from the carrier structure 25 by a pick-and-place system (not shown).

[0049] As described above, Figure 1 shows a plasma dicing process in which the silicon carbide substrate 10 is completely etched along the dicing street 40 by plasma etching to create individual pieces of the workpiece. However, a DBG process can also be employed in which the silicon carbide substrate 10 is partially etched along the dicing street 40 by plasma etching, and then the thickness of the silicon carbide substrate is reduced to create individual pieces of the workpiece.

[0050] Many variations are possible. For example, the workpiece shown in Figure 1 can be turned over, and the release layer 30 and mask 35 can be attached to the opposite side of the workpiece (for example, the side of the workpiece where the insulating component 20 is provided). Alternatively, the mask 35 can be placed on the release layer 30 first to form the mask structure, and then the mask structure can be placed on the workpiece.

[0051] Figure 2 shows images generated using a scanning electron microscope of a silicon substrate having a backside metallization layer (BSM), a water-washable coating (WWC) approximately 10 μm thick, a copper mask (Cu) approximately 8 μm thick, and a second water-washable coating (WWC) approximately 10 μm thick. The silicon substrate is properly exposed after an excimer laser scribing step in preparation for plasma etching to form trenches in the substrate. No delamination of the backside metallization layer or mask was observed. In this state, plasma dicing can be performed using ICP etching with SF6 and oxygen-based chemical reactions. The SynapseEtch® ICP module (manufactured by SPTS Technologies Limited), which generates high-density plasma, is highly suitable for this step. However, other etching equipment may also be used for this purpose.

Claims

1. A plasma dicing method for a workpiece having a compound semiconductor substrate, A workpiece having a compound semiconductor substrate is provided, A mask structure is provided on the workpiece having an upper layer containing a hard mask material and a peeling lower layer between the front side of the workpiece and the upper layer, defining one or more dicing streets. A method comprising plasma dicing a workpiece by a process that includes plasma etching the compound semiconductor substrate at least partially along the dicing street.

2. The aforementioned mask structure is The release layer is attached to the workpiece. The hard mask material is attached to the release layer. The method according to claim 1, which is provided by generating dicing streets in the release layer and the hard mask material.

3. The aforementioned mask structure is The release layer is attached to the hard mask material. The release layer is attached to the workpiece. The method according to claim 1, which is provided by generating dicing streets in the release layer and the hard mask material.

4. The method according to any one of claims 1 to 3, wherein the peeling layer comprises a water-washable coating, polycrystalline silicon, silicon dioxide, or germanium oxide.

5. The method according to any one of claims 1 to 3, wherein the release layer includes an adhesive tape.

6. The method according to any one of claims 1 to 5, wherein the hard mask material comprises a metal or a metal alloy.

7. The method according to claim 6, wherein the metal or metal alloy comprises one or more of copper, nickel, aluminum, indium, and tin.

8. The method according to any one of claims 1 to 7, wherein the etching selectivity ratio of the compound semiconductor substrate to the hard mask material is at least 10:

1.

9. The method according to any one of claims 1 to 8, wherein the plasma etching of the compound semiconductor substrate includes fluorine or chlorine-based plasma etching.

10. The method according to claim 9, wherein the plasma etching of the compound semiconductor substrate comprises the use of an etching gas mixture containing sulfur hexafluoride and optionally oxygen.

11. The method according to any one of claims 1 to 10, further comprising plasma etching the compound semiconductor substrate and then removing the delamination layer and the hard mask material.

12. The method according to any one of claims 1 to 11, wherein the workpiece comprises the compound semiconductor substrate and one or more additional structures formed on the compound semiconductor substrate, and the release layer is in contact with at least a portion of the compound semiconductor substrate and / or the additional structures.

13. The method according to any one of claims 1 to 12, wherein the release layer has a plurality of release coatings.

14. The method according to any one of claims 1 to 13, wherein the compound semiconductor substrate is a silicon carbide substrate.

15. The method according to any one of claims 1 to 14, wherein the compound semiconductor substrate is completely etched along the dicing street by the plasma etching to achieve piece separation of the workpiece.

16. The method according to any one of claims 1 to 14, wherein the compound semiconductor substrate is partially etched along the dicing street by the plasma etching, and thereafter the thickness of the compound semiconductor substrate is reduced, thereby achieving the individualization of the workpiece.

17. The method according to any one of claims 1 to 16, wherein the workpiece is attached to a carrier structure such as a tape / frame carrier structure.

18. A system for plasma dicing a workpiece including a compound semiconductor substrate, A mask installation configuration is provided on the workpiece having the compound semiconductor substrate, comprising an upper layer containing a hard mask material and a peeling lower layer between the workpiece and the upper layer, defining one or more dicing streets, and a mask structure. A system comprising: a plasma etching apparatus configured to plasma etch the compound semiconductor substrate at least partially along the dicing street; and a material removal apparatus configured to reduce the thickness of the compound semiconductor substrate to achieve piece formation of the workpiece, optionally.

19. A workpiece having a compound semiconductor substrate, comprising an upper layer containing a hard mask material and a delamination lower layer between the workpiece and the upper layer, wherein a mask structure defining one or more dicing streets is provided thereon.

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