Semiconductor device and method for manufacturing a semiconductor device

Abstract

The goal is to create a carrier lifetime reduction region in semiconductor devices while keeping manufacturing costs down. [Solution] The semiconductor device comprises a semiconductor substrate on which a first conductivity type drift layer (1) is formed, a plurality of trenches (8) formed on the first main surface of the semiconductor substrate, electrodes (11a, 12a) embedded in the trenches (8) via insulating films (11b, 12b), a mesa region which is the region between the trenches (8) on the semiconductor substrate, and a first conductivity type source layer (13) or a second conductivity type contact layer (14) formed on the surface layer on the first main surface side of the mesa region. Dislocations (201) with a total length longer than the width of the mesa region are formed at a position on the second main surface side of the source layer (13) or contact layer (14) in the mesa region.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] For example, Patent Document 1 discloses a technique for improving the switching characteristics of IGBTs and diodes in semiconductor devices by partially creating a carrier lifetime reduction region with a high defect density within the drift region using charged particles. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-129250 [Overview of the project] [Problems that the invention aims to solve]

[0004] Methods for forming carrier lifetime reduction regions with high defect density using charged particles, such as the technology described in Patent Document 1, involve an increase in the number of manufacturing steps for semiconductor devices, thus leading to an increase in the manufacturing cost of semiconductor devices.

[0005] This disclosure is made to solve the above-mentioned problems and aims to create a carrier lifetime reduction region in semiconductor devices while suppressing an increase in manufacturing man-hours. [Means for solving the problem]

[0006] The semiconductor device according to this disclosure comprises a semiconductor substrate having a first main surface and a second main surface and having a drift layer of a first conductivity type formed thereon; a plurality of trenches formed on the first main surface of the semiconductor substrate; electrodes embedded in the trenches via an insulating film; a mesa region which is a region between the trenches in the semiconductor substrate; and a source layer of the first conductivity type or a contact layer of the second conductivity type formed on the surface layer on the first main surface side of the mesa region, wherein the mesa region has a dislocation whose total length is longer than the width of the mesa region at a position on the second main surface side of the source layer or the contact layer. [Effects of the Invention]

[0007] According to this disclosure, it is possible to provide a carrier lifetime reduction region in a semiconductor device while suppressing an increase in manufacturing man-hours. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a diagram illustrating the overview of the technology related to this disclosure. [Figure 2] Figure 2 shows a three-dimensional image of the second dislocation. [Figure 3] Figure 3 is a graph showing the relationship between the thickness of the gate trench insulating film and the depth of the second dislocation. [Figure 4] Figure 4 is a plan view of a striped semiconductor chip. [Figure 5] Figure 5 is a plan view of the chip of an island-type semiconductor device. [Figure 6] Figure 6 is a plan view of the IGBT region. [Figure 7] Figure 7 is a cross-sectional view of the IGBT region. [Figure 8] Figure 8 is a cross-sectional view of the IGBT region. [Figure 9] Figure 9 is a plan view of the diode region. [Figure 10] Figure 10 is a cross-sectional view of the diode region. [Figure 11]Figure 11 is a cross-sectional view of the diode region. [Figure 12] Figure 12 is a cross-sectional view of the boundary between the IGBT region and the diode region (GG section). [Figure 13] Figure 13 is a cross-sectional view of the terminal region. [Figure 14] Figure 14 is a cross-sectional view of the terminal region. [Figure 15] Figure 15 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 16] Figure 16 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 17] Figure 17 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 18] Figure 18 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 19] Figure 19 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 20] Figure 20 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 21] Figure 21 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 22] Figure 22 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 23] Figure 23 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 24] Figure 24 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 25] Figure 25 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 26] Figure 26 is a diagram illustrating a method for manufacturing a semiconductor device. [Figure 27] Figure 27 shows an example of the configuration of a semiconductor device according to Embodiment 1. [Figure 28] Figure 28 shows an example of the configuration of a semiconductor device according to Embodiment 1. [Figure 29] Figure 29 shows an example of the configuration of a semiconductor device according to Embodiment 1. [Figure 30] Figure 30 shows an example of the configuration of a semiconductor device according to Embodiment 2. [Figure 31] Figure 31 is a diagram showing an example of the configuration of a semiconductor device according to Embodiment 2. [Figure 32] Figure 32 shows an example of the configuration of a semiconductor device according to Embodiment 2. [Figure 33] Figure 33 is a diagram showing an example of the configuration of a semiconductor device according to Embodiment 3. [Figure 34] Figure 34 shows an example of the configuration of a semiconductor device according to Embodiment 3. [Figure 35] Figure 35 shows an example of the configuration of a semiconductor device according to Embodiment 3. [Figure 36] Figure 36 shows an example of the configuration of a semiconductor device according to Embodiment 4. [Figure 37] Figure 37 shows an example of the configuration of a semiconductor device according to Embodiment 4. [Figure 38] Figure 38 shows an example of the configuration of a semiconductor device according to Embodiment 5. [Figure 39] Figure 39 shows an example of the configuration of a semiconductor device according to Embodiment 6. [Figure 40] Figure 40 shows an example of the configuration of a semiconductor device according to Embodiment 6. [Figure 41] Figure 41 is a diagram showing an example of the configuration of a semiconductor device according to Embodiment 6. [Modes for carrying out the invention]

[0009] [Introduction] In the following description, n and p represent the conductivity types of semiconductors. In this disclosure, the first conductivity type is described as n-type and the second conductivity type as p-type, but the first conductivity type may be described as p-type and the second conductivity type as n-type. - This indicates that the impurity concentration is lower than n, and n + This indicates that the impurity concentration is higher than n. Similarly, p - This indicates that the impurity concentration is lower than p, and p +This indicates that the impurity concentration is higher than p.

[0010] Furthermore, the level of impurity concentration in each region is determined by the peak concentration. In other words, a region with high (or low) impurity concentration means a region with high (or low) peak impurity concentration.

[0011] In the following description, IGBTs (Insulated Gate Bipolar Transistors) or RC-IGBTs (Reverse Conducting IGBTs) are used as examples of semiconductor elements in semiconductor devices. However, the technology described herein is broadly applicable to bipolar devices and is not limited to IGBTs or RC-IGBTs; it can also be applied to diodes, for example.

[0012] Furthermore, in the following explanation, silicon is used as an example of the main material (constituent element) of a semiconductor device. However, the main material of a semiconductor device may also be, for example, silicon carbide, gallium nitride, gallium oxide, or diamond.

[0013] Furthermore, in the following explanation, a first main surface and a second main surface are defined as the main surfaces of a semiconductor device. The first main surface is sometimes referred to as the "front surface." When the semiconductor device is an IGBT, the emitter electrode is formed on the first main surface. When the semiconductor device is an RC-IGBT, in addition to the emitter electrode, the anode electrode of the diode built into the RC-IGBT may be formed on the first main surface. The second main surface is sometimes referred to as the "back surface." When the semiconductor device is an IGBT, the collector electrode is formed on the second main surface. When the semiconductor device is an RC-IGBT, in addition to the collector electrode, the cathode electrode of the diode built into the RC-IGBT may be formed on the second main surface.

[0014] Furthermore, similar to semiconductor devices, a first main surface and a second main surface are also defined for the main surfaces of the semiconductor substrate that constitutes a semiconductor device. That is, the first main surface of the semiconductor substrate is the surface of the semiconductor substrate that is on the side of the semiconductor device's first main surface, and the second main surface of the semiconductor substrate is the surface of the semiconductor substrate that is on the side of the semiconductor device's second main surface.

[0015] [Basic principles of the technology related to this disclosure] Examples of bipolar devices used in power applications include IGBTs, diodes, and RC-IGBTs. In bipolar devices used in power applications, the emission of minority carriers during turn-off is often a challenge.

[0016] One physical property that contributes to carrier emission is carrier lifetime. Carrier lifetime refers to the time it takes for free carriers to effectively disappear; the shorter the carrier lifetime, the more carrier emission is promoted. In bipolar devices for power applications, a high-resistance drift layer is generally provided, and a technique is used to reduce conduction loss by using a conductivity modulation effect that accumulates electrons and holes in the drift layer. However, it takes time to emit the electrons and holes that have been accumulated, which is a problem because it worsens turn-off loss in the case of IGBTs and recovery loss in the case of diodes. To solve this problem, techniques for controlling carrier lifetime are widely used.

[0017] A common method for controlling carrier lifetime is the formation of point defects, as described in Patent Document 1 above. Point defects refer to crystalline defects with atomic-level size, such as silicon vacancies, interstitial silicon, or composites thereof, in the case of silicon semiconductors. Many point defects in semiconductors have energy levels within the band gap and trap free carriers, thus reducing carrier lifetime. Patent Document 1 describes a technique for reducing the carrier lifetime in a desired region of a semiconductor substrate by intentionally and partially forming point defects by irradiation with charged particles.

[0018] However, methods that reduce carrier lifetime by irradiating charged particles require processes such as forming a shielding material (mask) pattern to create non-irradiated areas, in addition to the irradiation process, which increases the manufacturing time of semiconductor devices. Therefore, there is a need for a method that reduces carrier lifetime at a desired location without increasing manufacturing time.

[0019] This disclosure proposes a novel bipolar device that utilizes dislocations. Dislocations are linear crystal defects that arise from the disorder of the periodic structure of atoms, and are distinctly different from point defects formed by irradiation with charged particles. Dislocations can exist unintentionally in semiconductor substrates and have been thought to affect the deterioration of electrical properties and reliability in semiconductor devices. Furthermore, there has been no technology to form dislocations at arbitrary locations in semiconductor substrates until now, and no devices that actively utilize dislocations have been proposed.

[0020] However, since dislocations can have energy levels within the band gap, they are expected to have the effect of trapping free carriers and thus reduce carrier lifetime. The inventors of the technology described herein have discovered a technique to improve electrical characteristics without degrading reliability by forming dislocations different from well-known dislocations at arbitrary locations.

[0021] [Method for observing the second translocation 201] The method for observing dislocations in the technology relating to this disclosure will be explained. Here, a well-known dislocation that is not intentionally formed will be referred to as the "first dislocation," and a dislocation newly formed in the technology relating to this disclosure will be referred to as the "second dislocation."

[0022] Figures 1 and 2 illustrate the overview of the technology relating to this disclosure. Figure 1 is a cross-sectional view of a semiconductor device, and Figure 2 is a three-dimensional image of the second dislocation. Figure 1 shows the n between the active trench gates 11 of the IGBT. -An example in which a second dislocation 201 is formed in the type drift layer 1 is shown. In FIG. 2, the second dislocation 201 between the two active trench gates 11 is shown three-dimensionally. Since the details of each element shown in FIG. 1 will be described later, the description here is omitted.

[0023] The second dislocation 201 has a linearly extended structure three-dimensionally. When the position closest to the second main surface of the semiconductor substrate in the second dislocation 201 is P, the distance from the first main surface of the semiconductor substrate to P is defined as the depth T1 of the second dislocation 201. The total length L1 of the second dislocation 201 refers to the length of the linearly extended dislocation three-dimensionally. The total length L1 of the second dislocation 201 is longer than the mesa width W1 which is the width of the mesa-shaped semiconductor layer sandwiched by the trench gates. Also, the total length L1 of the second dislocation 201 may include a component of the propagation distance L2 of the second dislocation 201 with respect to the extending direction of the trench gate.

[0024] The second dislocation 201 shown in FIG. 1 extends in the depth direction of the paper surface of FIG. 1 and has a three-dimensional linear structure as shown in FIG. 2. Therefore, its overall image cannot be grasped by observation with a general transmission electron microscope (TEM). The inventors of the technology according to the present disclosure have come to observe and control the formation position of the second dislocation 201, which is not well-known, by analyzing the dislocation extending in the three-dimensional direction in detail.

[0025] [Method of Arranging the Second Dislocation] The mechanism by which the second dislocation 201 is formed will be described. The second dislocation 二十1 is formed by utilizing the first dislocation 200. The first dislocation 200 is a well-known dislocation that is not intentionally formed and is generally formed so as to contact the first main surface of the semiconductor substrate in an n + -type source layer 13 or a p + -type contact layer 14. As described above, the regions of "n + " and "p + " refer to regions of high impurity concentration and are formed by ion implantation treatment with a high implantation dose. The high implantation dose means 10 14 cm [[ID=二十五]] -2 [[ID=二十六]]~10 [[ID=二十七]] 16cm -2 This refers to the order.

[0026] Generally, when impurities are doped using ion implantation, the crystallinity of the semiconductor substrate within the region (range) through which the implanted atoms pass is disrupted. That is, a high-density defect region is formed in the region of the semiconductor substrate through which the implanted atoms have passed. When heat treatment is performed to activate the dopant, the defect region is restored or recrystallized. However, if the implantation dose is above a certain level, the crystallinity is not completely restored even after heat treatment, and dislocations and point defects remain. The dislocation formed in this way is the first dislocation 200, which can be easily observed using a general TEM.

[0027] The second dislocation 201 is formed by heat treatment of the first dislocation 200, thereby moving the first dislocation 200 to an arbitrary depth. The depth T1 at which the second dislocation 201 is formed is related to the stress in the semiconductor substrate. Various models exist for the dislocation formation mechanism, but the common principle is energy relaxation. Crystals under high stress are in a high-energy state and are known to often release energy (become a low-energy state) by forming dislocations. In other words, dislocations are more likely to form in high-stress regions. Therefore, if the stress in the semiconductor substrate can be controlled, it will be possible to control the position of the second dislocation 201.

[0028] One of the stress control parameters is the thickness of the gate trench insulating film 11b. Increasing the thickness of the gate trench insulating film 11b results in n including the mesa-like portion (hereinafter referred to as the "mesa region"). - It has been experimentally shown that the stress in the drift layer 1 increases. The stress can be quantitatively evaluated using convergent electron diffraction (CBED), but it is also possible to roughly compare its magnitude using the contrast of TEM images.

[0029] Figure 3 shows the relationship between the thickness of the gate trench insulating film 11b shown in Figure 1 and the depth T1 of the second dislocation 201. Figure 3 is the result of analyzing an actual prototype semiconductor device. The depth T1 of the second dislocation 201 is normalized using the depth of the active trench gate 11, and the thickness of the gate trench insulating film 11b is normalized using the pitch of the active trench gate 11.

[0030] When the gate trench insulating film 11b is thickened, n including the mesa region - The stress in the drift layer 1 increases. To relieve this stress (or strain energy), the first dislocation 200 includes a mesa region n - It moves to the drift layer 1, and the second dislocation 201 is formed.

[0031] Here, as a model for the second dislocation 201, we have described the second dislocation 201 as being formed by the movement of the first dislocation 200. However, it is also possible that the second dislocation 201 originates from a different source. However, since accurately understanding the source of the second dislocation 201 requires extremely advanced analysis, and because an inaccurate understanding of the dislocation's origin does not affect the effectiveness of this technology, a detailed discussion will be omitted.

[0032] Here, we will explain the differences in the manufacturing process between the conventional method of reducing lifetime by irradiation with charged particles (e.g., Patent Document 1) and the technology of this disclosure. As mentioned above, the conventional method of reducing lifetime requires steps such as irradiating with charged particles and forming a shielding material (mask) pattern to create a non-irradiated area, which increases the manufacturing man-hours for semiconductor devices. On the other hand, in the technology of this disclosure, the position where the second dislocation 201 is placed (the position where stress is controlled) can be adjusted by adjusting a design parameter such as the thickness of the insulating film (gate trench insulating film 11b). In order to form the second dislocation 201, it is necessary to heat treat the first dislocation 200, but this heat treatment does not have to be an additional step for dislocation movement, for example n + Type source layer 13 or p +This can be performed simultaneously with the heat treatment to activate the mold contact layer 14. Therefore, the technology according to this disclosure makes it possible to reduce the lifetime at a desired position without increasing the manufacturing steps.

[0033] Furthermore, in the technology relating to this disclosure, the stress control parameters are not limited to the thickness of the gate trench insulating film 11b. For example, the pitch, shape, and depth of the trenches in the gate trench insulating film 11b, or the design parameters of the electrodes embedded in the trenches (gate trench electrodes 11a), can also be considered control parameters for adjusting the position where the second dislocation 201 is placed (the position where stress is controlled). In addition, the thickness of the insulating film, which is a stress control parameter, is not limited to the gate trench insulating film 11b, but also includes the thicknesses of the dummy trench insulating film 12b, diode trench insulating film 21b, terminal dummy trench insulating film 35b, upper gate trench insulating film 36b, and lower gate trench insulating film 36d, which will be described later. By adjusting these design parameters according to the region where the second dislocation 201 is to be placed, it is possible to place the second dislocation 201 at any position, and no special process is required for the formation of the second dislocation 201.

[0034] [Effects common to each embodiment] The technology disclosed herein improves the electrical characteristics of semiconductor devices by locally reducing carrier lifetime through the use of dislocations. This document introduces an example of its application in power control semiconductor devices (power semiconductors).

[0035] Reducing carrier lifetime generally has the effect of promoting the capture of minority carriers. In bipolar devices for power control applications, regions with high impurity concentrations are generally provided on the first and second main surfaces, and a region with low impurity concentrations called a drift layer is formed between the first and second main surfaces. The drift layer has high resistance due to its low impurity concentration, but the conductivity modulation effect unique to bipolar devices can reduce the resistance during conduction and reduce conduction losses. In the case of diodes, applying a voltage in the reverse direction causes a transition from a conducting (on) state to a non-conducting (off) state, and the power loss that occurs during this period is called the recovery loss. In the case of IGBTs, the on and off states can be transitioned at any timing by the gate potential. The power loss that occurs during the transition period from the on state to the off state is called the turn-off loss, and conversely, the power loss that occurs during the transition period from the off state to the on state is called the turn-on loss. The sum of the recovery loss, turn-off loss, and turn-on loss is called the switching loss. Conductivity modulation is effective in reducing power loss in the ON state, but it has the drawback of increasing switching losses. Switching losses are in a trade-off relationship with conduction losses and are adjusted by the impurity concentration in the collector layer and the cathode region.

[0036] There are technologies that improve the trade-off between switching loss and conduction loss by reducing carrier lifetime. Turn-off loss and recovery loss, which are the main components of switching loss, are caused by the discharge of minority carriers. In other words, it is possible to reduce switching loss by efficiently discharging minority carriers. Reducing carrier lifetime is one method of efficiently discharging minority carriers. Furthermore, by efficiently discharging minority carriers, an increase in interruption withstand capability can also be expected.

[0037] When reducing the carrier lifetime in any region of a semiconductor device, a crucial design consideration is which electrical characteristics to prioritize. On the other hand, introducing defects, not limited to dislocations, into a semiconductor device raises concerns such as increased leakage current during the off state, changes in threshold voltage, and decreased gate reliability. Furthermore, in the case of bipolar devices, while reducing the carrier lifetime can lead to reduced switching losses and increased interruption withstand capability, it also comes at the cost of reduced conductivity modulation and increased conduction losses. Designers must assess these trade-offs and place dislocations in the optimal locations.

[0038] The second dislocation 201 is characterized by having a total length L1 that is longer than the mesa width W1. The total length L1 of the second dislocation 201 refers to the propagation distance in three-dimensional space, and in Figure 2, it also includes the component in the depth direction of the paper. By arranging the second dislocation 201 with a long total length L1, the region in which the carrier lifetime is reduced can be expanded. The second dislocation 201 may be curved or convex towards the second main surface. By curving the second dislocation 201, the propagation distance of the second dislocation 201 is increased, and the region in which the carrier lifetime is reduced is expanded. Furthermore, when the second dislocation 201 is formed to control the stress near the active trench gate 11, the second dislocation 201 is formed at a position in contact with the active trench gate 11, as shown in Figures 1 and 2. - To reduce the carrier lifetime of the mold drift layer 1 in the direction of the second main surface, a greater effect can be achieved by making the second dislocation 201 convex toward the second main surface.

[0039] [Matters common to all embodiments] This section describes matters common to all embodiments described below.

[0040] Figure 4 is a plan view showing a semiconductor device that is an RC-IGBT. Figure 5 is a plan view showing a semiconductor device that is an RC-IGBT with a different configuration. The semiconductor device 100 shown in Figure 4 has IGBT regions 10 and diode regions 20 arranged in a stripe pattern and can simply be called a "stripe type". The semiconductor device 101 shown in Figure 5 has multiple diode regions 20 arranged in the vertical and horizontal directions, with IGBT regions 10 arranged around the diode regions 20 and can simply be called an "island type".

[0041] (1) Striped overall planar structure In Figure 4, the semiconductor device 100 includes IGBT regions 10 and diode regions 20 within a single semiconductor device. The IGBT regions 10 and diode regions 20 extend from one end to the other of the semiconductor device 100 and are arranged alternately in stripes in a direction perpendicular to the direction of extension of the IGBT regions 10 and diode regions 20. In Figure 4, three IGBT regions 10 and two diode regions are shown, with all diode regions 20 sandwiched between IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this; the number of IGBT regions 10 may be three or more, or three or less, and the number of diode regions 20 may be two or more, or two or less. Furthermore, the positions of the IGBT regions 10 and diode regions 20 in Figure 4 may be swapped, or all IGBT regions 10 may be sandwiched between diode regions 20. Also, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0042] As shown in Figure 4, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is the region where control pads 41 for controlling the semiconductor device 100 are provided. The IGBT region 10 and the diode region 20 together are called the cell region. A termination region 30 is provided around the combined cell region and pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintenance structure can be appropriately selected and provided in the termination region 30. For example, the breakdown voltage maintenance structure may be configured by providing an FLR (Field Limiting Ring) on ​​the first main surface side, which is the front side of the semiconductor device 100, with a p-type termination well layer of a p-type semiconductor surrounding the combined cell region and pad region 40, or a VLD (Variation of Lateral Doping) surrounding the combined cell region and pad region 40 with a p-type termination well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected according to the breakdown voltage design of the semiconductor device 100. Furthermore, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and IGBT cells or diode cells may be provided in the pad region 40.

[0043] The control pads 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d, 41e. The current sense pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region such that when current flows in the cell region of the semiconductor device 100, a current of one-several-thousandth to one-tens-thousandth of the current flowing in the entire cell region flows.

[0044] The Kelvin emitter pad 41b and gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is the p-type base layer and n-type base layer of the IGBT cell. +The gate pad 41c is electrically connected to the p-type emitter layer and to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer are connected to the p-type base layer. + They may be electrically connected via a contact layer. The temperature sense diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided on the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region.

[0045] (2) Island-type overall plan structure In Figure 5, the semiconductor device 101 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. Multiple diode regions 20 are arranged in a row in both the vertical and horizontal directions within the semiconductor device, and each diode region 20 is surrounded by the IGBT region 10. In other words, multiple diode regions 20 are provided in an island-like configuration within the IGBT region 10. In Figure 5, the diode regions 20 are shown arranged in a matrix configuration with 4 columns in the left-right direction and 2 rows in the upper-right direction of the page, but the number and arrangement of diode regions 20 are not limited to this. It is acceptable as long as one or more diode regions 20 are scattered within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0046] As shown in Figure 5, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is the region where control pads 41 for controlling the semiconductor device 101 are provided. The IGBT region 10 and the diode region 20 together are called the cell region. A termination region 30 is provided around the combined cell region and pad region 40 to maintain the breakdown voltage of the semiconductor device 101. A well-known breakdown voltage maintenance structure can be appropriately selected and provided in the termination region 30. For example, the breakdown voltage maintenance structure may be configured by providing an FLR (Flat Layer Ring) on ​​the first main surface side, which is the front side of the semiconductor device 101, where the combined cell region and pad region 40 are surrounded by a p-type termination well layer of a p-type semiconductor, or a VLD (Very Wide Layer) where the combined cell region and pad region 40 are surrounded by a p-type termination well layer with a density gradient. The number of ring-shaped p-type termination well layers used in the FLR and the density distribution used in the VLD can be appropriately selected according to the breakdown voltage design of the semiconductor device 101. Furthermore, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and IGBT cells or diode cells may be provided in the pad region 40.

[0047] The control pads 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d, 41e. The current sense pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 101, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region such that when current flows in the cell region of the semiconductor device 101, a current of one-several-thousandth to one-tens-thousandth of the current flowing in the entire cell region flows.

[0048] The Kelvin emitter pad 41b and gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 101. The Kelvin emitter pad 41b is the p-type base layer and n-type base layer of the IGBT cell. + The gate pad 41c is electrically connected to the p-type source layer and to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer are connected to the p-type base layer. +They may be electrically connected via a contact layer. The temperature sense diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided on the semiconductor device 101. The temperature of the semiconductor device 101 is measured by measuring the voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region.

[0049] (3) Example of the structure of the IGBT region 10 Figure 6 is a partially enlarged plan view showing the configuration of the IGBT region of a semiconductor device that is an RC-IGBT. Figures 7 and 8 are cross-sectional views showing the configuration of the IGBT region of a semiconductor device that is an RC-IGBT. Figure 6 is an enlarged view of the region enclosed by the dashed line 82 in the semiconductor device 100 shown in Figure 4 or the semiconductor device 101 shown in Figure 5. Figure 7 is a cross-sectional view of the semiconductor device 100 or semiconductor device 101 shown in Figure 6 along the dashed line AA, and Figure 8 is a cross-sectional view of the semiconductor device 100 or semiconductor device 101 shown in Figure 6 along the dashed line BB.

[0050] As shown in Figure 6, the IGBT region 10 is provided with active trench gates 11 and dummy trench gates 12 arranged in a stripe pattern. In semiconductor device 100, the active trench gates 11 and dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, so that the longitudinal direction of the IGBT region 10 is the longitudinal direction of the active trench gates 11 and dummy trench gates 12. On the other hand, in semiconductor device 101, there is no particular distinction between the longitudinal and short directions of the IGBT region 10, but the left-right direction of the paper may be considered the longitudinal direction of the active trench gates 11 and dummy trench gates 12, or the up-down direction of the paper may be considered the longitudinal direction of the active trench gates 11 and dummy trench gates 12.

[0051] The active trench gate 11 is configured with a gate trench electrode 11a provided in a trench formed in a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is configured with a dummy trench electrode 12a provided in a trench formed in a semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or semiconductor device 101.

[0052] n + The mold source layer 13 is provided on both sides of the active trench gate 11 in the width direction, in contact with the gate trench insulating film 11b. + The n-type source layer 13 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm³. 3 ~1.0E+20 / cm 3 n + The type source layer 13 is p along the extension direction of the active trench gate 11. + It is arranged alternately with the type contact layer 14. + The mold contact layer 14 is also provided between two adjacent dummy trench gates 12. + The p-type contact layer 14 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3 That is the case.

[0053] Furthermore, in Figure 6, p is shown between the dummy trench gates 12. + Although only the type contact layer 14 is placed, n + A type source layer 13 may also be included.

[0054] As shown in Figure 6, in the IGBT region 10 of semiconductor device 100 or semiconductor device 101, three active trench gates 11 are arranged in a row, followed by three dummy trench gates 12, and three dummy trench gates 12 are arranged in a row, followed by three active trench gates 11. The IGBT region 10 is thus configured with alternating sets of active trench gates 11 and dummy trench gates 12. In Figure 6, the number of active trench gates 11 in one set of active trench gates 11 is set to 3, but it is acceptable to have 1 or more. Also, the number of dummy trench gates 12 in one set of dummy trench gates 12 may be 1 or more, and the number of dummy trench gates 12 may be 0. In other words, all trenches provided in the IGBT region 10 may be active trench gates 11.

[0055] Figure 7 is a cross-sectional view of semiconductor device 100 or semiconductor device 101 along the dashed line AA in Figure 6, and is a cross-sectional view of the IGBT region 10. Semiconductor device 100 or semiconductor device 101 is made of n - It has a type drift layer 1. - The n-type drift layer 1 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm³. 3 ~1.0E+15 / cm 3 In Figure 7, the semiconductor substrate is n + Type source layer 13 and p + This range extends from the p-type contact layer 14 to the p-type collector layer 16. In Figure 7, n + Type source layer 13 and p + The upper edge of the paper of the p-type contact layer 14 is called the first main surface of the semiconductor substrate, and the lower edge of the paper of the p-type collector layer 16 is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10, which is a cell region, the semiconductor device 100 has n between the first main surface and the second main surface facing the first main surface. - It has a type drift layer 1.

[0056] Semiconductor substrates contain various impurities depending on the manufacturing method. These include oxygen, carbon, boron, and nitrogen. These are known to affect electrical properties and the diffusion of impurity elements.

[0057] As shown in Figure 7, in the IGBT region 10, n - On the first main surface side of the drift layer 1, n - An n-type carrier storage layer 2 is provided, which has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier storage layer 2 is a semiconductor layer having, for example, arsenic or phosphorus as n-type impurities, and the concentration of n-type impurities is 1.0E+13 / cm³. 3 ~1.0E+17 / cm 3 Furthermore, in semiconductor device 100 or semiconductor device 101, the n-type carrier storage layer 2 is not provided, and the region of the n-type carrier storage layer 2 shown in Figure 7 is also n - A configuration in which an n-type drift layer 1 is provided is also possible. By providing an n-type carrier storage layer 2, the current loss when current flows through the IGBT region 10 can be reduced. n-type carrier storage layer 2 and n - The drift layer 1 and this layer together can be called the drift layer.

[0058] n-type carrier storage layer 2 is n - n-type impurities are ion-implanted into the semiconductor substrate constituting the n-type drift layer 1, and then the implanted n-type impurities are removed by annealing. - It is formed by diffusion into the semiconductor substrate, which is the drift layer 1.

[0059] A p-type base layer 15 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm³. 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, in contact with the gate trench insulating film 11b of the active trench gate 11, is n +A type source layer 13 is provided, and the remaining area is p + A type contact layer 14 is provided. + Type source layer 13 and p + The type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15. + When it is necessary to distinguish between the type contact layer 14 and the p-type base layer 15, they may be referred to individually. + The p-type contact layer 14 and the p-type base layer 15 can together be called the p-type base layer.

[0060] Furthermore, the semiconductor device 100 or semiconductor device 101 is n - On the second main surface side of the drift layer 1, n - An n-type buffer layer 3 is provided, having a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 3 is provided to suppress punch-through of the depletion layer extending from the p-type base layer 15 towards the second main surface when the semiconductor device 100 is in the off state. The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) or protons (H+), or by implanting both phosphorus (P) and protons (H+). The concentration of n-type impurities in the n-type buffer layer 3 is 1.0E+12 / cm³ 3 ~1.0E+18 / cm 3 That is the case.

[0061] Furthermore, in semiconductor device 100 or semiconductor device 101, the n-type buffer layer 3 is not provided, and the region of the n-type buffer layer 3 shown in Figure 7 is also n - A configuration may also be provided with an n-type drift layer 1. - The drift layer 1 and this layer together can be called the drift layer.

[0062] The semiconductor device 100 or semiconductor device 101 has a p-type collector layer 16 on the second main surface side of the n-type buffer layer 3. -A p-type collector layer 16 is provided between the p-type drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm³. 3 ~1.0E+20 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 constitutes the p-type termination collector layer 16a. Furthermore, a portion of the p-type collector layer 16 may extend from the IGBT region 10 into the diode region 20.

[0063] As shown in Figure 7, the semiconductor device 100 or semiconductor device 101 penetrates the p-type base layer 15 from the first main surface of the semiconductor substrate, n - A trench is formed that reaches the drift layer 1. An active trench gate 11 is formed by providing a gate trench electrode 11a in the trench via a gate trench insulating film 11b. The gate trench electrode 11a is connected to the gate trench insulating film 11b via n - It faces the drift layer 1. Furthermore, the dummy trench gate 12 is formed by providing a dummy trench electrode 12a in the trench via a dummy trench insulating film 12b. The dummy trench electrode 12a is connected to the dummy trench insulating film 12b via n - It faces the type drift layer 1. The gate trench insulating film 11b of the active trench gate 11 is made of p-type base layer 15 and n + It is in contact with the type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0064] Although not shown in the diagram, two gate trench electrodes 11a with different potentials may be provided on the active trench gate 11 to control the gate capacitance. That is, the gate trench electrodes 11a may be divided into an upper and a lower stage, and the upper and lower stages may be electrically isolated from each other by an insulating film. Such a gate structure is called a two-stage gate structure.

[0065] As shown in Figure 7, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), for example, titanium nitride, or TiSi, which is an alloy of titanium and silicon (Si). As shown in Figure 7, the barrier metal 5 is n + Type source layer 13, p + The contact layer 14 and the dummy trench electrode 12a make ohmic contact, n + Type source layer 13, p + It is electrically connected to the type contact layer 14 and the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed from an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy) or a material composed mainly of copper, and the electrode configuration may consist of multiple layers of metal films formed on these electrodes by electroless plating or electrolytic plating. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. Furthermore, if there are fine regions such as between adjacent interlayer insulating films 4 where good embedding cannot be obtained with the emitter electrode 6, tungsten, which has better embedding properties than the emitter electrode 6, may be placed in the fine regions, and the emitter electrode 6 may be provided on top of the tungsten. Note that if the barrier metal 5 is not provided, n + Type source layer 13, p + An emitter electrode 6 may be provided on the type contact layer 14 and the dummy trench electrode 12a. +The barrier metal 5 may be provided only on the n-type semiconductor layer, such as the source layer 13. The barrier metal 5 and the emitter electrode 6 together may be called the emitter electrode. In Figure 7, the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. If the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a can be electrically connected in a different cross-section.

[0066] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7, like the emitter electrode 6, may be made of an aluminum alloy or a material mainly composed of copper, or a plating film made of these materials. The collector electrode 7 may also have a different configuration from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0067] Figure 8 is a cross-sectional view of semiconductor device 100 or semiconductor device 101 along the dashed line BB in Figure 6, and is a cross-sectional view of the IGBT region 10. The cross-sectional view along the dashed line AA shown in Figure 7 is a cross-sectional view of the n provided on the first main surface side of the semiconductor substrate, in contact with the active trench gate 11. + The difference is that the mold source layer 13 is not visible in the cross-section along the dashed line BB in Figure 8. In other words, as shown in Figure 7, n + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. The p-type base layer referred to here is the p-type base layer 15 and p + This refers to the p-type base layer, which is formed in conjunction with the type contact layer 14.

[0068] As shown in Figures 7 and 8, the second dislocation 201 is n of the semiconductor substrate. + Type source layer 13 and p + It is positioned on the second main surface side of the type contact layer 14. + Type source layer 13 and p +Although a well-known first dislocation 200 exists inside the type- contact layer 14, its illustration is omitted. The second dislocation 201 is a crystal defect that extends three-dimensionally also in the depth direction of the paper surface, and its total length L1 is longer than the mesa width W1. The total length L1 refers to the curved length in a three-dimensional view, not the curved length in a plan view. Although it is not easy to measure the three-dimensional curved length, in the case of the curve that extends also in the depth direction of the paper surface in FIGS. 7 and 8, generally, it is acceptable to consider that "the straight-line distance in the plan view" < "the curved length in the plan view" < "the curved length in the three-dimensional view". Here, when "the curved length in the plan view" = "the curved length in the three-dimensional view", it indicates a state where the dislocation does not extend in the depth direction of the paper surface. Also, when "the straight-line distance in the plan view" = "the curved length in the plan view", it indicates a state where the dislocation does not extend in the depth direction of the paper surface and is in a straight shape.

[0069] The second dislocation 201 is selectively arranged at a three-dimensionally different position from the first dislocation 200. The first dislocation 200 is generally formed by high-dose ion implantation to form an n + type source layer 13 or p + type contact layer 14 is a well-known dislocation generated during the formation. By amorphizing at least a part of the semiconductor substrate by high-dose ion implantation and performing a heat treatment for activation, the first dislocation 200 is formed at a high density. By appropriately controlling the stress of the n - type drift layer 1 including the mesa region, the position of the first dislocation 200 moves, and the second dislocation 201 is selectively formed. As shown in FIGS. 7 and 8, the position where the second dislocation 201 is formed is on the second main surface side rather than the n + type source layer 13 and p + type contact layer 14.

[0070] (4) Structure of the diode region 20 FIG. 9 is a partially enlarged plan view showing the configuration of the diode region of a semiconductor device that is an RC-IGBT. FIGS. 10 and 11 are cross-sectional views showing the configuration of the diode region of a semiconductor device that is an RC-IGBT. FIG. 9 shows an enlarged view of the region surrounded by the dashed line 83 in the semiconductor device 100 shown in FIG. 4 or the semiconductor device 101 shown in FIG. 5. FIG. 10 is a cross-sectional view taken along the dashed line C-C of the semiconductor device 100 shown in FIG. 9. FIG. 11 is a cross-sectional view taken along the dashed line D-D of the semiconductor device 100 shown in FIG. 9.

[0071] The diode trench gate 21 extends from one end side to the opposite end side of the diode region 20, which is a cell region, along the first main surface of the semiconductor device 100 or the semiconductor device 101. The diode trench gate 21 is constituted by providing a diode trench electrode 21a in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a faces the n - -type drift layer 1 through the diode trench insulating film 21b. Between two adjacent diode trench gates 21, a p + -type anode contact layer 24 and a p-type anode layer 25 are provided. The p + -type anode contact layer 24 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 . The p-type anode layer 25 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 . The p + -type anode contact layer 24 and the p-type anode layer 25 are alternately provided in the longitudinal direction of the diode trench gate 21.

[0072] Figure 10 is a cross-sectional view of semiconductor device 100 or semiconductor device 101 along the dashed line CC in Figure 8, and is a cross-sectional view of the diode region 20. The semiconductor device 100 or semiconductor device 101 is made of a semiconductor substrate in the diode region 20 as well as in the IGBT region 10. - It has a type drift layer 1. The n of the diode region 20 - n of the drift layer 1 and IGBT region 10 - The drift layer 1 is formed continuously and integrally with the same semiconductor substrate. In Figure 10, the semiconductor substrate is p + Type anode contact layer 24 to n + This is the range up to the type cathode layer 26. In Figure 10, p + The upper edge of the type anode contact layer 24 on the paper is the first main surface of the semiconductor substrate, n + The lower edge of the cathode layer 26 on the paper is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are the same surface.

[0073] As shown in Figure 10, in the diode region 20, similar to the IGBT region 10, n - An n-type carrier storage layer 2 is provided on the first main surface side of the n-type drift layer 1, - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier storage layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier storage layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that it is not necessary to provide the n-type carrier storage layer 2 in the IGBT region 10 and the diode region 20, and even if the n-type carrier storage layer 2 is provided in the IGBT region 10, the diode region 20 may be configured without the n-type carrier storage layer 2. Also, similar to the IGBT region 10, - The n-type drift layer 1, the n-type carrier storage layer 2, and the n-type buffer layer 3 can collectively be called the drift layer.

[0074] A p-type anode layer 25 is provided on the first main surface side of the n-type carrier storage layer 2. The p-type anode layer 25 is n - It is provided between the p-type drift layer 1 and the first main surface. The p-type anode layer 25 may be formed simultaneously with the p-type base layer 15 of the IGBT region 10 by making the concentration of p-type impurities the same as that of the p-type base layer 15 of the IGBT region 10. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 may be made lower than that of the p-type base layer 15 of the IGBT region 10 to reduce the amount of holes injected into the diode region 20 during diode operation. Reducing the amount of holes injected during diode operation can reduce recovery losses during diode operation.

[0075] On the first main surface side of the p-type anode layer 25, + A type anode contact layer 24 is provided. + The concentration of p-type impurities in the type anode contact layer 24 is the same as the p-type impurity in the IGBT region 10. + The concentration of the p-type impurities in the type contact layer 14 may be the same as, or it may be a different concentration. + The type anode contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type anode contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25. + When it is necessary to distinguish between the p-type anode contact layer 24 and the p-type anode layer 25, they may be referred to individually. + The p-type anode contact layer 24 and the p-type anode layer 25 together may be referred to as the p-type anode layer.

[0076] In the diode region 20, on the second main surface side of the n-type buffer layer 3, n + A type cathode layer 26 is provided. + The type cathode layer 26 is n - It is provided between the mold drift layer 1 and the second main surface. + The n-type cathode layer 26 is a semiconductor layer having n-type impurities such as arsenic or phosphorus, and the concentration of the n-type impurities is 1.0E+16 / cm³. 3 ~1.0E+21 / cm3 As shown in Figure 10, n + The cathode layer 26 is provided in part or all of the diode region 20. + The cathode layer 26 constitutes the second main surface of the semiconductor substrate. Although not shown in the diagram, as described above, n + In the region where the type cathode layer 26 is formed, p-type impurities are further selectively injected, + A portion of the region where the p-type cathode layer 26 is formed may be provided with a p-type cathode layer as a p-type semiconductor.

[0077] As shown in Figure 10, the diode region 20 of the semiconductor device 100 or semiconductor device 101 has a first main surface of the semiconductor substrate through the p-type anode layer 25, and n - A trench is formed that reaches the drift layer 1. The diode trench gate 21 is formed by providing a diode trench electrode 21a within the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is via the diode trench insulating film 21b - It is facing the drift layer 1.

[0078] As shown in Figure 10, the diode trench electrode 21a and p + A barrier metal 5 is provided on the type anode contact layer 24. The barrier metal 5 is provided on the diode trench electrodes 21a and p + The anode contact layer 24 is in ohmic contact with the diode trench electrode and p + It is electrically connected to the type anode contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 of the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. In addition, as in the case of the IGBT region 10, the diode trench electrodes 21a and p +The type anode contact layer 24 and the emitter electrode 6 may be in ohmic contact. Although Figure 10 shows a diagram in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. If the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a can be electrically connected in a different cross-section.

[0079] In the diode trench gate 21, a two-stage gate structure may be applied in which the diode trench electrode 21a is divided into an upper and lower gate trench electrode.

[0080] n + A collector electrode 7 is provided on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is n + Ohmic contact is made with the type cathode layer 26, n + It is electrically connected to the cathode layer 26.

[0081] Figure 11 is a cross-sectional view of semiconductor device 100 or semiconductor device 101 along the dashed line DD in Figure 9, and is a cross-sectional view of the diode region 20. Compared to the cross-sectional view along the dashed line CC shown in Figure 10, a cross-sectional view of the diode region 20 is shown between the p-type anode layer 25 and the barrier metal 5. + The difference is that there is no p-type anode contact layer 24, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. In other words, as shown in Figure 10, + The p-type anode contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25.

[0082] As shown in Figure 10, even in the diode region 20, p + The second dislocation 201 is positioned on the second main surface side of the type anode contact layer 24. +A well-known first dislocation 200 exists within the type anode contact layer 24, but it is not shown in the illustration. The second dislocation 201 is a crystal defect that extends three-dimensionally in the depth direction of the paper, and its total length L1 is longer than the mesa width W1. The total length L1 refers to the curve length in stereoscopic view, not the curve length in plan view. Measuring the curve length in stereoscopic view is not easy, but in the case of a curve that extends in the depth direction of the paper as shown in Figure 10, it is generally safe to assume that "straight-line distance in plan view" < "curve length in plan view" < "curve length in stereoscopic view". Here, when "curve length in plan view" = "curve length in stereoscopic view", it indicates that the dislocation does not extend in the depth direction of the paper. Also, when "straight-line distance in plan view" = "curve length in plan view", it indicates that the dislocation does not extend in the depth direction of the paper and has a linear shape.

[0083] The second dislocation 201 is selectively positioned in a three-dimensionally different location from the first dislocation 200. The first dislocation 200 is generally formed by high-dose ion implantation. + This is a well-known dislocation that occurs with the formation of the type anode contact layer 24. High-dose ion implantation causes at least a portion of the semiconductor substrate to become amorphous, and by applying heat treatment for activation, the first dislocation 200 is formed at high density. n including mesa region - By appropriately controlling the stress in the drift layer 1, the position of the first dislocation 200 shifts, and the second dislocation 201 is selectively formed. The position where the second dislocation 201 is formed is as shown in Figure 10, p + It is positioned on the second main surface side of the type anode contact layer 24. Note that in the region corresponding to the cross-section in Figure 11, p + Since the type anode contact layer 24 is not formed, the first dislocation 200 is also not formed.

[0084] (5) Boundary region between IGBT region 10 and diode region 20 Figure 12 is a cross-sectional view showing the boundary configuration between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. Figure 12 is a cross-sectional view along the dashed line GG in the semiconductor device 100 shown in Figure 4 or the semiconductor device 101 shown in Figure 5.

[0085] As shown in Figure 12, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided extending into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. By providing the p-type collector layer 16 extending into the diode region 20 in this way, the n of the diode region 20 is provided. + The distance between the cathode layer 26 and the active trench gate 11 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation, the channel formed adjacent to the active trench gate 11 in the IGBT region 10 can be reduced. + This can suppress the flow of current through the cathode layer 26. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 or 101, which is an RC-IGBT, the distance U1 may be zero or less than 100 μm.

[0086] As shown in Figure 12, the first dislocation 200 may also be placed at the boundary between the IGBT region 10 and the diode region 20, which includes the region corresponding to distance U1 (the region where the p-type collector layer 16 extends beyond the IGBT region 10). In this case, the recovery withstand capability can be increased by capturing minority carriers (holes in this case) when the diode is off. Here, the boundary between the IGBT region 10 and the diode region 20 refers to the region to which the minority carriers of the diode reach when it is turned off, and may be wider than, for example, distance U1. More quantitatively, the IGBT region 10 and the diode region 20 refer to the region within ±100 μm from the edge of the p-type collector layer 16.

[0087] (6) Structure of the terminal region 30 Figures 13 and 14 are cross-sectional views showing the configuration of the termination region of a semiconductor device that is an RC-IGBT. Figure 13 is a cross-sectional view along the dashed line EE in Figure 4 or Figure 5, showing the cross-section from the IGBT region 10 to the termination region 30. Figure 14 is a cross-sectional view along the dashed line FF in Figure 4, showing the cross-sectional view from the diode region 20 to the termination region 30.

[0088] As shown in Figures 13 and 14, the termination region 30 of the semiconductor device 100 is between the first main surface and the second main surface of the semiconductor substrate n - It has a type drift layer 1. The first main surface and the second main surface of the termination region 30 are the same as the first main surface and the second main surface of the IGBT region 10 and the diode region 20, respectively. - The drift layer 1 consists of n of the IGBT region 10 and the diode region 20, respectively. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0089] n - The first main surface side of the drift layer 1, that is, the first main surface of the semiconductor substrate and n - A p-type termination well layer 31 is provided between the p-type drift layer 1 and the other layer. The p-type termination well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm³. 3 ~1.0E+19 / cm 3 The p-type termination well layer 31 is provided surrounding the cell region which includes the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in multiple ring shapes, and the number of p-type termination well layers 31 is appropriately selected according to the breakdown voltage design of the semiconductor device 100 or semiconductor device 101. Furthermore, on the outer edge side of the p-type termination well layer 31, n + A channel stopper layer 32 is provided, n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31.

[0090] In the termination region 30, a termination dummy trench gate 35 is provided within a p-type termination well layer 31. The termination dummy trench gate 35 is constructed by providing a termination dummy trench electrode 35a within a trench formed in the semiconductor substrate via a termination dummy trench insulating film 35b.

[0091] n -A p-type termination collector layer 16a is provided between the p-type drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed integrally with the p-type collector layer 16 provided in the cell region. Therefore, the p-type termination collector layer 16a may also be included in the term p-type collector layer 16. Furthermore, in a configuration where the diode region 20 is adjacent to the termination region 30, as shown in Figure 4, the p-type termination collector layer 16a is provided with its end on the diode region 20 side extending into the diode region 20 by a distance U2, as shown in Figure 14. By providing the p-type termination collector layer 16a extending into the diode region 20 in this way, the n of the diode region 20 is... + The distance between the p-type cathode layer 26 and the p-type termination well layer 31 can be increased, thereby suppressing the p-type termination well layer 31 from acting as the anode of the diode. The distance U2 may be, for example, 100 μm.

[0092] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is formed integrally and continuously from the cell region, which includes the IGBT region 10 and the diode region 20, to the termination region 30. On the other hand, on the first main surface of the semiconductor substrate in the termination region 30, an emitter electrode 6 that is continuous with the cell region and a termination electrode 6a that is separated from the emitter electrode 6 are provided.

[0093] The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating silicon nitride). The termination electrode 6a and the p-type termination well layer 31 and n + The channel stopper layer 32 is electrically connected to the terminal region 30 via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the terminal region 30. Furthermore, a terminal protection film 34 is provided in the terminal region 30, covering the emitter electrode 6, the terminal electrode 6a, and the semi-insulating film 33. The terminal protection film 34 may be made of, for example, polyimide. Alternatively, the semi-insulating film 33 may be omitted, and the terminal protection film 34 may be formed directly.

[0094] In Figures 13 and 14, the p-type termination well layer 31 is formed in a region closer to the second main surface than the active trench gate 11, dummy trench gate 12, or termination dummy trench gate 35. However, the p-type termination well layer 31 may be formed at a position further from the second main surface than the active trench gate 11, dummy trench gate 12, or termination dummy trench gate 35. In other words, the p-type termination well layer 31 may be shallower than the active trench gate 11, dummy trench gate 12, or termination dummy trench gate 35. However, if the p-type termination well layer 31 is shallower than the termination dummy trench gate 35, the electric field strength on the second main surface side of the termination dummy trench gate 35 will be stronger. To suppress this, the termination dummy trench gate 35 may be formed shallower than the active trench gate 11 or dummy trench gate 12.

[0095] The number of terminal dummy trench gates 35 does not have to be one; it may be between one and ten. If there are multiple terminal dummy trench gates 35, the depth of the multiple terminal dummy trench gates 35 may be gradually reduced in the outward direction (from the cell region to the terminal region) in order to gradually reduce the electric field strength when the device is off. In other words, the terminal dummy trench gates 35 located further outward may be shallower. It is desirable not to place the second dislocation 201 in the terminal dummy trench gates 35 or the terminal region 30.

[0096] [Manufacturing method common to the embodiments] Figures 15 to 26 show the manufacturing method for a semiconductor device that is an RC-IGBT. Figures 15 to 22 show the process of forming the front side of the semiconductor device 100 or semiconductor device 101, and Figures 23 to 26 show the process of forming the back side of the semiconductor device 100 or semiconductor device 101.

[0097] First, as shown in Figure 15, n -Prepare the semiconductor substrate that constitutes the n-type drift layer 1. The semiconductor substrate may be, for example, a so-called FZ wafer fabricated by the FZ (Floating Zone) method or a so-called MCZ wafer fabricated by the MCZ (Magnetic applied CZochralki) method, and may be an n-type wafer containing n-type impurities. The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device to be fabricated. For example, in a semiconductor device with a breakdown voltage of 1200V, the n-type impurities constituting the semiconductor substrate are used. - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is approximately 40-120 Ω·cm. Depending on the semiconductor substrate manufacturing method, various impurities such as phosphorus, arsenic, nitrogen, boron, oxygen, and carbon may be present, but this is not a problem as long as the resistivity is adjusted to obtain the desired breakdown voltage. Alternatively, composite defects involving each impurity element, interstitial silicon, and atomic vacancies may be used to adjust the resistivity. As shown in Figure 15, in the process of preparing the semiconductor substrate, the entire semiconductor substrate is n-type. - Although it is a type drift layer 1, p-type or n-type impurity ions are implanted from the first main surface side or the second main surface side of such a semiconductor substrate, and then diffused into the semiconductor substrate by heat treatment or the like to form a p-type or n-type semiconductor layer, thereby manufacturing the semiconductor device 100 or semiconductor device 101.

[0098] As shown in Figure 15, n -The semiconductor substrate constituting the type drift layer 1 includes regions that will become IGBT regions 10 and diode regions 20. Although not shown, the region surrounding the IGBT regions 10 and diode regions 20 also includes a region that will become a termination region 30. The following description will primarily focus on the manufacturing method for the IGBT regions 10 and diode regions 20 of the semiconductor device 100 or 101, but the termination region 30 of the semiconductor device 100 or 101 may be manufactured by a well-known manufacturing method. For example, when forming an FLR having a p-type termination well layer 31 as a voltage-resistant holding structure in the termination region 30, p-type impurity ions may be implanted before processing the IGBT regions 10 and diode regions 20 of the semiconductor device 100 or 101, or p-type impurity ions may be implanted simultaneously when ion-implanting p-type impurities into the IGBT regions 10 or diode regions 20 of the semiconductor device 100.

[0099] Next, as shown in Figure 16, n-type impurities such as phosphorus (P) are implanted from the first main surface side of the semiconductor substrate to form an n-type carrier storage layer 2. Additionally, p-type impurities such as boron (B) are implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier storage layer 2, p-type base layer 15, and p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions through heat treatment. Since the n-type and p-type impurities are ion-implanted after a masking process on the first main surface of the semiconductor substrate, they are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier storage layer 2, p-type base layer 15, and p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type termination well layer 31 in the termination region 30. Mask processing refers to the process of forming a mask on a semiconductor substrate by applying a resist to the substrate, creating openings in predetermined areas of the resist using photolithography technology, and then performing ion implantation or etching on predetermined areas of the semiconductor substrate through these openings.

[0100] The p-type base layer 15 and the p-type anode layer 25 may be formed by simultaneously implanting p-type impurities into them using ion implantation. In this case, the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 will be the same, resulting in identical configurations. Alternatively, by separately implanting p-type impurities into the p-type base layer 15 and the p-type anode layer 25 using a masking process, the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 may be made different.

[0101] Furthermore, the p-type terminal well layer 31 formed in a different cross-section may be formed by ion implanting p-type impurities simultaneously with the p-type anode layer 25. In this case, the depth and p-type impurity concentration of the p-type terminal well layer 31 and the p-type anode layer 25 will be the same, making it possible to have the same configuration. Alternatively, the p-type terminal well layer 31 and the p-type anode layer 25 can be formed by ion implanting p-type impurities simultaneously, resulting in different p-type impurity concentrations in the p-type terminal well layer 31 and the p-type anode layer 25. In this case, the aperture ratio can be changed by using a mesh-like mask for one or both of the masks.

[0102] Furthermore, by separately ion implanting the p-type terminal well layer 31 and the p-type anode layer 25 through masking, the depths and p-type impurity concentrations of the p-type terminal well layer 31 and the p-type anode layer 25 may be made different.

[0103] The p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be formed by simultaneous ion implantation.

[0104] Next, as shown in Figure 17, n-type impurities are selectively injected into the first main surface side of the p-type base layer 15 of the IGBT region 10 by masking. + A p-type source layer 13 is formed. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Alternatively, by masking, p-type impurities can be selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10. + A type contact layer 14 is formed, and p-type impurities are selectively injected into the first main surface side of the p-type anode layer 25 of the diode region 20. +A p-type anode contact layer 24 is formed. The p-type impurity to be implanted may be, for example, boron (B) or aluminum (Al).

[0105] n + Type source layer 13 or p + The contact layer 14 has a high impurity concentration, so the implantation dose in ion implantation is generally high. When ion implantation is performed with a high dose, the region through which the implanted element passes has a high defect density, and under certain conditions, crystallinity is lost and it becomes amorphous. The implanted region or amorphous layer with a high defect density is generally improved by annealing treatment aimed at activating the implanted impurities. However, it is not necessary to return to a region with a low defect density like the unimplanted state, and defects may be left as long as they do not affect the electrical properties. The remaining defect region generally contains silicon atomic vacancies, interstitial silicon atoms, composites of silicon atomic vacancies and interstitial silicon, and dislocations whose crystal planes are not aligned. It is difficult to observe fine point defects such as atomic vacancies and interstitial atoms, but dislocations can be easily observed using commonly used methods (e.g., scanning tunneling microscope: STM), and are well known as the first dislocation 200. The first dislocation 200 is shown in n from Figures 17 to 26. + Type source layer 13, p + Type contact layer 14, p + Although present in all regions of the type anode contact layer 24, it is not shown in the diagram.

[0106] Next, as shown in Figure 18, the p-type base layer 15 and the p-type anode layer 25 are penetrated from the first main surface side of the semiconductor substrate, n - A trench 8 is formed that reaches the drift layer 1. In the IGBT region 10, n + The trench 8 that penetrates the mold source layer 13 has side walls n +It constitutes a part of the mold source layer 13. The trenches 8 may be formed by depositing an oxide film such as SiO2 on a semiconductor substrate, then creating openings in the oxide film in the area where the trenches 8 will be formed by a masking process, and finally etching the semiconductor substrate using the oxide film with the openings as a mask. In Figure 18, the pitch of the trenches 8 is the same in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. Furthermore, for stress design, areas with a different pitch of trenches 8 may be provided within the IGBT region 10, and areas with a different pitch of trenches 8 may also be provided within the diode region 20, and the depth of the trenches 8 may also be designed arbitrarily. The pitch of the trenches 8 can be appropriately changed by the mask pattern of the masking process. In addition, a microloading effect in which the trench depth changes according to the mask pattern may be used.

[0107] Next, as shown in Figure 19, the semiconductor substrate is heated in an oxygen-containing atmosphere to form an oxide film 9 on the inner walls of the trenches 8 and on the first main surface of the semiconductor substrate. Of the oxide films 9 formed on the inner walls of the trenches 8, the oxide film 9 formed in the trenches 8 of the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. The oxide film 9 formed in the trenches 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed in the trenches 8 of the termination region 30 is the termination dummy trench insulating film 35b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later process.

[0108] Next, as shown in Figure 20, polysilicon doped with n-type or p-type impurities is deposited in the trench 8, on which an oxide film 9 is formed on the inner wall, by CVD (chemical vapor deposition) or the like, to form a gate trench electrode 11a, a dummy trench electrode 12a, a diode trench electrode 21a, and a terminal dummy trench electrode 35a. This forms an active trench gate 11, a dummy trench gate 12, a diode trench gate 21, and a terminal dummy trench gate 35.

[0109] In the process of forming the active trench gate 11, dummy trench gate 12, diode trench gate 21 and termination dummy trench gate 35 (hereinafter collectively referred to as "trench gates"), n including a mesa region - The stress within the drift layer 1 is controlled. To increase the stress, for example, the trench gate is deepened, the trench pitch is narrowed, the oxide film 9 which becomes the gate trench insulating film 11b, the dummy trench insulating film 12b, the diode trench insulating film 21b, and the terminal dummy trench insulating film 35b is made thicker, the trench gate is made into a two-stage gate structure, and in the two-stage gate structure n - Setting design parameters such as increasing the thickness of the oxide film in contact with the drift layer 1 is effective. - The stress within the drift layer 1 can be easily measured by methods such as TEM analysis and focused electron diffraction (CBED). The designer can place the second dislocation 201 at an arbitrary location, including the mesa region n - Control the stress within the drift layer 1.

[0110] Next, as shown in Figure 21, an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 of the IGBT region 10, and then the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 may be, for example, SiO2. Then, contact holes are formed in the deposited interlayer insulating film 4 by masking. The contact holes are n + On type source layer 13, p + On the type contact layer 14, p+ It is formed on the type anode contact layer 24, on the dummy trench electrode 12a, and on the diode trench electrode 21a.

[0111] After forming the interlayer insulating film 4, heat treatment may be applied. The heat treatment is performed to ensure the thermal stability of the interlayer insulating film 4, as well as to control the stress n - This can be used to power the placement of the second dislocation 201 in the drift layer 1. The first dislocation 200 formed on the first main surface side by high dose injection is n - The stress and thermal energy within the drift layer 1 can be used as a driving force to be positioned at any location. This arbitrary location is a region different from the first dislocation 200, specifically n + Type source layer 13, p + Type contact layer 14, p + It is on the second main surface side of the type anode contact layer 24. The effects of placing the second dislocation 201 in the semiconductor device are as described above. Here, the second dislocation 201 formed by this method has a total length L1 longer than the mesa width W1, is curved, and has a convex shape toward the second main surface. By making the total length L1 of the second dislocation 201 longer than the mesa width W1, the carrier trapping effect can be enhanced. Also, by making the second dislocation 201 convex toward the second main surface, n - The effectiveness of capturing carriers in drift layer 1 increases.

[0112] n - The technique of positioning the second dislocation 201 at an arbitrary location by controlling the stress within the drift layer 1 is previously unknown. Compared to conventional lifetime reduction methods such as irradiation with charged particles, this method has the advantage of not requiring additional effort for lifetime control and allowing the formation of a lifetime reduction region at any location by considering stress during the design phase.

[0113] Next, as shown in Figure 22, a barrier metal 5 is formed on the first main surface and interlayer insulating film 4 of the semiconductor substrate, and then an emitter electrode 6 is formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by PDV (physical vapor deposition) or CVD.

[0114] The emitter electrode 6 may be formed by depositing an aluminum-silicon alloy (Al-Si alloy) or a material composed mainly of copper onto the barrier metal 5, for example, by PVD such as sputtering or vapor deposition. Alternatively, a nickel alloy (Ni alloy) may be further formed on the formed aluminum-silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. Forming the emitter electrode 6 by plating allows for the easy formation of a thick metal film, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. When forming the emitter electrode 6 from an aluminum-silicon alloy by PVD and then further forming a nickel alloy by plating, the plating process for forming the nickel alloy may be performed after processing the second main surface side of the semiconductor substrate.

[0115] Next, as shown in Figure 23, the second main surface of the semiconductor substrate is ground to thin the semiconductor substrate to the designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 60 μm to 200 μm.

[0116] Next, as shown in Figure 24, n-type impurities are injected from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are injected from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or it may be formed only in the IGBT region 10 or the diode region 20.

[0117] The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) ions. Alternatively, it may be formed by implanting protons (H+). Furthermore, it may be formed by implanting both protons and phosphorus. Protons can be implanted to a deep position from the second main surface of the semiconductor substrate with relatively low acceleration energy. Also, the depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. For this reason, when forming the n-type buffer layer 3 with protons, if multiple implantations are performed while changing the acceleration energy, it is possible to form an n-type buffer layer 3 that is wider in the thickness direction of the semiconductor substrate than when formed with phosphorus.

[0118] Furthermore, since phosphorus can have a higher activation rate as an n-type impurity compared to protons, forming an n-type buffer layer 3 with phosphorus can more reliably suppress punch-through of the depletion layer even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, in which case the protons are implanted at a deeper position from the second main surface than the phosphorus.

[0119] The p-type collector layer 16 may be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, the implanted boron is activated and the p-type collector layer 16 is formed by irradiating the second main surface with a laser and performing laser annealing. At this time, phosphorus for the n-type buffer layer 3, which is implanted at a relatively shallow position from the second main surface of the semiconductor substrate, is also activated simultaneously. On the other hand, since protons are activated at relatively low annealing temperatures of 350°C to 500°C, care must be taken to ensure that the entire semiconductor substrate does not exceed 350°C to 500°C after proton implantation, except for the proton activation process. Laser annealing can raise the temperature only near the second main surface of the semiconductor substrate, so it can be used to activate n-type and p-type impurities even after proton implantation.

[0120] Next, as shown in Figure 25, n in the diode region 20 + A type cathode layer 26 is formed. + The p-type cathode layer 26 may be formed, for example, by injecting phosphorus (P). As shown in Figure 25, a p-type collector layer 16 and n-type cathode layer 26 are formed at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 towards the diode region 20. + Phosphorus is selectively injected from the second main surface side by masking so that the boundary with the type cathode layer 26 is located. + The amount of n-type impurities injected to form the n-type cathode layer 26 is greater than the amount of p-type impurities injected to form the p-type collector layer 16. In Figure 25, the p-type collector layer 16 and n-type impurities from the second main surface are shown. + The depth of the type cathode layer 26 is shown to be the same, but n + The depth of the p-type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16. + The region where the p-type cathode layer 26 is formed requires the injection of n-type impurities into the region where p-type impurities have been implanted to create an n-type semiconductor, therefore, n + In all regions where the type cathode layer 26 is formed, the concentration of implanted p-type impurities is made higher than the concentration of n-type impurities.

[0121] Next, as shown in Figure 26, a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the IGBT region 10, the diode region 20, and the termination region 30 of the second main surface. Alternatively, the collector electrode 7 may be formed over the entire surface of the second main surface of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing aluminum-silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or vapor deposition, or by layering multiple metals such as aluminum-silicon alloy, titanium, nickel, or gold. Furthermore, a metal film may be formed on the metal film formed by PVD by electroless plating or electrolytic plating to form the collector electrode 7.

[0122] The semiconductor device 100 or semiconductor device 101 is manufactured through the process described above. Since multiple semiconductor devices 100 or semiconductor device 101 are manufactured in a matrix on a single n-type wafer, the semiconductor device 100 or semiconductor device 101 is completed by cutting them into individual semiconductor devices 100 or semiconductor device 101 using laser dicing or blade dicing.

[0123] Here, before the formation of the trench gate, n + Type source layer 13 and p + Type contact layer 14 and p + A type anode contact layer 24 was formed, but after the formation of the trench gate, n + Type source layer 13 or p + Type contact layer 14 or p + A type anode contact layer 24 may be formed after the formation of the trench gate. + Type source layer 13 or p + Type contact layer 14 or p + It is well known that even when a type anode contact layer 24 is formed, a first dislocation 200 is formed by high-dose injection and annealing treatment. However, n - It has not been previously known that the second dislocation 201 can be positioned at an arbitrary location by controlling the stress within the drift layer 1.

[0124] [Embodiment 1] In Embodiment 1, the second dislocation 201 is applied to an IGBT in the IGBT region 10, which is a bipolar device (bipolar semiconductor element) having a trench. Here, an IGBT constituting an RC-IGBT is used as an example, but the bipolar device to which the second dislocation 201 is applied may be a single IGBT or other bipolar devices. Furthermore, in the following, since the lifetime of the semiconductor substrate is long, the effects will be explained using a semiconductor device made of a semiconductor substrate mainly composed of silicon as an example. However, semiconductor substrates mainly composed of silicon carbide, gallium nitride, gallium oxide, diamond, etc. may be used if similar effects can be achieved.

[0125] Figures 27 to 29 show an example of the configuration of a semiconductor device according to Embodiment 1. Figures 27 to 29 show a simplified and combined structure of the IGBT region 10 shown in Figures 7 and 8.

[0126] Figure 27 shows the second dislocation 201, n + Type source layer 13 or p + This is an example where the second dislocation is placed in the p-type base layer 15 at a deeper position (on the second main surface side) than the type contact layer 14. The second dislocation 201 may be curved, or it may have a convex shape on the second main surface side, on the semiconductor substrate. <110> Direction and <100> It may have components in both directions. The second dislocation 201 is n - By placing it near the drift layer 1, the carrier lifetime can be locally reduced, improving switching losses.

[0127] Furthermore, the total length L1 of the second dislocation 201 is preferably longer than the mesa width W1 in order to enhance the effect of reducing carrier lifetime. As a method to ensure the total length L1 of the second dislocation 201, the dislocation may be curved. In this case, the second dislocation 201 is located on the semiconductor substrate. <100> and <110> Having a directional component is not a problem. Also, in order to reduce the carrier lifetime on the second principal surface side compared to the mesa region, the second dislocation 201 may be made convex toward the second principal surface.

[0128] Figure 28 shows an example in which the second dislocation 201 is located within the n-type carrier storage layer 2. That is, the second dislocation 201 is located at a position deeper than the p-type base layer 15, or at a position deeper than the interface between the p-type base layer 15 and the n-type carrier storage layer 2.

[0129] As shown in Figure 27, when the second dislocation 201 is placed in the p-type base layer 15, the second dislocation 201 has a different band gap and Fermi level than a perfect crystal, causing the threshold voltage for channel formation to fluctuate locally. Also, since the second dislocation 201 is a disorder of crystallinity, the channel mobility may decrease. To form a carrier lifetime reduction region while avoiding these issues, it is desirable to place the second dislocation 201 at a position deeper than the p-type base layer 15, as shown in Figure 28. "A position deeper than the p-type base layer 15" means n in a plan view. + This refers to a position deeper than the point where the net carrier concentration in the depth direction toward the second main surface reverses from n-type to p-type within the same region as the type source layer 13. In other words, it refers to the end of the region formed by the inversion layer when a voltage higher than the threshold voltage is applied to the gate, on the second main surface side.

[0130] Furthermore, since the electric field strength is high at the interface between the p-type base layer 15 and the n-type carrier storage layer 2 when the system is off, placing the second dislocation 201 at that location increases the leakage current. Therefore, in order to suppress the increase in leakage current while forming a carrier lifetime reduction region, it is desirable to place the second dislocation 201 at a position deeper than the interface between the p-type base layer 15 and the n-type carrier storage layer 2.

[0131] Figure 29 shows an example in which at least a portion of the second dislocation 201 is located deeper than the bottom of the active trench gate 11. When the second dislocation 201 is located deeper than the active trench gate 11, n - Since the carrier lifetime reduction region can be expanded even in the deep regions of the drift layer 1, the effect of reducing switching losses is increased.

[0132] [Embodiment 2] In Embodiment 2, the second dislocation 201 is applied to the diode in the diode region 20, which is a bipolar device having a trench. Here, a diode constituting an RC-IGBT is used as an example, but the bipolar device to which the second dislocation 201 is applied may be a single diode or any other bipolar device.

[0133] Figures 30 to 32 show an example of the configuration of a semiconductor device according to Embodiment 2. Figures 30 to 32 show a simplified and combined structure of the diode region 20 shown in Figures 10 and 11.

[0134] Figure 30 shows at least a portion of the second dislocation 201, p + This is an example in which the second dislocation 201 is located in the p-type anode layer 25, which is deeper than the p-type anode contact layer 24. By placing the second dislocation 201 in the diode region 20, recovery loss can be reduced. The second dislocation 201 is n - By placing the n-type drift layer 1 or the n-type carrier storage layer 2 in a region closer to it, it is expected that the amount of holes supplied during forward operation will be reduced, and hole discharge during off-mode will be promoted, thereby reducing recovery losses.

[0135] Figure 31 shows an example in which at least a portion of the second dislocation 201 is placed in the n-type carrier storage layer 2. That is, at least a portion of the second dislocation 201 is placed in the p-type anode layer 25 and n - It is located deeper than the interface with the type drift layer 1. p-type anode layer 25 and n - The interface with the p-type drift layer 1 has a high electric field strength when off, so placing the second dislocation 201 at that location increases the leakage current. Therefore, in order to form a carrier lifetime reduction region while avoiding an increase in leakage current, the second dislocation 201 is placed between the p-type anode layer 25 and n-type anode layer 25. - It is desirable to position it at a depth deeper than the interface with the mold drift layer 1.

[0136] Figure 32 shows an example in which at least a portion of the second dislocation 201 is located deeper than the diode trench gate 21. By positioning at least a portion of the second dislocation 201 on the second main surface side of the diode trench gate 21, n - In the region on the second main surface side of the drift layer 1, the carrier lifetime reduction area can also be expanded, thereby reducing recovery loss.

[0137] [Embodiment 3] Embodiments 1 and 2 show examples in which the second dislocation 201 is uniformly arranged in the left-right direction of the IGBT region 10, but Embodiment 3 shows an example in which the second dislocation 201 is partially arranged. In other words, Embodiment 3 shows an example of the arrangement of the second dislocation 201 in a plan view.

[0138] Figures 33 to 35 show examples of the configuration of a semiconductor device according to Embodiment 3. Figures 33 and 34 are simplified and combined versions of the structures shown in Figure 7 or Figure 8, and Figure 35 is a simplified and combined version of the structure shown in Figure 13.

[0139] Figure 33 shows the second dislocation 201, n + This is an example where it is placed below the type source layer 13. That is, the second dislocation 201 is n in plan view. + It is located in at least a portion of the formation region of the type source layer 13. The second dislocation 201 is n + By being positioned below the type source layer 13, n during turn-off + The discharge of holes directly beneath the mold source layer 13 is promoted, and latch-up can be suppressed. As a result, the break-off withstand capability of the semiconductor device is improved.

[0140] Figure 34 shows the second dislocation 201, p + This is an example where it is placed below the type contact layer 14. That is, the second dislocation 201 is p in plan view. + It is located in at least a portion of the formation region of the type contact layer 14. The second dislocation 201 is p + By being positioned below the type contact layer 14, the amount of holes injected during conduction is limited, and the amount of holes discharged is reduced, thereby reducing turn-off losses.

[0141] Figure 35 shows an example where the second dislocation 201 is not placed in the terminal region 30. That is, the second dislocation 201 is located in a region other than the terminal region 30. The second dislocation 201 is placed at the boundary between the IGBT region 10 and the terminal region 30.

[0142] In the termination region 30, the electric field strength is high when the device is off, so placing the second dislocation 201 in the termination region 30 increases the leakage current. Also, reducing the carrier lifetime in the termination region 30 has little effect on switching loss or breakthrough strength. Therefore, there is little benefit in placing the second dislocation 201 in the termination region 30, and it is not necessary to intentionally place the second dislocation 201 in the termination region 30; it is preferable not to place the second dislocation 201 in the termination region 30.

[0143] Furthermore, in Figure 35, multiple terminal dummy trench gates 35 are provided in the terminal region 30, and the depth of the multiple terminal dummy trench gates 35 gradually decreases in the direction toward the outside (from the cell region toward the terminal region). In other words, the terminal dummy trench gates 35 located further outward are shallower. In this case, the design is often such that the electric field strength on the second main surface side of the terminal dummy trench gate 35 is high, so it is more desirable not to place the second dislocation 201 in the terminal region 30.

[0144] On the other hand, it is desirable to place a second dislocation 201 at the boundary between the IGBT region 10 and the termination region 30. By doing so, it is possible to promote hole discharge when the device is off without changing the amount of hole injected when the device is conducting, thereby improving the breakthrough strength of the semiconductor device.

[0145] [Embodiment 4] Figures 36 and 37 show an example configuration of a semiconductor device according to Embodiment 4. Figures 36 and 37 are simplified and combined versions of the structure shown in Figure 12.

[0146] Figure 36 shows an example in which at least some of the second dislocations 201 are located in the boundary region between the IGBT region 10 and the diode region 20. Furthermore, at least a portion of the diode region 20 has a region where the density of the second dislocations 201 is greater than the density of the second dislocations 201 in the IGBT region 10. Also, in the diode region 20, in a plan view, p + The density of the second dislocation 201 in the formation region of the type anode contact layer 24 is p+ The density of the second dislocation 201 is greater than that of the region without the type anode contact layer 24.

[0147] When the diode is off, some of the holes reach the IGBT region 10, and p + It is discharged through the type contact layer 14. Therefore, n + Holes may accumulate near the type source layer 13, potentially causing latch-up. As shown in Figure 36, the break-off strength can be increased by placing a second dislocation 201 in the boundary region between the IGBT region 10 and the diode region 20. If you want to actively improve the diode's recovery loss and break-off strength, it is preferable to place the second dislocation 201 at a higher density in the diode region 20 than in the IGBT region 10.

[0148] In the diode region 20, p + The region where the type anode contact layer 24 is located, and p + There are regions where the type anode contact layer 24 is not placed. Of these, p + In order to suppress the amount of holes supplied from the type anode contact layer 24, in plan view, p + The density of the second dislocation 201 in the region overlapping with the type anode contact layer 24 is expressed in plan view as p + It is desirable to make the density greater than that of the second dislocation 201 in the region that does not overlap with the type anode contact layer 24. + By suppressing the amount of holes supplied from the type anode contact layer 24, recovery losses can be reduced. Here, the density of the second dislocation 201 does not necessarily refer to the density across the entire region. In practice, it is assumed that the density of the second dislocation 201 will be compared within the region observable in the TEM analysis cross-section.

[0149] Figure 37 shows an example in which at least a portion of the diode region 20 contains a region where the density of second dislocations 201 is lower than that of second dislocations 201 in the IGBT region 10. If you want to actively improve the turn-off loss and break-off strength of the IGBT, it is advisable to arrange the second dislocations 201 at a higher density in the IGBT region 10 than in the diode region 20. Here again, the density of second dislocations 201 does not necessarily refer to the density of each region as a whole. In practice, it is assumed that the density of second dislocations 201 will be compared within the region that can be observed in the TEM analysis cross-section.

[0150] [Embodiment 5] Figure 38 shows an example of the configuration of a semiconductor device according to Embodiment 5. Figure 38 is a simplified and combined version of the structures shown in Figures 7 and 8.

[0151] Figure 38 shows an example in which an active trench gate 11 and a dummy trench gate 12 are placed in the IGBT region 10. At least some of the second dislocations 201 are placed in contact with the dummy trench gate 12.

[0152] By utilizing the dummy trench gate 12, the disadvantages of placing the second dislocation 201 can be suppressed. The second dislocation 201 increases the hole discharge rate by reducing the carrier lifetime, which has the effect of increasing the breakout withstand capability and reducing switching losses. On the other hand, it also has the disadvantage of reducing the amount of holes when the device is ON and increasing the ON voltage. As shown in Figure 38, when the second dislocation 201 is placed around the dummy trench gate 12, no channel is formed on the side of the dummy trench gate 12, and no current flows in that part, so even if the carrier lifetime is reduced, the ON voltage does not increase. In addition, the effect of hole capture when the device is OFF can be expected, so the trade-off between ON voltage and switching losses can be improved.

[0153] Furthermore, if the second dislocation 201 comes into contact with the active trench gate 11, which has a gate potential, the electric field at the point of contact with the gate trench insulating film 11b may become stronger, raising concerns about a deterioration in gate reliability. Therefore, it is preferable for the second dislocation 201 to come into contact with the dummy trench gate 12 rather than the active trench gate 11. Here, "contact" refers to a substantially connected state as determined by analytical methods such as TEM.

[0154] [Embodiment 6] Figures 39 to 41 show an example of the configuration of a semiconductor device according to Embodiment 6. Figures 39 to 41 are simplified and combined versions of the structures shown in Figures 7 and 8. However, a two-stage trench gate 36 having a two-stage gate structure is provided instead of the active trench gate 11.

[0155] The configuration shown in Figure 39 is the same as the configuration of Embodiment 1 (Figure 27), but with a two-stage trench gate 36 instead of the active trench gate 11. The two-stage trench gate 36 is constructed by embedding a lower gate trench electrode 36c in the lower part (second main surface side) of the trench formed in the semiconductor substrate via a lower gate trench insulating film 36d, and embedding an upper gate trench electrode 36a in the upper part (first main surface side) of the trench via an upper gate trench insulating film 36b. The upper gate trench insulating film 36b and the upper gate trench electrode 36a are insulated by an intermediate insulating film 36e, and the upper gate trench electrode 36a and the upper gate trench insulating film 36b can be set to different potentials. In this embodiment, the upper gate trench electrode 36a is set to the gate potential, and the lower gate trench electrode 36c is set to the emitter potential. That is, the lower gate trench electrode 36c is electrically connected to the emitter electrode 6.

[0156] By using the two-stage trench gate 36 with a two-stage gate structure, compared to using the active trench gate 11 with a single-stage gate structure, n - This can increase the stress within the drift layer 1 and the second dislocation 201 -This makes it easier to place the drift layer 1.

[0157] Furthermore, in the configuration of Embodiment 1 (Figure 27), n - When stress control within the drift layer 1 is performed by changing the thickness of the gate trench insulating film 11b of the active trench gate 11, important electrical characteristics such as the threshold voltage fluctuate. In contrast, in the configuration of Embodiment 6 (Figure 39), if the lower gate trench electrode 36c is set to the emitter potential, n - Even if stress control within the drift layer 1 is performed by changing the thickness of the lower gate trench insulating film 36d of the two-stage trench gate 36, important electrical characteristics such as the threshold voltage do not change. Therefore, according to this embodiment, the thickness of the lower gate trench insulating film 36d can be designed as an independent parameter for stress control.

[0158] Figure 40 shows an example in which the second dislocation 201 is positioned in contact with the lower gate trench insulating film 36d. Furthermore, the lower gate trench insulating film 36d is thicker than the upper gate trench insulating film 36b. Also, the second dislocation 201 is not positioned at the boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d (the boundary between the upper gate trench electrode 36a and the lower gate trench electrode 36c).

[0159] If the second dislocation 201 comes into contact with the upper gate trench insulating film 36b, which controls the potential for channel formation, there is a concern that the gate electric field will become locally high at the contact point, reducing gate reliability. For this reason, it is desirable for the second dislocation 201 to come into contact with the lower gate trench insulating film 36d. Furthermore, by increasing the thickness of the lower gate trench insulating film 36d, n - The stress in the drift layer 1 can be increased.

[0160] Furthermore, by bringing the second dislocation 201 into contact with the thickly designed lower gate trench insulating film 36d, the degradation of gate reliability can be suppressed when the lower gate trench electrode 36c is not set to the emitter potential. Also, if the second dislocation 201 is placed at the boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d, the mechanical fragility of the boundary increases, raising concerns about reliability degradation, such as fracture when external stress is applied.

[0161] Figure 41 shows an example in which at least some of the second dislocations 201 are in contact with the boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d. The boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d is a region with high stress and is thermally unstable. Therefore, when external stress is applied that causes dislocations to move, the second dislocations 201 are likely to move to the boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d. Since the movement of the second dislocations 201 may cause changes in electrical properties, by pre-positioning the second dislocations 201 at the boundary between the upper gate trench insulating film 36b and the lower gate trench insulating film 36d, it is possible to suppress changes in electrical properties when external stress is applied during thermal cycle tests, etc.

[0162] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0163] <Note> The various aspects of this disclosure are summarized below as an appendix.

[0164] (Note 1) A semiconductor substrate having a first main surface and a second main surface, on which a first conductivity type drift layer is formed, A plurality of trenches formed on the first main surface of the semiconductor substrate, An electrode embedded in the trench via an insulating film, The mesa region, which is the region between the trenches in the semiconductor substrate, A first conductivity type source layer or a second conductivity type contact layer formed on the surface layer of the first main surface side of the mesa region, It comprises a bipolar semiconductor device having, In the mesa region, at a position on the second main surface side of the source layer or the contact layer, there is a dislocation having a total length longer than the width of the mesa region, Semiconductor equipment.

[0165] (Note 2) The dislocation has a curved shape, The semiconductor device described in Appendix 1.

[0166] (Note 3) The dislocation is curved so as to be convex toward the second main surface. Semiconductor device as described in Appendix 2.

[0167] (Note 4) The dislocation is of the semiconductor substrate <110> Directional components and <100> Having a directional component, A semiconductor device as described in any one of the appendices 1 through 3.

[0168] (Note 5) The main constituent element of the aforementioned semiconductor substrate is silicon. A semiconductor device as described in any one of the appendices 1 through 4.

[0169] (Note 6) The aforementioned bipolar semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting IGBT) which includes an IGBT and a diode. A semiconductor device as described in any one of the appendices 1 through 5.

[0170] (Note 7) The source layer or the contact layer is disposed on the surface layer of the second conductive base layer formed on the surface layer of the first main surface side of the mesa region. The dislocation is disposed on the second main surface side with respect to the base layer. The semiconductor device according to Supplementary Note 6.

[0171] (Supplementary Note 8) Further comprising a carrier accumulation layer formed on the second main surface side of the base layer, The dislocation is disposed on the second main surface side with respect to the interface between the base layer and the carrier accumulation layer. The semiconductor device according to Supplementary Note 7.

[0172] (Supplementary Note 9) At least a part of the dislocation is located on the second main surface side with respect to the bottom of the trench. The semiconductor device according to Supplementary Note 6.

[0173] (Supplementary Note 10) The dislocation overlaps at least a part of the source layer in plan view. The semiconductor device according to Supplementary Note 6.

[0174] (Supplementary Note 11) The dislocation overlaps at least a part of the contact layer in plan view. The semiconductor device according to Supplementary Note 6.

[0175] (Supplementary Note 12) Further comprising a termination region provided around the IGBT region where the IGBT is disposed, The dislocation is not disposed in the termination region. The semiconductor device according to Supplementary Note 6.

[0176] (Supplementary Note 13) [[ID=5​​​​​​​​​At least a portion of the dislocation is located in the boundary region between the IGBT region and the terminal region. Semiconductor device as described in Appendix 6.

[0178] (Note 15) A portion of the electrode embedded in the trench is a dummy trench electrode electrically connected to the emitter electrode. Semiconductor device as described in Appendix 6.

[0179] (Note 16) At least some of the dislocations are in contact with the trench in which the dummy trench electrode is embedded. Semiconductor device as described in Appendix 15.

[0180] (Note 17) The electrodes embedded in the trench are separated into an upper gate trench electrode located on the first main surface side and a lower gate trench electrode located on the second main surface side. The upper gate trench electrode and the lower gate trench electrode are insulated from each other by an intermediate insulating film. Semiconductor device as described in Appendix 6.

[0181] (Note 18) The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. At least some of the dislocations are in contact with the lower gate trench insulating film. Semiconductor device as described in Appendix 17.

[0182] (Note 19) The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. The lower gate trench insulating film is thicker than the upper gate trench insulating film. Semiconductor device as described in Appendix 17.

[0183] (Supplementary Note 20) At least a part of the dislocations is in contact with the lower gate trench insulating film. The semiconductor device according to Supplementary Note 19.

[0184] (Supplementary Note 21) The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. The dislocations are not in contact with the boundary portion between the upper gate trench insulating film and the lower gate trench insulating film. The semiconductor device according to Supplementary Note 17.

[0185] (Supplementary Note 22) The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. At least a part of the dislocations is in contact with the boundary portion between the upper gate trench insulating film and the lower gate trench insulating film. The semiconductor device according to Supplementary Note 17.

[0186] (Supplementary Note 23) The bipolar semiconductor element is a diode or an RC-IGBT (Reverse Conducting IGBT) including an IGBT (Insulated Gate Bipolar Transistor) and a diode. The semiconductor device according to any one of Supplementary Notes 1 to 5.

[0187] (Supplementary Note 24) The contact layer is disposed on the surface layer portion of the anode layer of the second conductivity type formed on the surface layer portion on the first main surface side of the mesa region. <000,09,93>At least a part of the dislocations is disposed in the anode layer. The semiconductor device according to Supplementary Note 23.

[0188] (Note 25) The contact layer is located on the surface of the second conductive anode layer formed on the surface of the first main surface side of the mesa region. At least a portion of the dislocations are located on the second principal surface side of the interface between the anode layer and the drift layer. Semiconductor device as described in Appendix 23.

[0189] (Note 26) At least a portion of the dislocation is located on the second main surface side of the trench bottom. Semiconductor device as described in Appendix 23.

[0190] (Note 27) The bipolar semiconductor device is the RC-IGBT, At least a portion of the dislocation is located at the boundary between the IGBT region where the IGBT is located and the diode region where the diode is located. Semiconductor device as described in Appendix 23.

[0191] (Note 28) The bipolar semiconductor device is the RC-IGBT, The dislocation is located in both the IGBT region where the IGBT is located and the diode region where the diode is located. A region is provided in at least a part of the IGBT region in which the dislocation density is greater than the dislocation density in the diode region. Semiconductor device as described in Appendix 23.

[0192] (Note 29) The bipolar semiconductor device is the RC-IGBT, The dislocation is located in both the IGBT region where the IGBT is located and the diode region where the diode is located. A region is provided in at least a part of the diode region in which the dislocation density is greater than the dislocation density in the IGBT region. Semiconductor device as described in Appendix 23.

[0193] (Note 30) The density of dislocations in the region overlapping with the contact layer in a plan view is greater than the density of dislocations in the region not overlapping with the contact layer in a plan view. Semiconductor device as described in Appendix 23.

[0194] (Note 31) A step of preparing a semiconductor substrate having a first main surface and a second main surface, on which a drift layer of first conductivity type is formed, A step of forming a source layer of the first conductivity type or a contact layer of the second conductivity type containing a first dislocation on the surface layer of the first main surface of the semiconductor substrate, A step of forming a second dislocation at a position on the second main surface side of the source layer or contact layer by subjecting the first dislocation to heat treatment, thereby moving the first dislocation to a position on the second main surface side of the source layer or contact layer, A method for manufacturing a semiconductor device comprising the same equipment.

[0195] (Note 32) A step of forming a plurality of trenches reaching the drift layer on the first main surface of the semiconductor substrate, The steps include embedding electrodes in the trench via an insulating film, It further includes, In the process of forming the second dislocation, the second dislocation is formed whose total length is longer than the width of the mesa region, which is the region between the trenches of the semiconductor substrate. The method for manufacturing a semiconductor device as described in Appendix 31. [Explanation of Symbols]

[0196] 1 n -1) n-type drift layer, 2) n-type carrier storage layer, 3) n-type buffer layer, 4) interlayer insulating film, 5) barrier metal, 6) emitter electrode, 6a) termination electrode, 7) collector electrode, 8) trench, 9) oxide film, 10) IGBT region, 11) active trench gate, 11a) gate trench electrode, 11b) gate trench insulating film, 12) dummy trench gate, 12a) dummy trench electrode, 12b) dummy trench insulating film, 13) n + Type source layer, 14 p + Type contact layer, 15 p-type base layer, 16 p-type collector layer, 16a p-type termination collector layer, 20 diode region, 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film, 24 p + 25-type anode contact layer, 26-p-type anode layer, 26-n + 30 type cathode layer, 30 termination region, 31 p-type termination well layer, 32 n + 33 Type channel stopper layer, 34 Semi-insulating film, 35 Termination protective film, 35 Termination dummy trench gate, 35a Termination dummy trench electrode, 35b Termination dummy trench insulating film, 36 Two-stage trench gate, 36a Upper gate trench electrode, 36b Upper gate trench insulating film, 36c Lower gate trench electrode, 36d Lower gate trench insulating film, 36e Intermediate insulating film, 40 Pad region, 41 Control pad, 41a Current sense pad, 41b Kelvin emitter pad, 41c Gate pad, 41d Temperature sense diode pad, 41e Temperature sense diode pad, 100, 101 Semiconductor device, 200 First dislocation, 201 Second dislocation.

Claims

1. A semiconductor substrate having a first main surface and a second main surface, on which a first conductivity type drift layer is formed, A plurality of trenches formed on the first main surface of the semiconductor substrate, An electrode embedded in the trench via an insulating film, The mesa region, which is the region between the trenches in the semiconductor substrate, A first conductivity type source layer or a second conductivity type contact layer formed on the surface layer of the first main surface side of the mesa region, It comprises a bipolar semiconductor device having, In the mesa region, at a position on the second main surface side of the source layer or the contact layer, there is a dislocation having a total length longer than the width of the mesa region, Semiconductor equipment.

2. The dislocation has a curved shape, The semiconductor device according to claim 1.

3. The dislocation is curved so as to be convex toward the second main surface. The semiconductor device according to claim 2.

4. The dislocation has a component in the <110> direction and a component in the <100> direction of the semiconductor substrate. The semiconductor device according to claim 1.

5. The main constituent element of the aforementioned semiconductor substrate is silicon. The semiconductor device according to claim 1.

6. The bipolar semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting IGBT) which includes an IGBT and a diode. The semiconductor device according to any one of claims 1 to 5.

7. The source layer or the contact layer is disposed on the surface layer of the second conductive base layer formed on the surface layer of the first main surface side of the mesa region. The dislocations are located on the second main surface side of the base layer. The semiconductor device according to claim 6.

8. The base layer further comprises a carrier accumulation layer formed on the second main surface side, The dislocations are located on the second main surface side of the interface between the base layer and the carrier storage layer. The semiconductor device according to claim 7.

9. At least a portion of the dislocation is located on the second main surface side of the trench bottom. The semiconductor device according to claim 6.

10. The dislocation overlaps with at least a portion of the source layer in a plan view. The semiconductor device according to claim 6.

11. The dislocation overlaps with at least a portion of the contact layer in a plan view. The semiconductor device according to claim 6.

12. The IGBT further comprises a terminal region provided around the IGBT region where the IGBTs are arranged. The dislocation is not located in the terminal region. The semiconductor device according to claim 6.

13. Multiple terminal dummy trench gates are formed in the terminal region, with the terminal dummy trench gates located on the outside being shallower. The semiconductor device according to claim 12.

14. The IGBT further comprises a terminal region provided around the IGBT region where the IGBTs are arranged. At least a portion of the dislocation is located in the boundary region between the IGBT region and the terminal region. The semiconductor device according to claim 6.

15. A portion of the electrode embedded in the trench is a dummy trench electrode electrically connected to the emitter electrode. The semiconductor device according to claim 6.

16. At least some of the dislocations are in contact with the trench in which the dummy trench electrode is embedded. The semiconductor device according to claim 15.

17. The electrodes embedded in the trench are separated into an upper gate trench electrode located on the first main surface side and a lower gate trench electrode located on the second main surface side. The upper gate trench electrode and the lower gate trench electrode are insulated from each other by an intermediate insulating film. The semiconductor device according to claim 6.

18. The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. At least some of the dislocations are in contact with the lower gate trench insulating film. The semiconductor device according to claim 17.

19. The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. The lower gate trench insulating film is thicker than the upper gate trench insulating film. The semiconductor device according to claim 17.

20. At least some of the dislocations are in contact with the lower gate trench insulating film. The semiconductor device according to claim 19.

21. The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. The dislocation is not in contact with the boundary between the upper gate trench insulating film and the lower gate trench insulating film. The semiconductor device according to claim 17.

22. The insulating film in the trench includes an upper gate trench insulating film on the first main surface side of the intermediate insulating film and a lower gate trench insulating film on the second main surface side of the intermediate insulating film. At least some of the dislocations are in contact with the boundary between the upper gate trench insulating film and the lower gate trench insulating film. The semiconductor device according to claim 17.

23. The aforementioned bipolar semiconductor device is an RC-IGBT (Reverse Conducting IGBT) which includes a diode or an IGBT (Insulated Gate Bipolar Transistor) and a diode. The semiconductor device according to any one of claims 1 to 5.

24. The contact layer is located on the surface of the second conductive anode layer formed on the surface of the first main surface side of the mesa region. At least some of the dislocations are located in the anode layer. The semiconductor device according to claim 23.

25. The contact layer is located on the surface of the second conductive anode layer formed on the surface of the first main surface side of the mesa region. At least a portion of the dislocations are located on the second main surface side of the interface between the anode layer and the drift layer. The semiconductor device according to claim 23.

26. At least a portion of the dislocation is located on the second main surface side of the trench bottom. The semiconductor device according to claim 23.

27. The bipolar semiconductor device is the RC-IGBT, At least a portion of the dislocation is located at the boundary between the IGBT region where the IGBT is located and the diode region where the diode is located. The semiconductor device according to claim 23.

28. The bipolar semiconductor device is the RC-IGBT, The dislocation is located in both the IGBT region where the IGBT is located and the diode region where the diode is located. A region is provided in at least a part of the IGBT region in which the dislocation density is greater than the dislocation density in the diode region. The semiconductor device according to claim 23.

29. The bipolar semiconductor device is the RC-IGBT, The dislocation is located in both the IGBT region where the IGBT is located and the diode region where the diode is located. A region is provided in at least a part of the diode region in which the dislocation density is greater than the dislocation density in the IGBT region. The semiconductor device according to claim 23.

30. The density of dislocations in the region overlapping with the contact layer in a plan view is greater than the density of dislocations in the region not overlapping with the contact layer in a plan view. The semiconductor device according to claim 23.

31. A step of preparing a semiconductor substrate having a first main surface and a second main surface, on which a drift layer of first conductivity type is formed, A step of forming a first conductivity type source layer or a second conductivity type contact layer containing a first dislocation on the surface layer of the first main surface side of the semiconductor substrate, A step of forming a second dislocation at a position on the second main surface side of the source layer or contact layer by subjecting the first dislocation to heat treatment, thereby moving the first dislocation to a position on the second main surface side of the source layer or contact layer, A method for manufacturing a semiconductor device comprising the same equipment.

32. The steps include forming a plurality of trenches reaching the drift layer on the first main surface of the semiconductor substrate, The steps include embedding electrodes in the trench via an insulating film, It further includes, In the step of forming the second dislocation, the second dislocation is formed whose total length is longer than the width of the mesa region, which is the region between the trenches of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 31.

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