PLL circuit

Abstract

This provides a PLL circuit that can suppress variations in loop characteristics and jitter. [Solution] The device includes a voltage-controlled oscillator comprising a first MOS transistor of a first conductivity type that receives a control voltage applied to its gate and generates an oscillation signal with a frequency corresponding to the control voltage; a phase comparator that receives a reference frequency signal and detects the phase difference between the reference frequency signal and a signal obtained by dividing the frequency of the oscillation signal; a charge pump that generates a phase difference signal corresponding to the phase difference; a loop filter that smooths the voltage level of the phase difference signal to generate a control voltage; and a current adjustment circuit comprising a second MOS transistor of a first conductivity type that adjusts the current flowing to the charge pump according to the threshold voltage of the second MOS transistor.

Description

Technical Field

[0001] The present disclosure relates to a PLL circuit.

Background Art

[0002] A PLL (Phase Locked Loop) circuit is provided with a VCO (Voltage Controlled Oscillator), which is a voltage-controlled oscillator that receives a control voltage and generates an oscillation signal having a frequency corresponding thereto. The VCO has a control transistor (for example, an NMOS transistor) to which a control voltage is applied to its gate, and controls the oscillation frequency by performing voltage-current conversion in the control transistor (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In a VCO having the above-described configuration, when the threshold voltage Vth of the control transistor varies due to manufacturing variations of the control transistor, the Kvco indicating the gain of the VCO varies accordingly, resulting in variations in the loop characteristics of the PLL and clock jitter.

[0005] A PLL circuit according to one aspect of the present disclosure includes a voltage-controlled oscillator comprising a first MOS transistor of a first conductivity type that receives a control voltage applied to its gate and generates an oscillation signal with a frequency corresponding to the control voltage; a phase comparator that receives a reference frequency signal and detects the phase difference between the reference frequency signal and a signal obtained by dividing the frequency of the oscillation signal; a charge pump that generates a phase difference signal corresponding to the phase difference; a loop filter that smooths the voltage level of the phase difference signal to generate the control voltage; and a current adjustment circuit comprising a second MOS transistor of a first conductivity type that adjusts the current flowing to the charge pump according to the threshold voltage of the second MOS transistor. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing the configuration of a PLL circuit according to Embodiment 1 of the present disclosure. [Figure 2] This is a circuit diagram showing the configuration of the VCO in Example 1. [Figure 3] This graph shows the change in charge pump current and VCO gain in response to fluctuations in threshold voltage. [Figure 4] This graph shows the waveforms of the open-loop gain and step response in response to changes in the threshold voltage. [Figure 5] This graph shows the change in charge pump current and VCO gain in response to fluctuations in threshold voltage. [Figure 6] This graph shows the waveforms of the open-loop gain and step response in response to changes in the threshold voltage. [Figure 7] This is a circuit diagram showing the configuration of the CP current control circuit and charge pump in Example 1. [Figure 8] This is a circuit diagram showing the configuration of the CP current control circuit and charge pump in Example 2. [Figure 9] This is a circuit diagram showing the configuration of the resistance value setting block. [Figure 10] This is a circuit diagram showing the configuration of a variable resistor.

[0007] [Detailed explanation] Preferred embodiments of the present disclosure are described in detail below. In the following descriptions and accompanying drawings, substantially identical or equivalent parts are denoted by the same reference numerals. [Example 1]

[0008] Figure 1 is a block diagram showing the configuration of a PLL circuit 100 according to Embodiment 1 of the present disclosure. The PLL circuit 100 includes a phase comparator (PFD) 11, a charge pump (CP) 12, a loop filter (LPF) 13, a voltage-controlled oscillator (VCO) 14, and a frequency divider (1 / N) 15. These constitute a feedback loop. The PLL circuit 100 also includes a CP current control circuit 16.

[0009] The phase comparator 11 is a circuit that detects the phase difference between two input signals and outputs a voltage corresponding to the detected phase difference. The phase comparator 11 uses the reference clock signal CLK. REF It receives a supply of the frequency and a divided clock signal DIV from the frequency divider 15, and outputs a control signal Up or Down according to the phase difference between them.

[0010] The charge pump 12 controls the reference clock signal CLK based on the control signal Up or Down supplied from the phase comparator 11. REF It outputs a current pulse signal PS corresponding to the phase difference between this signal and the divided clock signal DIV.

[0011] The loop filter 13 smooths the current pulse signal PS supplied from the charge pump 12 and controls the control voltage V CTRL Output as follows.

[0012] VCO14 controls the voltage V CTRL This is a voltage-controlled oscillator circuit that controls the oscillation frequency based on the following. VCO14 receives a control voltage V from the loop filter 13. CTRL The system receives a supply of a corresponding output clock signal CLK with a corresponding frequency. OUT Outputs.

[0013] FIG. 2 is a circuit diagram showing the configuration of the VCO 14. The VCO 14 includes inverters IV1 to IV3 connected in series to form a ring oscillator, and a control transistor NM1 that receives a control voltage V CTRL of the control voltage. The control transistor NM1 is composed of a MOS transistor of the first conductivity type (in this embodiment, an NMOS transistor), the source of which is grounded and the drain of which is connected to the current path of the bias current of the inverters IV1 to IV3.

[0014] Referring to FIG. 1 again, the frequency divider 15 receives the supply of the output clock signal CLK OUT and outputs a divided clock signal DIV obtained by dividing this.

[0015] The CP current control circuit 16 is a circuit that controls the charge pump current flowing through the charge pump 12. For example, the CP current control circuit 16 includes an NMOS transistor that is generated on the same chip in the same manufacturing process as the control transistor NM1 provided in the VCO 14 and has the same size, and adjusts the charge pump current according to the threshold voltage of the NMOS transistor.

[0016] The CP current control circuit 16 controls the charge pump current so that the characteristics of the PLL circuit 100 are constant. The relationship between the charge pump current and the characteristics of the PLL circuit 100 will be described below.

[0017] Generally, when the charge pump current is Icp and the gain (modulation sensitivity) of the VCO 14 is Kvco, the gain of the PLL is represented by Kvco×Icp. The charge pump current Icp is a current whose current amount and current direction are determined by the control signals Up and Down, and is hardly affected by the threshold voltage Vth of the control transistor NM1 provided in the VCO. On the other hand, Kvco, which is a characteristic of the VCO, is easily affected by variations in the threshold voltage Vth of the control transistor NM1 that controls the oscillator part.

[0018] Figure 3 is a graph showing the changes in charge pump current Icp and Kvco in response to fluctuations in the threshold voltage Vth of the control transistor, assuming that the charge pump current Icp is not controlled, unlike the PLL circuit 100 in this embodiment.

[0019] As shown on the left side of the figure, the charge pump current Icp remains constant regardless of fluctuations in the threshold voltage Vth of the control transistor NM1. In contrast, as shown on the right side of the figure, the VCO characteristic Kvco is large when the threshold voltage Vth of the control transistor NM1 is low, and changes so that its value decreases monotonically (for example, becomes linearly smaller) as the threshold voltage Vth increases.

[0020] The open-loop transfer function of a PLL is expressed by the following equation (Equation 1).

[0021]

number

[0022] Furthermore, the closed-loop transfer function of a PLL is expressed by the following equation (Equation 2).

[0023]

number

[0024] Figure 4 is a graph showing the waveforms of the open-loop gain and step response in response to the change in threshold voltage Vth, assuming that the charge pump current Icp is not controlled, similar to Figure 3.

[0025] As can be seen from Equation 1, the larger the value of Kvco × Icp, the higher the gain of Gopen(s). When the threshold voltage Vth of the control transistor NM1 is low, the value of Kvco is large, and when the threshold voltage Vth is high, the value of Kvco is small. Therefore, as shown on the left side of Figure 4, when the threshold voltage Vth of the control transistor NM1 is low, the open-loop gain is large, and when the threshold voltage Vth of the control transistor NM1 is high, the open-loop gain is small.

[0026] The step characteristics of the PLL can be determined from the closed-loop transfer function shown in Equation 2, and the responsiveness of the PLL can be determined. As shown on the right side of Figure 4, the larger the value of Kvco × Icp, that is, the lower the threshold voltage Vth of the control transistor NM1, the higher the responsiveness, the faster the convergence of the step response, and the greater the jitter.

[0027] In the PLL circuit 100 of this embodiment, the CP current control circuit 16 controls the charge pump current Icp according to the threshold voltage Vth of the control transistor NM1 so that the characteristics of the PLL remain constant.

[0028] Figure 5 is a graph showing the changes in charge pump current Icp and Kvco in response to fluctuations in the threshold voltage Vth of the control transistor in the PLL circuit 100 of this embodiment.

[0029] The VCO characteristic Kvco shown on the right side of the figure is the same as that in Figure 3. That is, The value of the control transistor NM1 is large when the threshold voltage Vth is low, and decreases as the threshold voltage Vth increases.

[0030] In contrast, in the PLL circuit 100 of this embodiment, as shown on the left side of the figure, the charge pump current Icp is controlled so that it has the opposite characteristics to Kvco, which is a VCO characteristic. That is, the CP current control circuit 16 controls the amount of charge pump current Icp so that the amount of current increases when the threshold voltage Vth of the control transistor NM1 is high, and decreases when the threshold voltage Vth is low. This makes it possible to suppress variations in PLL characteristics and clock jitter due to fluctuations in the threshold voltage Vth.

[0031] Figure 6 is a graph showing the waveforms of the open-loop gain and step response in the PLL circuit 100 of this embodiment in response to the change in threshold voltage Vth.

[0032] In the PLL circuit 100 of this embodiment, the charge pump current Icp is controlled so that it has the opposite characteristics to Kvco, thereby suppressing fluctuations in Kvco × Icp due to fluctuations in the threshold voltage Vth. As a result, as shown on the left side of the figure, the difference in the open-loop characteristics determined by Kvco × Icp due to fluctuations in the threshold voltage Vth can be reduced. Furthermore, as shown on the right side of the figure, the difference in the step response due to fluctuations in the threshold voltage Vth can also be reduced, thereby suppressing variations in clock jitter.

[0033] Figure 7 is a circuit diagram showing the configuration of the CP current control circuit 16 and the charge pump 12. The CP current control circuit 16 includes a Vth detection circuit 21 and a bias current control block 22.

[0034] The Vth detection circuit 21 includes a constant current source CS, a resistor R11, and a transistor N11. The constant current source CS receives the power supply voltage VDD at one end and the other end is connected to node n1. The resistor R11 is connected to node n11 at one end.

[0035] Transistor N11 is composed of an NMOS transistor. The drain of transistor N11 is connected to the other end of resistor R11. The source of transistor N11 is grounded. The gate of transistor N11 is connected to node n1.

[0036] For example, transistor N11 is an NMOS transistor manufactured on the same chip using the same manufacturing process as control transistor NM1 provided in VCO14, and has the same size (gate length, etc.), and has the same threshold voltage Vth as control transistor NM1.

[0037] The bias current control block 22 includes an amplifier VAP, a transistor P11, and a resistor R12.

[0038] Amplifier VAP has its first input terminal connected to node n1 and its second input terminal connected to node n2. The voltage output terminal of amplifier VAP is connected to node n3. Resistor R12 has one end connected to node n2 and the other end grounded.

[0039] Transistor P11 is composed of a MOS transistor (PMOS transistor in this embodiment) of the second conductivity type, which is the opposite conductivity type to the first conductivity type. The power supply voltage VDD is applied to the source of transistor PM11. The drain of transistor PM11 is connected to node n2. The gate of transistor PM11 is connected to node n3.

[0040] The charge pump 12 has transistors P12, P13, N12, and N13. Transistors P12 and P13 are made of PMOS transistors. Transistors N12 and N13 are made of NMOS transistors.

[0041] The power supply voltage VDD is applied to the source of transistor P12. The gate of transistor PM12 is connected to node n4, and through node n4, it is connected to node n3.

[0042] The source of transistor N12 is grounded. The drain of transistor N12 is connected to the drain of transistor PM12.

[0043] The source of transistor P13 is connected to switch SW1, and the power supply voltage VDD is applied when switch SW1 is ON. The gate of transistor P13 is connected to node n4 in common with the gate of transistor P12, and is connected to node n3 via node n4. The drain of transistor P13 is connected to node n5, and is connected to loop filter 13 via node n5.

[0044] The source of transistor N13 is connected to switch SW2 and is grounded when switch SW2 is ON. The gate of transistor N13 is connected to the gate of transistor N12. The drain of transistor N13 is connected to node n5 and, via node n5, to loop filter 13.

[0045] In the CP current control circuit 16 with the above configuration, the amplifier output of amplifier VAP fluctuates according to the threshold voltage Vth of transistor N11, and the bias voltage Vbias of node n2 is controlled to be equal to the value of the threshold voltage Vth. As a result, the amount of current flowing through resistor R12 increases or decreases. The current flowing through resistor R12 is current-mirrored by the charge pump 12 and becomes the charge pump current Icp.

[0046] In other words, with the CP current control circuit 16 configured in this way, the charge pump current Icp is controlled so that the current increases or decreases in accordance with the fluctuation of the threshold voltage Vth of transistor N11. This makes it possible to control the amount of charge pump current Icp to have the opposite characteristics to Kvco in accordance with the fluctuation of the threshold voltage Vth, thereby keeping the characteristics of the PLL circuit 100 constant.

[0047] In this embodiment, the PLL circuit 100 completes the correction of the charge pump current Icp according to the threshold voltage Vth of transistor N1 immediately after the circuit is powered on. Therefore, the PLL circuit 100 can operate at high speed without being significantly affected by noise or other factors. [Example 2]

[0048] Next, Embodiment 2 of this disclosure will be described. The PLL circuit in this embodiment differs from that in Embodiment 1 in the configuration of the CP current control circuit.

[0049] Figure 8 shows that the CP current control circuit 16A in this embodiment has a variable resistor R22 instead of the resistor R12 in the CP current control circuit 16 of Embodiment 1. Furthermore, the CP current control circuit 16A has a resistance value setting block 23 for setting the resistance value of the variable resistor R22.

[0050] The resistance setting block 23 has one end connected to node n1 via node n6. Based on the potential of node n1, the resistance setting block 23 sets the resistance value of the variable resistor R22 so that it corresponds to the threshold voltage Vth of transistor N11.

[0051] Figure 9 is a circuit diagram showing the configuration of the resistance setting block 23. The resistance setting block 23 includes ladder resistors 31 and comparators CP0 to CPn.

[0052] The ladder resistor 31 is composed of, for example, n resistor elements (not shown in the diagram), and outputs reference voltages ref0 to refn from the connection terminals between adjacent resistor elements. Comparators CP0 to CPn are provided corresponding to the (n+1) output terminals of the ladder resistor 31 that output the reference voltages ref0 to refn, and compare the reference voltage input to themselves with the threshold voltage Vth, outputting output signals CO[0] to CO[n] that indicate the comparison result. This performs N-bit wide AD conversion.

[0053] Figure 10 is a circuit diagram showing the configuration of the variable resistor R22. The variable resistor R22 has resistors R3-0 to R3-n connected in parallel to each other. One end of each resistor R3-0 to R3-n is connected to corresponding switches SWA0 to SWAn. The other end of each resistor R3-0 to R3-n is grounded.

[0054] Switches SWA0 to SWAn are controlled to be on or off based on the output signals CO[0] to CO[n] from the resistance value setting block 23. When switches SWA0 to SWAn are selectively turned on, one end of the corresponding resistors R3-0 to R3-n is connected to node n7. This increases or decreases the resistance value of the variable resistor R22 according to the threshold voltage Vth of transistor N11. For example, switches SWA0 to SWAn are switched so that the resistance value of the variable resistor R22 decreases when the threshold voltage Vth is high, and so on when the threshold voltage Vth is low.

[0055] According to the CP current control circuit 16A of this embodiment, the charge pump current Icp can be controlled more flexibly in response to fluctuations in the threshold voltage Vth by controlling the resistance value of the variable resistor R22. In other words, unlike the CP current control circuit of this embodiment, if the resistance value is constant, the change in charge pump current Icp may not be able to keep up with the change in Kvco, which changes with the threshold voltage Vth, if the amount of change in Kvco is large. However, with the configuration of the CP current control circuit 16A of this embodiment, it is possible to keep the characteristics of the PLL circuit constant even when the amount of change in Kvco is large by controlling the resistance value.

[0056] This disclosure is not limited to the embodiments described above. For example, while Embodiments 1 and 2 described the case where the control transistor (NM1) of VCO14 is an NMOS transistor, the disclosure is also applicable when the control transistor is a PMOS transistor. That is, the Vth detection circuit 21 is equipped with a PMOS transistor that is manufactured on the same chip using the same manufacturing process as the control transistor of VCO14 and has the same size, and the bias voltage Vbias of the bias current control block 22 is operated to a voltage value corresponding to the threshold voltage of the PMOS transistor, thereby enabling the charge pump current Icp to be controlled so that the characteristics of the PLL circuit 100 remain constant.

[0057] [Note] This specification discloses the following configuration:

[0058] (Composition 1) The device includes a voltage-controlled oscillator comprising a first MOS transistor of a first conductivity type that receives a control voltage applied to its gate and generates an oscillation signal with a frequency corresponding to the control voltage; a phase comparator that receives a reference frequency signal and detects the phase difference between the reference frequency signal and a signal obtained by dividing the frequency of the oscillation signal; a charge pump that generates a phase difference signal corresponding to the phase difference; a loop filter that smooths the voltage level of the phase difference signal to generate the control voltage; and a current adjustment circuit comprising a second MOS transistor of a first conductivity type that adjusts the current flowing to the charge pump according to the threshold voltage of the second MOS transistor.

[0059] (Configuration 2) The PLL circuit according to Configuration 1, wherein the second MOS transistor is produced using the same manufacturing process as the first MOS transistor and formed on the same chip.

[0060] (Composition 3) The PLL circuit according to configuration 1 or 2, wherein the second MOS transistor is produced using the same manufacturing process as the first MOS transistor and has the same size.

[0061] (Composition 4) The current adjustment circuit includes a first circuit section that includes the second MOS transistor and outputs the potential of a node connected to the gate of the second MOS transistor as a first voltage; a third MOS transistor of a second conductivity type; a differential amplifier that receives the first voltage at its first input terminal and whose output terminal is fed back to the second input terminal via the gate and drain of the third MOS transistor; and a resistor inserted in series with the third MOS transistor in the current path of the current flowing from the source to the drain of the third MOS transistor, and a second circuit section that controls the current flowing to the charge pump by current mirroring the current flowing in the current path to the charge pump, as described in any one of configurations 1 to 3.

[0062] (Composition 5) The PLL circuit according to configuration 4, wherein the resistor is a variable resistor, and the current adjustment circuit further includes a resistance value setting block for setting the resistance value of the variable resistor.

[0063] (Composition 6) The PLL circuit according to configuration 5, wherein the variable resistor includes a plurality of resistor elements, each connected to the current path via a switch and connected in parallel to one another, and the resistance value setting block sets the resistance value of the variable resistor by selectively switching the switches connected to each of the plurality of resistor elements.

[0064] (Composition 7) The PLL circuit according to any one of configurations 4 to 6, wherein the first MOS transistor and the second MOS transistor are NMOS transistors.

[0065] (Composition 8) The PLL circuit described in any one of configurations 4 to 7, wherein the third MOS transistor is a PMOS transistor. [Explanation of Symbols]

[0066] 100 PLL circuits 11 Phase comparator 12 Charge pump 13 Loop Filters 14 VCO 15 divider 16 CP Current Control Circuit 21 Vth detection circuit 22 Bias current control block 23. Resistance value setting block 31 Ladder Resistors

Claims

1. A voltage-controlled oscillator includes a first MOS transistor of a first conductivity type that receives a control voltage applied to its gate, and generates an oscillation signal with a frequency corresponding to the control voltage. A phase comparator that receives a reference frequency signal and detects the phase difference between the reference frequency signal and a signal obtained by dividing the frequency of the oscillation signal, A charge pump that generates a phase difference signal corresponding to the aforementioned phase difference, A loop filter that smooths the voltage level of the phase difference signal to generate the control voltage, A current adjustment circuit includes a second MOS transistor of a first conductivity type, which adjusts the current flowing to the charge pump according to the threshold voltage of the second MOS transistor, A PLL circuit.

2. The PLL circuit according to claim 1, wherein the second MOS transistor is produced using the same manufacturing process as the first MOS transistor and formed on the same chip.

3. The PLL circuit according to claim 1, wherein the second MOS transistor is produced by the same manufacturing process as the first MOS transistor and has the same size.

4. The current adjustment circuit is, A first circuit section including the second MOS transistor, which outputs the potential of the node connected to the gate of the second MOS transistor as a first voltage, A second circuit unit includes a third MOS transistor of a second conductivity type, a differential amplifier whose first input terminal receives the first voltage and whose output terminal is fed back to the second input terminal via the gate and drain of the third MOS transistor, and a resistor inserted in series with the third MOS transistor in the current path of the current flowing from the source to the drain of the third MOS transistor, and controls the current flowing to the charge pump by current mirroring the current flowing in the current path to the charge pump. A PLL circuit according to claim 1, having the following:

5. The aforementioned resistor is a variable resistor, The PLL circuit according to claim 4, further comprising a resistance value setting block for setting the resistance value of the variable resistor, wherein the current adjustment circuit further comprises a resistance value setting block for setting the resistance value of the variable resistor.

6. The variable resistor includes a plurality of resistive elements, each connected to the current path via a switch and connected in parallel with one another. The PLL circuit according to claim 5, wherein the resistance value setting block sets the resistance value of the variable resistor by selectively switching switches connected to each of the plurality of resistor elements.

7. The PLL circuit according to claim 4, wherein the first MOS transistor and the second MOS transistor are NMOS transistors.

8. The PLL circuit according to claim 7, wherein the third MOS transistor is a PMOS transistor.

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