Clock signal skew calibration apparatus and control method

Abstract

The apparatus includes a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via a plurality of delay lines, wherein the first clock skew calibration unit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signals and to generate a reduced frequency signal based on the clock signals; and a delay line control circuit configured to compare a duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to, and is specifically a continuation of, U.S. patent application Ser. No. 18 / 227,255, entitled "Clock Signal Skew Calibration Apparatus and Control Method," filed July 27, 2023, which is incorporated by reference herein as if reproduced in its entirety.

[0002] FIELD OF THE INVENTION

[0002] Embodiments of the present invention relate to a clock signal skew calibration device, and in a particular embodiment, to a clock signal skew calibration device for reducing clock skew of a four-phase clock signal. [Background technology]

[0003]

[0003] Data communication systems are constantly being adapted to meet the ever-increasing need for high-speed data communication. A data communication system, such as a serial communication system, includes a transmitter and a receiver. The transmitter modulates a slower-speed parallel data bus into a higher-speed serial data stream. The high-speed serial data stream is transferred over an appropriate communication channel. The serial data stream travels over the communication channel and is then picked up by a receiver. The serial data stream is then processed by the receiver to recover the original data.

[0004]

[0004] To achieve higher speeds, a transmitter transmits a data signal without a clock signal. A receiver includes a clock data recovery (CDR) circuit. The CDR circuit is used to sample an input data signal, extract a clock from the input data signal, and retime the sampled data. The clock generated by the CDR circuit is synchronized with the data signal. There can be various CDR circuits, such as a phase-locked loop (PLL)-based CDR circuit, a delay-locked loop (DLL)-based CDR circuit, and a phase interpolator (PI)-based CDR circuit.

[0005] In a PI-based CDR circuit, a multi-phase clock signal (e.g., a four-phase clock signal) is used to perform phase interpolation of a data signal. Multi-phase clock signals are also widely used in other data communication applications. For example, a time-interleaved analog-to-digital conversion (ADC) system in a receiver uses multi-phase clock signals to sample input data.

[0006]

[0006] Many techniques have been used to generate multiphase clock signals. One possible technique is to create a ring oscillator and tap its nodes. To generate multiphase clock signals, a voltage-controlled or current-controlled differential ring oscillator is used, which has multiple stages of delayed differential inverting amplifiers connected in a ring.

[0007]

[0007] In high-frequency data communication applications, the time-space shift or deviation between two clock signals is called skew. The skew in the clock signals can cause errors in the analog-to-digital conversion process and can degrade system performance. As clock rates in data communication systems increase, timing becomes more critical. It is desirable to have a simple and reliable calibration method for reducing the skew in multiphase clock signals. Summary of the Invention [Means for solving the problem]

[0008] These and other problems are generally solved or avoided, and technical advantages are generally achieved, by preferred embodiments of the present disclosure which provide a clock signal skew calibration apparatus for reducing clock skew in a four-phase clock signal.

[0009]

[0009] According to one embodiment, an apparatus comprises a clock skew calibration circuit configured to be coupled to a multi-phase clock generator via a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signals and to generate a reduced frequency signal based on the clock signals, wherein the reduced frequency signal has a duty cycle indicative of the skew of the first multi-phase clock signals; and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal for adjusting the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

[0010]

[0010] According to another embodiment, a method includes the steps of generating, by a frequency multiplier, a clock signal based on a plurality of multi-phase clock signals; generating, by a frequency divider, a reduced frequency signal based on the clock signal, wherein the reduced frequency signal has a duty cycle indicative of a skew of the first multi-phase clock signal; comparing the duty cycle of the reduced frequency signal with a predetermined duty cycle; and generating, by a delay line control circuit, a first control signal for adjusting the skew of the first multi-phase clock signal by adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

[0011] According to yet another embodiment, a system includes a multi-phase clock generator configured to generate a plurality of multi-phase clock signals, a plurality of delay lines configured to receive the respective multi-phase clock signals, and a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via the plurality of delay lines, wherein the clock skew calibration circuit includes a first clock skew calibration unit, a second clock skew calibration unit, and a third clock skew calibration unit, and the first clock skew calibration unit is configured to receive the plurality of multi-phase clock signals and to calibrate a clock skew based on the plurality of multi-phase clock signals. The delay line control circuit is configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

[0012] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the present disclosure will be described hereinafter which form the subject of the claims of the present disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims.

[0013] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is a block diagram of a clock signal skew calibration circuit according to various embodiments of the present disclosure. [Figure 2] 2 is a schematic diagram of the multi-phase clock generator shown in FIG. 1 in accordance with various embodiments of the present disclosure. [Figure 3] 2 is a schematic diagram of the delay line shown in FIG. 1 in accordance with various embodiments of the present disclosure. [Figure 4] 2 is a block diagram of a first clock skew calibration unit shown in FIG. 1 in accordance with various embodiments of the present disclosure. [Figure 5] 5 is a schematic diagram of the frequency multiplier shown in FIG. 4 according to various embodiments of the present disclosure. [Figure 6] 5 is a schematic diagram of the frequency divider shown in FIG. 4 according to various embodiments of the present disclosure. [Figure 7] 5 is a schematic diagram of the filter shown in FIG. 4 according to various embodiments of the present disclosure. [Figure 8] 5 is a schematic diagram of the delay line control circuit shown in FIG. 4 according to various embodiments of the present disclosure. [Figure 9] 5A-5C illustrate various waveforms associated with a first clock skew calibration unit according to various embodiments of the present disclosure. [Figure 10] 2 is a schematic diagram of a second clock skew calibration unit shown in FIG. 1 according to various embodiments of the present disclosure. [Figure 11] 5A-5C illustrate various waveforms associated with a second clock skew calibration unit according to various embodiments of the present disclosure. [Figure 12] 2 is a schematic diagram of a third clock skew calibration unit shown in FIG. 1 in accordance with various embodiments of the present disclosure. [Figure 13] 10A-10C illustrate various waveforms associated with a third clock skew calibration unit according to various embodiments of the present disclosure. [Figure 14] 2 is a flowchart of the control of the clock signal skew calibration circuit shown in FIG. 1 in accordance with various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0028] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale.

[0016]

[0029] The making and use of presently preferred embodiments are described in detail below. It should be understood, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to make and use the present disclosure and do not limit the scope of the disclosure.

[0017]

[0030] The present disclosure will be described with respect to preferred embodiments in a particular context, namely, a clock signal skew calibration device for reducing clock skew of a four-phase clock signal. However, the present disclosure can also be applied to a clock signal skew calibration device for reducing clock skew of a multi-phase clock signal. Various embodiments will be described in detail below with reference to the accompanying drawings.

[0018]

[0031] 1 shows a block diagram of a clock signal skew calibration circuit according to various embodiments of the present disclosure. As shown in FIG. 1, a clock skew calibration circuit 120 is configured to be coupled to a multi-phase clock generator 110 via a plurality of delay lines 111, 112, 113, and 114.

[0019]

[0032] The multi-phase clock generator 110 is configured to generate a plurality of multi-phase clock signals. In some embodiments, the multi-phase clock generator 110 is configured to generate four-phase clock signals, namely, a 0-degree clock signal PH0, a 90-degree clock signal PH90, a 180-degree clock signal PH180, and a 270-degree clock signal PH270, as shown in FIG. 1. The PH0, PH90, PH180, and PH270 generated by the multi-phase clock generator 110 are four-phase clock signals whose phases are separated by 90 degrees from each other.

[0020]

[0033] In some embodiments, PH0, PH90, PH180, and PH270 are four-phase clock signals having a frequency of 5 GHz. The four-phase clock signals PH0, PH90, PH180, and PH270 are used for 20 Gbps (billion bits per second) data transfer applications. A detailed implementation of multi-phase clock generator 110 is described below with respect to FIG. 2.

[0021]

[0034] As shown in Figure 1, the first delay line 111 is configured to receive the 0-degree clock signal PH0 and a predetermined reference signal Vref1. The first delay line 111 adds a predetermined delay to the 0-degree clock signal based on the predetermined reference signal Vref1. As shown in Figure 1, PH0D is generated by the first delay line 111.

[0022]

[0035] In some embodiments, the 0-degree clock signal PH0D is a reference clock signal for the four-phase clock signals. Thus, the delay added to PH0 is not adjusted in the skew calibration process. The skew of other clock signals (e.g., 180-degree clock signals) is determined with reference to the reference clock signal PH0D. The skew of the other clock signals can be reduced by adjusting the delay added to the respective clock signals.

[0023]

[0036] As shown in FIG. 1, the second delay line 112 is configured to receive the 180-degree clock signal PH180 and a first control signal VC1. VC1 is generated by the clock skew calibration circuit 120. VC1 is used to determine the delay to be added to the 180-degree clock signal PH180. By adjusting the delay to be added to the 180-degree clock signal, the skew of the 180-degree clock signal is reduced accordingly. As shown in FIG. 1, the second delay line 112 receives PH180 and generates PH180D by adding an initial delay. Both PH180 and PH180D are 180-degree clock signals with a delay between them. During the calibration process of the 180-degree clock signal, the initial delay is adjusted to a first delay determined by the first control signal VC1. When the initial delay is changed to the first delay, PH180C is generated at the output of the second delay line 112. PH180C is the calibrated 180-degree clock signal. In other words, the phase difference between the reference clock signals PH0D and PH180C is 180 degrees.

[0024]

[0037] As shown in FIG. 1, the third delay line 113 is configured to receive the 90-degree clock signal PH90 and a second control signal VC2. VC2 is generated by the clock skew calibration circuit 120. VC2 is used to determine the delay to be added to the 90-degree clock signal PH90. By adjusting the delay to be added to the 90-degree clock signal, the skew of the 90-degree clock signal is reduced accordingly. As shown in FIG. 1, the third delay line 113 receives PH90 and generates PH90D by adding an initial delay. Both PH90 and PH90D are 90-degree clock signals with a delay between them. During the calibration process of the 90-degree clock signal, the initial delay is adjusted to a second delay determined by the second control signal VC2. When the initial delay is changed to the second delay, PH90C is generated at the output of the third delay line 113. PH90C is the calibrated 90-degree clock signal. In other words, the phase difference between the reference clock signals PH0D and PH90C is 90 degrees.

[0025]

[0038] As shown in FIG. 1, the fourth delay line 114 is configured to receive the 270-degree clock signal PH270 and a third control signal VC3. VC3 is generated by the clock skew calibration circuit 120. VC3 is used to determine the delay to be added to the 270-degree clock signal PH270. By adjusting the delay to be added to the 270-degree clock signal, the skew of the 270-degree clock signal is reduced accordingly. As shown in FIG. 1, the fourth delay line 114 receives PH270 and generates PH270D by adding an initial delay. Both PH270 and PH270D are 270-degree clock signals with a delay between them. During the calibration process of the 270-degree clock signal, the initial delay is adjusted to a third delay determined by the third control signal VC3. When the initial delay is changed to the third delay, PH270C is generated at the output of the fourth delay line 114. PH270C is the calibrated 270-degree clock signal. In other words, the phase difference between the reference clock signals PH0D and PH270C is 270 degrees.

[0026]

[0039] Clock skew calibration circuit 120 includes a PH180 calibration unit 121, a PH90 calibration unit 122, and a PH270 calibration unit 123. Throughout the description, PH180 calibration unit 121 is alternatively referred to as the first clock skew calibration unit 121. PH90 calibration unit 122 is alternatively referred to as the second clock skew calibration unit 122. PH270 calibration unit 123 is alternatively referred to as the third clock skew calibration unit 123.

[0027]

[0040] In some embodiments, the first clock skew calibration unit 121 comprises a frequency multiplier, a frequency divider, and a delay line control circuit. The detailed structure of the first clock skew calibration unit 121 is described below in connection with FIG.

[0028]

[0041] In operation, the first clock skew calibration unit 121 and the second delay line 112 form a closed-loop control system that determines a first control signal VC1 based on the skew of the 180-degree clock signal and adjusts a delay added to the 180-degree clock signal to reduce or eliminate the skew of the 180-degree clock signal, thereby calibrating the skew of the 180-degree clock signal.

[0029]

[0042] In operation, the first clock skew calibration unit 121 is configured to receive a plurality of multi-phase clock signals, including PH0D, PH90D, PH180D, and PH270D, as shown in FIG. 1 . The frequency multiplier generates a clock signal based on the plurality of multi-phase clock signals PH0D, PH90D, PH180D, and PH270D. The frequency divider is configured to receive the clock signals and generate a reduced frequency signal based on the clock signals. The reduced frequency signal has a duty cycle indicative of the skew of the first multi-phase clock signals (e.g., 180-degree clock signals). The delay line control circuit is configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle and generate a first control signal VC1. The first control signal VC1 is used to adjust a first delay applied to the first multi-phase clock signals (e.g., 180-degree clock signals) until a calibrated signal of the first multi-phase clock signals is achieved. Once the skew calibration process is complete, PH180C generated by the second delay line 112 is a calibrated version of the 180 degree clock signal.

[0030]

[0043] In some embodiments, the second clock skew calibration unit 122 comprises a first logic gate, a second logic gate, and a first comparator. A detailed structure of the second clock skew calibration unit 122 is described below in connection with FIG.

[0031]

[0044] In operation, the second clock skew calibration unit 122 and the third delay line 113 form a closed-loop control system that determines the second control signal VC2 based on the skew of the 90-degree clock signal and adjusts the delay added to the 90-degree clock signal to reduce or eliminate the skew of the 90-degree clock signal, thereby calibrating the skew of the 90-degree clock signal.

[0032]

[0045] In operation, the second clock skew calibration unit 122 is configured to receive PH0D, PH90D, and PH180C. In some embodiments, PH0D is a reference multi-phase clock signal. PH180C is a calibrated version of the first multi-phase clock signal. PH90D is a second multi-phase clock signal.

[0033]

[0046] The first logic gate is configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal (PH180C) and the second multi-phase clock signal (PH90D). The second logic gate is configured to perform a second AND operation on the reference multi-phase clock signal (PH0D) and the second multi-phase clock signal (PH90D). The first comparator is configured to compare the output of the first logic gate with the output of the second logic gate and generate a second control signal VC2. The second control signal VC2 is used to adjust the second delay applied to the second multi-phase clock signal (90-degree clock signal) until the calibrated signal of the second multi-phase clock signal is achieved. When the skew calibration process is completed, PH90C generated by the third delay line 113 is the calibrated signal of the 90-degree clock signal.

[0034]

[0047] In some embodiments, the third clock skew calibration unit 123 comprises a third logic gate, a fourth logic gate, and a second comparator. A detailed structure of the third clock skew calibration unit 123 will be described later in connection with FIG. 12.

[0035]

[0048] In operation, the third clock skew calibration unit 123 and the fourth delay line 114 form a closed-loop control system that determines the third control signal VC3 based on the skew of the 270-degree clock signal and adjusts the delay added to the 270-degree clock signal to reduce or eliminate the skew of the 270-degree clock signal, thereby calibrating the skew of the 270-degree clock signal.

[0036]

[0049] In operation, the third clock skew calibration unit 123 is configured to receive PH0D, PH180C, and PH270D. In some embodiments, PH0D is a reference multi-phase clock signal. PH180C is a calibrated version of the first multi-phase clock signal. PH270D is a third multi-phase clock signal.

[0037]

[0050] The third logic gate is configured to perform a third AND operation on the calibrated signal of the first multi-phase clock signal (PH180C) and the third multi-phase clock signal (PH270D). The fourth logic gate is configured to perform a fourth AND operation on the reference multi-phase clock signal (PH0D) and the third multi-phase clock signal (PH270D). The second comparator is configured to compare the output of the third logic gate with the output of the fourth logic gate and generate a third control signal VC3. The third control signal VC3 is used to adjust the third delay applied to the third multi-phase clock signal (270-degree clock signal) until the calibrated signal of the third multi-phase clock signal is achieved. When the skew calibration process is completed, PH270C generated by the fourth delay line 114 is the calibrated signal of the 270-degree clock signal.

[0038]

[0051] 2 shows a schematic diagram of the multi-phase clock generator shown in FIG. 1 in accordance with various embodiments of the present disclosure. In some embodiments, multi-phase clock generator 110 is implemented as a four-phase clock generator as shown in FIG. 2. Multi-phase clock generator 110 comprises a first oscillator 211, a second oscillator 212, a third oscillator 213, and a fourth oscillator 214 cascaded together.

[0039]

[0052] 2, the inverting output of the first oscillator 211 is connected to the non-inverting input of the second oscillator 212. The inverting output of the first oscillator 211 is configured to generate a 270-degree clock signal PH270. The non-inverting output of the first oscillator 211 is connected to the inverting input of the second oscillator 212. The inverting output of the second oscillator 212 is connected to the non-inverting input of the third oscillator 213. The inverting output of the second oscillator 212 is configured to generate a 180-degree clock signal PH180. The non-inverting output of the second oscillator 212 is connected to the inverting input of the third oscillator 213.

[0040]

[0053] The inverting output of the third oscillator 213 is connected to the non-inverting input of the fourth oscillator 214. The inverting output of the third oscillator 213 is configured to generate a 90-degree clock signal PH90. The non-inverting output of the third oscillator 213 is connected to the inverting input of the fourth oscillator 214. The inverting output of the fourth oscillator 214 is connected to the non-inverting input of the first oscillator 211. The inverting output of the fourth oscillator 214 is configured to generate a 0-degree clock signal PH0. The non-inverting output of the fourth oscillator 214 is connected to the inverting input of the first oscillator 211.

[0041]

[0054] The operating principles of the four-phase clock generator shown in FIG. 2 are well known in the art and therefore will not be described here to avoid repetition.

[0042]

[0055] 3 shows a schematic diagram of the delay line shown in FIG. 1 according to various embodiments of the present disclosure. The four delay lines shown in FIG. 1 may have the same structure. The second delay line 112 is used as an example to explain the structure and operation principle of the delay line shown in FIG. 1.

[0043]

[0056] The second delay line 112 includes a bias circuit and multiple inverting legs. The bias circuit includes an upper transistor M41 and a lower transistor M42 connected in series between a power supply voltage VDD and ground. The multiple inverting legs are connected in parallel between the power supply voltage VDD and ground. Each inverting leg includes a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series. As shown in FIG. 2 , a first inverting leg of the multiple inverting legs includes transistors M11, M12, M13, and M14 connected in series between VDD and ground. A second inverting leg of the multiple inverting legs includes transistors M21, M22, M23, and M24 connected in series between VDD and ground. A final inverting leg of the multiple inverting legs includes transistors M31, M32, M33, and M34 connected in series between VDD and ground. In some embodiments, M11, M12, M21, M22, M31, M32, and M41 are p-type transistors, and M13, M14, M23, M24, M33, M34, and M42 are n-type transistors.

[0044]

[0057] As shown in FIG. 3, the gates of transistors M11, M21, and M31 are connected to the gate of upper transistor M41. In the first inverting leg, the gates of M12 and M13 are connected together and serve as the input of the first inverting leg. The midpoint VM1 of the first inverting leg serves as the output of the first inverting leg. In the second inverting leg, the gates of M22 and M23 are connected together and serve as the input of the second inverting leg. The midpoint VM2 of the second inverting leg serves as the output of the second inverting leg. In the last inverting leg, the gates of M32 and M33 are connected together and serve as the input of the last inverting leg. The midpoint VM3 of the last inverting leg serves as the output of the last inverting leg. The gates of transistors M14, M24, and M34 are connected to the gate of lower transistor M42.

[0045]

[0058] As shown in FIG. 3, the input of the first inverting leg is configured to receive the first multi-phase clock signal PH180. The output of the first inverting leg is connected to the input of the second inverting leg. The output of the second inverting leg is connected to the input of an adjacent inverting leg (not shown). The input of the last inverting leg is connected to the output of the adjacent inverting leg (not shown). The output of the last inverting leg is configured to generate PH180D as shown in FIG. 3. When the calibration process of the first multi-phase clock signal PH180 is completed, the output of the last inverting leg is configured to generate a calibrated signal (PH180C) of the first multi-phase clock signal.

[0046]

[0059] In operation, each inverting leg functions as a current-starved inverter. The second delay line 112 is configured to receive a first control signal VC1 at the gate of M42. The current-starved inverter can convert the first control signal VC1 into a voltage-controlled delay. In each inverting leg, the top transistor (e.g., M11) and the bottom transistor (e.g., M14) function as current sources. The two middle transistors (e.g., M12 and M13) function as inverters. In response to the first control signal VC1, the current sources (e.g., M11 and M14) can control the current supplied to the inverters (e.g., M12 and M13). In particular, the current supplied to the inverters is determined by the bias circuit formed by M41 and M42. The current through M42 is proportional to the gate-source voltage (VC1) of M42. Therefore, the maximum current results in the shortest delay. Therefore, increasing VC1 reduces the delay. On the other hand, the smaller the current, the larger the delay. Therefore, as VC1 decreases, the delay increases. The second delay line 112 can add an adjustable delay to PH180 in response to VC1. When the appropriate delay is added to PH180, the second delay line 112 generates PH180C. PH180C is the calibrated signal of PH180.

[0047]

[0060] 4 shows a block diagram of the first clock skew calibration unit 121 shown in FIG. 1 in accordance with various embodiments of the present disclosure. The first clock skew calibration unit 121 includes a frequency multiplier 402, a frequency divider 404, a latch circuit 406, a buffer 408, a delay line control circuit 410, and a filter 412.

[0048]

[0061] As shown in FIG. 4, the frequency multiplier 402 is configured to receive multiple multi-phase clock signals PH0D, PH90D, PH180D, and PH270D. The frequency multiplier 402 generates a clock signal CLKOUT based on the multiple multi-phase clock signals. The frequency divider 404 is configured to receive the clock signal CLKOUT and generate a reduced frequency signal CLKDIV2 based on the clock signal CLKOUT. The frequency of CLKDIV2 is half the frequency of CLKOUT. The reduced frequency signal CLKDIV2 has a duty cycle that represents the skew of the first multi-phase clock signal PH180D.

[0049]

[0062] The reduced frequency signal CLKDIV2 is provided to a date input of latch circuit 406. The 90 degree clock signal PH90 is provided to a clock input of latch circuit 406 via buffer 408. Latch circuit 406 is configured to generate a direction control signal SEL.

[0050]

[0063] Filter 412 is configured to receive reduced frequency signal CLKDIV2 and generate a dc signal VDUTY, the voltage of which is proportional to the duty cycle of reduced frequency signal CLKDIV2.

[0051]

[0064] The delay line control circuit 410 is configured to receive VDUTY, SEL, and a predetermined reference voltage Vref. The delay line control circuit 410 is configured to compare the duty cycle of the reduced frequency signal CLKDIV2 with the predetermined duty cycle. In some embodiments, VDUTY represents the duty cycle of the reduced frequency signal CLKDIV2. Vref represents the predetermined duty cycle. In some embodiments, the predetermined duty cycle is equal to 50%.

[0052]

[0065] In operation, based on VDUTY, Vref and SEL, the delay line control circuit 410 generates a first control signal VC1 to adjust the skew of the first multi-phase clock signal PH180 by adjusting a first delay added to the first multi-phase clock signal PH180 until a calibrated signal of the first multi-phase clock signal is achieved.

[0053]

[0066] 5 shows a schematic diagram of the frequency multiplier shown in FIG. 4 according to various embodiments of the present disclosure. Frequency multiplier 402 includes a first transmission gate 501 and a second transmission gate 502. Frequency multiplier 402 is configured to receive PH0D, PH90D, PH180D, and PH270D and generate a clock signal CLKOUT.

[0054]

[0067] An input of the first transmission gate 501 is configured to receive the 0-degree clock signal PH0D. An output of the first transmission gate 501 is connected to the output of the frequency multiplier 402. A first control terminal of the first transmission gate 501 is configured to receive the 90-degree clock signal PH90D. A second control terminal of the first transmission gate 501 is configured to receive the 270-degree clock signal PH270D.

[0055]

[0068] The input of the second transmission gate 502 is configured to receive the 180-degree clock signal PH180D. The output of the second transmission gate 502 is connected to the output of the frequency multiplier 402. The first control terminal of the second transmission gate 502 is configured to receive the 270-degree clock signal PH270D. The second control terminal of the second transmission gate 502 is configured to receive the 90-degree clock signal PH90D.

[0056]

[0069] The operating principles of the frequency multiplier shown in FIG. 5 are well known in the art and therefore will not be described here to avoid repetition.

[0057]

[0070] 6 shows a schematic diagram of the frequency divider shown in FIG. 4 in accordance with various embodiments of the present disclosure. The frequency divider 404 is implemented as a latch circuit 602. The clock signal CLKOUT is provided to a clock input of the latch circuit 602. The date input and Q-bar output of the latch circuit 602 are connected together. The Q output of the latch circuit 602 is configured to generate a reduced frequency signal CLKDIV2.

[0058]

[0071] The operating principles of the frequency divider shown in FIG. 6 are well known in the art and therefore will not be described here to avoid repetition.

[0059]

[0072] 7 shows a schematic diagram of the filter shown in FIG. 4 in accordance with various embodiments of the present disclosure. Filter 412 includes resistor R1 and capacitor C1. One terminal of R1 is the input of filter 412. The common node of R1 and C1 is the output of filter 412. Filter 412 is a low-pass filter configured to convert reduced-frequency signal CLKDIV2 into dc signal VDUTY. The voltage of dc signal VDUTY is proportional to the duty cycle of reduced-frequency signal CLKDIV2.

[0060]

[0073] 8 shows a schematic diagram of the delay line control circuit shown in FIG. 4 according to various embodiments of the present disclosure. The delay line control circuit 410 includes an inverter 804, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a comparator 802.

[0061]

[0074] 8, an inverter 804 is configured to receive a direction control signal SEL and generate an inverted signal SELB of the direction control signal SEL. A first drain / source terminal of a first switch S1 is configured to receive a dc signal VDUTY. A second drain / source terminal of the first switch S1 is connected to a non-inverting input of the comparator 802. A gate of the first switch S1 is controlled by the direction control signal SEL.

[0062]

[0075] A first drain / source terminal of the second switch S2 is configured to receive a reference voltage Vref, and a second drain / source terminal of the second switch S2 is connected to the non-inverting input of the comparator 802. A gate of the second switch S2 is controlled by an inverted signal SELB of the direction control signal SEL.

[0063]

[0076] A first drain / source terminal of the third switch S3 is configured to receive the dc signal VDUTY. A second drain / source terminal of the third switch S3 is connected to the inverting input of the comparator 802. A gate of the third switch S3 is controlled by the inverted signal SELB of the direction control signal SEL.

[0064]

[0077] A first drain / source terminal of the fourth switch S4 is configured to receive a reference voltage Vref. A second drain / source terminal of the fourth switch S4 is connected to the inverting input of the comparator 802. A gate of the fourth switch S4 is controlled by a direction control signal SEL.

[0065]

[0078] In operation, SEL and SELB control the on and off of switches S1, S2, S3, and S4. When SEL is in a logic high state, VDUTY is provided to the non-inverting input of comparator 802 and Vref is provided to the inverting input of comparator 802. On the other hand, when SEL is in a logic low state, VDUTY is provided to the inverting input of comparator 802 and Vref is provided to the non-inverting input of comparator 802. The output of comparator 802 is configured to generate a first control signal VC1.

[0066]

[0079] FIG. 9 illustrates various waveforms associated with the first clock skew calibration unit according to various embodiments of the present disclosure. The horizontal axis of FIG. 9 represents time intervals. There may be eight rows in FIG. 9. Row 1 represents PH0D. Row 2 represents PH90D. Row 3 represents PH180D. Row 4 represents PH270D. Row 5 represents the clock signal CLKOUT. Row 6 represents the first reduced frequency signal CLKDIV2A. Row 7 represents the second reduced frequency signal CLKDIV2B. Row 8 represents the direction control signal SEL.

[0067]

[0080] Referring back to FIG. 1, the multi-phase clock generator 110 is configured to generate PH0, PH90, PH180, and PH270. After PH0, PH90, PH180, and PH270 pass through their respective delay lines, PH0D, PH90D, PH180D, and PH270D are generated and provided to a clock signal skew calibration circuit. In some embodiments, PH180D has a skew. This skew is indicated by the dashed line between t2 and t3.

[0068]

[0081] The clock signal CLKOUT is generated based on PH0D, PH90D, PH180D, and PH270D. As shown in FIG. 9, at t1, CLKOUT changes from a logic high state to a logic low state in response to a rising edge of PH90D and a falling edge of PH270D. At t3, CLKOUT changes from a logic low state to a logic high state (dashed line) in response to a rising edge of PH180D. At t4, CLKOUT changes from a logic high state to a logic low state in response to a rising edge of PH270D and a falling edge of PH90D. At t5, CLKOUT changes from a logic low state to a logic high state in response to a rising edge of PH0D.

[0069]

[0082] There are two reduced frequency signals CLKDIV2A and CLKDIV2B. As shown in Figure 9, the rising edge of CLKDIV2A is aligned with the rising edge of PH0. The rising edge of CLKDIV2B is aligned with the rising edge of PH180D. When PH180D is delayed, the duty cycle of CLKDIV2A is greater than 50% and the duty cycle of CLKDIV2B is less than 50%. Therefore, the skew calibration process has two opposite directions.

[0070]

[0083] Referring back to Figure 8, when the rising edge of the reduced frequency signal is aligned with the rising edge of PH0, SEL has a logic high state. When the rising edge of the reduced frequency signal is aligned with the rising edge of PH180, SEL has a logic low state. When SEL has a logic high state and PH180D is lagging, the duty cycle of the reduced frequency signal is greater than 50%. When SEL has a logic low state and PH180D is lagging, the duty cycle of the reduced frequency signal is less than 50%.

[0071]

[0084] Referring back to FIG. 8, when SEL has a logic high state, VDUTY is connected to the non-inverting input of the comparator 802, and Vref is connected to the inverting input of the comparator 802. Because the duty cycle of the reduced frequency signal is greater than 50%, VDUTY is greater than Vref. Referring back to FIG. 3, increasing VC1 reduces the delay added to PH180. As a result, the skew of PH180 is reduced. When SEL has a logic low state, VDUTY is connected to the inverting input of the comparator 802, and Vref is connected to the non-inverting input of the comparator 802. Because the duty cycle of the reduced frequency signal is less than 50%, VDUTY is less than Vref. Referring back to FIG. 3, increasing VC1 reduces the delay added to PH180. As a result, the skew of PH180 is reduced.

[0072]

[0085] During operation, the skew calibration process has two opposite directions. The direction of the skew calibration process can be determined by sampling the reduced frequency signal using PH90D. For example, PH90D is used to sample CLKDIV2A, resulting in a logic high state. This logic high state indicates that the rising edge of CLKDIV2A is aligned with PH0D. The duty cycle of CLKDIV2A is greater than 50%. After determining this direction of the skew calibration process, the delay line control circuit can reduce the delay added to PH180D to make the duty cycle of CLKDIV2A equal to 50%. When the duty cycle of CLKDIV2A equals 50%, the corresponding delay is the appropriate delay added to PH180D. With this appropriate delay, the output PH180C is the calibrated signal of PH180.

[0073]

[0086] 9 is that the duty cycle of the reduced frequency signal (e.g., CLKDIV2A) is set to 50% by adjusting the delay added to PH180. When the duty cycle of the reduced frequency signal (e.g., CLKDIV2A) is set to 50%, the phase difference between PH0D and PH180C is equal to 180 degrees.

[0074]

[0087] 1 shows a schematic diagram of the second clock skew calibration unit 122 shown in FIG. 1 according to various embodiments of the present disclosure. The second clock skew calibration unit 122 includes a first logic gate 1011, a second logic gate 1021, a first filter 1012, a second filter 1022, and a first comparator 1002. The first logic gate 1011 and the second logic gate 1021 are implemented as AND gates.

[0075]

[0088] The first logic gate 1011 is configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and the second multi-phase clock signal. As shown in Figure 10, the calibrated signal of the first multi-phase clock signal is PH180C. The second multi-phase clock signal is PH90D.

[0076]

[0089] The second logic gate 1021 is configured to perform a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signal. As shown in Figure 10, the reference multi-phase clock signal is PH0D.

[0077]

[0090] The output of the first logic gate 1011 is provided to the non-inverting input of the first comparator 1002 via a first filter 1012. The output of the second logic gate 1021 is provided to the inverting input of the first comparator 1002 via a second filter 1022. Both filters 1012 and 1022 are RC filters similar to filter 412 described above with respect to FIG.

[0078]

[0091] The first comparator 1002 is configured to compare the output of the first logic gate 1011 with the output of the second logic gate 1021 and to generate a second control signal VC2 for adjusting the skew of the second multi-phase clock signal PH90D by adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal PH90C of the second multi-phase clock signal is achieved.

[0079]

[0092] FIG. 11 illustrates various waveforms associated with the second clock skew calibration unit according to various embodiments of the present disclosure. The horizontal axis of FIG. 11 represents time intervals. There may be five rows in FIG. 11. Row 1 represents PH0D. Row 2 represents PH90D. Row 3 represents PH180C. Row 4 represents the result after performing an AND operation on PH0D and PH90D. Row 5 represents the result after performing an AND operation on PH90D and PH180C.

[0080]

[0093] PH90D is the clock signal to be calibrated. PH90D has a skew. This skew is indicated by the dashed line between t1 and t2. The output of the second logic gate 1021 (PH0D & PH90D) has a logic high state from t2 to t3. The output of the first logic gate 1011 (PH90D & PH180C) has a logic high state from t3 to t4. When PH90D is delayed, the duty cycle of the output of the first logic gate 1011 is greater than the duty cycle of the output of the second logic gate 1021. This duty cycle difference can be used to generate a second control signal VC2, as shown in FIG. 10. For example, in response to VC2, the delay added to PH90D is reduced to make the duty cycle of the output of the first logic gate 1011 equal to the duty cycle of the output of the second logic gate 1021. When these two duty cycles are equal, the corresponding delay is the appropriate delay added to PH90. Under this appropriate delay, the output PH90C is the calibrated signal of PH90.

[0081]

[0094] 1 shows a schematic diagram of the third clock skew calibration unit shown in FIG. 1 according to various embodiments of the present disclosure. The third clock skew calibration unit 123 includes a third logic gate 1211, a fourth logic gate 1221, a third filter 1212, a fourth filter 1222, and a second comparator 1202. The third logic gate 1211 and the fourth logic gate 1221 are implemented as AND gates.

[0082]

[0095] The third logic gate 1211 is configured to perform a third AND operation on the reference multi-phase clock signal and the third multi-phase clock signal. As shown in Figure 12, the reference multi-phase clock signal is PH0D. The third multi-phase clock signal is PH270D.

[0083]

[0096] The fourth logic gate 1221 is configured to perform a fourth AND operation on the calibrated signal of the first multi-phase clock signal and the third multi-phase clock signal. As shown in FIG. 12, the calibrated signal of the first multi-phase clock signal is PH180C.

[0084]

[0097] The output of the third logic gate 1211 is provided to the non-inverting input of the second comparator 1202 via a third filter 1212. The output of the fourth logic gate 1221 is provided to the inverting input of the second comparator 1202 via a fourth filter 1222. Both filters 1212 and 1222 are RC filters similar to filter 412 described above with respect to FIG.

[0085]

[0098] The second comparator 1202 is configured to compare the output of the third logic gate 1211 with the output of the fourth logic gate 1221 and to generate a third control signal VC3 to adjust the skew of the third multi-phase clock signal PH270 by adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved.

[0086]

[0099] FIG. 13 illustrates various waveforms associated with the third clock skew calibration unit according to various embodiments of the present disclosure. The horizontal axis of FIG. 13 represents time intervals. There may be five rows in FIG. 13. Row 1 represents PH0D. Row 2 represents PH180C. Row 3 represents PH270D. Row 4 represents the result after performing an AND operation on PH0D and PH270D. Row 5 represents the result after performing an AND operation on PH180C and PH270D.

[0087]

[0100] PH270D is the clock signal to be calibrated. PH270D has a skew. This skew is indicated by the dashed line between t1 and t2. The output of the third logic gate 1211 (PH0D & PH270D) has a logic high state from t3 to t4. The output of the fourth logic gate 1221 (PH180C & PH270D) has a logic high state from t2 to t3. When PH270D is delayed, the duty cycle of the output of the third logic gate 1211 is greater than the duty cycle of the output of the fourth logic gate 1221. This duty cycle difference can be used to generate the third control signal VC3, as shown in FIG. 12. For example, in response to VC3, the delay added to PH270D is reduced to make the duty cycle of the output of the fourth logic gate 1221 equal to the duty cycle of the output of the third logic gate 1211. When these two duty cycles are equal, the corresponding delay is the appropriate delay added to PH270. Under this appropriate delay, the output PH270C is the calibrated signal of PH270.

[0088]

[0101] 14 illustrates a flowchart of the control of the clock signal skew calibration circuit shown in FIG. 1 in accordance with various embodiments of the present disclosure. This flowchart illustrated in FIG. 14 is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, various steps illustrated in FIG. 14 may be added, deleted, substituted, rearranged, and repeated.

[0089]

[0102] 1, the clock signal skew calibration circuit includes a first clock skew calibration unit 121, a second clock skew calibration unit 122, and a third clock skew calibration unit 123. Referring back to FIG. 4, the first clock skew calibration unit 121 includes a frequency multiplier 402, a frequency divider 404, a latch circuit 406, a buffer 408, a delay line control circuit 410, and a filter 412.

[0090]

[0103] In step 1402, a clock signal is generated based on a plurality of multi-phase clock signals by a frequency multiplier.

[0091]

[0104] In step 1404, a reduced frequency signal is generated based on the clock signal by a frequency divider, the reduced frequency signal having a duty cycle indicative of the skew of the first multi-phase clock signal.

[0092]

[0105] In step 1406, the duty cycle of the reduced frequency signal is compared to a predetermined duty cycle.

[0093]

[0106] In step 1408, a first control signal is generated by the delay line control circuitry. The first control signal is used to adjust the skew of the first multi-phase clock signals by adjusting the first delays applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

[0094]

[0107] The method further includes the steps of performing a first AND operation on the calibrated signals of the first multi-phase clock signal and the second multi-phase clock signals, performing a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signals, comparing a result of the first AND operation with a result of the second AND operation, and generating, based on a comparison result from the step of comparing the result of the first AND operation with a result of the second AND operation, a second control signal to adjust skew of the second multi-phase clock signals by adjusting second delays applied to the second multi-phase clock signals until a calibrated signal of the second multi-phase clock signal is achieved.

[0095]

[0108] The method further includes performing a third AND operation on the calibrated signals of the first multi-phase clock signal and the third multi-phase clock signals; performing a fourth AND operation on the reference multi-phase clock signal and the third multi-phase clock signals; comparing a result of the third AND operation with a result of the fourth AND operation; and generating, based on a comparison result from the comparing the result of the third AND operation with the result of the fourth AND operation, a third control signal to adjust skew of the third multi-phase clock signals by adjusting third delays applied to the third multi-phase clock signals until calibrated signals of the third multi-phase clock signals are achieved.

[0096]

[0109] The method further includes generating, by a multi-phase clock generator, four-phase clock signals including a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal, wherein the reference multi-phase clock signal is a 0-degree clock signal, the first multi-phase clock signal is a 180-degree clock signal, the second multi-phase clock signal is a 90-degree clock signal, and the third multi-phase clock signal is a 270-degree clock signal.

[0097]

[0110] In some embodiments, the multi-phase clock generator comprises a first oscillator, a second oscillator, a third oscillator, and a fourth oscillator connected in cascade, and an inverting output of the first oscillator is connected to a non-inverting input of the second oscillator, the inverting output of the first oscillator configured to generate a 270-degree clock signal, and a non-inverting output of the first oscillator is connected to an inverting input of the second oscillator, the inverting output of the second oscillator is connected to a non-inverting input of the third oscillator, the inverting output of the second oscillator configured to generate a 180-degree clock signal. a non-inverting output of the second oscillator connected to an inverting input of a third oscillator, an inverting output of the third oscillator connected to a non-inverting input of a fourth oscillator, the inverting output of the third oscillator configured to generate a 90-degree clock signal, the non-inverting output of the third oscillator connected to an inverting input of the fourth oscillator, the inverting output of the fourth oscillator connected to the non-inverting input of the first oscillator, the inverting output of the fourth oscillator configured to generate a 0-degree clock signal, and the non-inverting output of the fourth oscillator connected to the inverting input of the first oscillator.

[0098]

[0111] In some embodiments, the frequency divider is a latch circuit, and the frequency multiplier comprises a first transmission gate and a second transmission gate, and an input of the first transmission gate is configured to receive a 0-degree clock signal, an output of the first transmission gate is connected to an output of the frequency multiplier, a first control terminal of the first transmission gate is configured to receive a 90-degree clock signal, a second control terminal of the first transmission gate is configured to receive a 270-degree clock signal, an input of the second transmission gate is configured to receive a 180-degree clock signal, an output of the second transmission gate is connected to an output of the frequency multiplier, a first control terminal of the second transmission gate is configured to receive the 270-degree clock signal, and a second control terminal of the second transmission gate is configured to receive the 90-degree clock signal.

[0099]

[0112] The method further includes converting the reduced frequency signal to a dc signal, wherein a voltage of the dc signal is proportional to a duty cycle of the reduced frequency signal, and comparing the voltage of the dc signal to a reference voltage proportional to a predetermined duty cycle to obtain a first control signal.

[0100]

[0113] In some embodiments, the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch, and a third comparator, and the inverter is configured to receive a direction control signal and generate an inverted signal of the direction control signal, a first drain / source terminal of the first switch configured to receive a dc signal, a second drain / source terminal of the first switch connected to a non-inverting input of the third comparator, a gate of the first switch is controlled by the direction control signal, a first drain / source terminal of the second switch configured to receive a reference voltage proportional to a predetermined duty cycle, and a second drain / source terminal of the second switch connected to a non-inverting input of the third comparator. a first drain / source terminal of a fourth switch configured to receive a reference voltage proportional to a predetermined duty cycle; a second drain / source terminal of the fourth switch connected to the inverting input of the third comparator; a gate of the fourth switch controlled by an inverted signal of the direction control signal; a first drain / source terminal of the fourth switch configured to receive a reference voltage proportional to a predetermined duty cycle; a second drain / source terminal of the fourth switch connected to the inverting input of the third comparator; a gate of the fourth switch controlled by an inverted signal of the direction control signal; and an output of the third comparator configured to generate the first control signal.

[0101]

[0114] Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0102]

[0115] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described herein. As will be readily apparent to those skilled in the art from the present disclosure, any now-existing or later-developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein can be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. 1. A clock skew calibration circuit configured to be coupled to a multi-phase clock generator via a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signal and to generate a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicative of a skew of the first multi-phase clock signal; a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved; A clock skew calibration circuit comprising: an apparatus comprising: a second clock skew calibration unit of the clock skew calibration circuit; a first logic gate configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal; a second logic gate configured to perform a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signal; a first comparator configured to compare an output of the first logic gate with an output of the second logic gate and to generate a second control signal to adjust a skew of the second multi-phase clock signals by adjusting a second delay applied to the second multi-phase clock signals until a calibrated signal of the second multi-phase clock signals is achieved; An apparatus comprising:

2. a third clock skew calibration unit of the clock skew calibration circuit, a third logic gate configured to perform a third AND operation on the calibrated version of the first multi-phase clock signal and a third multi-phase clock signal; a fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signals and the third multi-phase clock signals; a second comparator configured to compare an output of the third logic gate with an output of the fourth logic gate and to generate a third control signal for adjusting a skew of the third multi-phase clock signals by adjusting a third delay applied to the third multi-phase clock signals until a calibrated signal of the third multi-phase clock signals is achieved; The apparatus of claim 1 , comprising:

3. the multi-phase clock generator is configured to generate four-phase clock signals including a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal, the reference multi-phase clock signal being the 0-degree clock signal; the first multi-phase clock signal is the 180-degree clock signal; the second multi-phase clock signal is the 90-degree clock signal; the third multi-phase clock signal is the 270-degree clock signal; 3. The device according to claim 1 or 2.

4. the frequency multiplier comprises a first transmission gate and a second transmission gate; an input of the first transmission gate configured to receive the 0 degree clock signal; an output of the first transmission gate connected to an output of the frequency multiplier; a first control terminal of the first transmission gate configured to receive the 90-degree clock signal; a second control terminal of the first transmission gate configured to receive the 270-degree clock signal; an input of the second transmission gate configured to receive the 180 degree clock signal; an output of the second transmission gate connected to the output of the frequency multiplier; a first control terminal of the second transmission gate configured to receive the 270 degree clock signal; a second control terminal of the second transmission gate configured to receive the 90-degree clock signal; 4. An apparatus according to any one of claims 1 to 3.

5. the first clock skew calibration unit: a latch circuit configured to generate a direction control signal; a filter configured to receive the reduced frequency signal and generate a dc signal, the voltage of the dc signal being proportional to the duty cycle of the reduced frequency signal; The apparatus of claim 1 , further comprising:

6. the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch, and a third comparator; the inverter is configured to receive the direction control signal and generate an inverted signal of the direction control signal; a first drain / source terminal of the first switch configured to receive the dc signal; a second drain / source terminal of the first switch connected to the non-inverting input of the third comparator; a gate of the first switch is controlled by the direction control signal; a first drain / source terminal of the second switch configured to receive a reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the second switch connected to the non-inverting input of the third comparator; a gate of the second switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the third switch configured to receive the dc signal; a second drain / source terminal of the third switch connected to an inverting input of the third comparator; a gate of the third switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the fourth switch configured to receive the reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the fourth switch connected to the inverting input of the third comparator; a gate of the fourth switch is controlled by the direction control signal; an output of the third comparator configured to generate the first control signal; 6. An apparatus according to any one of claims 1 to 5.

7. The first delay is generated by a first delay line, and the first delay line comprises: a bias circuit comprising an upper transistor and a lower transistor connected in series between a power supply voltage and ground; a plurality of inverting legs connected in parallel between the power supply voltage and ground, each inverting leg comprising a first transistor, a second transistor, a third transistor, and a fourth transistor connected in series; Equipped with a gate of the first transistor connected to a gate of the upper transistor; a gate of the second transistor and a gate of the third transistor are connected to each other and serve as an input of an inverting leg, and a midpoint of the inverting leg serves as an output of the inverting leg; the gate of the fourth transistor is connected to the gate of the lower transistor; an input of a first inverting leg of the plurality of inverting legs configured to receive the first multi-phase clock signal; an output of the first of the plurality of reversing legs connected to an input of a second of the plurality of reversing legs; an output of a last inverting leg of the plurality of inverting legs configured to generate the calibrated signal of the first multi-phase clock signal; 7. An apparatus according to any one of claims 1 to 6.

8. generating, by a frequency multiplier, a clock signal based on the plurality of multi-phase clock signals; generating, by a frequency divider, a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicative of a skew of the first multi-phase clock signal; comparing the duty cycle of the reduced frequency signal to a predetermined duty cycle; generating, by a delay line control circuit, a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved; performing a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal; performing a second AND operation on a reference multi-phase clock signal and the second multi-phase clock signals; comparing a result of the first AND operation with a result of the second AND operation; generating, based on a comparison result from the step of comparing the result of the first AND operation with the result of the second AND operation, a second control signal for adjusting a skew of the second multi-phase clock signals by adjusting second delays applied to the second multi-phase clock signals until a calibrated signal of the second multi-phase clock signals is achieved; 10. The method of claim 9, further comprising:

9. performing a third AND operation on the calibrated signal of the first multi-phase clock signal and a third multi-phase clock signal; performing a fourth AND operation on the reference multi-phase clock signals and the third multi-phase clock signals; comparing a result of the third AND operation with a result of the fourth AND operation; generating, based on a comparison result from the step of comparing the result of the third AND operation with the result of the fourth AND operation, a third control signal for adjusting a skew of the third multi-phase clock signals by adjusting a third delay applied to the third multi-phase clock signals until a calibrated signal of the third multi-phase clock signals is achieved; The method of claim 8 further comprising:

10. generating, by a multi-phase clock generator, four-phase clock signals including a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal; further comprising the reference multi-phase clock signal is the 0 degree clock signal; the first multi-phase clock signal is the 180-degree clock signal; the second multi-phase clock signal is the 90-degree clock signal; the third multi-phase clock signal is the 270-degree clock signal; 10. The method according to claim 8 or 9.

11. the multi-phase clock generator comprises a first oscillator, a second oscillator, a third oscillator, and a fourth oscillator that are cascaded; an inverted output of the first oscillator connected to a non-inverting input of the second oscillator, the inverted output of the first oscillator configured to generate the 270 degree clock signal; a non-inverting output of the first oscillator connected to an inverting input of the second oscillator; an inverted output of the second oscillator connected to a non-inverting input of the third oscillator, the inverted output of the second oscillator configured to generate the 180 degree clock signal; a non-inverting output of the second oscillator connected to an inverting input of the third oscillator; an inverted output of the third oscillator connected to a non-inverting input of the fourth oscillator, the inverted output of the third oscillator configured to generate the 90-degree clock signal; a non-inverting output of the third oscillator connected to an inverting input of the fourth oscillator; an inverted output of the fourth oscillator connected to the non-inverting input of the first oscillator, the inverted output of the fourth oscillator configured to generate the 0 degree clock signal; a non-inverting output of the fourth oscillator connected to an inverting input of the first oscillator; 11. The method according to any one of claims 8 to 10.

12. the frequency divider is a latch circuit; the frequency multiplier comprises a first transmission gate and a second transmission gate; an input of the first transmission gate configured to receive the 0 degree clock signal; an output of the first transmission gate connected to an output of the frequency multiplier; a first control terminal of the first transmission gate configured to receive the 90-degree clock signal; a second control terminal of the first transmission gate configured to receive the 270-degree clock signal; an input of the second transmission gate configured to receive the 180 degree clock signal; an output of the second transmission gate connected to the output of the frequency multiplier; a first control terminal of the second transmission gate configured to receive the 270 degree clock signal; a second control terminal of the second transmission gate configured to receive the 90-degree clock signal; 12. The method according to any one of claims 8 to 11.

13. converting the reduced frequency signal to a dc signal, the voltage of the dc signal being proportional to the duty cycle of the reduced frequency signal; comparing the voltage of the dc signal to a reference voltage proportional to the predetermined duty cycle to obtain the first control signal; 13. The method of any one of claims 8 to 12, further comprising:

14. the delay line control circuit comprises an inverter, a first switch, a second switch, a third switch, a fourth switch, and a third comparator; the inverter is configured to receive a direction control signal and generate an inverted version of the direction control signal; a first drain / source terminal of the first switch configured to receive the dc signal; a second drain / source terminal of the first switch connected to the non-inverting input of the third comparator; a gate of the first switch is controlled by the direction control signal; a first drain / source terminal of the second switch configured to receive the reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the second switch connected to the non-inverting input of the third comparator; a gate of the second switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the third switch configured to receive the dc signal; a second drain / source terminal of the third switch connected to an inverting input of the third comparator; a gate of the third switch is controlled by the inverted signal of the direction control signal; a first drain / source terminal of the fourth switch configured to receive the reference voltage proportional to the predetermined duty cycle; a second drain / source terminal of the fourth switch connected to the inverting input of the third comparator; a gate of the fourth switch is controlled by the direction control signal; an output of the third comparator configured to generate the first control signal; 14. The method according to any one of claims 8 to 13.

15. a multi-phase clock generator configured to generate a plurality of multi-phase clock signals; a plurality of delay lines configured to receive respective multi-phase clock signals; a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via the plurality of delay lines, the clock skew calibration circuit comprising: a first clock skew calibration unit, a second clock skew calibration unit, and a third clock skew calibration unit, the first clock skew calibration unit comprising: a frequency multiplier configured to receive the plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signal and to generate a reduced frequency signal based on the clock signal, the reduced frequency signal having a duty cycle indicative of a skew of the first multi-phase clock signal; a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal for adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved; a clock skew calibration circuit comprising: A system comprising:

16. the second clock skew calibration unit of the clock skew calibration circuit a first logic gate configured to perform a first AND operation on the calibrated signal of the first multi-phase clock signal and a second multi-phase clock signal; a second logic gate configured to perform a second AND operation on the reference multi-phase clock signal and the second multi-phase clock signal; a first comparator configured to compare the output of the first logic gate with the output of the second logic gate and to generate a second control signal for adjusting a second delay applied to the second multi-phase clock signal until a calibrated signal of the second multi-phase clock signal is achieved; Equipped with the third clock skew calibration unit of the clock skew calibration circuit, a third logic gate configured to perform a third AND operation on the calibrated version of the first multi-phase clock signal and a third multi-phase clock signal; a fourth logic gate configured to perform a fourth AND operation on the reference multi-phase clock signals and the third multi-phase clock signals; a second comparator configured to compare the output of the third logic gate with the output of the fourth logic gate and to generate a third control signal for adjusting a third delay applied to the third multi-phase clock signal until a calibrated signal of the third multi-phase clock signal is achieved; Equipped with The system of claim 15.

17. the multi-phase clock generator is configured to generate four-phase clock signals including a 0-degree clock signal, a 90-degree clock signal, a 180-degree clock signal, and a 270-degree clock signal; the reference multi-phase clock signal is the 0 degree clock signal; the first multi-phase clock signal is the 180-degree clock signal; the second multi-phase clock signal is the 90-degree clock signal; the third multi-phase clock signal to be calibrated is the 270-degree clock signal; 17. A system according to claim 15 or 16.

18. a first delay line of the plurality of delay lines configured to receive the zero degree clock signal and a predetermined reference signal and to add a predetermined delay to the zero degree clock signal based on the predetermined reference signal; a second delay line of the plurality of delay lines configured to receive the 180-degree clock signal and the first control signal, and to add the first delay to the 180-degree clock signal based on the first control signal; a third delay line of the plurality of delay lines configured to receive the 90-degree clock signal and the second control signal, and to add the second delay to the 90-degree clock signal based on the second control signal; a fourth delay line of the plurality of delay lines configured to receive the 270-degree clock signal and the third control signal, and to add the third delay to the 270-degree clock signal based on the third control signal; 18. A system according to any one of claims 15 to 17.

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