Pre-textured silicon wafers and methods for making same, textured wafers, and solar cells

Abstract

A pre-textured silicon wafer, a method for producing the same, a textured wafer, and a solar cell are provided. The pre-textured silicon wafer includes a substrate layer and a pre-textured layer provided on at least one surface of the substrate layer, the pre-textured layer including a plurality of protrusions, each of which has a truncated quadrangular pyramid shape, and the length of the base of the protrusion is in the range of 2 μm to 8 μm.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202211732332.X, entitled "PRE-TEXTURED SILICON WAFER AND PREPARATION METHOD THEREOF, TEXTURED WAFER, AND SOLAR CELL," filed with the State Intellectual Property Office of the People's Republic of China on December 30, 2022, which is incorporated herein by reference in its entirety.

[0002] This application relates to the field of solar cell technology, and in particular to pre-textured silicon wafers and methods for making same, textured wafers, and solar cells. [Background technology]

[0003] Solar cells are one of the key approaches to alleviating the global energy crisis and environmental pollution. Heterojunction cells are gradually becoming the future development direction for solar cells due to their high photoelectric conversion efficiency, high bifaciality, almost no light-induced degradation, good temperature characteristics, and simple fabrication process. The heterojunction is formed by depositing an amorphous silicon film on a crystalline silicon layer. The distribution of light-trapping structures on the textured surface of the crystalline silicon layer directly affects the cell performance.

[0004] Currently, silicon wafers for heterojunction cells must undergo rough polishing, texturing, chamfering, passivation using hydrofluoric acid, and other processes. The rough polishing process can completely remove the damaged layer on the surface of the silicon wafer caused by the cutting process, and the structures formed on the rough polished surface of the silicon wafer can be used as a basis to form light-capturing structures on the silicon wafer during subsequent texturing. In conventional technologies, a strong alkali with a concentration of about 5 wt. % is typically used to rough polish the silicon wafer to completely remove the aforementioned damaged layer. However, this results in large sizes and low distribution density of the ultimately formed light-capturing structures, as well as large size differences among multiple light-capturing structures, which increases the internal resistance of the final cell and affects the performance of typical cells. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of this, this application provides a pre-textured silicon wafer and a method for fabricating the same. A textured wafer having a textured surface layer with high flatness and low contact resistance can be smoothly produced from the pre-textured silicon wafer. Therefore, the pre-textured silicon wafer can be used to provide solar cells with excellent performance. [Means for solving the problem]

[0006] A first aspect of the present application provides a pre-textured silicon wafer including a substrate layer and a pre-textured layer provided on at least one surface of the substrate layer, wherein the pre-textured layer includes a plurality of protrusions, each of which has a truncated quadrangular pyramid shape, and the length of the base of the protrusion is in the range of 2 μm to 8 μm.

[0007] The protrusion structures of the pre-textured silicon wafer are in the shape of a truncated quadrangular pyramid, and the length of the base of the protrusion structures is controlled in the range of 2 μm to 8 μm. In this way, the protrusions can form small, densely spaced light-trapping structures in the subsequent texturing process, thereby improving the flatness of the textured surface of the textured wafer and reducing the contact resistance of the textured surface of the textured wafer. Therefore, the pre-textured silicon wafer can be used to provide solar cells with low internal resistance.

[0008] In one embodiment, the nucleation sites are distributed on the sidewalls of the protrusions.

[0009] In one embodiment, the nucleation sites are square pyramids with a maximum cross-sectional width in the range of 0 μm to 1 μm and a height in the range of 0 μm to 0.75 μm.

[0010] In one embodiment, the pre-textured layer has a thickness of 100 μm 2 Each contains 2 to 11 projections.

[0011] In one embodiment, the height of the protrusions is in the range of 0.5 μm to 2 μm.

[0012] In one embodiment, the cross-sectional size of the protrusions gradually decreases in a direction away from the substrate layer.

[0013] A second aspect of the present application provides a method for making a pre-textured silicon wafer, the method comprising the steps of:

[0014] Sequentially subjecting a raw material of a textured wafer to cleaning and alkaline polishing treatments to obtain a pre-textured silicon wafer, wherein the pre-textured silicon wafer includes a substrate layer and a pre-textured layer provided on at least one surface of the substrate layer, the pre-textured layer including a plurality of protrusions, each of which has a shape of a truncated square pyramid.

[0015] The alkaline polishing treatment includes the following conditions: alkaline etching of the silicon wafer with a 15% to 30% by weight strong alkaline solution, the duration of the alkaline polishing treatment is 40 to 120 seconds, and the temperature of the alkaline polishing treatment is 50°C to 80°C.

[0016] This fabrication method has simple steps, high process reliability, and high production efficiency, and is applicable to large-scale industrial production.

[0017] In one embodiment, subjecting the silicon wafer to sequential cleanings includes:

[0018] Cleaning a silicon wafer with a first cleaning solution at a cleaning temperature of 60°C to 90°C for a cleaning duration of 5 to 20 minutes, wherein the first cleaning solution contains hydrogen peroxide and aqueous ammonia, the aqueous ammonia having a concentration of about 2% to about 10% by weight and the hydrogen peroxide having a concentration of about 2% to about 10% by weight, and further cleaning the silicon wafer with a second cleaning solution at a cleaning temperature of 60°C to 90°C for a cleaning duration of 5 to 20 minutes, wherein the second cleaning solution is an aqueous solution of hydrochloric acid and hydrogen peroxide, the concentrations of both the hydrochloric acid and the hydrogen peroxide being 2% to 10% by weight.

[0019] A third aspect of this application provides a textured wafer. The textured wafer is fabricated from the pre-textured silicon wafer provided by the first aspect of this application. The textured surface of the textured wafer has high flatness, which facilitates the deposition of another film layer (such as an amorphous silicon film layer or a transparent oxide layer) and the subsequent adhesion of the other film layer to the bus bars and fingers in subsequent cell fabrication steps.

[0020] In one embodiment, the textured wafer includes a substrate layer and a textured surface layer disposed on at least one surface of the substrate layer, the textured surface layer including densely arranged light capture structures, the maximum cross-sectional width of the light capture structures being in the range of 1 μm to 4 μm.

[0021] In one embodiment, the light capture structures are pyramidal in shape, with the largest cross-sectional dimension of the light capture structures gradually decreasing in a direction away from the substrate layer.

[0022] In one embodiment, the textured surface layer is 100 μm 2 Each contains 60 to 100 light-capturing structures.

[0023] In one embodiment, the height of the light trapping structures ranges from 1.23 μm to 1.58 μm.

[0024] In one embodiment, adjacent light capture structures are spaced apart.

[0025] A fourth aspect of the present application provides a solar cell comprising the textured wafer provided by the third aspect of the present application. [Brief explanation of the drawings]

[0026] [Figure 1]FIG. 1 is a diagram of the principle by which light-trapping structures are gradually formed from protrusions during the texturing process. [Figure 2A] FIG. 2A is a scanning electron microscopy (SEM) image of a pre-textured silicon wafer according to Example 1 of this application. [Figure 2B] FIG. 2B is an SEM image of a cross section of a pre-textured silicon wafer according to Example 1 of this application. [Figure 2C] FIG. 2C is an SEM image of a cross section of a textured wafer according to Example 1 of this application. [Figure 3A] FIG. 3A is an SEM image of a cross section of a pre-textured silicon wafer according to Example 5 of this application. [Figure 3B] FIG. 3B is an SEM image of a cross section of a textured wafer according to Example 5 of this application. [Figure 4A] FIG. 4A is an SEM image of a cross section of a pre-textured silicon wafer according to Comparative Example 1 of this application. [Figure 4B] FIG. 4B is an SEM image of a cross section of a textured wafer according to Comparative Example 1 of this application. [Figure 5] FIG. 5 is an image of an electrode pattern for testing the contact resistance between each textured wafer and the electrode according to this application. [Figure 6] FIG. 6 is a diagram of the structure of a solar cell. DETAILED DESCRIPTION OF THE INVENTION

[0027] An embodiment of this application provides a pre-textured silicon wafer 1 including a substrate layer 10 and a pre-textured layer provided on at least one surface of the substrate layer. The pre-textured layer includes a plurality of protrusions 201, each of which has a truncated quadrangular pyramid shape, and the length of the base of the protrusion is in the range of 2 μm to 8 μm. In this application, the length of the base of the protrusion is understood to be the length of the intersection line between the protrusion and the substrate layer, i.e., the maximum width of the cross section of the protrusion.

[0028] See Figure 1. The pre-textured layer of the pre-textured silicon wafer contains multiple protrusions in the shape of a truncated square pyramid. During the subsequent texturing process, the texturing solution further corrodes the protrusions, gradually forming light-capturing structures, as shown in Figure 1(a). The black dotted outline in the figure represents the front-view outline of a theoretically possible light-capturing structure. The base length of the protrusions is controlled to be within the aforementioned range, thereby reducing the likelihood of adjacent light-capturing structures bonding when the protrusions are further etched to form the light-capturing structures during the subsequent texturing process, thereby controlling the size of the light-capturing structures. In this case, the final light-capturing structures have small size, high distribution density, and uniform size distribution, which allows the textured surface to have high flatness and low contact resistance. Therefore, pre-textured silicon wafers can be used to provide solar cells with low internal resistance and high photoelectric conversion efficiency.

[0029] As shown in Figure 1(b), if the base length of the protrusions is too short (less than 2 μm), the bonding of neighboring growing light-capturing structures is likely to ultimately result in the formation of excessively large light-capturing structures, resulting in a small number and low density of light-capturing structures on the final textured surface. This results in large undulations and low flatness on the textured surface, as well as large differences in size between the multiple light-capturing structures. As a result, the internal resistance of the final solar cell will be excessively high. As shown in Figure 1(c), if the base length of the protrusions is too long (more than 8 μm), the growing light-capturing structures may not be affected by steric hindrance from other growing light-capturing structures, resulting in a large number, small number, and low density of light-capturing structures on the final textured surface, resulting in excessively large undulations on the surface of the textured layer. This also does not contribute to the performance of the final solar cell.

[0030] The length of the base of the protrusion may be, for example, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, etc.

[0031] In some embodiments of this application, nucleation sites 202 are distributed on the sidewalls of the protrusions. In this way, the texturing solution can more easily etch the protrusions during subsequent texturing based on the nucleation sites, smoothly forming "small, dense, and uniformly sized" light-trapping structures. In some embodiments of this application, the nucleation sites 202 are specifically small raised structures with a maximum cross-sectional width w of more than 0 μm and less than or equal to 1 μm and a height h of more than 0 μm and less than or equal to 0.75 μm. In some embodiments, the small raised structures are square pyramids, i.e., "small pyramids." In scanning electron microscope (SEM) images of pre-textured silicon wafers, the nucleation sites appear as "small white spots" of a certain size (e.g., 1 μm) with obvious tip and edge effects on the contrast of secondary or backscattered electrons. In some other embodiments, the nucleation sites 202 may be speck-shaped structures attached to the sidewalls A and B of the protrusions, with a maximum cross-sectional width w equal to 0 and a height h equal to 0.

[0032] In some embodiments of the present application, the height of the protrusions is in the range of 0.5 μm to 2 μm. Thus, once the nucleation sites on the sidewalls begin to "grow," the height of the protrusions is controlled to be within the aforementioned range, thereby ensuring that the distance between any given point on each of the sidewalls A and B, which are located opposite each other on the protrusions, falls within an appropriate range. In other words, the distance between the nucleation sites on sidewall A and the nucleation sites on sidewall B of the protrusions is controlled to be within an appropriate range. This further contributes to obtaining textured wafers with high surface flatness. The height of the protrusions may be, for example, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 1.9 μm, 2 μm, etc.

[0033] In some embodiments of this application, the cross-sectional size of the protrusions gradually decreases in a direction away from the substrate layer, so that the "frustums" are provided upright on the substrate layer, and the resulting light capture structures are also provided upright on the substrate layer, which further contributes to multiple absorption of light.

[0034] In some embodiments of this application, the pre-textured layer has a thickness of 100 μm 2 In this way, the protrusion structures of the pre-textured layer are densely distributed, so that the nucleation sites have a more suitable distribution density, which is more conducive to obtaining a textured wafer with high surface flatness. 2 The number of protrusions per unit may be, for example, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, etc.

[0035] In some embodiments of this application, when the raw material of the silicon wafer is crystalline silicon, a first crystal face of the crystalline silicon is exposed on the sidewall of the protrusion, and a second crystal face of the crystalline silicon is exposed on the top surface of the protrusion.

[0036] In order to fabricate the pre-textured silicon wafer provided in the embodiments of this application, an embodiment of this application provides a method for fabricating a pre-textured silicon wafer, which includes the following steps:

[0037] A pre-textured silicon wafer is obtained by sequentially subjecting a raw material for a textured wafer to cleaning and alkaline polishing treatment. The alkaline polishing includes etching at least one surface of the raw material for a textured wafer with a strong alkali having a concentration of 15% by weight to 30% by weight, the duration of the alkaline polishing being 40 seconds to 120 seconds, and the temperature of the alkaline polishing being 50°C to 80°C. The pre-textured silicon wafer thus obtained includes a substrate layer and a pre-textured layer provided on at least one surface of the substrate layer, the pre-textured layer including a plurality of protrusions, each of which has a shape of a truncated quadrangular pyramid.

[0038] During the aforementioned alkaline polishing, a strong alkali of 15% to 30% by weight simultaneously etches the first and second crystal faces of the crystalline silicon at comparable etching rates, allowing for rapid etching and removal of damaged layers of the crystalline silicon. Additionally, the first crystal face of the crystalline silicon is vertical, while the second crystal face has an inclination angle of approximately 54°. In this case, tetrahedral structures are continuously formed on the surface of the crystalline silicon during alkaline polishing, and the alkaline solution continuously etches the tops of the tetrahedral structures to form a flat upper surface. Therefore, the continuous, balanced etching in the two etching directions results in protrusions in the shape of a square truncated pyramid. If the concentration of the alkaline polishing solution is too low, the etching rates of different crystal faces of the crystalline silicon differ, resulting in the failure to produce protrusions in the shape of a square truncated pyramid, which is not conducive to the fabrication of highly flat, textured wafers. If the concentration of the alkaline polishing liquid is too high, the corrosiveness will be too strong, resulting in the edges of the protrusions in the shape of a truncated square pyramid being too long, which does not contribute to obtaining a uniformly textured surface.

[0039] In addition, the duration of alkaline polishing and the temperature of alkaline polishing are controlled to be 40 to 120 seconds and 50 to 80°C, respectively. Through the synergistic effects of the three factors of the concentration of the alkaline polishing solution, the duration of alkaline polishing, and the temperature of alkaline polishing, the base length of the protrusions (i.e., the maximum width of the cross-section of the protrusions) can be controlled to be in the range of 2 μm to 8 μm, thereby subsequently achieving a highly flat textured surface. If the duration of alkaline polishing is less than 40 seconds, the etching amount is insufficient to completely remove the damaged layer (i.e., many obvious cutting lines remain on the surface of the final textured wafer), and the aforementioned protrusions are insufficient to be obtained. If the duration of alkaline polishing exceeds 120 seconds, the etching amount is too large, resulting in an excessively long base length of each protrusion, and as a result, a highly flat textured surface cannot be obtained. If the temperature of alkaline polishing is too low, the aforementioned square pyramid-shaped protrusion structures cannot be obtained, and the damaged layer cannot be sufficiently removed. It is understood that the higher the temperature of alkaline polishing, the faster the etching rate. However, if the temperature of alkaline polishing is too high, the etching rate will be too fast, and the processing conditions will become uncontrollable, so that the shape and size of the protrusions cannot be adjusted.

[0040] The duration of the alkaline polishing may be, for example, 40 seconds, 50 seconds, 60 seconds, 70 seconds, 80 seconds, 90 seconds, 100 seconds, 110 seconds, 120 seconds, and the like.

[0041] The temperature of the alkaline polishing may be, for example, 50°C, 52°C, 55°C, 57°C, 60°C, 62°C, 65°C, 68°C, 70°C, 72°C, 75°C, 78°C, and the like.

[0042] The above-mentioned fabrication method has simple steps and strong process reliability, so that the damaged layer of the silicon wafer can be efficiently and completely removed, where "completely removing the damaged layer" means that almost no cutting lines are observed in the final product, and protrusions of appropriate size can be obtained, so that nucleation sites can be enlarged to form light trapping structures of appropriate size.

[0043] In some embodiments of this application, the alkaline solution further etches the sidewalls of the protrusions to form nucleation sites on the sidewalls of the protrusions, thus contributing to obtaining a smoother, more evenly textured surface layer from the pre-textured layer.

[0044] An embodiment of the present application further provides a textured wafer 2 including a substrate 10 and a textured surface provided on at least one surface of the substrate, wherein the textured surface layer includes densely arranged light-capturing structures, the maximum cross-sectional width of the light-capturing structures being in the range of 1 μm to 4 μm. The maximum cross-sectional width of the light-capturing structures may be, for example, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 3.8 μm, etc.

[0045] These light-capturing structures are densely arranged on the textured wafer surface, resembling a mountain range. After incident light strikes the first side of a light-capturing structure, the reflected light strikes the surface of an adjacent light-capturing structure again, resulting in a second round of light absorption, and then n additional rounds of light absorption. Specifically, the small size and high density of the light-capturing structures allow light to be more easily reflected and absorbed multiple times between different light-capturing structures, thereby enabling the textured wafer to achieve low reflectivity. Additionally, the resulting textured surface has low undulations and high flatness due to the small size and high density of the light-capturing structures, which facilitates the deposition of additional film layers (such as amorphous silicon or transparent oxide layers) in subsequent cell fabrication processes, as well as their adhesion to the bus bars and fingers. This helps reduce the cell's internal resistance and further improves the cell's photoelectric conversion efficiency.

[0046] In this application, a textured wafer may include a textured surface layer on both opposing sides, or may include a textured surface layer on one side and a polished surface on the other side.

[0047] In some embodiments of this application, the textured surface layer has a thickness of 100 μm 2 The density of the light trapping structures in the textured surface layer is thus in a more appropriate range, which further contributes to improving the flatness of the textured surface and thus further improving the photoelectric conversion efficiency of the cell. 2 The number of light capture structures per unit area may be, for example, 60, 65, 70, 75, 80, 85, 90, 95, 100, etc.

[0048] In some embodiments of this application, adjacent light-capturing structures are spaced apart. It will be appreciated that there is a clear boundary between the bottom edge of one light-capturing structure and the bottom edge of an adjacent light-capturing structure, but there is little or no gap. In this way, the density of light-capturing structures in the textured surface layer is increased, and the flatness of the textured surface is increased, which further contributes to improving the photoelectric conversion efficiency of the final solar cell.

[0049] In some embodiments of this application, the light capture structure is a square pyramid shape, and the maximum cross-sectional size of the light capture structure gradually decreases in a direction away from the substrate layer. The light capture structure thus has an upright "pyramid" shape, which is more conducive to multiple absorption of light. In this application, "square pyramid shape" specifically means that the light capture structure is square pyramid-shaped throughout, but has straight or curved side edges and flat or curved sidewalls. In this case, the maximum cross-sectional width of the light capture structure is the length of the base of the square pyramid structure, i.e., the intersection line between the square pyramid structure and the substrate layer.

[0050] In some embodiments of the present application, the height of the light-capturing structures is in the range of 1.23 μm to 1.58 μm. In this way, the undulations of the textured surface layer are also controlled to be within the aforementioned range, resulting in a textured surface layer with higher flatness. In addition, as an example, a light-capturing structure in the shape of a square pyramid is used, in which the length of the base of the light-capturing structure is in the range of 1 μm to 4 μm and the height of the light-capturing structure is controlled to be within the aforementioned range, thereby controlling the tilt angle between the sidewall of the light-capturing structure and the substrate layer to be within an appropriate range that is more conducive to multiple absorption of light. The height of the light trapping structures may be, for example, 1.23 μm, 1.25 μm, 1.27 μm, 1.3 μm, 1.32 μm, 1.35 μm, 1.37 μm, 1.4 μm, 1.42 μm, 1.45 μm, 1.47 μm, 1.5 μm, 1.52 μm, 1.55 μm, 1.58 μm, etc.

[0051] In some specific embodiments, the preparation of the aforementioned textured wafer comprises the following steps:

[0052] S01: A silicon wafer is cleaned with cleaning solution 1 (also referred to as the first cleaning solution) at a cleaning temperature of 60°C to 90°C for a cleaning duration of 5 to 20 minutes, where cleaning solution 1 contains hydrogen peroxide and aqueous ammonia, with the concentration of aqueous ammonia being about 2% to 10% by weight and the concentration of hydrogen peroxide being about 2% to 10% by weight. It is understood that organic contaminants are inevitably mixed in during the production, transportation, and storage of silicon wafers, and these organic contaminants interfere with subsequent processes. Hydrogen peroxide can oxidize and decompose organic contaminants into small molecules, and aqueous ammonia can form complexes with small molecules to dissolve them. Thus, the organic contaminants are removed.

[0053] S02: The silicon wafer is further cleaned using cleaning solution 2 (also referred to as the second cleaning solution) at a cleaning temperature of 60°C to 90°C for a cleaning duration of 5 to 20 minutes, where cleaning solution 2 is an aqueous solution of hydrochloric acid and hydrogen peroxide, and the concentrations of both hydrochloric acid and hydrogen peroxide are 2% by weight to 10% by weight. It is understood that metal contaminants remain on the surface of the silicon wafer. Metals introduce intermediate levels into the band gap of single-crystal silicon and act as strong carrier recombination centers. The aforementioned metal contaminants can be removed by using strong acids and strong oxidizing agents.

[0054] S03: Alkaline polishing. A silicon wafer is sequentially subjected to cleaning and alkaline polishing processes to obtain a pre-textured silicon wafer. The pre-textured silicon wafer includes a substrate layer and a pre-textured layer provided on at least one surface of the substrate layer, the pre-textured layer including a plurality of protrusions, each of which has a truncated square pyramid shape, and nucleation sites distributed on at least one sidewall of the protrusion.

[0055] The alkaline polishing treatment includes the following conditions: the silicon wafer is subjected to alkaline etching with a 15% to 30% by weight strong alkaline solution, the duration of the alkaline polishing treatment is 40 to 120 seconds, and the temperature of the alkaline polishing is 50°C to 80°C.

[0056] S04: Pre-cleaning. The pre-cleaning solution is a mixture of KOH and H2O2. The KOH concentration is about 0.5% by weight to about 5% by weight, and the H2O2 concentration is about 1% by weight to about 10% by weight. The cleaning temperature is 40°C to 80°C, and the cleaning duration is about 120 seconds to about 360 seconds. It should be understood that the surface of the silicon wafer is inevitably contaminated with organic substances, such as oily contaminants, due to the previous process. This will affect the subsequent contact between the texturing solution and the silicon wafer, so the organic substances must be removed. In this case, H2O2 can oxidize the organic substances, and the diluted KOH can dissolve the oxidized organic substances.

[0057] S05: Texturing. The texturing temperature is about 60°C to about 90°C, and the texturing duration is 6 to 15 minutes. The texturing solution is a mixture of a strong alkali and an organic additive. The concentration of the strong alkali (KOH and / or NaOH) is about 1% to about 10% by weight. In some specific embodiments, the texturing solution further contains an organic additive (such as glycerol, ethylene glycol, or propanol). The mass percentage of the organic additive in the texturing solution is greater than 0% by weight and less than or equal to 5% by weight. Crystalline silicon can be anisotropically etched using a texturing solution in this concentration range, and the aforementioned protrusion structures can be etched into "pyramidal" light-trapping structures, resulting in a textured surface layer.

[0058] S06: First post-cleaning. The process parameters are the same as those of S04, and the same pre-cleaning solution is used. This can remove organic additives remaining from the previous texturing process.

[0059] S07: Chamfering. The texturing process creates sharp edges at the top and bottom of the "pyramid." This structure does not contribute to the subsequent film coating and screen printing processes. In the chamfering process, acid etching transforms the sharp edges into chamfered corners of a specific curvature. The etching solution used is an aqueous solution of concentrated nitric acid and hydrofluoric acid. The volume percentage of hydrofluoric acid is less than 1%. The process temperature is 5°C to 20°C, and the process duration is 1 to 10 minutes.

[0060] S08: Second post-cleaning. After the previous process, metal contaminants may still remain on the surface of the silicon wafer, and these must be removed. The cleaning temperature is 50°C to 70°C, and the cleaning duration is 1 to 3 minutes. The cleaning solution used is an aqueous solution of hydrochloric acid and hydrogen peroxide, with the concentrations of both hydrochloric acid and hydrogen peroxide being 1% to 10% by weight.

[0061] S09: Passivation using hydrofluoric acid. After the previous process, a textured wafer is produced. However, silicon wafers naturally oxidize in air, forming a thin layer of silicon dioxide. In this case, the silicon wafer is immersed in hydrofluoric acid to form a protective film consisting of a monolayer of fluorine atoms on the surface of the silicon wafer, preventing oxidation of the silicon wafer. The textured wafer is then slowly removed from the water, ensuring that no water droplets remain.

[0062] S10: Drying After all steps, the textured wafer is blown dry with nitrogen.

[0063] As shown in Figure 6, an embodiment of the present application further provides a solar cell 100 including the textured wafer 2 provided in the embodiment of the present application. By using the textured wafer provided in the embodiment of the present application, the solar cell has low internal resistance and high photoelectric conversion efficiency.

[0064] In some embodiments of the present application, the solar cell comprises a heterojunction cell. In some specific embodiments, the heterojunction cell comprises, in order, a conductive oxide layer, a P-type amorphous silicon film layer, an intrinsic hydrogen-rich amorphous silicon film layer, a textured wafer layer, an intrinsic hydrogen-rich amorphous silicon film layer, an N-type amorphous silicon film layer, and a conductive oxide layer. In some embodiments, a bus bar and a finger layer are further provided on the conductive oxide layer.

[0065] The amorphous silicon membrane layer and the conductive oxide layer may be fabricated by deposition methods, and the busbar and finger layers may be fabricated by screen printing. [Example]

[0066] The technical solutions of this application are further illustrated below with several examples.

[0067] Example 1 S01: A silicon wafer was cleaned with cleaning solution 1 at a cleaning temperature of 80° C. for a cleaning duration of 10 minutes. Cleaning solution 1 contains hydrogen peroxide and aqueous ammonia, with the concentration of aqueous ammonia being 3% by weight and the concentration of hydrogen peroxide being 6% by weight.

[0068] S02: The silicon wafer was further cleaned with cleaning solution 2 at a cleaning temperature of 80° C. for a cleaning duration of 10 minutes. Cleaning solution 2 is an aqueous solution of hydrochloric acid and hydrogen peroxide, with a concentration of hydrochloric acid of 4 wt % and a concentration of hydrogen peroxide of 6 wt %.

[0069] S03: 44 mL of 50 wt% KOH solution was mixed with 106 mL of water to obtain an alkaline polishing solution (having a KOH concentration of approximately 20 wt%). The silicon wafer cleaned in S02 was immersed in the alkaline polishing solution at 80°C for 60 seconds to obtain a pre-textured silicon wafer. The pre-textured silicon wafer had a pre-textured layer, and the surface of the pre-textured layer had a plurality of closely spaced protrusions, each in the shape of a truncated square pyramid.

[0070] S04: The pre-textured silicon wafer obtained in S03 was cleaned using a mixture of KOH and H2O2. The concentration of KOH was about 1 wt % and the concentration of H2O2 was about 5 wt %. The cleaning temperature was 65 °C and the duration of cleaning was about 240 s.

[0071] S05: A cleaned, pre-textured silicon wafer was immersed in a texturing solution at 80°C for 480 seconds. The texturing solution was a mixture of KOH and TS53™. The concentration of KOH was 2% by weight, and the concentration of TS53 was approximately 1% by weight.

[0072] S06: First post-cleaning, the process parameters are the same as those of S04, and the same pre-cleaning solution is used.

[0073] S07: Chamfering. The etching solution used is an aqueous solution of concentrated nitric acid and hydrofluoric acid. The volume percentage of hydrofluoric acid is less than 1%. The temperature of the process is 12°C and the duration of the process is 4 minutes.

[0074] S08: Second post-wash. The wash temperature is 60°C, and the wash duration is 2 minutes. The wash liquid used is an aqueous solution of hydrochloric acid and hydrogen peroxide, and the concentrations of both hydrochloric acid and hydrogen peroxide are 5% by weight.

[0075] S09: Passivation with hydrofluoric acid.

[0076] S10: The textured wafer was blown dry with nitrogen to obtain the textured wafer in Example 1.

[0077] Example 2 The only difference from Example 1 is that in S03, the alkaline polishing solution is 15 wt % KOH, the duration of alkaline polishing is 60 seconds, and the temperature of alkaline polishing is 65° C. The obtained pre-textured silicon wafer has a pre-textured layer, and the surface of the pre-textured layer has a plurality of closely arranged protrusions, each in the shape of a truncated square pyramid.

[0078] Example 3 The difference from Example 1 is that in S03, the alkaline polishing solution is 30 wt % KOH, the duration of alkaline polishing is 60 seconds, and the temperature of alkaline polishing is 65° C. The obtained pre-textured silicon wafer has a pre-textured layer, and the surface of the pre-textured layer has a plurality of closely arranged protrusions, each in the shape of a truncated square pyramid.

[0079] Example 4 The difference from Example 1 is that in S03, the duration of alkaline polishing is 40 seconds, wherein the obtained pre-textured silicon wafer has a pre-textured layer, the surface of which has a plurality of closely arranged protrusions, each of which has the shape of a truncated square pyramid; and in S05, the obtained pre-textured silicon wafer is immersed in a texturing solution at 80°C for 360 seconds to obtain the textured wafer provided in Example 4.

[0080] Example 5 The difference from Example 1 is that the duration of alkaline polishing in S03 is 100 seconds. The obtained pre-textured silicon wafer has a pre-textured layer, and the surface of the pre-textured layer has a plurality of closely arranged protrusions, each of which has the shape of a truncated square pyramid.

[0081] Example 6 The difference from Example 1 is that in S03, the temperature of alkaline polishing is 55° C. The obtained pre-textured silicon wafer has a pre-textured layer, and the surface of the pre-textured layer has a plurality of closely arranged protrusions, each of which is in the shape of a truncated square pyramid.

[0082] Example 7 The difference from Example 1 is that in S03, the duration of alkaline polishing is 75° C. The obtained pre-textured silicon wafer has a pre-textured layer, and the surface of the pre-textured layer has a plurality of closely arranged protrusions, each in the shape of a truncated square pyramid.

[0083] To highlight the beneficial effects of the embodiments of this application, the following comparative examples are presented.

[0084] (Comparative Example 1) The only difference from Example 1 is that the alkaline polishing solution in S03 is 35 wt % KOH. The obtained pre-textured silicon wafer has a pre-textured layer, and the surface of the pre-textured layer has a plurality of protrusions, each of which is in the shape of a truncated square pyramid.

[0085] (Comparative Example 2) The only difference from Example 1 is that the duration of alkaline polishing in S03 is 600 seconds. The obtained pre-textured silicon wafer has a pre-textured layer, and the surface of the pre-textured layer has protrusions, each of which is in the shape of a truncated square pyramid.

[0086] (Comparative Example 3) The only difference from Example 1 is that in S03, the pre-textured silicon wafer is obtained at a temperature of 35°C.

[0087] (Performance characteristic test) (1) The textured wafers obtained in the examples and comparative examples were examined using a scanning electron microscope.

[0088] (2) A special electrode pattern (as shown in FIG. 5) was printed on the surface of the textured wafer obtained in each example and comparative example, and the contact resistance between the textured wafer and the bus bar or finger was tested according to the following steps.

[0089] Using the AT510Pro DC Resistance Meter, the fifth measurement level and high current (670 μA) signal source mode were selected, with a maximum measurement range of 300 Ω and a resolution of 10 mΩ. First, the resistance R1 between the first and second electrodes was measured, with the first and second electrodes spaced 1 mm apart. R1 is equivalent to the contact resistance of each of the two electrodes plus the resistance of a 1-mm silicon wafer. Next, the resistance R2 between the second and third electrodes was measured, with the second and third electrodes spaced 2 mm apart. R2 is equivalent to the contact resistance of each of the two electrodes plus the resistance of a 2-mm silicon wafer. R3, R4, and R5 can also be measured using the same method. Using R1 through R5, a curve of electrode spacing was plotted. The half intercept of the Y-axis represents the contact resistance.

[0090] [Table 1]

[0091] FIG. 2A is an SEM image of a pre-textured silicon wafer obtained in Example 1 of this application. FIG. 2B is an SEM image of a cross section of a pre-textured silicon wafer obtained in Example 1 of this application. From FIG. 2A, it can be seen that the base length of each protrusion is approximately 5 μm, and small white spots (nucleation sites) are distributed on the sidewalls of the protrusions. From FIG. 2B, it can be seen that each protrusion is a low-profile, generally flat structure, and the damaged layer of the silicon wafer has been completely removed. The textured wafer obtained from the pre-textured silicon wafer (as shown in FIG. 2C) has a textured surface layer with densely arranged light-capturing structures, each with a base length of approximately 2 μm, and the size distribution of the light-capturing structures is uniform. Therefore, the textured surface layer has a high degree of flatness, as can be seen from the contact resistance data in Table 1.

[0092] 3A and 3B are SEM images of a pre-textured silicon wafer and a textured wafer, respectively, obtained in Example 5 of this application. It can be seen that the base length of the protrusions on the pre-textured silicon wafer is about 8 μm, the base length of the light capture structures is about 3 μm, and the distribution of the base lengths of the multiple light capture structures is relatively uniform.

[0093] However, the pre-textured silicon wafer and textured wafer obtained in the comparative example are clearly inferior to those obtained in the example. Figures 4A and 4B are SEM images of the pre-textured silicon wafer and textured wafer obtained in comparative example 1, respectively. The base length of the protrusions on the pre-textured silicon wafer was approximately 20 μm, the base length of the light-capturing structures was 1 μm to 5 μm, the distribution of the base lengths of the multiple light-capturing structures was extremely non-uniform, and the textured surface layer had low surface flatness and large contact resistance with the busbar or fingers (see data in Table 1).

[0094] The above description is an exemplary embodiment of this application. It should be noted that a person skilled in the art may make some further improvements and modifications without departing from the principle of this application, and such improvements and modifications shall fall within the protection scope of this application.

Claims

1. A pre-textured silicon wafer (1), comprising a substrate layer (10) and a pre-textured layer provided on at least one surface of the substrate layer, the pre-textured layer comprising a plurality of protrusions (201), each of which has a shape of a truncated quadrangular pyramid, and the length of the base of the protrusion is in the range of 2 μm to 8 μm.

2. 2. The pre-textured silicon wafer of claim 1, wherein nucleation sites (202) are distributed on the sidewalls (A / B) of the protrusions (201).

3. 3. The pre-textured silicon wafer of claim 2, wherein the nucleation sites (202) are square pyramids with a maximum cross-sectional width in the range of 0 μm to 1 μm and a height in the range of 0 μm to 0.75 μm.

4. The pre-textured layer has a thickness of 100 μm ２ A pre-textured silicon wafer according to any one of claims 1 to 3, comprising 2 to 11 protrusions (201) per wafer.

5. A pre-textured silicon wafer according to any one of claims 1 to 4, wherein the height of the protrusions (201) is in the range of 0.5 μm to 2 μm.

6. A pre-textured silicon wafer according to any one of claims 1 to 5, wherein the cross-sectional size of the protrusions (201) gradually decreases in a direction away from the substrate layer.

7. 1. A method for making a pre-textured silicon wafer, comprising: Sequentially subjecting a silicon wafer to cleaning and alkaline polishing treatments to obtain the pre-textured silicon wafer, the pre-textured silicon wafer comprising a substrate layer and a pre-textured layer provided on at least one surface of the substrate layer, the pre-textured layer comprising a plurality of protrusions, each of which has a shape of a truncated square pyramid. Equipped with The alkaline polishing treatment comprises subjecting the silicon wafer to alkaline etching with a 15 wt % to 30 wt % strong alkaline solution, the duration of the alkaline polishing treatment being 40 seconds to 120 seconds, and the temperature of the alkaline polishing treatment being 50°C to 80°C.

8. subjecting the silicon wafer to sequential cleaning, Cleaning the silicon wafer with a first cleaning solution at a cleaning temperature of 60°C to 90°C for a cleaning duration of 5 minutes to 20 minutes, wherein the first cleaning solution contains hydrogen peroxide and aqueous ammonia, the aqueous ammonia having a concentration of about 2% to about 10% by weight, and the hydrogen peroxide having a concentration of about 2% to about 10% by weight; Further cleaning the silicon wafer with a second cleaning liquid at a cleaning temperature of 60°C to 90°C for a cleaning duration of 5 minutes to 20 minutes, wherein the second cleaning liquid is an aqueous solution of hydrochloric acid and hydrogen peroxide, and the concentrations of both the hydrochloric acid and the hydrogen peroxide are 2% to 10% by weight.

8. The method of making a pre-textured silicon wafer of claim 7, comprising:

9. A textured wafer (2), said textured wafer being made from a pre-textured silicon wafer according to any one of claims 1 to 6.

10. 10. The textured wafer of claim 9, wherein the textured wafer comprises a substrate layer and a textured surface layer provided on at least one surface of the substrate layer, the textured surface layer comprising densely arranged light capture structures, the light capture structures having a maximum cross-sectional width in the range of 1 μm to 4 μm.

11. 11. The textured wafer of claim 10, wherein the light capture structures are pyramidal in shape, and the largest cross-sectional dimension of the light capture structures gradually decreases in a direction away from the substrate layer.

12. The textured surface layer has a thickness of 100 μm. ２ 12. The textured wafer of claim 10 or 11, comprising 60 to 100 light capture structures per wafer.

13. The textured wafer of any one of claims 10 to 12, wherein the height of the light trapping structures is in the range of 1.23 μm to 1.58 μm.

14. The textured wafer of any one of claims 10 to 13, wherein adjacent light capture structures are spaced apart.

15. A solar cell (100), said solar cell comprising a textured wafer (2) according to any one of claims 9 to 14.

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