Photolithography Enhancement Techniques

Abstract

An exemplary semiconductor processing method may include delivering a deposition precursor to a processing region of a semiconductor processing chamber. The processing region may contain a substrate. The substrate may include a photoresist material overlying a silicon-containing material. The photoresist material may define an opening. The processing region may be at least partially defined on a substrate support on which the substrate rests. The method may include forming a plasma effluent of the deposition precursor. The method may include depositing a material on the photoresist material. The method may include delivering an etch precursor to the processing region of the semiconductor processing chamber. A bias power may be applied to the substrate support from a bias power supply. The method may include etching a portion of the photoresist material. The etching may reduce uniformity of a local critical dimension of the opening in the photoresist material.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 18 / 096,207, filed January 12, 2023, entitled "PHOTOLITHOGRAPHY ENHANCEMENT TECHNIQUES," which is incorporated herein by reference in its entirety.

[0002] Technical Field TECHNICAL FIELD The present technology relates to semiconductor processes and materials, and more particularly to improving material uniformity during photolithography operations. [Background technology]

[0003] Integrated circuits are made possible by processes for fabricating intricately patterned layers of material on a substrate surface. Fabricating patterned materials on a substrate requires controlled methods for the formation and removal of exposed material. Chemical etching is used for a variety of purposes, including transferring a photoresist pattern to an underlying layer, thinning a layer, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches one material faster than another, for example, to facilitate the pattern transfer process. Such an etching process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etching processes have been developed that are selective to a variety of materials.

[0004] Etching processes are sometimes referred to as wet or dry based on the materials used in the process. For example, wet etching can preferentially remove some oxide dielectrics over other dielectrics and materials. However, wet processes can have difficulty penetrating some restricted trenches and can sometimes deform the remaining material. Dry etching, which is generated in a localized plasma formed within the substrate processing region, allows for more restricted trench penetration and can reduce deformation of delicate remaining structures. However, localized plasmas can damage the substrate by generating electric arcs when they discharge.

[0005] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0006] An exemplary semiconductor processing method may include delivering a deposition precursor to a processing region of a semiconductor processing chamber. The processing region may contain a substrate. The substrate may include a photoresist material overlying a silicon-containing material. The photoresist material may define an opening. The processing region may be at least partially defined on a substrate support on which the substrate rests. The method may include forming a plasma effluent of the deposition precursor. The method may include depositing a material on the photoresist material. The method may include delivering an etch precursor to the processing region of the semiconductor processing chamber. A bias power may be applied to the substrate support from a bias power supply. The method may include etching a portion of the photoresist material. The etching may reduce local critical dimension (CD) uniformity of the opening in the photoresist material.

[0007] In embodiments, the deposition precursor may be or include a silicon-containing precursor. The material deposited on the photoresist material may be or include silicon oxide. The source plasma power applied from the source power supply to form the plasma effluent of the deposition precursor may be about 1,000 W or less. The etch precursor may be or include a fluorine-containing precursor. The local critical dimension uniformity may be about 3 nm 3σ or less. Deposition of the material on the photoresist material may be performed at a first pressure. Etching of portions of the photoresist material may be performed at a second pressure. The second pressure may be greater than the first pressure. The second pressure may be about 30 Torr or less. The bias plasma power applied from the bias power supply when etching portions of the photoresist material may be about 500 W or less. The source plasma power applied from the source power supply when etching portions of the photoresist material may be about 100 W or less. The method can include etching a portion of the photoresist material, followed by etching the silicon-containing material to form an opening in the silicon-containing material.

[0008] Some embodiments of the present technology may include delivering a silicon-containing precursor to a processing region of a semiconductor processing chamber. The processing region may contain a substrate. The substrate may include a photoresist material overlying a first silicon-containing material. The photoresist material may define an opening. The processing region may be at least partially defined above a substrate support on which the substrate rests. The method may include forming a plasma effluent of the silicon-containing precursor. The method may include depositing a second silicon-containing material on the photoresist material. The method may include delivering a fluorine-containing precursor to the processing region of the semiconductor processing chamber. The method may include etching a portion of the photoresist material extending outward from the second silicon-containing material.

[0009] In embodiments, the openings in the photoresist material can be characterized by a width of about 30 nm or less. The first silicon-containing material can be or include a silicon-oxygen-nitrogen material. The pressure in the semiconductor processing chamber can be maintained at about 30 Torr or less. Etching can reduce the uniformity of the local critical dimensions of the openings in the photoresist material. Prior to etching, the uniformity of the local critical dimensions can be greater than 4 nm 3σ.

[0010] Some embodiments of the present technology may include a semiconductor processing method. The method may include supplying a silicon-containing precursor to a processing region of a semiconductor processing chamber. The processing region may contain a substrate. The substrate may include a photoresist material overlying a first silicon-containing material. The photoresist material may define an opening. The opening may have a width of about 30 nm or less. The processing region may be at least partially defined on a substrate support on which the substrate is placed. The method may include forming a plasma effluent of the silicon-containing precursor. The method may include depositing a second silicon-containing material on the photoresist material. The method may include stopping the flow of the silicon-containing precursor. The method may include supplying a fluorine-containing precursor to the processing region of the semiconductor processing chamber. The method may include etching a portion of the photoresist material extending outward from the second silicon-containing material.

[0011] In embodiments, the silicon-containing precursor can be or include silicon tetrachloride (SiCl4). The deposition of the second silicon-containing material and the etching of the portion of the photoresist material can be performed in the same processing region of the same semiconductor processing chamber.

[0012] Such technology can provide many advantages over conventional systems and techniques. For example, the process and structure can etch a tapered profile into an opening defined in the photoresist material to transfer the critical dimension (CD) of the photoresist material at the top surface of the photoresist material throughout the thickness of the photoresist material. Additionally, operation of embodiments of the present technology can enable reduced ultraviolet or extreme ultraviolet radiation exposure during lithography operations to pattern the photoresist material. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the following description and accompanying figures.

[0013] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic top view of an exemplary processing system in accordance with some embodiments of the present technique; [Figure 2] 1 is a schematic cross-sectional view of an exemplary processing system in accordance with some embodiments of the present technique; [Figure 3] 1 illustrates selected operations of a forming method in accordance with some embodiments of the present technique. [Figure 4A] 1A-1C are schematic cross-sectional views of substrate material performing selected operations in accordance with some embodiments of the present technique; [Figure 4B] 1A-1C are schematic cross-sectional views of substrate material performing selected operations in accordance with some embodiments of the present technique; [Figure 4C] 1A-1C are schematic cross-sectional views of substrate material performing selected operations in accordance with some embodiments of the present technique; [Figure 4D] 1A-1C are schematic cross-sectional views of substrate material performing selected operations in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0015] Some figures are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically and explicitly stated to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include unnecessary or exaggerated material for illustrative purposes.

[0016] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numerals, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0017] As semiconductor manufacturing moves to smaller technology nodes, such as the 7 nm node and below, improved patterning techniques, such as extreme ultraviolet ("EUV") lithography, may be used. EUV lithography utilizes a photomask structure that is patterned with a specific integrated circuit design. The photomask is then incorporated into a lithography scanner and used to pattern the image onto a substrate. EUV technology can be characterized by several challenges, including patterning small features in the photoresist that are to be patterned. One challenge involves imperfect patterning of the photoresist, resulting in openings or apertures in the photoresist that are characterized by tapered sidewalls. These tapered sidewalls are not uniform and can vary for each individual opening created in the photoresist. These non-uniformities can propagate to underlying layers during the patterning process.

[0018] The present technique overcomes these problems by depositing a material onto a photoresist material, preferentially depositing the material on the top surface of the photoresist. After depositing the material on the top surface of the photoresist, etching can be performed to transfer the upper critical dimension of the opening in the photoresist throughout the thickness of the photoresist. The upper critical dimension of the opening in the photoresist can be much more uniform throughout the photoresist compared to the lower critical dimension.

[0019] While the remaining disclosure routinely identifies particular materials and semiconductor structures that utilize the disclosed technology, it will be readily understood that the systems, methods, and materials are equally applicable to many other structures that can benefit from aspects of the technology. Thus, the technology should not be considered limited to use with only the processes or materials described. Furthermore, while exemplary chambers are described to provide a foundation for the technology, it should be understood that the technology can be applied to any semiconductor processing chamber, or combination of such chambers, that can enable the described operations.

[0020] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and / or cure chamber processing system 10, according to embodiments. The tool or processing system 10 illustrated in FIG. 1 may include multiple processing chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The processing chambers may include any number of structures or components and any number or combination of processing chambers.

[0021] To transfer substrates between chambers, the transfer chamber 20 can include a robotic transport mechanism 22. The transport mechanism 22 can each have a pair of substrate transport blades 22a attached to the distal end of an extendable arm 22b. The blades 22a can be used to transport individual substrates into and out of the processing chambers. In operation, one of the substrate transport blades, such as blade 22a of the transport mechanism 22, can retrieve a substrate W from one of the load lock chambers, such as chambers 16a-b, and transport the substrate W to a first processing stage, such as a processing process described below for chambers 24a-d. Chambers can be included to perform individual or combinations of the described techniques. For example, one or more chambers can be configured to perform deposition or etching operations, while one or more other chambers can be configured to perform pre-processing operations and / or one or more of the described post-processing operations. Any number of configurations are encompassed by the present technology, which can also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0022] If a chamber is occupied, the robot can wait until processing is complete, then remove the processed substrate from the chamber using one blade 22a and insert a new substrate using a second blade. Once the substrate has been processed, it can then be moved to a second stage of processing. At each move, the transport mechanism 22 can generally have one blade carrying the substrate and one empty blade to perform the substrate swap. The transport mechanism 22 can wait at each chamber until the swap is accomplished.

[0023] Once processing is completed in a processing chamber, the transport mechanism 22 can remove the substrate W from the last processing chamber and transport the substrate W to a cassette in the load lock chambers 16a-b. From the load lock chambers 16a-b, the substrate can be moved to the factory interface 12. The factory interface 12 can operate to transfer substrates between the pod loaders 14a-d and the load lock chambers 16a-b in a generally atmospheric clean environment. The clean environment within the factory interface 12 can generally be provided through an air filtration process, such as HEPA filtration. The factory interface 12 can also include a substrate orienter / aligner that can be used to properly align substrates prior to processing. At least one substrate robot, such as robots 18a-b, can be positioned within the factory interface 12 to transport substrates between various locations within the factory interface 12 and to other locations in communication therewith. The robots 18a-b may be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0024] The processing system 10 may further include an integrated metrology chamber 28 for providing control signals, which may provide adaptive control for any of the processes being performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices for measuring various film properties, such as thickness, roughness, composition, etc., which may further characterize lattice parameters, such as critical dimensions, sidewall angle, and feature height under vacuum, in an automated manner.

[0025] Each of the processing chambers 24a-d can be configured to perform one or more processing steps in the fabrication of semiconductor structures, and any number and combination of processing chambers can be used on the multichamber processing system 10. For example, any of the processing chambers can be configured to perform many substrate processing operations, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and any number of deposition processes, including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, alignment, and other substrate processes. Some specific processes that can be performed in any of the chambers or any combination of chambers can be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma treatment. Any other processes can be similarly performed in a specific chamber incorporated within the multichamber processing system 10, including any of the processes described below, as will be readily recognized by those skilled in the art.

[0026] FIG. 2 illustrates a schematic cross-sectional view of an exemplary processing chamber 200 suitable for patterning a material layer disposed on a substrate 202 therein. While the exemplary processing chamber 200 is suitable for performing a patterning process, it should be understood that aspects of the present technique can be practiced in a variety of chambers, and that substrate support according to the present technique can be included in an etch chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 200 can include a chamber body 205 defining a chamber volume 201 in which a substrate can be processed. The chamber body 205 can have sidewalls 212 and a bottom 218 connected to a ground 226. The sidewalls 212 can have a liner 215 to protect the sidewalls 212 and extend the maintenance interval of the plasma processing chamber 200. The dimensions of the chamber body 205 and associated components of the plasma processing chamber 200 are not limited and can generally be increased in proportion to the size of the substrate 202 to be processed. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, among others, such as display substrates or solar cell substrates.

[0027] The chamber body 205 can support a chamber lid assembly 210 that surrounds the chamber volume 201. The chamber body 205 can be fabricated from aluminum or other suitable materials. A substrate access port 213 can be formed through a sidewall 212 of the chamber body 205 to facilitate transfer of the substrate 202 into and out of the plasma processing chamber 200. This access port 213 can be coupled to a transfer chamber and / or other chambers of a substrate processing system, as described above. A pumping port 245 can be formed through the sidewall 212 of the chamber body 205 and connected to the chamber volume 201. A pumping device can be connected to the chamber volume 201 through the pumping port 245 to evacuate and control the pressure within the processing volume. The pumping device can include one or more pumps and a throttle valve.

[0028] The gas panel 260 can be connected to the chamber body 205 by gas lines 267 to supply process gases to the processing volume 201. The gas panel 260 can include one or more process gas sources 261, 262, 263, 264, and can further include inert, non-reactive, and reactive gases for various processes. Examples of process gases that can be provided by the gas panel 260 include, but are not limited to, hydrocarbon gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon gas, chlorine, nitrogen, helium, or oxygen gas, as well as various additional materials. Additionally, the process gas can include nitrogen, chlorine, fluorine, oxygen, silicon, and hydrogen-containing gases, such as BCl3, Cl2, SiCl4, CF4, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, COS, N2, NO2, N2O, O2, HBr, and H2, among various additional precursors.

[0029] A valve 266 can control the flow rate of process gases from the sources 261, 262, 263, and 264 of the gas panel 260 and can be managed by a controller 265. The flow of gas supplied from the gas panel 260 to the chamber body 205 can include a combination of gases from one or more sources. The lid assembly 210 can include a nozzle 214. The nozzle 214 can be one or more ports for introducing process gases from the sources 261, 262, 264, and 263 of the gas panel 260 into the chamber volume 201. After the process gases are introduced into the plasma processing chamber 200, the gases are excited to form a plasma. An antenna 248, such as one or more inductor coils, can be provided adjacent to the plasma processing chamber 200. An antenna power supply 242 can power the antenna 248 via a matching circuit 241 that inductively couples energy (e.g., RF energy) to the process gases to maintain a plasma formed from the process gases in the chamber volume 201 of the plasma processing chamber 200. Alternatively, or in addition to the antenna power supply 242, a process electrode below the substrate 202 and / or above the substrate 202 may be used to capacitively couple RF power to the process gas to maintain a plasma within the chamber volume 201. The operation of the power supply 242 may be controlled by a controller (e.g., controller 265) that also controls the operation of other components within the plasma processing chamber 200.

[0030] A substrate support pedestal 235 may be disposed within the chamber volume 201 to support the substrate 202 during processing. The substrate support pedestal 235 may include an electrostatic chuck 222 for holding the substrate 202 during processing. The electrostatic chuck ("ESC") 222 holds the substrate 202 to the substrate support pedestal 235 using electrostatic attraction. The ESC 222 is powered by an RF power supply 225 integrated with a matching circuit 224. The ESC 222 may include an electrode 221 embedded in a dielectric. The electrode 221 may be coupled to the RF power supply 225 to provide a bias that attracts plasma ions formed by the process gases in the chamber volume 201 toward the ESC 222 and the substrate 202 positioned on the pedestal. The RF power supply 225 may be cycled on and off or pulsed during processing of the substrate 202. The ESC 222 may include an isolator 228 to reduce the plasma's attraction to the sidewalls of the ESC 222 to extend the maintenance lifecycle of the ESC 222. Additionally, the substrate support pedestal 235 may include a cathode liner 236 to protect the sidewalls of the substrate support pedestal 235 from the plasma gases and extend the maintenance intervals of the plasma processing chamber 200.

[0031] The electrode 221 may be connected to a power supply 250. The power supply 250 may provide a chucking voltage of about 200 volts to about 2000 volts to the electrode 221. The power supply 250 may also include a system controller for controlling the operation of the electrode 221 by inducing a DC current to the electrode 221 to chuck and dechuck the substrate 202. The ESC 222 may include a heater disposed within the pedestal and connected to a power supply for heating the substrate, while the cooling base 229 supporting the ESC 222 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 222 and the substrate 202 disposed thereon. The ESC 222 may be configured to operate within a temperature range required by the thermal budget of a device fabricated on the substrate 202. For example, the ESC 222 may be configured to maintain the substrate 202 at a temperature of about −150° C. or lower to about 500° C. or higher, depending on the process being performed.

[0032] A cooling base 229 may be provided to assist in controlling the temperature of the substrate 202. To mitigate process drift and time, the temperature of the substrate 202 may be maintained substantially constant by the cooling base 229 while the substrate 202 is in the chamber. In some embodiments, the temperature of the substrate 202 may be maintained at a temperature between about −150° C. and about 500° C. throughout subsequent processes, although any temperature may be utilized. A cover ring 230 may be disposed on the ESC 222 and along the periphery of the substrate support pedestal 235. The cover ring 230 may be configured to contain etching gases to desired portions of the exposed upper surface of the substrate 202 while shielding the upper surface of the substrate support pedestal 235 from the plasma environment in the plasma processing chamber 200. Lift pins may be selectively moved through the substrate support pedestal 235 to lift the substrate 202 above the substrate support pedestal 235 and facilitate access to the substrate 202 by a transfer robot or other suitable transfer mechanism, as previously described.

[0033] The controller 265 can be utilized to control process sequences and regulate gas flow rates and other process parameters from the gas panel 260 to the plasma processing chamber 200. The software routines, when executed by the CPU, can transform the CPU into a special-purpose computer, such as a controller, that controls the plasma processing chamber 200 to perform processes according to the present disclosure. The software routines may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 200.

[0034] As described above, the present technique can trim the photoresist material to make the openings defined therein more uniform. FIG. 3 illustrates exemplary operations in a semiconductor processing method 300 according to embodiments of the present technique. Method 300 can include one or more operations prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or other operations that can be performed before the described operations. For example, the method can begin after multiple layers of material overlying a substrate have been deposited and after the photoresist material has been patterned, such as by photoprocessing. However, as noted above, it should be understood that the illustration illustrates only one exemplary process that can be employed to improve photolithographic patterning according to embodiments of the present technique, and the description herein is not intended to limit the present technique to only this process. Some or all of the operations can be performed in a chamber or system tool, as described above, or in different chambers on the same system tool, which may include a chamber capable of performing the operations of method 300.

[0035] Method 300 may include several optional operations that may or may not be specifically associated with some embodiments of methods according to the present technology, as illustrated. For example, while many of the operations are described to provide a broader range of structure formation, they are not critical to the technology or may be performed by alternative methodologies discussed further below. Method 300 describes operations shown generally in FIGS. 4A-4D that will be described in conjunction with the operations of method 300. It should be understood that FIGS. 4A-4D show only partial schematic views, and that a substrate may include various structural sections having the aspects shown in the figures, as well as alternative structural aspects that can still benefit from the operations of the present technology.

[0036] Method 300 may or may not include optional operations to develop the semiconductor structure for a particular manufacturing operation. It should be understood that method 300 can be performed on a variety of semiconductor structures, and that FIGS. 4A-4D illustrate one exemplary structure on which an etching process can be performed. As shown in FIG. 4A, processed semiconductor structure 400 can include a substrate 405, which can include a carbon-containing material 410, such as an amorphous carbon-containing material, overlying substrate 405. Processed semiconductor structure 400 can also include a silicon-containing material 415 overlying carbon-containing material 410. Silicon-containing material 415 can be a silicon-oxygen-containing material, a silicon-nitrogen-containing material, a silicon-oxygen-nitrogen-containing material, or any other silicon-containing material. Processed semiconductor structure 400 can also include a photoresist material 420.

[0037] The photoresist material 420 can be patterned to define at least one aperture 425 extending through the entire thickness of the photoresist material 420. The aperture 425 can expose the underlying silicon-containing material 415. While only three openings 425 are shown in the processed semiconductor structure 400, it is understood that the exemplary structure 400 can include any number of apertures as described above, i.e., tens or hundreds of apertures, and these illustrations are merely schematic diagrams for illustrating aspects of the present technology. The aperture 425 can be characterized by a width of about 30 nm or less, and can be characterized by a width of about 28 nm or less, about 26 nm or less, about 24 nm or less, about 22 nm or less, about 20 nm or less, about 18 nm or less, about 16 nm or less, about 14 nm or less, about 12 nm or less, about 10 nm or less, or less.

[0038] The method 300 may include, in operation 305, providing deposition precursors to a processing region of a semiconductor processing chamber. The processing region may contain a substrate, such as the processed semiconductor structure 400. The deposition precursors may include silicon-containing precursors and oxygen-containing precursors. Silicon-containing precursors that may be used during deposition include silane (SiH), disilane (SiH), trisilane (SiH), tetrasilane (SiH), and tetrasilane (SiH). 10 ), pentasilane (Si5H 12 ), or other organosilanes including cyclohexasilane, silicon tetrafluoride (SiF), silicon tetrachloride (SiCl), dichlorosilane (SiHCl), tetraethyl orthosilicate (TEOS), and any other silicon-containing precursor that can be used to form silicon-oxygen-containing films. Oxygen-containing precursors that can be used during deposition include, but are not limited to, diatomic oxygen (O), ozone (O), and any other oxygen-containing precursor that can be used to form silicon-oxygen-containing ozone films.

[0039] The deposition precursors may include various carrier gases, which may include nitrogen, helium, argon, or other noble, inert, or useful precursors. The carrier gas can be used to dilute the deposition precursors, thereby slowing down the deposition rate and making the deposition more controllable. However, it is contemplated that the deposition precursors can be delivered without other gases.

[0040] The flow rate of the deposition precursor can be adjusted along with any other process conditions. For example, the flow rate of the silicon-containing precursor and / or the oxygen-containing precursor can be decreased, maintained, or increased during operations 305 and / or 310 of method 300. The flow rate of the silicon-containing precursor can be between about 1 sccm and about 1,000 sccm during operations 305 and / or 310 of method 300. In addition, the flow rate of the silicon-containing precursor can be about 900 sccm or less, about 800 sccm or less, about 700 sccm or less, about 600 sccm or less, about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, about 150 sccm or less, about 100 sccm or less, about 80 sccm or less, about 60 sccm or less, about 40 sccm or less, about 20 sccm or less, or less. The flow rate may also be between any of these recited flow rates or within a narrower range encompassed by any of these values.

[0041] Similarly, during operations 305 and / or 310 of method 300, the flow rate of the oxygen-containing precursor can be between about 1 sccm and about 1,000 sccm. In addition, the flow rate of the oxygen-containing precursor can be about 900 sccm or less, about 800 sccm or less, about 700 sccm or less, about 600 sccm or less, about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 250 sccm or less, about 200 sccm or less, about 150 sccm or less, about 100 sccm or less, about 80 sccm or less, about 60 sccm or less, about 40 sccm or less, about 20 sccm or less, or less. The flow rate can also be between any of these recited flow rates or within a narrower range encompassed by any of these values.

[0042] The method 300 may include forming a plasma in a processing region of a semiconductor processing chamber in operation 310. The plasma may produce plasma effluents of deposition precursors, including silicon-containing precursors and / or oxygen-containing precursors. Operations 305 and 310 may be performed sequentially or substantially simultaneously in some embodiments. Furthermore, the plasma may be first formed from the silicon-containing precursor, the oxygen-containing precursor, or one or more inert precursors in different embodiments prior to adding the deposition precursors, if present.

[0043] The localized plasma formed from the deposition precursors can provide a directional flow of plasma effluents to the structure 400, providing top-heavy deposition. The plasma can be a low-density plasma to limit the amount of bombardment, sputtering, and surface modification. In embodiments, an inductively coupled plasma can be formed in the processing region by applying a source plasma power above the substrate 405 or to a substrate support, such as a substrate support pedestal, as described above. The source plasma power can be about 1,000 W or less, about 900 W or less, about 800 W or less, about 700 W or less, about 600 W or less, about 500 W or less, about 400 W or less, about 300 W or less, or less. The plasma power can be between any of these recited plasma powers or within a narrower range encompassed by any of these values. For example, utilizing a plasma power of about 1,000 W or less can provide better control of plasma effluents to selectively deposit a material 430, such as a top-heavy silicon-containing material, on the photoresist material 420 in operation 315.

[0044] During operation 310, the duty cycle of the source power may be about 75% or less, and the source power may be operated at a duty cycle of about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, or less. By operating the source power at a reduced duty cycle, such as an on-time duty of about 50% or less, the material 430 deposited on the photoresist material may be preferentially deposited on top of the photoresist material 420.

[0045] 4B, material 430 deposited on photoresist material 420 can be deposited on top of photoresist material 420. As discussed above, material 430 can be a top-heavy silicon-containing material, such as silicon oxide. The deposited material 430 can form a cap or helmet on photoresist material 420. Material 430 can maintain the top critical dimension of photoresist material 420 during subsequent trimming operations, as described below.

[0046] To improve the uniformity of the opening 425 defined in the photoresist material 420, the method 300 may include a trimming operation after depositing the material 430 on the photoresist material 420. The method 300 may include, in operation 320, supplying an etch precursor to a processing region of the semiconductor processing chamber. In embodiments, the etch precursor may be a fluorine-containing precursor. The fluorine-containing precursor used in operation 320 of the method 300 may include any fluorine-containing precursor. An exemplary fluorine-containing precursor may include nitrogen trifluoride (NF), which may be flowed into the processing region without passing through a plasma. Other fluorine sources may be used in conjunction with or in place of nitrogen trifluoride. Generally, a fluorine-containing precursor is flowed into the processing region, and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride (CF), hydrogen fluoride (HF), sulfur hexafluoride (SF), xenon difluoride (XeF), and various other fluorine-containing precursors used or useful in semiconductor processing. In embodiments, a hydrogen-containing precursor, such as diatomic hydrogen (H), or an oxygen-containing precursor, such as diatomic oxygen (O), may be provided in conjunction with the fluorine-containing precursor. The etch precursor may also be provided with various carrier gases, which may include nitrogen, helium, argon, or other noble gases, inert gases, or useful precursors. The carrier gas may be used to dilute the fluorine-containing precursor, thereby reducing the etch rate and allowing for better etching control. However, it is contemplated that the fluorine-containing precursor may be provided without other gases.

[0047] The semiconductor structure 400 may be contacted with an etch precursor or its plasma effluents, which may etch or remove portions of the photoresist material 420 in operation 325. As shown in FIG. 4C , the plasma effluents may contact the semiconductor structure 400 and may contact all exposed surfaces, including surfaces to be etched, such as the photoresist material 420, and surfaces to be maintained, such as the silicon-containing material 415 and material 430. During operation 325, sidewalls of the opening 425 in the photoresist material 420 may be etched. Specifically, photoresist material 420 that extends outwardly of or beyond the outer dimensions of the material 430 may be removed. Such a trimming operation may straighten the tapered profile of the photoresist material 420, thereby reducing or eliminating non-uniformities in the critical dimensions of the opening 425 defined in the photoresist material 420 while maintaining the upper critical dimensions of the opening 425 in the photoresist material 420. By etching the photoresist material 420, the dimensions of the openings 425 at the top surface of the photoresist material 420 opposite the surface of the photoresist material 420 that contacts the underlying silicon-containing material 415 can be translated throughout the thickness of the photoresist material 420.

[0048] Embodiments of the present technology can remove photoresist material 420 that extends beyond either material 430 or other materials on structure 400 at a rate of at least about 1:1, and can etch hafnium oxide relative to silicon oxide or other materials at a selectivity of about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 10:1 or greater, or greater. For example, etches performed according to some embodiments of the present technology can etch photoresist material 420 that extends outside of material 430 while substantially or essentially preserving material 430 or other materials.

[0049] During operations 320 and / or 325, bias power may be applied to the substrate support from a bias power supply. The plasma may be a low-level plasma to enhance directionality of the etch precursor. The bias plasma power may be about 1,000 W or less, about 900 W or less, about 800 W or less, about 700 W or less, about 600 W or less, about 500 W or less, about 400 W or less, about 300 W or less, about 200 W or less, about 100 W or less, or less. The plasma power may also be between any of these recited plasma powers or within a narrower range encompassed by any of these values. For example, utilizing a bias plasma power of about 1,000 W or less may enhance directionality of plasma effluents, resulting in a trimming operation that reduces or eliminates non-uniformities in the critical dimension of the opening 425 defined in the photoresist material 420. In embodiments, only bias power, and not source power, may be applied during operations 320 and / or 325. However, in some embodiments, it is contemplated that the source power may be applied at a source plasma power of about 250 W or less, about 200 W or less, about 150 W or less, about 100 W or less, about 50 W or less, about 25 W or less, about 10 W or less, or less.

[0050] Trimming the photoresist material 420 in operation 325 can provide a reduced local critical dimension uniformity (LCDU) of about 3 nm 3σ or less, and can provide an LCDU of about 2.8 nm 3σ or less, about 2.6 nm 3σ or less, about 2.4 nm 3σ or less, about 2.2 nm 3σ or less, about 2.0 nm 3σ or less, about 1.8 nm 3σ or less, or less. LCDU can be greater than 4 nm before etching in operation 325, and conventional techniques that do not trim the photoresist material can suffer increases in LCDU values, such as greater than 4 nm 3σ, due to variations in the taper of the openings defined in the photoresist material.

[0051] After the photoresist material 420 is trimmed in operation 325, further processing can include etching the silicon-containing material 415, as shown in FIG. 4D. The trimmed photoresist material 420, with improved uniformity of the openings 425, can enable more uniform etching of the silicon-containing material. The silicon-containing material 415 can be etched using any etching process capable of etching silicon-containing materials, such as silicon oxide, silicon nitride, and / or silicon oxynitride. In one exemplary embodiment, an etching precursor for etching the silicon-containing material 415 can include a fluorine-containing precursor, such as carbon tetrafluoride (CF), a hydrogen-containing precursor, such as diatomic hydrogen (H), and one or more carrier gases, such as diatomic nitrogen (N). However, any other etching process operable to remove silicon-containing materials with high selectivity relative to the photoresist material 420 is contemplated. As shown in FIG. 4D, operation 325 can also etch material 430 deposited on top of the photoresist material 420.

[0052] Process conditions can affect the operations performed in method 300. Each operation of method 300 can be performed at a constant temperature in embodiments, although in some embodiments, the temperature can be adjusted during different operations. For example, the temperature of the substrate, pedestal, or chamber during processing can be maintained at about 100° C. or less, about 90° C. or less, about 80° C. or less, about 70° C. or less, about 60° C. or less, about 50° C. or less, and in some embodiments, the temperature can be maintained at about 40° C. or less, about 30° C. or less, about 20° C. or less, about 10° C. or less, about 0° C. or less, about −10° C. or less, about −20° C. or less, about −30° C. or less, or less.

[0053] The pressure in the processing chamber can be controlled during method 300. For example, the pressure in the processing chamber can be maintained at or below about 30 Torr. Additionally, in embodiments, the pressure in the processing chamber can be maintained at or below about 28 Torr, about 26 Torr, about 24 Torr, about 22 Torr, about 20 Torr, about 18 Torr, about 16 Torr, about 14 Torr, about 12 Torr, about 10 Torr, about 8 Torr, about 6 Torr, or lower, although the pressure can fall within a range between any two of these recited values, or any smaller range encompassed within any of the recited ranges. In embodiments, the pressure can be maintained at about 4 Torr or greater, about 6 Torr or greater, about 8 Torr or greater, about 10 Torr or greater, about 12 Torr or greater, about 14 Torr or greater, about 16 Torr or greater, about 18 Torr or greater, about 20 Torr or greater, about 22 Torr or greater, about 24 Torr or greater, about 26 Torr or greater, about 28 Torr or greater, or greater. Pressure can affect the deposition of material 430, with higher pressures resulting in more conformal deposition. Lower pressures can result in top-heavy deposition, forming a helmet or cap that protects the photoresist material 420 during the trimming operation. Pressure can also affect the uniformity of the trimming of the photoresist material 420. Pressures below about 30 Torr can increase ion distribution, resulting in highly directional etching of the photoresist material 420. This highly directional etching can trim the photoresist and improve the uniformity of the openings 425 throughout the thickness of the photoresist material 420. Conversely, increasing pressure can decrease the mean free path and impair directionality.

[0054] In an embodiment, the deposition in operation 315 may be performed at a first pressure, and the etching in operation 325 may be performed at a second pressure greater than the first pressure. The reduced pressure compared to the etching in operation 325 may allow material 430 to be deposited on top of photoresist material 420. The etching in operation 325 may be performed at a pressure of about 30 Torr or less to ensure directional etching of photoresist material 420 and remove a taper from photoresist material 420 that defines opening 425.

[0055] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0056] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. In addition, while a method or process may be described sequentially or stepwise, it should be understood that operations may be performed simultaneously or in an order different from that described.

[0057] Where a range of values ​​is presented, unless the context clearly dictates otherwise, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value within that stated range is also encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded from the range, and each range where either, neither, or both limits are included in the smaller range is also encompassed within the scope, subject to any specifically excluded limits in the stated range. When one or both limits are included in a stated range, ranges excluding either or both of those included limits are also included.

[0058] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the material" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0059] Additionally, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and the appended claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: delivering a deposition precursor to a processing region of a semiconductor processing chamber, the processing region containing a substrate, the substrate including a photoresist material overlying a silicon-containing material, the photoresist material defining an opening, the processing region being above at least a portion of a substrate support on which the substrate rests; forming a plasma effluent of the deposition precursor; depositing a material over the photoresist material; supplying an etch precursor to the processing region of the semiconductor processing chamber, wherein a bias power is applied to the substrate support from a bias power supply; and Etching portions of the photoresist material, the etching reducing uniformity of local critical dimensions of openings in the photoresist material. A semiconductor processing method comprising:

2. The semiconductor processing method of claim 1 , wherein the deposition precursor comprises a silicon-containing precursor.

3. 10. The semiconductor processing method of claim 1, wherein the material deposited over the photoresist material comprises silicon oxide.

4. 10. The semiconductor processing method of claim 1, wherein a source plasma power applied from a source power supply to form plasma effluents of the deposition precursor is about 1,000 W or less.

5. The semiconductor processing method of claim 1 , wherein the etch precursor comprises a fluorine-containing precursor.

6. 10. The semiconductor processing method of claim 1, wherein the local critical dimension uniformity is less than or equal to about 3 nm 3σ.

7. Depositing the material onto the photoresist material is performed at a first pressure; and Etching the portion of the photoresist material is performed at a second pressure greater than the first pressure.

10. The semiconductor processing method of claim 1.

8. 8. The semiconductor processing method of claim 7, wherein said second pressure is less than or equal to about 30 Torr.

9. 2. The semiconductor processing method of claim 1, wherein the bias plasma power applied from the bias power supply when etching portions of the photoresist material is about 500 W or less.

10. 10. The semiconductor processing method of claim 1, wherein a source plasma power applied from a source power supply during etching of the portion of the photoresist material is about 100 W or less.

11. etching the silicon-containing material to form an opening in the silicon-containing material after etching a portion of the photoresist material.

10. The semiconductor processing method of claim 1, further comprising:

12. 1. A semiconductor processing method comprising: delivering a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is accommodated in the processing region, the substrate including a photoresist material overlying a first silicon-containing material, the photoresist material defining an opening, the processing region being defined above at least a portion of a substrate support on which the substrate rests; forming a plasma effluent of said silicon-containing precursor; depositing a second silicon-containing material over the photoresist material; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; and Etching the portion of the photoresist material extending outwardly of the second silicon-containing material. A semiconductor processing method comprising:

13. 13. The semiconductor processing method of claim 12, wherein the openings in the photoresist material are characterized by a width of about 30 nm or less.

14. The semiconductor processing method of claim 12, wherein the first silicon-containing material comprises a silicon-oxygen-nitrogen material.

15. 13. The semiconductor processing method of claim 12, wherein the pressure in the semiconductor processing chamber is maintained at about 30 Torr or less.

16. 13. The semiconductor processing method of claim 12, wherein said etching reduces the uniformity of local critical dimensions of openings in said photoresist material.

17. 17. The semiconductor processing method of claim 16, wherein prior to said etching, said local critical dimension uniformity is greater than 4 nm 3σ.

18. 1. A semiconductor processing method comprising: delivering a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is accommodated in the processing region, the substrate including a photoresist material overlying a first silicon-containing material, the photoresist material defining an opening, the opening having a width of about 30 nm or less, the processing region being defined above at least a portion of a substrate support on which the substrate rests; forming a plasma effluent of said silicon-containing precursor; depositing a second silicon-containing material over the photoresist material; stopping the flow of the silicon-containing precursor; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; and Etching the portion of the photoresist material extending outwardly of the second silicon-containing material. A semiconductor processing method comprising:

19. The silicon-containing precursor is silicon tetrachloride (SiCl ４ 20. The semiconductor processing method of claim 18, comprising:

20. 20. The semiconductor processing method of claim 18, wherein depositing the second silicon-containing material and etching the portion of the photoresist material are performed in the same processing region of the same semiconductor processing chamber.

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