Silicon carbide transistors with channel counter-doping and pocket doping

Abstract

Silicon carbide transistors can be formed with a channel that includes a p-type doped region between n-type doped source and drain regions. A counter-doped region can be formed on top of the channel directly under the gate oxide. Instead of using conventional doping levels for the p-type doped region, the doping concentration can be increased to approximately 1e18 cm 3 The doping can be increased to a greater concentration. The transistor may further include pocket regions on one or both sides of the channel. The pocket regions may be formed within the counter-doped region and extend to the gate oxide. These improvements, individually and / or in combination, can increase the current in the transistor's channel without significantly increasing the threshold voltage beyond acceptable operating limits.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 18 / 160,949, filed Jan. 27, 2023, entitled "SILICON CARBIDE TRANSISTOR WITH CHANNEL COUNTER-DOPING AND POCKET-DOPING," the entire contents of which are incorporated herein by reference.

[0002] This disclosure generally describes channel doping for silicon carbide transistors. More specifically, this disclosure describes channel doping concentrations and / or pocket implants to improve mobility and channel current while maintaining a low threshold voltage. [Background technology]

[0003] Silicon carbide transistors offer an alternative to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, silicon carbide transistors can be used in applications requiring higher blocking voltages, lower on-state resistance, and / or higher thermal conductivity. These advantages can stem from material advantages inherent in the physical properties of silicon carbide. Like conventional MOSFETs, silicon carbide transistors can include gate, drain, and source components that function in the same way. Recently, further improvements have been realized in silicon carbide transistors to improve mobility in the transistor channel. Specifically, an n-type counter-doped region in the channel can be formed to work in conjunction with a relatively lightly doped p-well. This counter-doped region allows the channel to form further away from the surface of the gate oxide, forming a buried channel device. However, while counter-doping a thin region of the channel can increase mobility in the channel, it also dramatically increases leakage current. Therefore, improvements in the art are needed. Summary of the Invention

[0004] In some embodiments, a silicon carbide transistor may include a source region, a drain region, a gate oxide, and a channel region between the source and drain regions and below the gate oxide. The channel region may have an area of ​​about 1e18 cm 3 The channel region may include a region of p-type doped silicon carbide that is doped at a higher concentration. The channel region may further include a counter-doped region comprising n-type doped silicon carbide, the counter-doped region being between the p-type doped silicon carbide region and the gate oxide.

[0005] In some embodiments, the silicon carbide transistor may include a source region, a drain region, a gate oxide, and a channel region between the source and drain regions and below the gate oxide. The channel region may include a p-type doped silicon carbide region below the gate oxide. The channel region may further include a counter-doped region including n-type doped silicon carbide, which may be between the p-type doped silicon carbide region and the gate oxide. The channel region may further include a first p-type doped pocket region between the source region and the counter-doped region, and a second p-type doped pocket region between the drain region and the counter-doped region.

[0006] In some embodiments, a method for forming a channel region for a silicon carbide transistor may include providing a silicon carbide layer, the method including implanting a p-type dopant into the silicon carbide layer to form a channel region having a thickness of about 1e18 cm between a source region and a drain region. 3 The method may further include implanting an n-type dopant into the silicon carbide layer to form a counter-doped region comprising n-type doped silicon carbide between the source and drain regions, the counter-doped region overlying the p-type dopant region.

[0007] In any embodiment, any and all of the following features may be implemented in any combination, without limitation: the counterdoped region is about 1e18 cm 3 The channel region may be doped to a concentration of less than 10 μm. The counter-doped region and the p-type doped silicon carbide region may increase the threshold voltage of the silicon carbide transistor by about 3 V or less. The counter-doped region and the p-type doped silicon carbide region may increase the drive current by about 70% or more. The first p-type doped pocket region and the second p-type doped pocket region may contact the gate oxide. The first p-type doped pocket region and the second p-type doped pocket region need not contact the p-type doped silicon carbide region. The first p-type doped pocket region and the second p-type doped pocket region may have a vertical depth that is about half the vertical depth of the counter-doped region. The first p-type doped pocket region and the second p-type doped pocket region may have a horizontal length between about 0.5 nm and about 2.0 nm. The first p-type doped pocket region and the second p-type doped pocket region may have a vertical depth between about 0.5 μm and about 1.0 μm. The first p-type doped pocket region may contact the source region and the counter-doped region. The second p-type doped pocket region may contact the drain region and the counter-doped region. The method may further include implanting the first p-type doped pocket region between the source region and the counter-doped region and implanting the second p-type doped pocket region between the drain region and the counter-doped region. The method may further include determining the length and depth of the first p-type doped pocket region and the second p-type doped pocket region to produce a target threshold voltage shift and drive current gain. The method may further include determining doping concentrations of the first p-type doped pocket region and the second p-type doped pocket region to produce a target threshold voltage shift and drive current gain.

[0008] A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings. In the drawings, like reference numerals are used throughout several views to refer to like components. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When referring to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components. [Brief explanation of the drawings]

[0009] [Figure 1] 1 illustrates a top view of a substrate processing tool or processing system for deposition, implantation, etching, baking, and curing chambers according to some embodiments. [Figure 2] FIG. 1 illustrates a flow diagram of a method for forming a silicon carbide transistor channel with improved mobility and threshold voltage, according to some embodiments. [Figure 3A] 1 illustrates a silicon carbide transistor having a counter-doped region according to some embodiments. [Figure 3B] 1 illustrates a silicon carbide transistor having a counter-doped region according to some embodiments. [Figure 4A] 1 illustrates a silicon carbide transistor with pocket implants according to some embodiments. [Figure 4B] 4 shows a silicon carbide trench transistor 401 with pocket implants according to some embodiments. [Figure 5] 10 shows a graph illustrating how adjusting the doping concentration of the pocket region can affect threshold voltage shift and current gain, according to some embodiments. [Figure 6] 10 shows a graph illustrating how adjusting the doping concentration of a counter-doped region can affect threshold voltage shift and current gain, according to some embodiments. [Figure 7]10 shows graphs illustrating how adjusting the depth of the pocket region can affect threshold voltage shift and current gain, according to some embodiments. [Figure 8] 10 shows graphs illustrating how adjusting the length of the pocket region can affect threshold voltage shift and current gain, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0019] Described herein are embodiments of silicon carbide transistors with lower threshold voltages and increased drive currents. The silicon carbide transistors may be formed with a channel including a p-type doped region between n-type doped source and drain regions. A counter-doped region may be formed at the top of the channel directly beneath the gate oxide. Instead of using conventional doping levels for the p-type doped region, the doping concentration may be increased to approximately 1e18 cm 3 The doping can be increased to a greater concentration. The transistor may further include pocket regions on one or both sides of the channel. The pocket regions may be formed within the counter-doped region and extend to the gate oxide. These improvements, individually and / or in combination, can increase the current in the transistor's channel without significantly increasing the threshold voltage beyond acceptable operating limits.

[0011]

[0020] FIG. 1 illustrates a top view of a substrate processing tool or processing system 100 with deposition, implant, etch, bake, and cure chambers, according to some embodiments. A set of front-opening unified pods 102 can supply substrates of various sizes. The substrates are received into a factory interface 103 by robotic arms 104 a and 104 b and then placed in a load lock or low-pressure holding area 106 before being delivered to one of the substrate processing regions 108 arranged in chamber systems or quad sections 109 a-c (each of which may be a substrate processing system having a transfer region fluidly connected to multiple processing regions 108). While a quad system is shown here, it should be understood that standalone chambers, twin chambers, and platforms incorporating other multiple chamber systems can also be used. A second robot arm 110 housed within a transfer chamber 112 can be used to transfer substrate wafers from the holding area 106 to the quad section 109 and from the quad section 109 back to the holding area 106, and the second robot arm 110 can be housed within the transfer chamber to which each of the quad sections or processing systems can be connected. Each substrate processing area 108 can be equipped to perform several substrate processing operations, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and any number of deposition processes, including etching, pre-cleaning, annealing, plasma treatment, degassing, alignment, and other substrate processes.

[0012]

[0021] Each quad section 109 may include a transfer region that can receive substrates from and deliver substrates to the second robot arm 110. The transfer region of the chamber system may be aligned with a transfer chamber having the second robot arm 110. In some embodiments, the transfer region may be laterally accessible to a robot. Components of the transfer section may vertically translate substrates to the processing region 108 thereon in subsequent operations. Similarly, the transfer region may be further operable to rotate substrates between positions within each transfer region. The substrate processing region 108 may include any number of system components for depositing, annealing, curing, and / or etching a film of material on a substrate or wafer. In one configuration, two sets of processing regions (e.g., processing regions in quad sections 109a and 109b) may be used to deposit material on a substrate, and a third set of processing chambers (e.g., processing chambers or processing regions in quad section 109c) may be used to cure, anneal, or otherwise process the deposited film. In another configuration, all three sets of chambers (e.g., all 12 chambers shown) may be configured to both deposit a film on a substrate and / or cure a film on a substrate.

[0013]

[0022] The second robot arm 110 may include two arms for simultaneously supplying and / or retrieving multiple substrates. For example, each quad section 109 may include two accesses 107 along a surface of the transfer region housing, which may be laterally aligned with the second robot arm. The accesses may be defined along a surface adjacent to the transfer chamber 112. In some embodiments, as shown, a first access may be aligned with a first substrate support of the quad section's plurality of substrate supports. Additionally, a second access may be aligned with a second substrate support of the quad section's plurality of substrate supports. The first substrate support may be adjacent to the second substrate support, and the two substrate supports may define a first row of substrate supports in some embodiments. As shown in the illustrated configuration, the second row of substrate supports may be positioned laterally outward from the transfer chamber 112 and behind the first row of substrate supports. The two arms of the second robot arm 110 can be separated to allow the two arms to simultaneously enter the quad section or chamber system to supply or retrieve one or two substrates to or from a substrate support in the transfer region.

[0014]

[0023] Any one or more of the described transfer regions may be incorporated with additional chambers separate from the fabrication system shown in various embodiments. It will be understood that additional configurations of deposition, implantation, etching, annealing, and curing chambers for material films are contemplated by processing system 100. Additionally, any number of other processing systems may be utilized with the present technology that may incorporate transfer systems for performing any of the specific operations, such as substrate movement. In some embodiments, a processing system that may provide access to multiple processing chamber regions while maintaining a vacuum environment in various sections, such as the holding and transfer areas mentioned, may enable operations to be performed in multiple chambers while maintaining a specific vacuum environment between separate processes.

[0015]

[0024] Silicon carbide transistors offer an alternative to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, silicon carbide transistors can be used in applications requiring higher blocking voltages, lower on-state resistance, and / or higher thermal conductivity. These advantages may stem from material advantages inherent in the physical properties of silicon carbide. Like conventional MOSFETs, silicon carbide transistors may include gate, drain, and source components that function in the same way. Recently, further improvements have been realized in silicon carbide transistors to improve mobility in the transistor channel. Specifically, an n-type counter-doped region in the channel can be formed to work in conjunction with a relatively lightly doped p-well. This counter-doped region positions the channel further from the surface of the gate oxide, forming a buried channel device. However, counter-doping a thin region in the channel region can increase mobility in the channel, but at the expense of transistor leakage current. For example, increasing the threshold voltage results in higher leakage current and higher standby power consumption in many applications. Compensating for threshold voltage loss can require additional processing and complex circuitry.

[0016]

[0025] The embodiments described herein solve these and other technical problems by providing a silicon carbide transistor design that offers increased mobility, reduced on-resistance, and increased channel current while still maintaining a low operating threshold voltage. The silicon carbide transistor may be formed with a channel that includes a p-type doped region between n-type doped source and drain regions. A counter-doped region may be formed at the top of the channel directly below the gate oxide. However, instead of using conventional doping levels for the p-type doped region, these embodiments reduce the doping concentration to approximately 1e18 cm 3, which is significantly higher than the doping concentrations of existing designs. Some embodiments can further improve transistor performance by including pocket regions on one or both sides of the channel. The pocket regions can be formed within the counter-doped region and extend to the gate oxide. These improvements, individually and / or in combination, can increase the current in the transistor's channel without significantly increasing the threshold voltage beyond acceptable operating limits.

[0017]

[0026] FIG. 2 illustrates a flow diagram of a method for forming a silicon carbide transistor channel with improved mobility and threshold voltage, according to some embodiments. Many of the operations in flow diagram 200 can be performed, for example, within processing system 100, as described above. The method of flow diagram 200 can include one or more operations prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method can also include some optional operations, as illustrated in the figures, which may or may not be specifically associated with some embodiments. For example, many of the operations are described to provide greater scope for structural configurations, but may not be critical to the technology or may be implemented by alternative methods, as described in more detail below. Flow diagram 200 describes the operations structurally illustrated in FIGS. 3A-3B and 4A-4B, which are described in conjunction with the operations of the method of flow diagram 200. 3-4 show only partial structural diagrams, and it should be understood that a substrate may include any number of semiconductor sections having the features shown in the figures, as well as alternative structural features that may still benefit from aspects of the present technology. For example, flow diagram 200 does not describe the explicit formation of gate, source, and / or drain regions, as these regions may be formed using conventional techniques in combination with the novel channel design described below.

[0018]

[0027] The method may include various steps performed in any order to form a silicon carbide transistor structure. Non-limiting examples of silicon carbide transistors that may be formed from this method are shown in FIGS. 3A-3B and 4A-4B. Accordingly, as the various processing steps of flow diagram 200 are described, reference may be made to the resulting transistor structures shown in FIGS. 3A-3B and 4A-4B. Note that this method focuses specifically on the formation of a transistor channel instead of source regions, drain regions, gate oxides, and / or other transistor components. These additional transistor components may be formed using conventional techniques not described in detail herein. These additional components may be formed at any stage of the method of flow diagram 200. For example, the source and / or drain regions may be formed before or after the transistor channel.

[0019]

[0028] The method may include providing (202) a silicon carbide layer. The silicon carbide layer may serve as a base upon which one or more silicon carbide transistors and other semiconductor structures are formed. While the examples described herein show a single silicon carbide transistor structure, this single structure is provided for illustrative purposes only and is not intended to be limiting. In practice, the silicon carbide layer may include multiple transistors arranged in various patterns along with other semiconductor circuits and / or structures. The silicon carbide layer may include a layer of silicon carbide deposited on an underlying substrate. Alternatively, the substrate itself may be formed of silicon carbide (e.g., instead of conventional silicon).

[0020]

[0029] The method may include implanting p-type dopants into the silicon carbide layer to form a p-type doped region (204). FIG. 3A shows a silicon carbide transistor 300 having a counter-doped region 304 according to some embodiments. The silicon carbide transistor 300 may include a silicon carbide layer 302, as described above. The p-type doped region 304 may be formed in the silicon carbide layer 302 by implanting the p-type dopants into the silicon carbide layer 302. For example, some embodiments may use an implantation process to dope the silicon carbide layer 302 with a dopant such as aluminum. The p-type doped region 304 may also be generally referred to as a p-type well. The p-type doped region 304 may extend to a depth below the source region 314 and / or the drain region 316. The source region 314 and / or the drain region 316 may be formed by implanting an n-type dopant, such as nitrogen, into the silicon carbide layer 302. The p-type doped region 304 may extend laterally beyond the vertical edges of the source region 314 and / or the drain region 316 such that the source region 314 and / or the drain region 316 are formed entirely within the p-type doped region 304, as shown in FIG. 3A.

[0021]

[0030] The method may include implanting 206 p-type dopants into the silicon carbide layer 302 to form a counter-doped region. As shown in FIG. 3A , the counter-doped region 306 may include n-type doped silicon carbide between the source region 314 and the drain region 316. The counter-doped region 306 may further be disposed directly below the gate oxide 310. For example, the counter-doped region 306 may be located between the gate oxide 310 and the p-type doped region 304 in the channel. In some embodiments, the counter-doped region 306 may directly contact the gate oxide 310 such that there is no intermediate layer between the counter-doped region 306 and the gate oxide 310. The counter-doped region 306 may be doped using any type of n-type dopant, such as nitrogen or other similar material. In forming the counter-doped region 306, n-type dopants may be implanted into the p-type doped region 304 to form the counter-doped region 306. A portion of the p-type doped region 304 and the counter-doped region 306 between the source region 314 and the drain region 316 may together form a channel region 322 of the silicon carbide transistor 300. When a sufficient gate voltage is applied to the gate 312 of the silicon carbide transistor 300, a conductive channel may form in the channel region 322.

[0022]

[0031] Some embodiments may further include forming a shallow channel 311 in the counter-doped region 306. The channel 311 may be formed by applying a p-type dopant to the counter-doped region 306 at a concentration of about 1e15 cm3 to 1e17 cm3. The depth of the channel 311 may be between about 20 nm and about 100 nm.

[0023]

[0032] The silicon carbide transistor 300 may further include a source 318 and a drain 320. The source 318 and the drain 320 may be formed from any conductive material to provide electrode contacts to the silicon carbide transistor 300. The gate oxide 310 may be formed from any oxide or insulating material (e.g., silicon oxide). The gate 312 may be formed on top of the silicon oxide 310 using existing techniques. Various dimensions may be used for any of the regions and components of the silicon carbide transistor 300. By way of example, the length of the gate 312 and / or the length of the channel region 322 may be between about 8 μm and about 15 μm (e.g., about 10 μm), depending on the embodiment.

[0024]

[0033] Adding only a counter-doped region 306 with a relatively low level of doping within the p-type doped region 304 can dramatically increase the normalized drive current through the silicon carbide transistor 300. For example, in some transistor configurations with the counter-doped region 306, the normalized drive current for the p-type doped region 304 can be increased by approximately 1e17 cm. 3 A doping concentration of less than 1e17 cm can be used. This level of doping can increase the drive current through the silicon carbide transistor 300 by a factor of eight. In fact, this low level of doping in the p-type doped region 304 has generally been used precisely to increase the drive current through the transistor. However, increasing the drive current by adding a counter-doped region 306 with a low level of p-type doping also increases the threshold voltage for operating the transistor. For example, adding about 1e17 cm for the p-type doped region 304 3 A doping concentration of less than 0.1 V may result in a threshold voltage of approximately −10 V for operating the silicon carbide transistor 300. This relatively high threshold voltage may preclude the use of the silicon carbide transistor 300 in certain applications, despite increased drive current.

[0025]

[0034] To solve this technical problem, some embodiments may increase the doping concentration of the p-type doped region 304 when used in combination with the counter-doped region 306. For example, some embodiments may increase the doping concentration of the p-type doped region 304 to about 1e18 cm 3 or more. This high doping concentration in the p-type doped region 304 still increases the drive current by approximately 1.7 times (i.e., a 70% increase in performance compared to embodiments with lower doping levels), while only raising the threshold voltage to approximately −3 V. This provides a silicon carbide transistor 300 with a corresponding increase in drive current that is much smaller than the increase in threshold voltage. These designs may therefore be more versatile and may result in lower leakage current, reduced power handling, and easier integration into various on-chip systems.

[0026]

[0035] About 1e18 cm for p-type doped region 304 3 These doping levels have not been used prior to this disclosure due to the reduced mobility and drive current in the channel region, however, it has been discovered that these higher doping concentrations can significantly reduce the increase in threshold voltage while still producing a moderate gain in drive current.

[0027]

[0036] As mentioned above, in some embodiments, for p-type doped regions 304 with various thresholds and / or spacings, the thickness may be about 1e18 cm. 3 Doping levels of about 1e18 cm or greater may be used. For example, in some embodiments, 3 ~About 2e18cm 3 Distance: approximately 2e18cm 3 ~About 3e18cm 3 Distance: approximately 3e18cm 3 ~About 4e18cm 3 Distance: approximately 4e18cm 3 ~About 5e18cm 3 Between the two, approximately 5e18cm 3 ~About 6e18cm3 Distance: approximately 6e18cm 3 ~About 7e18cm 3 Distance: approximately 7e18cm 3 ~About 8e18cm 3 Distance: approximately 8e18cm 3 ~About 9e18cm 3 Distance: approximately 9e18cm 3 ~About 1e19cm 3 Between the two, approximately 1e19cm 3 ~About 2e19cm 3 Distance: approximately 2e19cm 3 ~About 3e19cm 3 Distance: approximately 3e19cm 3 ~About 4e19cm 3 Distance: approximately 4e19cm 3 ~About 5e19cm 3 Between the two, approximately 5e19cm 3 ~6e19cm 3 Distance: approximately 6e19cm 3 ~About 7e19cm 3 Distance: approximately 7e19cm 3 ~approx. 8e19cm 3 Distance: approximately 8e19cm 3 ~About 9e19cm 3 Distance: approximately 9e19cm 3 ~About 1e20cm 3 Between, or about 1e20cm 3 Doping levels above 0.1 can be used. Some embodiments may place an upper limit on the doping level to minimize reduction in drive current.

[0028]

[0037] In addition to the silicon carbide transistor 300 shown in FIG. 3A , the method of flow diagram 200 can be used to form a silicon carbide trench transistor. FIG. 3B illustrates a silicon carbide transistor 301 having a counter-doped region 370 according to some embodiments. The silicon carbide trench transistor 301 can include a silicon carbide drift layer 364. A p-type doped region 360 can be formed in the silicon carbide layer 364 by implanting a p-type dopant into the silicon carbide layer 364. For example, some embodiments may use an implantation process to dope the silicon carbide layer 364 with a dopant such as aluminum. The p-type doped region 360 can also be generally referred to as a p-type well. The p-type doped region 360 can extend to a depth below the source electrode 350.

[0029]

[0038] The silicon carbide trench transistor 301 may further include an isolation region 354. The isolation region 354 may extend laterally over a gate 356 surrounded by a gate oxide 358. The gate 356 may be formed as a trench in a p-type doped region 360 and a silicon carbide drift layer 364. The trench may be aligned with the gate oxide 358. An N-well may be formed by implanting an n-type dopant (e.g., nitrogen) into the p-type doped region 360.

[0030]

[0039] As described above, the method may further include implanting 206 n-type dopants into the silicon carbide layer 364 and / or the p-type doped region 360 to form a counter-doped region 368. As shown in FIG. 3B , the counter-doped region 368 may include n-type doped silicon carbide lining a trench for the gate 356. For example, a trench may be formed in the p-type doped region 360 and / or the silicon carbide drift layer 364. The lining of the trench may then be doped with an n-type dopant to form the counter-doped region 368. The trench may then be lined with a gate oxide 358 and filled with material for the gate 356. The counter-doped region 368 may be located directly below the N-well 352. In some embodiments, the N-well 352 may extend laterally beyond the counter-doped region 368 and / or beyond the isolation region 354. In some embodiments, the N-wells 352 may be formed in direct contact with the counter-doped regions 368 and / or in direct contact with the gate oxide 358, such that there is no intermediate layer between the N-wells 352 and / or the gate oxide 358. Other embodiments may allow for an intermediate layer. Some embodiments may also provide recesses between the counter-doped regions 368 and the N-wells 352. These gaps may be filled with P-type doped regions 360, or alternatively, with a pocket implant, as described below. The counter-doped regions may extend beyond the bottom of the pre-doped regions 360 but may terminate before the bottom of the gate oxide 358. Alternatively, as shown in FIG. 3B, the counter-doped regions 368 may extend into the bottom of the gate oxide 358, and in some embodiments, may extend beyond the bottom of the gate oxide 358.

[0031]

[0040] Counter-doped region 368 may be doped using any type of n-type dopant, such as nitrogen or other similar materials. In forming counter-doped region 368, n-type dopants may be implanted into p-type doped region 360 to form counter-doped region 360. The portion of p-type doped region 360 between source electrode 350 and drain 366, counter-doped region 368, and silicon carbide drift layer 364 may together form channel region 362 of silicon carbide trench transistor 301. When a sufficient gate voltage is applied to gate 356 of silicon carbide transistor 301, a conductive channel may form in channel region 362. The doping levels of p-type doped region 360 and counter-doped region 368 may be the same as or similar to those described above for silicon carbide transistor 300. The relative doping of counterdoped region 368 and P-type doped region 360 may also be used as described above to produce similar beneficial effects.

[0032]

[0041] In addition to increasing the doping concentration, some embodiments may further improve the operation of the silicon carbide transistor 300 by adding pocket implants on one or both sides of the counter-doped region 306. Accordingly, the method of flow diagram 200 may optionally include implanting a first p-type doped pocket region (208) and / or implanting a second p-type doped pocket region (210). FIG. 4A shows a silicon carbide transistor 400 with pocket implants, according to some embodiments. For illustrative purposes only, the silicon carbide transistor 400 may include many of the same regions and components shown above in the silicon carbide transistor 300 of FIG. 3A. For example, the silicon carbide transistor 400 may include a silicon carbide layer 302, a p-type doped region 304, a counter-doped region 306, a source region 314, a drain region 316, a source 318, a drain 320, a gate oxide 310, a gate 312, a channel region 322, etc.

[0033]

[0042] Additionally, the channel region 322 may further include a first pocket region 402 and / or a second pocket region 404. The first pocket region 402 and / or the second pocket region 404 may be formed by implanting a p-type dopant into the silicon carbide of the counter-doped region 306. For example, a p-type dopant such as aluminum may be implanted into the first pocket region 402 and / or the second pocket region 404. These pocket regions may act as a potential barrier to the flow of electrons. It has been discovered that forming this potential barrier can recover some of the threshold voltage loss caused by the addition of the counter-doped region 306.

[0034]

[0043] It should be noted that first pocket region 402 and second pocket region 404 differ significantly from previous features of silicon transistors, which may be referred to as "halo" implants or regions. For example, previous halo implants in silicon transistors were typically formed around the bottom of the source and drain regions to prevent punch-through and leakage current between the source / drain depletion regions. These halo implants were traditionally located below the current flow channel, along the bottom edges or corners of the source and drain regions. Previous halo implants did not extend all the way to the gate oxide or into counter-doped regions of the channel, if such regions exist.

[0035]

[0044] In contrast to halo implants in silicon transistors, the pocket regions 402, 404 in the silicon carbide transistor 400 may be formed between the source and drain regions and the counter-doped regions. For example, a first pocket region 402 may be formed between the source region 314 and the counter-doped region 306, while a second pocket region 404 may be formed between the drain region 316 and the counter-doped region 306. Thus, the pocket regions 402, 404 differ in both location and purpose from the halo implants in silicon transistors.

[0036]

[0045] In some embodiments, the pocket regions 402, 404 may extend upward to contact the gate oxide 310. In some embodiments, the pocket regions 402, 404 may not extend below the counter-doped region 306, thereby not extending into the p-type doped region 304. For example, the pocket regions 402, 404 may extend downward approximately halfway to the depth (i.e., the vertical dimension in FIG. 4A ) of the counter-doped region 306. A counter-doped region 306 having a depth of approximately 200 nm may include pocket regions 402, 404 having a depth of approximately 100 nm. As described below in FIG. 7 , variation in the depth of the pocket regions 402, 404 can be used to adjust the tradeoff between drive current and threshold voltage. Similarly, variation in the length of the pocket regions 402, 404 in the horizontal dimension in FIG. 4A can also be used to further adjust this tradeoff, as described below in FIG. 8 .

[0037]

[0046] 4B shows a silicon carbide trench transistor 401 with pocket implants according to some embodiments. By way of example only, the silicon carbide transistor 401 may include many of the same regions and components shown above in the silicon carbide transistor 301 of FIG. 3B. For example, the silicon carbide trench transistor 401 may include a source electrode 350, a drain 366, an isolation region 354, an N-well 352, a gate oxide 358 and a counter-doped region 368 surrounding the gate 356, a p-type doped region 360, a silicon carbide drift layer 364, a channel region 362, and / or other features.

[0038]

[0047] Additionally, channel region 362 may further include first pocket region 450 and / or second pocket region 452. First pocket region 450 and / or second pocket region 452 may be formed by implanting p-type dopants into the silicon carbide of counterdoped region 368 and / or P-type doped region 360. For example, a p-type dopant, such as aluminum, may be implanted into first pocket region 450 and / or second pocket region 452. As discussed above, these pocket regions may act as potential barriers to electron flow.

[0039]

[0048] The pocket regions 450, 452 of the silicon carbide trench transistor 401 may be formed between the N-wells 352 within the counter-doped regions 368. The pocket regions 450, 452 may extend laterally beyond the counter-doped regions 368. The N-wells 352 may extend laterally further beyond the pocket regions 450, 452. In some embodiments, the pocket regions 450, 452 may directly contact the N-wells 352, the counter-doped regions 368, and / or the gate oxide 358, with no intervening layers between them. In other embodiments, small intervening layers may be present.

[0040]

[0049] 5 shows graphs 500, 502 illustrating how adjusting the doping concentration of the pocket regions 402, 404 can affect threshold voltage shift and current gain, according to some embodiments. As shown in these graphs 500, 502, increasing the doping concentration of the pocket regions 402, 404 can increase the threshold voltage shift while simultaneously decreasing the current gain. Various levels of doping concentration for the pocket regions 402, 404 can be used to adjust the threshold voltage and / or current gain to desired levels. For example, in some embodiments, a doping concentration of about 1e17 cm 3 ~About 2e17cm 3 Distance: approximately 2e17cm 3 ~About 3e17cm 3 Between the two, approximately 3e17cm 3 ~About 4e17cm 3Between the two, approximately 4e17cm 3 ~About 5e17cm 3 Between the two, approximately 5e17cm 3 From about 6e17cm 3 Distance: approximately 6e17cm 3 From about 7e17cm 3 Between the two, approximately 7e17cm 3 ~About 8e17cm 3 , about 8e17cm 3 ~About 9e17cm 3 , about 9e17cm 3 ~About 1e18cm 3 Pocket region doping levels between about 1e18 cm3 and above can be used.

[0041]

[0050] In some embodiments, the doping levels of the pocket regions 402, 404 may be selected based on a desired threshold voltage shift. For example, graph 500 shows various doping levels of the pocket regions 402, 404, with the doping concentration of the counterdoped region 306 being approximately 1e17 cm 3 Using graph 500, a threshold voltage shift of approximately 0.0 V is obtained by 3 A doping concentration of about 1.4e17 cm can be selected. Graph 502 shows the corresponding percentage of current gain as a function of the same doping concentration in the pocket regions 402, 404. For example, 3 Using a doping concentration of 1000 Ω results in a current gain of approximately 45%.

[0042]

[0051] Some design methods may involve increasing or decreasing the doping concentrations of the pocket regions 402, 404 to select a desired threshold voltage shift and current gain. For example, a predetermined threshold voltage shift may be selected, and the corresponding doping concentrations of the pocket regions 402, 404 may be selected from a data table or graph generated from experimental or simulation results. Similarly, a predetermined current gain may be selected, and the corresponding doping concentrations of the pocket regions 402, 404 may be selected from a data table or graph.

[0043]

[0052] 6 illustrates graphs 600, 602 that illustrate how adjusting the doping concentration of the counter-doped region 306 can affect threshold voltage shift and current gain, according to some embodiments. As shown in these graphs 600, 602, increasing the doping concentration of the counter-doped region can shift the voltage threshold and current gain as discussed above in FIG. 5. Various levels of doping concentration for the counter-doped region 306 can be used to adjust the threshold voltage and / or current gain to desired levels. Graphs 600, 602 illustrate a doping concentration of approximately 2e17 cm 3 1 shows threshold voltage and current gain as a function of pocket doping concentration for a counter doping concentration of about 1e17 cm. Other similar graphs or data sets can be generated for each doping concentration available in the counter doped region. For example, in some embodiments, 3 ~About 2e17cm 3 Distance: approximately 2e17cm 3 ~About 3e17cm 3 Between the two, approximately 3e17cm 3 ~About 4e17cm 3 Between the two, approximately 4e17cm 3 ~About 5e17cm 3 Between the two, approximately 5e17cm 3 ~About 6e17cm 3 Distance: approximately 6e17cm 3 ~About 7e17cm 3 Between the two, approximately 7e17cm 3 ~About 8e17cm 3 , about 8e17cm 3 ~About 9e17cm 3 , about 9e17cm 3 ~About 1e18cm 3 Doping levels of the counter-doped region 306 between about 1e18 cm3 and above can be used.

[0044]

[0053] In some embodiments, the doping level of the counter-doped region 306 may be selected based on the desired threshold voltage shift or other performance characteristics of the silicon carbide transistor. For example, graph 600 shows a doping level of 2e17 cm3 6 shows how a counter-doped region concentration of 402 can create an "always-on" device. By increasing the doping concentration of the pocket regions 402, 404, a significant 77% current gain can be achieved without significantly shifting the threshold voltage in graph 602.

[0045]

[0054] Some design methods may involve increasing or decreasing the doping concentration of the pocket regions 402, 404 and increasing or decreasing the doping concentration of the counter-doped region 306 to select a desired threshold voltage shift and current gain. For example, a predetermined threshold voltage shift may be selected, and the corresponding doping concentrations of the pocket regions 402, 404 may be selected from a data table or graph generated from experimental or simulation results for various levels of doping concentration of the counter-doped region 306. Similarly, a predetermined current gain may be selected, and the corresponding doping concentrations of the pocket regions 402, 404 may be selected from a data table or graph specific to the doping concentration of the counter-doped region 306.

[0046]

[0055] 7 shows graphs 700, 702 illustrating how adjusting the depth of the pocket regions 402, 404 can affect threshold voltage shift and current gain, according to some embodiments. As used herein, the "depth" of the pocket regions 402, 404 refers to the depth in the vertical dimension shown in FIG. 4. As shown in these graphs 700, 702, increasing the depth of the pocket regions 402, 404 can increase the threshold voltage shift while simultaneously decreasing the current gain. Varying the depth of the pocket regions 402, 404 can be used to adjust the threshold voltage and / or current gain to desired levels. For example, some embodiments may employ pocket region depths between about 0 nm and about 10 nm, about 10 nm and about 20 nm, about 20 nm and about 30 nm, about 30 nm and about 40 nm, about 40 nm and about 50 nm, about 50 nm and about 60 nm, about 60 nm and about 70 nm, about 80 nm and about 90 nm, about 90 nm and about 100 nm, about 100 nm and about 110 nm, about 110 nm and about 120 nm, about 120 nm and about 130 nm, about 130 nm and about 140 nm, about 140 nm and about 150 nm, about 150 nm and about 160 nm, about 160 nm and about 170 nm, about 170 nm and about 180 nm, about 180 nm and about 190 nm, about 190 nm and about 00 nm, and greater than about 200 nm. As shown in graphs 700 and 702, in some embodiments, best performance may be found at pocket depths of less than about 100 nm. For example, a shallower pocket depth may result in more threshold voltage loss without a significant difference in drive current due to partial depletion of the pocket region. The optimal depth of the pocket region may depend on the doping concentration of the counter-doped region 306; therefore, additional graphs or data sets may be generated for various concentrations of the pocket region and / or counter-doped region based on the needs of each particular embodiment.

[0047]

[0056] In some embodiments, the depth of the pocket regions 402, 404 may be selected based on the desired threshold voltage shift. For example, graph 700 shows a depth of approximately 1e17 cm 3Graph 700 shows various depth levels of pocket regions 402, 404 having a doping concentration of about 1 μm and a pocket length of about 1 μm. Using graph 700, the depth can be selected to produce a desired threshold voltage shift. Graph 702 shows the corresponding percentage of current gain as a function of the same depth of pocket regions 402, 404. For example, using a depth of about 100 nm produces a current gain of about 52% with a threshold voltage shift of about −0.9 V.

[0048]

[0057] Some design methods may involve increasing or decreasing the depth of the pocket regions 402, 404 to select a desired threshold voltage shift and current gain. For example, a predetermined threshold voltage shift may be selected, and the corresponding depth of the pocket regions 402, 404 may be selected from a data table or graph generated from experimental or simulation results. Similarly, a predetermined current gain may be selected, and the corresponding depth of the pocket regions 402, 404 may be selected from a data table or graph.

[0049]

[0058] 8 shows graphs 800, 802 illustrating how adjusting the length of the pocket regions 402, 404 can affect threshold voltage shift and current gain, according to some embodiments. As used herein, the "length" of the pocket regions 402, 404 refers to the length of the horizontal dimension shown in FIG. 4A. As shown in these graphs 800, 802, increasing the length of the pocket regions 402, 404 can increase the threshold voltage shift while simultaneously decreasing the current gain. Varying the lengths of the pocket regions 402, 404 can be used to adjust the threshold voltage and / or current gain to desired levels. For example, in some embodiments, the thickness may be between about 0.0 μm and about 0.1 μm, between about 0.1 μm and about 0.2 μm, between about 0.2 μm and about 0.3 μm, between about 0.3 μm and about 0.4 μm, between about 0.4 μm and about 0.5 μm, between about 0.5 μm and about 0.6 μm, between about 0.6 μm and about 0.7 μm, between about 0.7 μm and about 0.8 μm, between about 0.8 μm and about 0.9 μm, between about 0.9 μm and about 1.0 μm, or between about 1.0 μm and about 2.0 μm. Pocket region lengths between about 0.0 μm and about 1.1 μm, between about 1.1 μm and about 1.2 μm, between about 1.2 μm and about 1.3 μm, between about 1.3 μm and about 1.4 μm, between about 1.4 μm and about 1.5 μm, between about 1.5 μm and about 1.6 μm, between about 1.6 μm and about 1.7 μm, between about 1.7 μm and about 1.8 μm, between about 1.8 μm and about 1.9 μm, and between about 1.9 μm and about 2.0 μm may be used. As shown in graphs 800 and 802, in some embodiments, best performance may be found within a pocket length depth range of between about 0.5 μm and about 1.0 μm. With longer pocket lengths, pocket doping may have more of an impact on device resistance compared to its impact on threshold voltage.

[0050]

[0059] In some embodiments, the length of the pocket regions 402, 404 may be selected based on the desired threshold voltage shift. For example, graph 800 shows a length of approximately 1e17 cm 3Graph 800 shows various length levels of pocket regions 402, 404 having a doping concentration of about 1.0 μm and a pocket depth of about 100 nm. Using graph 800, the depth can be selected to produce a desired threshold voltage shift. Graph 802 shows the corresponding percentage of current gain as a function of the same depth of pocket regions 402, 404. For example, using a length of about 1.0 μm produces a current gain of about 52% with a threshold voltage shift of about −0.9 V.

[0051]

[0060] Some design methods may involve increasing or decreasing the depth of the pocket regions 402, 404 to select a desired threshold voltage shift and current gain. For example, a predetermined threshold voltage shift may be selected, and the corresponding length of the pocket regions 402, 404 may be selected from a data table or graph generated from experimental or simulation results. Similarly, a predetermined current gain may be selected, and the corresponding length of the pocket regions 402, 404 may be selected from a data table or graph.

[0052]

[0061] As used herein, terms such as "about," "approximately," or "substantially" may be interpreted as being within the range expected by one of ordinary skill in the art in light of this specification. For example, these terms may be interpreted as plus or minus 10% from the nominal value.

[0053]

[0062] In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0054]

[0063] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments provides an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments, as set forth in the appended claims.

[0055]

[0064] Specific details are given in the above description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments can be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0056]

[0065] It should also be noted that particular embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when operations are completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function or the main function.

[0057]

[0066] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media that can store, contain, or carry one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or a hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0058]

[0067] Furthermore, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented by software, firmware, middleware, or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. One or more processors may perform the necessary tasks.

[0059]

[0068] While features have been described in the foregoing specification with reference to specific embodiments thereof, it should be recognized that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or together. Moreover, embodiments may be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of the specification. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

[0060]

[0069] Furthermore, for purposes of explanation, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described. Furthermore, it should be understood that the methods described above may be performed by hardware components or embodied by sequences of machine-executable instructions, which can be used to cause a machine, such as a general-purpose or special-purpose processor, or logic circuitry programmed with the instructions, to perform the methods. These machine-executable instructions may be stored on one or more machine-readable media (e.g., a CD-ROM or other type of optical disk, a floppy diskette, a ROM, a RAM, an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or another type of machine-readable medium suitable for storing electronic instructions). Alternatively, the methods may be implemented by a combination of hardware and software.

Claims

1. 1. A silicon carbide transistor, comprising: Source region, Drain region, gate oxide, and a channel region between the source and drain regions and below the gate oxide, Approximately 1e18cm ３ a p-type doped silicon carbide region that is doped at a higher concentration; a counter-doped region comprising n-type doped silicon carbide, the counter-doped region being between the p-type doped silicon carbide region and the gate oxide; a channel region including 1. A silicon carbide transistor comprising:

2. 2. The silicon carbide transistor of claim 1, wherein said channel region further comprises a first p-type doped pocket region between said source region and said counter-doped region.

3. 3. The silicon carbide transistor of claim 2, wherein said channel region further comprises a second p-type doped pocket region between said drain region and said counter-doped region.

4. The counterdoped region has a thickness of about 1e18 cm ３ 10. The silicon carbide transistor of claim 1, wherein the silicon carbide transistor is doped to a concentration of less than 1000 .mu.m.

5. The silicon carbide transistor of claim 1 , wherein the channel region has a length of about 10 μm.

6. 10. The silicon carbide transistor of claim 1, wherein the doping concentrations of the counter-doped region and the p-type doped silicon carbide region increase the threshold voltage of the silicon carbide transistor by no more than about 3 volts.

7. 10. The silicon carbide transistor of claim 1, wherein the doping concentrations of the counter-doped region and the p-type doped silicon carbide region increase drive current by about 70% or more.

8. 1. A silicon carbide transistor, comprising: Source region, Drain region, gate oxide, and a channel region between the source and drain regions and below the gate oxide, a p-type doped silicon carbide region below the gate oxide; a counter-doped region comprising n-type doped silicon carbide, the counter-doped region being between the p-type doped silicon carbide region and the gate oxide; a first p-type doped pocket region between the source region and the counterdoped region; a second p-type doped pocket region between the drain region and the counterdoped region; and A channel region including 1. A silicon carbide transistor comprising:

9. The p-type doped silicon carbide region has an area of ​​about 1e18 cm ３ The silicon carbide transistor of claim 8 which is doped to a greater extent.

10. 9. The silicon carbide transistor of claim 8, wherein the first p-type doped pocket region and the second p-type doped pocket region are in contact with the gate oxide.

11. 9. The silicon carbide transistor of claim 8, wherein the first p-type doped pocket region and the second p-type doped pocket region do not contact the p-type doped silicon carbide region.

12. 9. The silicon carbide transistor of claim 8, wherein said first p-type doped pocket region and said second p-type doped pocket region have a vertical depth that is approximately half the vertical depth of said counter-doped region.

13. 9. The silicon carbide transistor of claim 8, wherein the first p-type doped pocket region and the second p-type doped pocket region have a lateral length of between about 0.5 nm and about 2.0 nm.

14. 9. The silicon carbide transistor of claim 8, wherein the first p-type doped pocket region and the second p-type doped pocket region have a vertical depth of between about 0.5 μm and about 1.0 μm.

15. 9. The silicon carbide transistor of claim 8, wherein the first p-type doped pocket region contacts the source region and the counter-doped region.

16. 9. The silicon carbide transistor of claim 8, wherein the second p-type doped pocket region contacts the drain region and the counter-doped region.

17. 1. A method of forming a channel region for a silicon carbide transistor, comprising: providing a silicon carbide layer; A p-type dopant is implanted into the silicon carbide layer to form a layer having a thickness of about 1e18 cm between the source and drain regions. ３ forming a p-type doped region doped at a concentration equal to or greater than 1000 .mu.m; implanting an n-type dopant into the silicon carbide layer to form a counter-doped region comprising n-type doped silicon carbide between the source region and the drain region, the counter-doped region overlying the p-type dopant region; A method comprising:

18. implanting a first p-type doped pocket region between the source region and the counterdoped region; implanting a second p-type doped pocket region between said drain region and said counterdoped region; 20. The method of claim 17, further comprising:

19. 20. The method of claim 18, further comprising determining lengths and depths of the first p-type doped pocket region and the second p-type doped pocket region to produce a target threshold voltage shift and drive current gain.

20. 20. The method of claim 18, further comprising determining doping concentrations of the first p-type doped pocket region and the second p-type doped pocket region to produce a target threshold voltage shift and drive current gain.

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