Capacitance as a control of the power applied by the bias power supply

Abstract

A bias supply system and method are disclosed. The method includes coupling and decoupling a first voltage to a first node to produce a peak of a waveform and applying a step in the waveform after the peak of the waveform. A current is provided to the first node after the step in the waveform to produce a ramp of the waveform, and a capacitance at the first node is controlled to adjust the ramp of the waveform. An apparatus for producing the waveform includes the first node, a switch configured to apply the peak voltage of the waveform to the first node before the voltage step of the waveform is applied to the first node, a power supply coupled to the first node, the power supply applying the ramp voltage of the waveform at the first node after the voltage step, and a capacitor coupled to the first node and a second node.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to power supplies. More particularly, but not by way of limitation, the present disclosure relates to controlling the application of power to a load. [Background technology]

[0002] (background) Many types of semiconductor devices are fabricated using plasma-based etching techniques. If it is a conductor to be etched, a negative voltage relative to ground can be applied to the conductive substrate such that the positive ions have substantially the same energy across the surface of the substrate conductor, creating a substantially uniform negative voltage that attracts positively charged ions toward the conductor, resulting in the conductor being etched.

[0003] However, if the substrate is a dielectric, a constant voltage is ineffective for applying a voltage across the surface of the substrate. However, an alternating current (AC) voltage (e.g., a high-frequency AC or a time-varying periodic voltage waveform) can be applied to a conductive plate (or chuck) by a bias source such that the AC field induces a voltage on the surface of the substrate. During the negative portion of the applied waveform, the surface of the substrate becomes negatively charged, which causes ions to be attracted toward the negatively charged surface during the negative portion of the periodic cycle. Also, when ions collide with the surface of the substrate, the impact removes material from the surface of the substrate, resulting in etching.

[0004] During operation of the bias source, the bias source undergoes state changes and the periodic waveform can be changed consistently with the state changes to result in different ion energy distribution functions (IEDFs). For example, feature profiles and selectivity to masks and stop layers can be controlled by changing the state of the bias source and adjusting the IEDF.

[0005] In some situations, a particular distribution of ion energies (or IEDF) may be desired, which depends on the sheath voltage (V sheath ), which generally refers to the potential difference (or voltage drop) from the plasma to the substrate surface. A bias source can be utilized to control the voltage drop across the sheath, and some bias sources rely on the fundamental frequency of a voltage waveform applied to achieve a desired sheath voltage. However, some bias source topologies are limited by the range of frequencies they can provide, and in some cases, satellite bias sources are frequency synchronized with the main bias source, and therefore may not be able to adjust their frequency. As a result, new technology is needed to allow bias sources to adjust the waveform they apply when frequency control is limited. Summary of the Invention [Means for solving the problem]

[0006] (summary) The following description is not intended to be an extensive overview relating to all discussed aspects and / or embodiments, nor is it intended to identify key or critical elements relating to all discussed aspects and / or embodiments, nor is it intended to delineate the scope associated with any particular aspect and / or embodiment. Thus, the following summary is intended only to present certain concepts related to one or more aspects and / or embodiments related to the mechanisms disclosed herein in a simplified form as a prelude to the detailed description presented below.

[0007] One aspect may be characterized as a bias supply system comprising an output node, a feedback node, a bias supply source configured to apply an asymmetric periodic voltage waveform between the output node and the feedback node, a variable capacitance coupled between the output node and the feedback node, and a controller coupled to the variable capacitance, the controller configured to receive a setting defining a slope of a workpiece voltage, monitor an electrical parameter at the output node to obtain an indication of an actual slope of the workpiece voltage, and control the variable capacitance so that the actual slope of the workpiece voltage approaches the slope defined by the setting.

[0008] Another aspect may be characterized as a method for biasing a substrate, the method including coupling an output node and a feedback node of a bias supply to a plasma processing chamber; applying an asymmetric periodic voltage waveform across the output node and the feedback node to the plasma processing chamber using the bias supply; receiving a setting that defines a slope of a voltage at a surface of a workpiece in the plasma processing chamber; monitoring an electrical parameter at the output node to obtain an indication of an actual slope of the voltage at the surface of the workpiece; and controlling a variable capacitance positioned across the output node and the feedback node such that the actual slope of the workpiece voltage approaches the slope defined by the setting.

[0009] Another aspect disclosed herein may be characterized as a non-transitory processor-readable storage medium encoded with processor-readable instructions, the instructions comprising instructions for applying, with a bias source, an asymmetric periodic voltage waveform across an output node and a feedback node of the bias source; receiving a workpiece voltage setting that defines a slope of the voltage at the surface of the workpiece; monitoring an electrical parameter at the output node to obtain an indication of an actual slope of the voltage at the surface of the workpiece; and controlling a variable capacitance positioned across the output node and the feedback node such that the actual slope approaches the slope defined by the workpiece voltage setting.

[0010] Yet another aspect may be characterized as a method that includes coupling and decoupling a first voltage to a first node to produce a peak of a waveform, and applying a step in the waveform after the peak of the waveform, wherein a current is provided to the first node after the step in the waveform to produce a ramp of the waveform, and wherein a capacitance at the first node is controlled to regulate the ramp of the waveform.

[0011] Additionally, another aspect may be characterized as an apparatus for producing a waveform comprising: a first node; a switch configured to apply a peak voltage of the waveform to the first node before a voltage step of the waveform is applied to the first node; and a power supply coupled to the first node, the power supply applying a ramp voltage of the waveform at the first node after the voltage step. Also, a capacitor is coupled to the first node and the second node. In a variation of this apparatus, the capacitor is a variable capacitor, and the controller is configured to adjust the ramp voltage by adjusting the variable capacitor.

[0012] Another aspect may be characterized as a system for producing a waveform comprising a bias supply configured to apply an asymmetric periodic voltage waveform to a first node, the asymmetric periodic voltage waveform comprising a peak voltage, a voltage step following the peak voltage, and a ramp voltage, and a capacitor coupled between the first node and a second node. In some variations, the capacitor comprises a variable capacitor coupled between the first node and the second node, and the controller is adapted to enable control of the ramp voltage by controlling the variable capacitor.

[0013] These and other aspects, features, and characteristics of the present technology, as well as the method of operation and function of the associated elements of structure, and combination with economies of parts and manufacture, will become more apparent upon consideration of the following description and appended claims, with reference to the accompanying drawings, all of which form a part of this specification and in which like reference numerals designate corresponding parts in the various views. It is to be expressly understood, however, that the drawings are for purposes of illustration and description only and are not intended as a definition of the limits of the invention. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram depicting an exemplary plasma processing environment utilizing one or more bias sources in accordance with various aspects of the present disclosure.

[0015] [Figure 2] FIG. 2 is a schematic diagram depicting an embodiment of a bias supply system.

[0016] [Figure 3] FIG. 3 is a schematic diagram showing an electrical side view of the bias supply system and plasma processing chamber.

[0017] [Figure 4] FIG. 4 depicts a conceptual graph of the voltage and current waveforms generated by the bias supply system.

[0018] [Figure 5] FIG. 5 depicts conceptual graphs of voltage and current waveforms generated by another bias supply system.

[0019] [Figure 6] FIG. 6 is a block diagram depicting a control architecture in accordance with various aspects of the present disclosure.

[0020] [Figure 7] FIG. 7 is a flow chart depicting the control aspects of the present disclosure.

[0021] [Figure 8] FIG. 8 is a block diagram depicting control aspects associated with modes of operating the bias supply system.

[0022] [Figure 9] FIG. 9 is a flowchart depicting an example for controlling a variable capacitor according to various aspects of the disclosure.

[0023] [Figure 10] FIG. 10 is another flow chart depicting a method for controlling variable capacitance and frequency of a bias supply system.

[0024] [Figure 11A] FIG. 11A is a schematic diagram of the bias supply.

[0025] [Figure 11B] FIG. 11B is a schematic diagram of an alternative bias supply.

[0026] [Figure 12]FIG. 12 illustrates a block diagram depicting components that may be utilized to implement the control aspects disclosed herein in accordance with various aspects of the disclosure.

[0027] [Figure 13] FIG. 13 is a graph depicting operational aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] (Detailed explanation) The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0029] Preliminary Note: The flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, some blocks in these flowcharts or block diagrams may represent modules, segments, or portions of code, comprising one or more executable instructions for implementing the specified logical functions. The instructions may be executable by a processor or may be used to program a field programmable gate array. It should also be noted that in some alternative implementations, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may, in fact, be executed substantially in parallel, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a special-purpose hardware-based system or a combination of special-purpose hardware and computer instructions that performs the specified functions or actions.

[0030] For purposes of this disclosure, a "source generator" and an "excitation source" are those whose energy is primarily directed to generating and sustaining a plasma, while a "bias source" is those whose energy is primarily directed to generating a surface potential to attract ions and electrons from the plasma. As used herein, the terms "workpiece," "substrate," "wafer," or "wafer substrate" may be used interchangeably throughout this disclosure.

[0031] Referring initially to FIG. 1 , shown is an exemplary plasma processing environment 100, such as a deposition or etching system, in which one or more bias sources may be utilized. The plasma processing environment 100 may include many pieces of equipment coupled, directly and indirectly, to a plasma processing chamber 101, which contains a volume containing a plasma 102 and a workpiece 103 (e.g., a wafer or substrate) and an electrode 104 (which may be embedded in a substrate support). The equipment may include vacuum handling and gas delivery equipment (not shown), one or more bias sources 108, 109, one or more source generators 112, and one or more source matching networks 113. In many applications, power from a single source generator 112 is connected to one or more source electrodes 105. The source generator 112 may be a higher frequency RF generator (e.g., 13.56 MHz to 120 MHz). Electrode 105 generally represents what may be implemented using an inductively coupled plasma (ICP) source, a dual frequency capacitively coupled plasma source (CCP) with a secondary upper electrode biased at another RF frequency, a helicon plasma source, a microwave plasma source, a magnetron, or other independently operated source of plasma energy.

[0032] 1, the source generator 112 and source matching network 113 may be replaced by or augmented with a remote plasma source. Also, other variations of the system may include only a single bias source 108. It should be appreciated that many other variations of the plasma processing environment depicted in FIG. 1 may be utilized. By way of example, and not limitation, U.S. Patent No. 10,707,055, issued July 7, 2020, and U.S. Patent No. 10,811,227, issued October 20, 2020 (both of which are incorporated by reference in their entirety), disclose various types of system designs.

[0033] Also, while the following disclosure generally refers to plasma-based workpiece processing, it should be recognized that implementations can include any substrate processing in a plasma chamber. In some cases, objects other than substrates can also be processed using the systems, methods, and apparatus disclosed herein. In other words, the present disclosure also applies to plasma processing of any object in a sub-atmospheric pressure plasma processing chamber to affect surface or sub-surface changes, deposition, or removal by physical or chemical means.

[0034] Some currently used techniques often apply a time-varying radio frequency (RF) signal, such as a sinusoidal wave, as a substrate bias. This type of sinusoidal RF bias produces a time-varying substrate voltage that accelerates ions toward the workpiece surface, but the sinusoidal waveform can produce a wide, uncontrolled ion energy distribution. In contrast, consistent with aspects of the present disclosure, an asymmetric periodic waveform can be utilized to apply the substrate bias, which serves to improve plasma etching and deposition processes compared to the prior art. For example, the asymmetric waveform helps to alleviate one or more of the problems found in the prior art, most notably the wide, uncontrolled ion energy distribution typically associated with a sinusoidal bias. In this manner, the bias source of the present disclosure helps provide direct control of ion energy distribution by delivering a controlled asymmetric periodic waveform.

[0035] As shown in Figure 1, there may be multiple bias sources used to produce the corresponding asymmetric waveform. Although more than two bias sources may be utilized, Figure 1 depicts a main bias source 108 and a satellite bias source 109. The main bias source 108 in the depicted system may establish the frequency of the asymmetric periodic waveform applied to the plasma processing chamber 101.

[0036] More specifically, the main bias source 108 may provide a synchronization signal 115 (defining a synchronization frequency) to the satellite bias source 109, allowing the asymmetric periodic waveform applied by the satellite bias source 109 to be synchronized with the asymmetric periodic waveform applied by the main bias source 108. As will be recognized by those skilled in the art, this synchronization is generally beneficial, but in some bias source topologies, the frequency of the asymmetric periodic waveform is a control parameter used to achieve a desired sheath voltage (or range of sheath voltages) to produce a desired voltage (or range of voltages) at the surface of the workpiece 103 to produce a desired distribution of ion energy. However, the satellite bias source 109 is limited to applying the frequency established by the main bias source 108, and as a result, the frequency of the satellite bias source 109 may not be able to be controlled to achieve a desired sheath voltage.

[0037] Even outside the context of the primary bias source 108 controlling the frequency of the satellite bias sources 109, a single bias source may be limited by the range of asymmetric periodic waveform frequencies it can apply, and as a result, even a single bias source may not be able to be controlled to achieve the desired sheath voltage. For example, if a plasma processing chamber has a high chuck capacitance, it may be easy to reach the lower limit of its fundamental frequency bias source before it is able to obtain the desired sheath voltage.

[0038] To address issues associated with frequency limitations that a bias source may have, a variable capacitance may be added to the output of a bias source (e.g., bias source 109) so that it can be adjusted to shift the frequency range required to achieve a desired sheath voltage or range of sheath voltages. The variable capacitance may also be varied to control the sheath voltage when the bias source operates at a fixed fundamental frequency.

[0039] 2, for example, shown is a bias supply system 200 comprising a controllable capacitance 250 coupled between an output node 210 and a feedback node 212. The depicted bias supply system 200 may be implemented within a single bias supply housing; in these implementations, the bias supply system 200 may also be characterized as a bias supply. In other implementations, the variable capacitance 250 may be implemented as an external variable capacitance located outside the bias supply housing 208, and the remaining components depicted in FIG. 2 may be implemented with the bias supply housing as part of the bias supply. The components within the bias supply housing 208 constitute the bias supply; as a result, these components are also referred to herein as the bias supply 208.

[0040] Bias supply system 200 generally represents many variations of bias supply systems, further described herein, for applying a controllable asymmetric periodic voltage waveform. As shown, the bias supply system includes an output node 210 (also referred to as output node 210), a feedback node 212, a switch network 220, and an inductance 214 and a power supply 216 (referred to herein as V supply 216). In general, bias supply system 200 functions to apply an asymmetric periodic voltage function between output node 210 and feedback node 212. An output current i out is returned to the bias source 208 through a feedback node 212, which may be common with the load. In some cases, the load is a plasma load.

[0041] FIG. 2 also illustrates the inductor voltage v, which is the voltage across the inductance 214, which can be measured as the voltage between the output node 210 and the negative node of the power supply 216. b2 depicts examples of electrical parameters associated with bias supply system 200, including: b =I comp may be measured along the current path, which includes the inductance 214 and the power supply 216. Yet another electrical parameter that may be measured is the output current i out , which may be measured along the current path between switch network 220 and output node 210 as shown. In addition, the output voltage v out is another electrical parameter that can be measured and utilized as described herein. For example, v out may be the voltage (or potential difference) between the output node 210 and the feedback node 212. As described herein, the feedback node 212 may be grounded or another non-zero voltage in some variations of the bias supply 208. It should be appreciated that other electrical parameters of the bias supply system 200 may be monitored and / or measured depending on the particular design of the bias supply system 200.

[0042] As shown, the bias supply system 200 controls the electrical parameters (e.g., i b , v b , i out , and v out), the bias supply housing 208 may include a controller 234 that functions to control the power supply 216, the switch network 220, and / or the variable capacitance 250 based on one or more of the following: a bias voltage, a voltage drop ... It is also contemplated that the controller 234 may be implemented within the housing of another device, such as a source generator, such as source generator 112 in FIG. 1, or that the controller 234 may be implemented as a distributed controller resident within several devices.

[0043] As shown, the controller 234 controls the output current i out , the current signal 226 and the output voltage v out 2, and a voltage signal 228 indicative of the output current i. out and the output voltage v out It will be readily understood that the signals 226, 228 may be sensed by current and voltage sensors readily understood in the art to produce a current signal 226 and a voltage signal 228, respectively, which may be sampled and converted to produce digital representations of the signals 226, 228.

[0044] As discussed further herein, controller 234 is configured to receive the measurements and generally control (by providing control signals to) switch network 220 and power supply 216 to effect desired aspects (as described further herein) of the asymmetric periodic voltage waveform applied to output node 210 and feedback node 212. In addition, however, controller 234 is configured to control variable capacitance 250, as described further herein.

[0045] 3, a schematic diagram 300 is shown that electrically depicts the lumped components (e.g., lumped inductive and capacitive components) of the bias supply system 200 and the plasma processing chamber 101. As shown, the plasma processing chamber 101 has an input 310 (also referred to as input node 310) to the plasma processing chamber 101 and a sheath voltage V at the surface of the workpiece 103. s , which represents the chuck capacitance C Chuck (including the capacitance of the chuck and a workpiece, such as workpiece 103 shown in FIG. 1). As a result, the sheath voltage V s The reference to the voltage at the surface of the workpiece (V in Figure 3) w Additionally, a feedback node 312 (which may be a connection to ground) is depicted. The plasma in the processing chamber 101 (shown in FIG. 1 as plasma 102) is coupled to the sheath capacitance C sheath , diode, and current source I ion The diode represents the nonlinear diode-like nature of the plasma sheath, resulting in rectification of the applied AC field such that a direct current (DC) voltage drop appears between the workpiece 103 and the plasma 102.

[0046] As can be seen, Figure 3 also shows the lumped element capacitance C stray_0 and C stray_1 In this example, C stray_0is the lumped element capacitance representing the parasitic capacitance from the output node 210 of the bias source 208 to the feedback node 312, while C stray_1 is a lumped element capacitance representing the capacitance from the input node 310 to the feedback node 312 of the process chamber 101. In some cases, C stray_0 and C stray_1 One or more of the lumped element capacitances may include connector capacitance and filter capacitance. Also shown is variable capacitance 250, which is a parasitic capacitance C stray_0 The variable capacitance 250 is positioned so as to be in parallel with C stray0 and C stray1 and therefore the total parasitic capacitance C stray is C stray0 +C stray1 + Variable capacitance equals a capacitance of 250.

[0047] 4 and 5, shown are timing diagrams 400 and 500 associated with implementations of switch network 220 having two switches and one switch, respectively. FIGS. 4 and 5 each show an asymmetric periodic voltage waveform (v out ) and the corresponding current waveform (i out 4, the bias supply 208 disclosed herein generates an asymmetric periodic voltage waveform V out between an output node 210 of the bias supply 208 and a feedback node 212. As shown, an asymmetric periodic voltage waveform V out comprises a first segment t0 to t3, starting from a first negative voltage and reaching a second peak voltage V pp At time t3, the asymmetric periodic voltage waveform V out also comprises a second segment from t3 to t4, starting from a second negative voltage and comprising a voltage ramp between the second negative voltage and a third negative voltage level.

[0048] Asymmetric periodic voltage waveform Vout may also be characterized in terms of voltage components. As shown, the asymmetric periodic voltage waveform V out comprises a first portion (time t0 to t1) that starts with a first negative voltage and reaches a second positive peak voltage V at or near the end of the first portion. pp (at time t1). The asymmetric periodic voltage waveform V out Also during the second portion (time t1 to t2), V changes from the second peak positive voltage level to a third positive voltage level at time t2, which is slightly lower than the peak voltage level V pp At or near the end of the second portion, the asymmetric periodic voltage waveform V out is at a second negative voltage (at time t3), step ) during the third portion (time t2 to t3), the asymmetric periodic voltage waveform drops at t3 by a step voltage V step In some cases, the asymmetric periodic voltage waveform also includes a fourth portion (from time t3 to t4) that drops to a second negative voltage level at t3 and a third negative voltage level (V pk- As can be seen, at time t4, the asymmetric periodic voltage waveform V out is the peak negative voltage V pk- wherein the peak negative voltage may have the same or similar magnitude as the first negative voltage at the beginning of the cycle (i.e., at t0).

[0049] As shown in Figures 4 and 5, the asymmetric periodic voltage waveform V out is the voltage step V between times t2 and t3 step voltage step or V step is the ion at a certain energy level -E ion The energy level of the ion is V step Since it is a function of V step is a parameter that, in some embodiments, is used as a set point for the bias supply system 200.

[0050] In some circumstances, during the fourth portion of the asymmetric periodic voltage waveform (t3 to t4), the sheath voltage becomes -(E ion +ΔE ion ) may become more negative so that ions at energy levels ion The magnitude of ΔE corresponds to the distribution of ion energies 460 and 560. ion indicates that there will be a larger distribution of ion energies, with a smaller magnitude of ΔE ion indicates that there will be a smaller distribution of ion energies 460, 560. As a result, ΔE ion is another set point used in embodiments of bias supply system 200, and as discussed further herein, the frequency of the asymmetric periodic voltage waveform and / or the capacitance of variable capacitance 250 may affect ΔE ion may be used to control ΔE ion The set point is -E ion (shown in t3) and t4 -(E ion +ΔE ion ), which may be referred to as the workpiece voltage setting, and which defines the slope of the workpiece voltage (between times t3 and t4), as shown in FIGS. 4 and 5.

[0051] 4 and 5 are also shown at time t reset (the time between t0 and t3) and t ramp (the time between t3 and t4). As shown, t reset covers the time including the first, second, and third portions (t0 to t3) of the asymmetric periodic voltage waveform, while t ramp includes a fourth portion (t3 to t4). In many operating modes, t ramp is an effective approach to control the period, and hence the frequency, of the asymmetric periodic voltage waveform.

[0052] Figures 4 and 5 also show the peak negative voltage V pk- , which identifies the end of the fourth portion of the asymmetric periodic voltage function. As further described herein, the negative voltage peak V pk- may be used as a control parameter. For example, the negative voltage peak V pk- A threshold for may trigger the closing of switch S1 and the opening of switch S2 (as shown in FIG. 4) or the closing of a single switch S1, controlled with reference to FIG.

[0053] As shown in Figures 4 and 5, a complete current cycle occurs between times t0 and t3 of the asymmetric periodic voltage waveform. In addition, t between t3 and t4 ramp corresponds to the time between two adjacent complete current cycles. Aspects of the present disclosure relate to the output current i out and adjust the ion current i ion A method for compensating for (I in FIG. 3) ion Another aspect of the present disclosure addresses the problem of ion energy E ion This invention addresses the issue of methods for adjusting the level and distribution of ion energy (IEDF) within a plasma processing chamber 101.

[0054] In a variation of bias source 208 with two switches, as shown in FIG. 4, the second portion of the asymmetric periodic voltage waveform may transition to a third portion of the asymmetric periodic voltage waveform (during the time between times t1 and t2). Also, in a variation of bias source 208 with one switch, as shown in FIG. 5, t1 may be equal to t2, and the first portion of the asymmetric periodic voltage waveform may transition to a positive peak voltage level (V pp ) may end (and a second portion may begin). Further details of both the single-switch and two-switch bias supplies are further disclosed herein in connection with FIGS. 11A and 11B, while FIGS. 4 and 5 provide references for various control methodologies and various structural variations, further disclosed herein.

[0055] Illustrated in FIG. 4 is the switching sequence of the first switch S1 and the second switch S2 and the output current i provided to the output node 210. out and the output voltage v at the output node 210 out and the sheath or workpiece voltage V s ~V w (also shown in FIG. 3) and the corresponding ion energy distribution function (IEDF), depicted as ion flux versus ion energy.

[0056] As shown in FIG. 4, the first switch S1 and the second switch S2 are connected to each other to supply the output current i out may be controlled so that the output current i completes a full current cycle between times t0 and t3. During the start of the current cycle at t0, the output current i out Level-I o From t1, the current is controlled to reach a positive peak current value, and then at t2, the current o Then, at t2, the output current i out Level-I o to a peak value in the opposite direction (i.e., opposite to the positive peak current value or decreasing to a negative peak current value), and then at t3, -I o More specifically, during the positive portion of the current cycle (when the first switch S1 is closed and the second switch S2 is open), the current increases to a peak positive value and then drops back down to -I o Additionally, during the negative portion of the complete current cycle (time t2 to t3), the current increases to a negative peak value and then decreases to -I o decreases to.

[0057] As shown in FIG. 4, the first switch S1 and the second switch S2 may be controlled using an adjustable dead time, which is the time from t1 to t2 (after switch S1 is released from a closed position and before switch S2 is closed). As depicted in FIG. 4, controlling the dead time is achieved by adjusting the time t reset Furthermore, t reset and tramp Adjusting the ratio of t helps adjust the average power delivered to the plasma processing chamber by the bias supply system 200. reset Control of also allows the fundamental switching frequency to be controlled (eg, remain below a level that affects the plasma density within the plasma processing chamber 101).

[0058] Another aspect of control that can be achieved using the bias supply system 200 disclosed herein is ion current compensation I. comp More specifically, the length of the dead time, t ramp The length of t and / or the period of the periodic voltage function (between t and t) may be controlled to control the level of ionic current compensation. ramp , Dead Time, and / or Level I o is the ion current i ion may be controlled (if desired) to compensate to the point: I o =I ion -(C Chuck +C stray_1 )*Slope, and I comp =I ion -(C Chuck +C stray_0 +C stray_1 )*slope, where "slope" in this context refers to the output voltage v from t3 to t4. out As discussed further herein, the addition of variable capacitance 250 corresponds to a slope of I comp =I ion -(C Chuck +C stray_total )*slope, the parasitic capacitance C stray_total =C stray0 +C stray1 + Variable capacitance is added to the capacitance of 250.

[0059] As shown in Figure 4, when overcompensating the ion current, the sheath voltage V s(and the voltage at the surface of the workpiece 103 in FIG. 1) between times t3 and t4 (i.e., t ramp In some cases, there is a distribution of ion energies as a result of the range of sheath voltages between t3 and t4. However, the ion current is proportional to the sheath voltage V s (and the voltage at the surface of the workpiece 103) between times t3 and t4 (t ramp It should be recognized that the ion current may be undercompensated so that it is not too negative during the time frame t ramp During the time frame, V out a less negative slope and / or sheath voltage V s This can result in a positive slope at

[0060] Also, the workpiece voltage V w and sheath voltage V s is substantially constant between t3 and t4. out It is possible to adjust the slope of the flat workpiece voltage (ΔE ion =0), I comp =(1+C stray_total / C Chuck )*I ion This becomes:

[0061] Dead time and t ramp By adjusting both the frequency of the asymmetric periodic voltage waveform, t ramp By varying the voltage, an asymmetric periodic voltage waveform V out The dead time can also affect the frequency of t ramp As discussed, in some cases, there are limits to the changes that can be made to the frequency of the asymmetric periodic voltage waveform, and adjustments to the variable capacitance 250 may be necessary to reduce ΔE when frequency limits exist. ion This allows adjustment to

[0062] In a single switch network, as shown in FIG. 5, the switch network (e.g., switch network 220 in FIG. 2) outputs an output current i out But Level-I o to the peak positive value, and from there to Level-I o , and returns to the peak value in the opposite direction (i.e., the peak negative value), and then to Level -I o It should be appreciated that the peak value of the current in the first half of the current cycle (e.g., the peak positive value between t0 and t1=t2) may be different from the peak value of the current in the second half of the current cycle (e.g., the peak negative value between t1=t2 and t3).

[0063] 6, shown is a block diagram depicting general aspects of measurement, readback, and control in accordance with various aspects of the present disclosure. More specifically, FIG. 6 depicts a controller 634 (which is an example of controller 234), a switch network 220, a variable capacitance 650, and a load 608. As shown, controller 634 controls a measurement component 620, a data processing component 630, and a V step / E ion Controller 632, timing parameter estimator 633, and ΔE ion controller 636 and a gate drive signal generator 638. The depicted variable capacitance 650 is an example of variable capacitance 250 that includes a first adjustable capacitor C1 coupled between the output node and the feedback node and a series combination of a second capacitor C2 and a dissipation resistor R2 coupled between the output node and the feedback node.

[0064] The second variable capacitor C2 is an optional filtering capacitance that filters ringing that may occur due to the addition of the first variable capacitor C1. The current associated with the filtered ringing is dissipated by the dissipation resistor R2. As discussed further herein, the second variable capacitor C2 may be adjusted to filter the ringing while limiting the heat dissipated by the dissipation resistor R2.

[0065] In general, the measurement component 620 receives and samples a signal indicative of an electrical parameter value and provides a digital representation of the electrical parameter value to the data processing component 630. For example, the electrical parameter may be an output current i out and the output voltage v out It may also include I comp and v b It is contemplated that other electrical parameters, such as may also be monitored.

[0066] The current signal line 626 is provided at the output of the bias supply system 200, and outputs the output current i out , and a voltage line 628 may provide an analog signal from the current transducer indicative of the output voltage v at the output of the bias supply system 200. out An analog signal may be provided that indicates the signal (i out and v out In response to receiving the signal, the measurement component 620 samples and digitizes the signal. For example, the measurement component 620 may out and the output current i out As shown, the current signal line 626′ may optionally provide a fully digital representation of the output current i provided to the output node 210. out , and a voltage line 628′ may provide an analog signal from the current transducer indicative of the output voltage v across the output node 210 and the feedback node. out An analog signal may be provided that indicates:

[0067] Although not required, the measurement component 620 may be implemented in part by a field programmable gate array (FPGA), and the data processing component 630, V step / E ion Controller 632, timing parameter estimator 633, ΔE ion The controller 636 and the gate drive signal generator 638 may be implemented by one or more processors executing code (e.g., processor-executable code) stored in a non-transitory medium, although other combinations of hardware, software, and firmware may also be used in different embodiments.

[0068] As shown, the asymmetric periodic voltage waveform V out , output current i out , and / or I comp The digital representation of may be provided to a data processing component 630, which further processes the asymmetric periodic voltage waveform V out , output current i out and / or I comp and process the digital representation of the sheath voltage V s (representing the workpiece voltage) and E ion , V step , and ΔE ion One or more other parameter values ​​may also be provided, such as:

[0069] For example, the data processing component 630 may process E ion may be calculated.

number

[0070] In the formula, V step is V out It may be measured at

[0071] The data processing component 630 also calculates the workpiece voltage V from time t3 to time t4. wAs the difference in ion may be determined, and the reconstructed workpiece voltage V w may be determined as follows:

number

[0072] ΔE ion The relationship between and the capacitance of the variable capacitance 250 can also be understood as follows:

number

number

number

[0073] As shown, V step / E ion The controller 632 is step Set point or E ion A set point is received from an operator of the bias supply system 200 and a power supply signal V supply.set to the power supply and set the voltage of the power supply 216. step and E ion is related

number

[0074] The timing parameter estimator 633 calculates the output waveform V out and the output current i out , and may produce a pulse width control signal. In some embodiments, timing parameter estimator 633 detects when zero current flows through the switches of bias supply 208, reducing switching-related losses. Timing parameter estimator 633 also detects when t reset may be determined (as shown in Figures 4 and 5), and t reset The values ​​for may be provided to the data processing component 630.

[0075] The gate drive signal generator 638 receives the pulse width control signal 637 from the timing parameter estimator 633, the frequency set point signal f sw_set, and / or in response to synchronization signal 115, provides gate drive signals to switches of bias supply 208 (e.g., switches S1 and / or S2 in FIGS. 11A and 11B ) to control the frequency of switching of bias supply 208. While many types of switches are controlled by electrical gate drive signals, it is contemplated that optical control signals may also be used. In one non-limiting example, gate drive signal generator 638 is configured to provide optical control signals. As shown, gate drive signal generator 638 may also receive synchronization signal 115 (also referred to as common exciter signal (CEX)), which gate drive signal generator 638 may use to produce gate drive signals that result in an asymmetric periodic voltage waveform having a frequency indicated by synchronization signal 115.

[0076] As shown, ΔE ion The controller 636 generates a setpoint signal ΔE that defines values ​​for a number of relevant parameters. ion.set For example, the setpoint signal ΔE ion.set defines the slope of the negative voltage ramp (shown between t3 and t4 in Figures 4 and 5), which is related to the workpiece voltage (sheath voltage V between t3 and t4 in Figures 4 and 5). s , which defines the distribution of ion energies 460, 560. Therefore, the setpoint signal ΔE ion.set may be referred to as voltage settings, negative voltage ramp settings, workpiece-voltage settings, and ion energy distribution settings.

[0077] As shown, ΔE ion The controller 636 also controls the set point parameter ΔE ion.set The measured parameter value ΔE ion Therefore, the set point signal ΔE ion.set is a negative voltage ramp setting, ΔE ion The parameter values ​​measured for the negative voltage ramp (v between times t3 and t4 in Figures 4 and 5) outAs another example, the set point signal ΔE ion.set is the workpiece voltage setting, ΔE ion The measured parameter value for is the actual slope value of the workpiece voltage (V between times t3 and t4 in Figures 4 and 5). s (shown as the slope of

[0078] ΔE ion The controller 636 also outputs the synchronization signal 115 and a current signal i indicative of the current through the dissipation resistor R2. R2 As shown, ΔE ion The controller 636 generates a frequency setpoint signal f sw_set may be provided to the gate drive signal generator 638 to control the frequency of switching of the bias supply 208. In addition, ΔE ion The controller 636 also provides one or more control signals to the variable capacitance 250. In the embodiment depicted in FIG. ion The controller 636 provides a first control signal to control the first variable capacitor C1, and ΔE ion The controller 636 provides a second control signal to control the second variable capacitor C2.

[0079] Referring briefly to FIG. 13, shown is the switching frequency f required to reach a flat workpiece voltage for three different asymmetric periodic voltage waveforms. sw 13 is a graph depicting a first waveform 1302 of 500 volts V step The second waveform 1304 is characterized by a V step The third waveform 1306 is characterized by a V step As discussed above, the switching frequency f sw corresponds to the frequency of the asymmetric periodic voltage waveform, and the flat workpiece voltage will produce a relatively narrow distribution of ion energies.

[0080] As shown, for any of the three waveforms, the capacitance of variable capacitance 250 is increased to achieve a flat workpiece voltage at a switching frequency f sw For example, a V of 1,000 volts step Waveform 1306 with a switching frequency f will achieve a flat workpiece voltage at a frequency of 200 kHz when the value of variable capacitance 250 is zero farads (time t3 to t4 in FIGS. 4 and 5). However, if the value of variable capacitance 250 is increased to 1,000 pF, a switching frequency f sw This shift to higher frequencies (to achieve a flat workpiece voltage) can be beneficial if the bias supply 208 has limitations in its frequency range. For example, if the bias supply 208 has a V of 1,000 volts, step If the bias supply 208 can operate effectively above 300 kHz only with

[0081] 13 also illustrates the benefit of variable capacitance 250 when the frequency of the bias source is fixed. For example, if the operating frequency of bias source 208 is fixed at 350 kHz (e.g., because bias source 208 receives synchronization signal 115 and fixes its frequency at 350 kHz), adjusting variable capacitance 250 to 1,000 pF reduces the benefit when bias source 208 operates at a V of 750 volts. step , which would allow a flat workpiece voltage to be achieved.

[0082] 7, shown is a general flow chart depicting a method for controlling a bias supply system 200 that utilizes, at least in part, a variable capacitance 250. As shown, when a synchronization signal 115 (also referred to as a common exciter signal (CEX)) is utilized to control the frequency of the bias supply system 200 (block 702), the bias supply system 200 may adjust the ΔE ion However, if CEX is not utilized, the bias supply system 200 utilizes both frequency control and capacitance control methodologies to control ΔE ion (block 706).

[0083] Referring to FIG. 8, what is shown is a variable capacitance 250 that can be used to adjust ΔE ion 1 is a process flow diagram depicting a method for adjusting ΔE ion affects the distribution of ion energies (also referred to as spread), the method performed by Figure 8 can also be characterized as a method for controlling the distribution of ion energies using variable capacitance 250. As shown, Figure 8 ion The controller 836 is depicted in FIG. ion 1 is an embodiment of a controller 636. As shown, ΔE ion The controller 636 includes an optional look-up table 862, which may be provided by the data processing component 630, for determining ΔE ion Based on the value of ext_est may be used to produce the estimated value C ext_est may be used as an initial value for the variable capacitance 250 by the proportional-integral-derivative (PID) compensator 864 when producing a setting for the variable capacitance 250 .

[0084] Referring again to Figure 13, shown is an example of data that may be stored in optional lookup table 862. As shown in Figure 13, V stepis available, and the operating frequency f of the bias source 208 sw When V is known, a value for the variable capacitance 250 can be obtained. For example, V step is 500 volts and the bias supply frequency f sw When set to 500kHz, a C of 1,250pF _ext may be obtained and used (by the PID compensator 864) as a starting value for the variable capacitance 250, 650.

[0085] As shown, ΔE ion Comparator 860 of controller 836 generates a set point signal ΔE ion.set and ΔE ion and receive feedback values ​​of ΔE and ΔE to determine the desired set point (e.g., negative voltage ramp, workpiece voltage slope, or ion energy distribution). ion The error signal ΔE is the difference between the corresponding feedback value of ion_error In turn, the PID compensator 864 provides the setting C for the variable capacitance 250. _ext As one skilled in the art will appreciate, the PID compensator may be configured with a min-max limiter.

[0086] If the variable capacitance 250 comprises a single capacitor (e.g., as depicted in FIG. 3), then C _ext may be used to set a single capacitor. However, if variable capacitance 250 includes two variable capacitors (such as variable capacitance 650), capacitor controller 866 may generate signals to control the setting of the capacitors (such as capacitors C1 and C2 depicted in FIG. 6). In some implementations, the capacitors are motor-controlled variable vacuum capacitors, and capacitor controller 866 provides motor control signals (as shown in FIG. 8) to control the motors for C1 and C2. However, it is contemplated that the capacitors may each be solid-state adjustable capacitors.

[0087] 9, shown is a flowchart depicting a method for controlling variable capacitance 650 that may be performed by capacitor controller 866. As shown, the power dissipated in damping resistor R2 is P2=R2*I R2 2 (block 902), and the power loss P2 is calculated as P max If the threshold value of P is exceeded (block 904), the capacitance of C2 is reduced in block 908 to reduce the amount of energy dissipated through the damping resistor R2 (e.g., to limit the temperature of R2). The setting for C2 is max -P2 can be calculated using a simple integrator or a proportional-integrator compensator.

[0088] Capacitor C1 then becomes C _ext However, the power loss P2 is adjusted to be equal to P max If the threshold value of K*C is not exceeded (block 904), then C1 is _ext and C2 is set equal to (1-K)*C _ext (block 906), where K is a programmable value that can be greater than 0.25 and less than 0.5.

[0089] Referring to FIG. 10, what is shown is a method for controlling the ΔE using both the frequency of the asymmetric periodic waveform and the capacitance of the variable capacitance 250. ion 1 is a flow chart depicting a method for controlling ΔE ion_error An indication of ΔE is obtained (block 1002), which is ion_error = set point - ΔE ion Then, the frequency f of the asymmetric voltage waveform that achieves an acceptable error level may be obtained by calculating sw is determined (block 1004). For example, the acceptable error may be substantially zero error.

[0090] As shown, the frequency f of the asymmetric voltage waveformsw However, the bias supply system 200 can provide a minimum frequency F min and maximum frequency F max If the frequency is within a threshold range between ion_error , and values ​​for the desired frequency f sw continues to be calculated and used as the frequency of the asymmetric periodic voltage waveform in block 1004. However, the calculated frequency f sw is the minimum frequency F min and maximum frequency F max If the frequency is outside the range between f and , the frequency is clamped (block 1008) and the capacitance control algorithm described with reference to Figure 8 is invoked. In general, the method depicted in Figure 10 applies a frequency f sw ΔE using ion The bias supply system prioritizes the control of frequency f sw When the variable capacitance 250 is unable to provide a capacitance ΔE ion is adjusted to control

[0091] Figure 11A shows a single power supply V supply11A illustrates an example topology 1100A of a bias supply, such as bias supply 208, comprising a first switch S1 and a first diode D1, and a switch network 1120A comprising two active switches S1 and S2. In the variation depicted in FIG. 11A , a series combination of a first switch S1 and a first diode D1 is arranged between the bias supply's feedback node 212 and a node 862. In addition, a series combination of a second switch S2 and a second diode D2 is arranged between the node 862 and the bias supply's feedback node 212. As shown in FIG. 11A , the first diode D1 is arranged between the first switch S1 and the node 862, with its anode coupled to the first switch S1 and its cathode coupled to the node 862. The second diode D2 is arranged between the second switch S2 and the node 862, with its cathode coupled to the second switch S2 and its anode coupled to the node 862. In this arrangement, the cathode of the first diode D1, the anode of the second diode D2, and one end of the inductor L1 are coupled at node 862, while the opposite end of the inductor is coupled to the output node 210.

[0092] In operation, the first diode D1 conducts when the first switch S1 is closed, and the second diode D2 conducts when the second switch D2 is closed. The first switch S1 and the second switch S2 are controlled as depicted in FIG. 4 to generate an asymmetric periodic voltage waveform V out and the output current i out (shown in FIG. 4). Although not depicted, it should be appreciated that the positions of the first switch S1 and the first diode D1 may be interchanged. Similarly, the positions of the second switch S2 and the second diode D2 may be interchanged.

[0093] FIG. 11B illustrates a single power supply V supply 11 illustrates a fourth example topology 1100B of a bias source, such as bias source 208, comprising a first bias supply and a second bias supply, and a switch network 1120B having a single active switch S1.

[0094] 11B, a first inductor L1 is coupled between node 870 and output node 210, and a switch S1 is coupled between node 870 and feedback node 212. A diode D1 is coupled in parallel with switch S1 between node 870 and feedback node 212. In operation, switch S1 is opened and closed as shown in FIG. 5, generating an asymmetric periodic voltage function V out and the output current i out For example, application of an asymmetric periodic voltage waveform closes switch S1, producing an output current i out -I o to the peak value, -I o After switch S1 is opened, the current increases in the opposite direction, from a peak value of -I o To reduce or minimize losses, the timing parameter estimator 633 optionally adjusts the output current i out I o and provides a signal to the gate drive signal generator 638 to generate an output current i out I o When this occurs, switch S1 may be opened.

[0095] In operation, switches S1 and / or S2, as described in connection with FIGS. 11A and 11B, are operated as previously described to generate the asymmetric periodic waveform V out and the output current i out It should be appreciated that because switch S1 and diode D1 are arranged in series (e.g., in FIG. 11A), the order of switch S1 and diode D1 may be swapped. Similarly, because switch S2 and diode D2 are arranged in series, the order of switch S2 and diode D2 may also be swapped.

[0096] In many implementations, the switches disclosed herein are realized by field-effect switches such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In some implementations, the switches are realized by silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) or gallium nitride metal-oxide-semiconductor field-effect transistors (GaN MOSFETs). As another example, the switches may be realized by insulated-gate bipolar transistors (IGBTs). In these implementations, the gate drive signal generator 638 may include an electrical driver known in the art configured to apply an electrical drive signal to the switch. It is also contemplated that the drive signal may be transmitted via an optical line to convey an optical switching signal. Additionally, the switch may switch in response to an optical signal and / or an optical signal converted to an electrical drive signal.

[0097] It should be appreciated that the switches depicted herein generally represent one or more switches that can be closed and opened, respectively, to connect and disconnect a current path. For example, each switch may be realized by multiple switches arranged in series (for improved voltage capability), multiple switches arranged in parallel (for improved current capability), or each switch may consist of multiple switches arranged in a series-parallel combination (for improved voltage and / or current capability). In these variations, those skilled in the art will appreciate that each switch may be driven synchronously by a corresponding drive signal.

[0098] It should also be appreciated that any of the diodes depicted herein may be implemented with multiple diodes. For example, any diode may be implemented with multiple series-connected diodes (to improve voltage capability), multiple diodes arranged in parallel (to improve current capability), or may consist of multiple diodes arranged in a series-parallel combination (for improved voltage and / or current capability).

[0099] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0100] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

[0101] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

[0102] Many embodiments and methods described herein may be implemented using a processor in conjunction with processor-executable instructions and a field-programmable gate array (programmed by hardware description language instructions). In some embodiments, an FPGA is used for high-speed processing and control, including switching control, measurement, pulsing, and multi-level operation, while a processor is utilized for other, slower processing. Referring to Figure 12, for example, shown is a block diagram 1000 depicting the physical components of a controller that may be utilized to implement the control aspects disclosed herein.

[0103] As shown, in this embodiment, a display 1012 and non-volatile memory 1020 are coupled to a bus 1022, which is also coupled to a random access memory ("RAM") 1024, a processing portion (including N processing components) 1026, a field programmable gate array (FPGA) 1027, and a transceiver component 1028, which includes N transceivers. While the components depicted in FIG. 12 represent physical components, FIG. 12 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 12 may be realized by a general structure or distributed among additional physical components. Furthermore, it is contemplated that other existing and yet-to-be-developed physical components and architectures may also be utilized to implement the functional components described with reference to FIG. 12.

[0104] The display 1012 generally operates to provide a user interface for a user, and in some implementations, the display is realized by a touch screen display. Generally, the non-volatile memory 1020 is a non-transitory memory that functions to store (e.g., persistently store) data and processor executable code (including executable code associated with steps that effectuate the methods described herein). In some embodiments, for example, the non-volatile memory 1020 includes boot loader code, operating system code, file system code, and non-transitory processor executable code to facilitate execution of a method for predicting plasma behavior, for example, by measuring a current waveform during application of an asymmetric bias waveform.

[0105] In many implementations, non-volatile memory 1020 is an example of a non-transitory processor-readable storage medium and is realized by flash memory (e.g., NAND or ONENAND memory), although it is contemplated that other memory types may be utilized as well. While it may be possible to execute code from non-volatile memory 1020, executable code in non-volatile memory is typically loaded into RAM 1024 and executed by one or more of the N processing components in processing portion 1026.

[0106] The N processing components, in association with RAM 1024, generally operate to execute instructions encoded in non-volatile memory 1020 to enable performance of the algorithms and functions disclosed herein. While several algorithms are disclosed herein, it should be appreciated that some of these algorithms are not represented in flowcharts. Processor-executable code for effecting the methods described herein may be persistently stored in non-volatile memory 1020 and executed by the N processing components in association with RAM 1024. As one skilled in the art would appreciate, processing portion 1026 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing component or a combination of hardware and software processing components (e.g., an FPGA or FPGAs including digital logic processing portions).

[0107] Additionally or alternatively, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 1020 and accessed (e.g., during boot-up) to configure a field programmable gate array (FPGA) to implement the algorithms disclosed herein.

[0108] The input component 1030 is an electrical signal (e.g., an output current I) obtained (e.g., by a current transducer, a VI sensor, a current transducer, and / or a voltage sensor) at the output node 210 and / or the feedback node 212 of the disclosed bias supply 208. out and voltage V out A signal indicating

[0109] Although not required, in some implementations, FPGA 1027 samples the electrical signal and generates an output current I out and the output voltage V out, and may provide a digital representation of the power parameters. In some embodiments, the processing portion 1026 (in conjunction with processor-executable instructions stored in the non-volatile memory 1020) is used to realize the functional blocks disclosed herein. However, the FPGA 1027 may also be used to implement these functions. Additionally, the input component 1030 may receive a synchronization signal 115. Signals received at the input component 1030 may generally include, for example, synchronization signals, power control signals for various generators and power supply units, or control signals from a user interface. Those skilled in the art will readily understand that any of a variety of types of sensors, such as, but not limited to, directional couplers and voltage-current (VI) sensors, may be used to sample electrical parameters such as voltage and current, and that signals indicative of the power parameters may be generated in the analog domain and converted to the digital domain.

[0110] The output component 1040 generally operates to provide one or more analog or digital signals to result in gate drive signals for opening and closing the switches. The output component 1040 may also provide a control signal to control the variable capacitance 250, 650. For example, the output component 1040 may provide a control signal to control more than one capacitor, such as a single capacitor C1 or C1 and C2 (shown in FIG. 6).

[0111] The depicted transceiver component 1028 includes N transceiver chains that can be used to communicate with external devices over wireless or wired networks. Each of the N transceiver chains can represent a transceiver associated with a particular communication scheme (e.g., Wifi, Ethernet, Profibus, etc.).

[0112] As will be appreciated by those skilled in the art, aspects of the present disclosure may be embodied as a system, method, or computer program product. Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining all software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer-readable program code embodied thereon.

[0113] As used herein, the recitation of "at least one of A, B, and C" or "at least one of A, B, or C" is intended to mean "any of A, B, or C or any combination of A, B, and C." The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. An apparatus for producing a waveform, said apparatus comprising: a first node; and a switch configured to apply a peak voltage of the waveform to the first node before a voltage step of the waveform is applied to the first node; a power supply coupled to the first node, the power supply applying a ramp voltage of the waveform at the first node after the voltage step; a capacitor coupled to the first node and the second node; An apparatus comprising:

2. The apparatus of claim 1 , wherein the capacitor is a variable capacitor.

3. The capacitor is a first variable capacitor coupled between the first node and the second node; a series combination of a second capacitor and a dissipation resistor coupled between the first node and the second node; and The apparatus of claim 2 , comprising:

4. The apparatus of claim 2 , comprising a controller configured to adjust the variable capacitor and thereby adjust the lamp voltage.

5. The apparatus of claim 1 , comprising a housing enclosing the switch, the power supply, and the capacitor.

6. The apparatus of claim 1 , further comprising a housing enclosing the switch and the power supply, the capacitor being located outside the housing.

7. 2. The apparatus of claim 1, comprising: a second switch coupled to the first node through a diode, the combination of the second switch and the diode configured to apply the voltage step.

8. The apparatus of claim 1 , wherein the switch comprises a plurality of switches, the plurality of switches being synchronously actuated and configured to open and close simultaneously.

9. 1. A method for producing a waveform, the method comprising: coupling and decoupling a first voltage to a first node to produce peaks of the waveform; applying a step in the waveform after the peak of the waveform; providing a current to the first node after the step in the waveform to produce a ramp of the waveform; adjusting the ramp of the waveform by controlling a capacitance at the first node; A method comprising:

10. 10. The method of claim 9, comprising adjusting the ramp of the waveform by controlling the capacitance and controlling the frequency of the waveform.

11. controlling the frequency of the waveform to a desired frequency; adjusting the ramp of the waveform by controlling the capacitance while the frequency is at the desired frequency; The method of claim 10, comprising:

12. receiving a synchronization signal; The method of claim 11 , wherein the frequency of the waveform is controlled to be the desired frequency based on the synchronization signal.

13. Controlling the capacitance includes: controlling a first variable capacitor coupled to the first node; controlling a second variable capacitor, the second variable capacitor arranged in a series combination of a second capacitor and a dissipation resistor coupled between the first node and a second node; 10. The method of claim 9, comprising:

14. 1. A system for producing a waveform, comprising: a bias supply configured to apply an asymmetric periodic voltage waveform to a first node, the asymmetric periodic voltage waveform comprising a peak voltage, a voltage step following the peak voltage, and a ramp voltage; a capacitor coupled between the first node and a second node; A system comprising:

15. The system of claim 14 , wherein the capacitor comprises a variable capacitor coupled between the first node and the second node.

16. a controller coupled to the variable capacitor, the controller comprising: monitoring one or more electrical parameters at the first node; controlling the variable capacitor to control the lamp voltage; The system of claim 15 configured to:

17. 17. The system of claim 16, wherein the controller is configured to control the lamp voltage by controlling the variable capacitor and the frequency of the asymmetric periodic voltage waveform.

18. The controller First, controlling the lamp voltage by adjusting the frequency of the asymmetric periodic voltage waveform; adjusting the variable capacitor if adjusting the frequency does not achieve the desired lamp voltage; The system of claim 17 configured to:

19. The controller receiving a synchronization signal and setting the frequency of the asymmetric periodic voltage waveform to a synchronization frequency indicated by the synchronization signal; controlling the variable capacitor to control the lamp voltage; The system of claim 16 configured to:

20. The system of claim 14 , wherein the capacitor is located outside a housing of the bias supply.

21. The system of claim 14 , wherein the capacitor is located inside a housing of the bias supply.

22. The capacitor is a first variable capacitor coupled between the first node and the second node; a series combination of a second capacitor and a dissipation resistor coupled between the first node and the second node; and The system of claim 14, comprising:

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