Charged particle optical element, charged particle optical module, evaluation device, chip assembly, and manufacturing method

Abstract

A charged particle optical element is disclosed. The element is for use in a charged particle optical module configured to direct charged particles toward a sample along at least one beam path. In one configuration, the element includes a chip including an integrated circuit formed on a semiconductor substrate. The substrate defines at least one aperture for passing at least one beam path therethrough. The size of the substrate exceeds the die size of a lithographic imaging system used during the fabrication of the integrated circuit.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to European Application No. 23156956.7, filed February 16, 2023, which is incorporated herein by reference in its entirety. [Background technology]

[0002] FIELD OF THE INVENTION

[0002] Embodiments provided herein generally relate to devices for directing charged particles, such as electrons, toward a sample, as well as related devices and methods.

[0003]

[0003] When manufacturing semiconductor integrated circuit (IC) chips, unwanted pattern defects can occur on substrates (e.g., wafers) or masks during the fabrication process, thereby reducing yield. Defects can occur, for example, as a result of optical effects and incident particles or other processing steps such as etching, deposition, or chemical-mechanical polishing. Therefore, monitoring the degree of unwanted pattern defects is an important process in the manufacture of IC chips. More generally, inspection and / or measurement of the surface of a substrate or other object / material is an important process during and / or after its manufacture.

[0004]

[0004] Pattern evaluation systems, such as pattern inspection tools using charged particle beams, have been used to evaluate objects, for example, to detect pattern defects. These tools typically use electron microscopy techniques, such as scanning electron microscopes (SEMs). In an SEM, a primary electron beam of relatively high-energy electrons is targeted with a final deceleration step to land on the target with a relatively low landing energy. The electron beam is focused as a probing spot on the target. Interaction of the landing electrons from the electron beam with the material structure at the probing spot causes electrons, such as secondary electrons, backscattered electrons, or Auger electrons, to be emitted from the surface, which may be collectively referred to as signal electrons or, more generally, signal particles. The generated secondary electrons may be emitted from the material structure of the target.

[0005]

[0005] By scanning a primary electron beam as a probe spot over the target surface, secondary electrons can be emitted across the surface of the target. By collecting these secondary electrons emitted from the target surface, a pattern inspection tool (or apparatus) can obtain an image-like signal that represents characteristics of the material structure of the target's surface. In such an inspection, the collected secondary electrons are detected by a detector within the apparatus. The detector generates a signal in response to incident charged particles. When an area of ​​a sample is inspected, the signal contains data that is processed to generate an inspection image corresponding to that inspection area of ​​the sample.

[0006] Charged particle optical elements (e.g., electron optical elements) can be used to manipulate beams of charged particles and / or detect signal particles. Such elements may require relatively high power or may be located in locations where space is limited. Additionally, charged particles may impinge on such elements or on structures in thermal contact with such elements, leading to heating. Controlling the temperature of charged particle elements can be difficult, and / or the need to control the temperature may impose functional limitations on the elements, such as limiting their performance. Integrated circuits may be used to perform complex functions in charged particle optical elements. Integrated circuits generate heat and are typically required to operate without exceeding a maximum recommended operating temperature. Summary of the Invention

[0007]

[0007] It is an object of the present disclosure to at least partially address one or more of the problems set forth above, including, for example, improving thermal management in charged particle optical elements.

[0008]

[0008] According to one aspect of the present invention, there is provided a charged particle optical element for a charged particle optical module configured to direct charged particles along at least one beam path towards a sample, the charged particle optical element comprising a chip including an integrated circuit formed on a semiconductor substrate, the substrate defining at least one aperture for at least one beam path to pass therethrough, the size of the substrate exceeding the die size of a lithographic imaging system used during the manufacture of the integrated circuit.

[0009] Configuring the substrate to have a size that exceeds the die size can facilitate temperature control by providing additional space for cooling configurations and / or allowing heat sources to be positioned further away from the beam area. Additionally or alternatively, the increased size provides design freedom for improving mechanical support of the substrate. Improved mechanical support can contribute to effective temperature control, for example, by providing a low thermal resistance path for heat to be efficiently conducted away from the substrate.

[0010] In one embodiment, the substrate includes an inner region and a peripheral region, with integrated circuits formed within the inner region and the peripheral region being free of functional integrated circuits, the peripheral region being laterally outward of the inner region when viewed perpendicular to the major surface of the substrate. In one embodiment, a cooling element is mounted in the peripheral region and configured to extract heat from the substrate. The increased space provided by configuring the substrate size to exceed the die size facilitates configuring the cooling element to have high performance. The peripheral region provides a relatively large contact area for the cooling element, which may promote improved cooling performance. The increased space may allow the cooling element to be larger and / or may facilitate providing an effective inner channel for heat exchange fluid.

[0011] In one embodiment, the contact area between the cooling element and the substrate is greater than 10% of the die size of a lithographic imaging system used during the manufacture of integrated circuits. Providing a large contact area can improve cooling performance.

[0012]

[0012] In one embodiment, the mechanical support element is configured to mechanically support the substrate, where the mechanical support element is configured to support the substrate via a peripheral region of the substrate. The increased space provided by configuring the substrate size to exceed the die size facilitates configuring the mechanical support element to have high performance. The mechanical support element can, for example, contact the substrate over a larger area, thereby distributing forces applied to the substrate and reducing potentially damaging pressures and / or torques. Additionally, the large contact area can allow the mechanical support element to contribute to improved cooling of the substrate by providing a high thermal conduction path for heat to flow away from the substrate.

[0013]

[0013] According to one aspect of the present invention, a chip assembly is provided, the chip assembly including a chip including an integrated circuit formed on a semiconductor substrate, the size of the substrate exceeding the die size of a lithographic imaging system used during the manufacture of the integrated circuit, and a cooling element mounted in a peripheral region laterally outside the inner region in which the integrated circuit is formed, the cooling element including a heat sink body, the heat sink body defining one or more inner channels for directing the flow of a heat exchange fluid through the body.

[0014]

[0014] According to one aspect of the present invention, there is provided a method for manufacturing a charged particle optical element, the method comprising: manufacturing an integrated circuit in a die of a semiconductor wafer, the die size of the die being defined by a lithographic imaging system used during the manufacture of the integrated circuit; cutting chips from the wafer, the chips including the integrated circuit formed in a substrate derived from the wafer; and forming at least one aperture in the substrate for at least one beam path of a charged particle beam to pass through the substrate, the size of the substrate exceeding the die size of the lithographic imaging system.

[0015]

[0015] Advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, in which specific embodiments of the invention are shown and illustrated. [Brief explanation of the drawings]

[0016]

[0016] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments taken in conjunction with the accompanying drawings. [Figure 1]

[0017] FIG. 1 is a schematic diagram illustrating an exemplary evaluation device. [Figure 2]

[0018] 2 is a schematic diagram illustrating an exemplary multi-beam charged particle optical device that is part of the exemplary evaluation apparatus of FIG. 1. [Figure 3]

[0019] 2 is a schematic diagram of an exemplary charged particle optical device including a collimator element array and a scanning deflector array that is part of the exemplary evaluation apparatus of FIG. 1. [Figure 4]

[0020] 4 is a schematic diagram of an exemplary charged particle optical device array including the charged particle optical device of FIG. 3. [Figure 5]

[0021] 2 is a schematic diagram of an alternative exemplary charged particle optical device that is part of the exemplary evaluation apparatus of FIG. 1. [Figure 6]

[0022] FIG. 6 is a schematic diagram of an exemplary charged particle optics module that may be part of the charged particle optics device of FIGS. [Figure 7]

[0023] 1 is a schematic diagram of an exemplary charged particle optical element. [Figure 8]

[0024] 1 is a schematic diagram of an exemplary charged particle optical element. [Figure 9]

[0025] FIG. 9 is a schematic plan view of a charged particle optical element of the type shown in FIG. 8.

[0017]

[0026] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with inventive aspects as set forth in the appended claims. DETAILED DESCRIPTION OF THE INVENTION

[0018]

[0027] The reduction in physical size of devices and the increase in computing power of electronic devices can be achieved by significantly increasing the packing density of circuit components such as transistors, capacitors, and diodes on IC chips. This has been made possible by improvements in resolution, which allow for the creation of ever-smaller structures. The fabrication of semiconductor ICs is a complex and time-consuming process involving hundreds of individual steps. An error in any step of the process used to fabricate IC chips can adversely affect the functionality of the final product. A single defect can cause device failure. It is desirable to improve the overall yield of a process. For example, to achieve a 75% yield for a 50-step process (a step can refer to the number of layers formed on a wafer), each individual step must have a yield greater than 99.4%. If each individual step has a 95% yield, the overall process yield is as low as 7–8%.

[0019]

[0028] It is also desirable to maintain high substrate (i.e., wafer) throughput, defined as the number of substrates processed per hour. High process yield and high substrate throughput can be affected by the presence of defects. This is especially true when operator intervention is required to investigate the defects. High-throughput detection and identification of microscale and nanoscale defects by characterization systems (such as scanning electron microscopes ("SEMs")) is desirable to maintain high yields and low costs for IC chips.

[0020]

[0029] A scanning electron microscope includes a scanning device and a detector. The scanning device includes an illumination device, including an electron source, for generating primary electrons and a projection device for scanning a target, such as a substrate, with one or more focused beams of primary electrons. The primary electrons interact with the target and generate interaction products, such as signal particles, e.g., secondary electrons and / or backscattered electrons. Secondary electrons may be considered to have energies up to 50 eV. Backscattered electrons range in energy from essentially zero to the maximum energy of the charged particle device, but are conventionally designated as electrons (or signal electrons) with energies greater than 50 eV. A detector captures signal particles (e.g., secondary electrons and / or backscattered electrons) from the target as it is scanned, enabling the scanning electron microscope to generate an image of the scanned area of ​​the target. Charged particle optical device designs embodying these scanning electron microscope functions can have a single beam. To achieve higher throughput, such as for characterization, some device designs use multiple focused beams of primary electrons, i.e., multibeams. The constituent beams of a multibeam may be referred to as subbeams or beamlets. Multiple beams can scan different portions of a target simultaneously, and therefore a multi-beam evaluation system can evaluate a target much more quickly than a single-beam evaluation system, for example by moving the target at a higher speed.

[0021]

[0030] An implementation of a known multi-beam evaluation device is described below.

[0022]

[0031] The figures are schematic. Accordingly, the relative dimensions of components in the drawings have been exaggerated for clarity. In the following description of the drawings, the same or similar reference numbers refer to the same or similar components or entities, and only differences relative to individual embodiments are described. While the description and drawings are directed to electron-optical devices, it is understood that the embodiments are not used to limit the present disclosure to specific charged particles. Thus, throughout this document, references to electrons and items referred to in connection with electrons can be considered to be references to charged particles and items referred to in connection with charged particles more generally, and charged particles are not necessarily electrons.

[0023]

[0032] Reference is now made to Figure 1, which is a schematic diagram illustrating an exemplary electron beam evaluation or inspection apparatus 100. The evaluation apparatus 100 of Figure 1 includes a vacuum chamber 10, a load lock chamber 20, a charged particle optical apparatus, a front end of equipment module (EFEM) 30, and a controller 50. A charged particle optical device 40 may be located within the vacuum chamber 10. The electron optical apparatus may include a charged particle optical device 40 (also known as an electron optical device or electron beam device) and a motorized or actuated stage.

[0024]

[0033] The EFEM 30 includes a first load port 30a and a second load port 30b. The EFEM 30 may include one or more additional load ports. The first load port 30a and the second load port 30b may receive, for example, substrate front-opening integrated pods (FOUPs) containing substrates (e.g., semiconductor substrates or substrates made of other materials) or targets to be evaluated (hereinafter, substrates, wafers, and samples are collectively referred to as "targets"). One or more robotic arms (not shown) within the EFEM 30 transport the targets to the load lock chamber 20.

[0025]

[0034] The load lock chamber 20 is used to remove gas from around the target. The load lock chamber 20 may be connected to a load lock vacuum pumping system (not shown), which removes gas particles from within the load lock chamber 20. Operation of the load lock vacuum pumping system allows the load lock chamber to reach a first pressure below atmospheric pressure. The main chamber 10 is connected to a main chamber vacuum pumping system (not shown). The main chamber vacuum pumping system removes gas molecules from within the main chamber 10 so that the pressure around the target reaches a second pressure below the first pressure. After reaching the second pressure, the target can be transported to and evaluated by the charged particle optical device 40. The charged particle optical device 40 may include either a single beam or a multi-beam charged particle optical device.

[0026]

[0035] The controller 50 is electronically connected to the charged particle optical device 40. The controller 50 may be a processor (e.g., a computer) configured to control the charged particle beam evaluation apparatus 100. The controller 50 may also include processing circuitry configured to perform various signal and image processing functions. While the controller 50 is shown in FIG. 1 as being external to the structure including the main chamber 10, the load lock chamber 20, and the EFEM 30, it is understood that the controller 50 may be part of the structure. The controller 50 may be located within one of the component elements of the charged particle beam evaluation apparatus, or the controller 50 may be distributed among at least two of the component elements. While the present disclosure provides an example of a main chamber 10 housing an electron beam evaluation apparatus, it should be noted that aspects of the present disclosure, in its broadest sense, are not limited to a chamber housing a charged particle optical device. Rather, it is understood that the principles described above may also be applied to other apparatuses and other configurations of apparatuses operating under a second pressure.

[0027]

[0036] Reference is now made to FIG. 2, which is a schematic diagram of a multi-beam charged particle optical device 40 of an exemplary evaluation apparatus, such as the evaluation apparatus 100 of FIG. 1. In an alternative embodiment, the evaluation apparatus 100 is a single-beam evaluation apparatus. The charged particle optical device 40 may include an electron source 201, a beamformer array 372 (also known as a gun aperture plate, a Coulomb aperture array, or a pre-sub-beam forming aperture array), a condenser lens 310, a source converter (or micro-optic array) 320, an objective lens 331, and a target 308. In one embodiment, the condenser lens 310 is magnetic. The target 308 may be supported by a support on a stage. The stage may be motorized. The stage moves so that the target 308 is scanned by the incident electrons. The electron source 201, the beamformer array 372, and the condenser lens 310 may be components of an illumination system included by the charged particle optical device 40. The source converter 320 (also known as a source conversion unit), which will be described in more detail below, and the objective lens 331 may be components of the projection apparatus included by the charged particle optical device 40 .

[0028]

[0037] The electron source 201, the beamformer array 372, the collector lens 310, the source converter 320 and the objective lens 331 are aligned with a primary electron optical axis 304 of the charged particle optical device 40. The electron source 201 can generally generate a primary beam 302 along the electron optical axis 304 and with a (virtual or real) source crossover 301S. In operation, the electron source 201 is configured to emit electrons. The electrons are extracted or accelerated by an extractor and / or an anode to form the primary beam 302.

[0029]

[0038] The beamformer array 372 cuts edge electrons of the primary electron beam 302 to reduce the resulting Coulomb effect. The primary electron beam 302 may be trimmed by the beamformer array 372 into a specified number of sub-beams, such as three sub-beams 311, 312, and 313. It should be understood that this description is intended to apply to charged particle optical device 40 having any number of sub-beams, such as one, two, or four or more. The beamformer array 372 is configured, in operation, to block edge electrons to reduce the Coulomb effect.

[0030]

[0039] The source converter 320 is configured to convert the beam propagated by the beamformer array 372 (including sub-beams, if any) into sub-beams that are projected towards the target 308. In one embodiment, the source converter is a unit. Alternatively, the term source converter may simply be used as a general term for a group of components that form beamlets from the sub-beams.

[0031]

[0040] 2 , in one embodiment, the charged particle optical device 40 includes a beam-limiting aperture array 321 having an aperture pattern (i.e., apertures arranged in an arrangement) configured to define the outer dimensions of the beamlets (or sub-beams) projected toward the target 308. In one embodiment, the beam-limiting aperture array 321 is part of the source converter 320. In an alternative embodiment, the beam-limiting aperture array 321 is part of the main device's up-beam system. In one embodiment, the beam-limiting aperture array 321 splits one or more of the sub-beams 311, 312, 313 into beamlets such that the number of beamlets projected toward the target 308 is greater than the number of sub-beams propagating through the beamformer array 372. In an alternative embodiment, the beam-limiting aperture array 321 maintains the number of sub-beams incident on the beam-limiting aperture array 321, where the number of sub-beams may be equal to the number of beamlets projected toward the target 308.

[0032]

[0041] 2 , in one embodiment, the charged particle optical device 40 includes a pre-bending deflector array 323 having pre-bending deflectors 323_1, 323_2, and 323_3 that respectively bend the sub-beams 311, 312, and 313. The pre-bending deflectors 323_1, 323_2, and 323_3 can bend the paths of the sub-beams 311, 312, and 313 onto the beam-limiting aperture array 321.

[0033]

[0042] The charged particle optical device 40 may also include an image-forming element array 322 having image-forming deflectors 322_1, 322_2, and 322_3. There is a respective deflector 322_1, 322_2, and 322_3 associated with the path of each beamlet. The deflectors 322_1, 322_2, and 322_3 are configured to deflect the path of the beamlets toward the electron optical axis 304. The deflected beamlets form virtual images (not shown) of the source crossover 301S. In the current embodiment, these virtual images are projected onto the target 308 by the objective lens 331, forming probe spots 391, 392, and 393 on the target 308. The charged particle optical device 40 may also include an aberration compensator array 324 configured to compensate for aberrations that may be present in each sub-beam. In one embodiment, the aberration compensator array 324 includes lenses configured to act on each beamlet. The lens may take the form of an array of lenses. The array of lenses may act on different beamlets of the multi-beam. The aberration compensator array 324 may include, for example, a field curvature compensator array (not shown) with microlenses. The field curvature compensators and microlenses may be configured to compensate individual sub-beams for field curvature aberrations that are evident at the probe spots 391, 392, and 393, for example. The aberration compensator array 324 may include an astigmatism compensator array (not shown) with microastigmatism correctors. The microastigmatism correctors may be controlled to act on the sub-beams to compensate for astigmatism that would otherwise be present at the probe spots 391, 392, and 393, for example.

[0034]

[0043] The imaging element array 322, the aberration compensator array 324, and the pre-bending deflector array 323 may include multiple layers of sub-beam steering devices, some of which may be in the form of arrays, for example, micro-deflectors, micro-lenses, or micro-astigmatism correctors. The beam path may be rotationally steered. The rotational correction may be applied by magnetic lenses. Additionally or alternatively, the rotational correction may also be realized by existing magnetic lenses, such as in a focusing lens arrangement.

[0035]

[0044] The objective lens 331 focuses the beamlets onto the surface of the target 308, i.e., projects three virtual images onto the target surface. The three images formed by the three sub-beams 311-313 on the target surface form three probe spots 391, 392, and 393 on the target. In one embodiment, the deflection angles of the sub-beams 311-313 are adjusted to pass through or approach the front focus of the objective lens 331 to reduce or limit off-axis aberrations of the three probe spots 391-393. In one configuration, the objective lens 331 is magnetic. Although three beamlets are mentioned, this is merely an example. Any number of beamlets may be used.

[0036]

[0045] In one embodiment, a beam separator (not shown) is provided. The beam separator may be in the down beam of the radiation source converter 320. The beam separator may be, for example, a Wien filter including an electrostatic dipole field and a magnetic dipole field. The beam separator may be in the up beam of the objective lens 331. In operation, the beam separator may be configured to exert an electrostatic force on individual electrons of the sub-beam due to the electrostatic dipole field. In one embodiment, the electrostatic force is equal in magnitude but opposite in direction to the magnetic force exerted on individual primary electrons of the sub-beam by the magnetic dipole field of the beam separator. Thus, the sub-beams can pass through the beam separator in at least a substantially straight line with at least a substantially zero deflection angle. While the direction of the magnetic force depends on the direction of electron movement, the direction of the electrostatic force is independent of the direction of electron movement. Therefore, because the secondary and backscattered electrons (or signal electrons) generally travel in the opposite direction compared to the primary electrons, the magnetic forces acting on the secondary and backscattered electrons (or signal particles) no longer cancel out the electrostatic forces, and as a result, the secondary and backscattered electrons traveling through the beam separator are deflected away from the electron optical axis 304.

[0037]

[0046] In one embodiment, a secondary device (not shown) is provided that includes a detector element for detecting a corresponding secondary charged particle beam. When the secondary beam is incident on the detector element, the element can generate a corresponding intensity signal output. This output can be directed to an image processing system (e.g., controller 50). Each detector element can include an array that can be in the form of a grid. The array can have one or more pixels, and each pixel can correspond to an element of the array. The intensity signal output of the detector element can be the sum of signals generated by all pixels in the detector element.

[0038]

[0047] In one embodiment, a secondary projection device and associated electron detection device (not shown) are provided. The secondary projection device and associated electron detection device may be aligned with the secondary electron optical axis of the secondary device. In one embodiment, a beam separator is positioned to deflect the path of the secondary electron beam toward the secondary projection device. The secondary projection device then focuses the path of the secondary electron beam onto multiple detection regions of the electron detection device. The secondary projection device and associated electron detection device may use the secondary electrons or backscattered electrons (or signal particles) to register and generate an image of the target 308.

[0039]

[0048] Such a Wien filter, secondary device, and / or secondary projection device may be provided within the single beam evaluation device. Additionally and / or alternatively, a detection device may be present in the down-beam of the objective lens, for example, facing the sample during operation. In an alternative configuration, the detector device is positioned along the path of the charged particle beam toward the sample. Such a configuration does not have a Wien filter, secondary device, or secondary projection device. The detection device may be positioned at one or more positions along the path of the charged particle beam toward the sample, for example, around the path of the charged particle beam, facing the sample during operation. Such a detector device may have an aperture or may be annular. Different detector devices may be arranged along the path of the charged particle beam to detect signal particles with different characteristics. Electron-optical elements along the path of the charged particle beam may include one or more electrostatic plates with apertures for the path of the charged particle beam, and these electron-optical elements may be arranged and controlled to focus signal particles of different respective characteristics onto respective detector devices at different positions along the path of the charged particle beam. Such electrostatic plates may be arranged in a series of two or more adjacent plates along the path of the charged particle beam.

[0040]

[0049] Any element or group of elements in the charged particle optical device may be replaceable or field replaceable. One or more of the electron-optical components in the charged particle optical device, particularly those that act on or generate sub-beams, such as the aperture array and manipulator array, may include one or more microelectromechanical systems (MEMS). The pre-bending deflector array 323 may be a MEMS. MEMS are miniature mechanical and electromechanical elements fabricated using microfabrication techniques. In one embodiment, the charged particle optical device 40 includes apertures, lenses, and deflectors formed as MEMS. In one embodiment, the lenses and manipulators, such as the lenses and deflectors 322_1, 322_2, and 322_3, are passively or actively controllable as an entire array, individually, or in groups within the array, to control the beamlets of charged particles projected toward the target 308.

[0041]

[0050] In one embodiment, the charged particle optical device 40 may include alternative and / or additional components along the charged particle path, such as lenses and other components as described above with reference to FIGS. 1 and 2. Examples of such configurations are shown in FIGS. 3 and 4, which are described in more detail below. A detector is provided to detect charged particles emitted by the sample. The detector may be integrated into the objective lens. The detector may be on the bottom surface of the objective lens so as to face the sample during use. The detector may include an array (e.g., of detector elements) that may correspond to the array of beamlets in the multi-beam configuration. The detector (or detector elements) in the detector array may generate detection signals that may be associated with pixels in the generated image. The collection lens, objective lens, and / or detector may be formed as MEMS or CMOS devices.

[0042]

[0051] 3 is a schematic diagram of another design of an exemplary charged particle optical device 40. The charged particle optical device 40 may include a radiation source 201 and one or more electron optical assemblies. Alternatively, an electron optical apparatus including the charged particle optical device 40 may include the radiation source 201. The charged particle optical device 40 may include an upper beam limiter 252, a collimator element array 271, a control lens array 250, a scanning deflector array 260, an objective lens array 241, a beam shaping limiter 242, and a detector array. The radiation source 201 provides a beam of charged particles (e.g., electrons).

[0043]

[0052] The upper beam limiter 252 defines an array of beam-limiting apertures. The upper beam limiter 252 may be referred to as an upper beam-limiting aperture array or an up-beam beam-limiting aperture array. The upper beam limiter 252 may include a plate (which may be a plate-like object) having a plurality of apertures. The upper beam limiter 252 forms sub-beams from the beam of charged particles emitted by the radiation source 201. Beam portions other than those contributing to forming the sub-beams may be blocked (e.g., absorbed) by the upper beam limiter 252 so as not to interfere with the down-beam sub-beams. The upper beam limiter 252 may be referred to as a sub-beam-defining aperture array.

[0044]

[0053] A collimator element array 271 is provided in the down beam of the upper beam limiter 252. Each collimator element collimates a respective sub-beam. The collimator element array 271 can be formed using MEMS fabrication techniques to be spatially compact. In some embodiments, as illustrated in FIG. 3, the collimator element array 271 is the first deflection or focusing electron optical array element in the beam path in the down beam of the radiation source 201. In another configuration, the collimator can take the form, in whole or in part, of a macro-collimator. Such a macro-collimator can be in the up beam of the upper beam limiter 252, so as to act on the beam from the radiation source before generating the multiple beams. A magnetic lens can be used as the macro-collimator.

[0045]

[0054] In the down beam of the collimator element array is a control lens array 250. The control lens array 250 includes a plurality of control lenses. Each control lens includes at least two electrodes (e.g., two or three electrodes) connected to a respective potential source. The control lens array 250 may include two or more (e.g., three) plate electrode arrays connected to respective potential sources. The control lens array 250 is associated with the objective lens array 241 (e.g., the two arrays are located near each other and / or mechanically connected to each other and / or controlled together as a unit).

[0046]

[0055] As previously mentioned, the control lens array 250 is associated with the objective lens array 241. As noted above, the control lens array 250 can be thought of as providing additional electrodes to the electrodes 242, 243 of the objective lens array 241, for example, as part of the objective lens array assembly. The additional electrodes of the control lens array 250 provide an additional degree of freedom in controlling the electro-optical parameters of the sub-beams.

[0047]

[0056] For ease of illustration, lens arrays are generally illustrated herein by an array of elliptical shapes. Each elliptical shape represents one of the lenses in the lens array. An elliptical shape is conventionally used to represent a lens by analogy with the biconvex shape often employed in optical lenses. However, it should be understood that in the context of charged particle configurations as discussed herein, lens arrays typically operate electrostatically and may not require physical elements employing a biconvex shape. As noted above, the lens array may instead include a plurality of plates having apertures.

[0048]

[0057] A scan deflector array 260 may be provided that includes a plurality of scan deflectors. The scan deflector array 260 may be formed using MEMS fabrication techniques. Each scan deflector scans a respective sub-beam across the sample 208. In one embodiment, the scan deflector array 260 may be implemented using the scan deflectors described in European Application No. 2425444, which is incorporated herein by reference in its entirety, particularly with respect to the scan deflectors.

[0049]

[0058] An objective lens array 241 including multiple objective lenses is provided to direct the sub-beams onto the sample 208. Each objective lens includes at least two electrodes (e.g., two or three electrodes) connected to respective potential sources.

[0050]

[0059] The objective lens array may form part of an objective lens array assembly together with any or all of the scan deflector array 260, the control lens array 250, and the collimator element array 271. The objective lens array assembly may further include a beam shaping limiter 242. The beam shaping limiter 242 defines an array of beam limiting apertures.

[0051]

[0060] In one configuration, the beam shaping limiter 242 is structurally integral with the electrodes 302 of the objective lens array 241. The beam shaping limiter 242 is preferably located in an area of ​​low electrostatic field strength. Each of the beam limiting apertures is aligned with a corresponding objective lens in the objective lens array 241.

[0052]

[0061] In one embodiment, the charged particle optical device 40 is configured to control the objective lens array assembly (e.g., by controlling the potential applied to the electrodes of the control lens array 250) so that the focal length of the control lens is greater than the separation distance between the control lens array 250 and the objective lens array 241.

[0053]

[0062] A power supply may be provided to apply respective potentials to electrodes of the control lenses of the control lens array 250 and the objective lenses of the objective lens array 241 .

[0054]

[0063] A detector array (not shown) is provided to detect charged particles emitted from the sample 208. The detected charged particles may include any of the charged particles (e.g., signal particles) detected by a scanning electron microscope, including secondary electrons (e.g., emitted) and / or backscattered electrons from the sample 208. The detector may be an array serving a surface of the charged particle optical device facing the sample 208, such as the bottom surface of the charged particle optical device. Alternatively, the detector array may be in the up-beam of the bottom surface, or in, for example, an objective lens array or a control lens array, or in the up-beam thereof. Elements of the detector array may correspond to beamlets in a multi-beam configuration. Signals generated by detection of electrons by elements of the array are sent to a processor to generate an image. The signals may correspond to pixels of the image.

[0055]

[0064] In other embodiments, there may be provided both a macro scan deflector and a scan deflector array 260. In such a configuration, scanning of the sub-beams over the sample surface may be achieved by controlling the macro scan deflector and the scan deflector array 260 together, preferably synchronously.

[0056]

[0065] In one embodiment, as illustrated in Figure 4, an array of charged particle optical devices 500 is provided. The array 500 may include a plurality of any of the charged particle optical devices described herein, each of which simultaneously focuses a respective multi-beam onto a different region of the same sample.

[0057]

[0066] Any number of charged particle optical devices may be used in array 500. Each charged particle optical device in array 500 may be configured in any of the manners described herein when referring to a single charged particle optical device, for example, with respect to the embodiment shown and described above, particularly with reference to Figure 3. Details of such configurations are described in European Application No. 20184161.6, filed July 6, 2020, which is incorporated herein by reference with respect to methods for incorporating and adapting objectives for use in multi-device configurations.

[0058]

[0067] In the example of FIG. 4, array 500 includes a plurality of charged particle optical devices of the type described above with reference to FIG.

[0059]

[0068] An alternative design of the multi-beam charged particle optical device may have the same features as described with respect to Figure 3, but differs as described below and illustrated in Figure 5. An alternative design of the multi-beam charged particle optical device may include a focusing lens array 231 in the up-beam of the objective lens array arrangement 241, as disclosed in European Application No. 20158804.3, filed February 21, 2020, which is incorporated herein by reference for its description of a multi-beam device with a collimator and its components.

[0060]

[0069] In the embodiment of the configuration shown in and described with reference to Figure 5, the detector may be located in a similar location in the charged particle optical device 40 as shown in and described with reference to the charged particle optical device of Figure 3. The detector 240 may be integrated into the objective lens array 241 and the control lens array 250 (if present, not shown in Figure 5). The detector may have multiple detectors at different positions along the paths of the sub-beams of the multi-beam.

[0061]

[0070] A charged particle optical device array may have a plurality of multi-beam devices of this design as described with reference to the multi-beam device of FIG. 3, as shown in FIG. 4. Multiple multi-beam devices may be arranged in an array of multi-beam devices. Such a configuration is shown and described in European Application No. 20158732.6, filed February 21, 2020, which is incorporated herein by reference for its multi-device configuration of a multi-beam device featuring a multi-beam device design disclosed with a collimator at an intermediate focus. A further alternative design of a multi-beam device includes a plurality of single-beam devices.

[0062]

[0071] The charged particle optical device 40 may be a component of an evaluation apparatus (e.g., for inspection, metrology, metrology inspection, or any other type of evaluation), or part of an e-beam lithography apparatus or other type of charged particle induced sample patterning device. Multi-beam charged particle apparatus may be used in many different applications, including scanning electron microscopy as well as electron microscopy in general and lithography.

[0063]

[0072] 6 to manipulate the electron beamlets. For example, the charged particle optical module 55 may include one or more of (as a non-limiting list) an objective lens array 241, and / or a condenser lens array 231, and / or a collimator element array 271, and / or individual beam correctors, and / or deflectors, and / or a Wien filter array. In particular, the objective lens 331 and / or the condenser lens 310 and / or the control lens 250 may constitute the charged particle optical module 55. The charged particle optical module 55 is configured to create a potential difference between two or more plates (or substrates).

[0064]

[0073] FIG. 6 schematically illustrates a charged particle optics module 55. The charged particle optics module 55 is configured to direct electrons along at least one beam path toward a sample position. In the orientation shown in FIG. 6, the at least one beam path extends vertically from top to bottom through the center of the charged particle optics module 55. There may be one beam path corresponding to one electron beam. Alternatively, there may be multiple beam paths corresponding to multiple charged particle sub-beams of a multi-beam.

[0065]

[0074] As shown in FIG. 6 , in one embodiment, the charged particle optics module 55 includes multiple planar elements positioned across the beam path. In one embodiment, one or more of the planar elements are charged particle optics elements 60. The charged particle optics elements 60 are configured to act on one or more charged particle beams. As shown in FIG. 6 , in one embodiment, all of the planar elements are charged particle optics elements 60. Alternatively, one or more of the planar elements may be planar elements other than charged particle optics elements. For example, one or more of the planar elements may be elements that do not require a voltage to perform their function, or may be planar elements that require a voltage to be applied so that there is a substantially zero potential difference between the element and adjacent elements along the beam path. One example is a planar element that is a beam-limiting aperture array containing apertures sized to shape the charged particle beam. For example, the apertures may allow charged particle beams of a particular shape to pass while blocking charged particles outside of those beams. As a further alternative, the planar element configured to shape the charged particle beam may, in addition to the beam shaping function, also have a potential difference relative to the up beam and / or down beam planar element such that an electromagnetic field affects the charged particle beam.

[0066]

[0075] As shown in FIG. 6 , in one embodiment, the charged particle optical module 55 includes one or more spacers 70. The spacers 70 are configured to mechanically support the planar elements. As shown in FIG. 6 , in one embodiment, the spacers 70 are configured to mechanically separate the planar elements, such as the charged particle optical elements 60, from one another. In one embodiment, the spacers 70 are configured to electrically isolate the planar elements, such as the charged particle optical elements 60, from one another. However, it is not necessary for the spacers 70 to provide electrical isolation. For example, two adjacent charged particle optical elements 60 may be positioned to operate at the same voltage (i.e., there is no potential difference between them), in which case electrical isolation may not be necessary. In one embodiment, one or more pairs of adjacent planar elements abut one another (i.e., there is no intermediate spacer 70). The spacers 70 are optional.

[0067]

[0076] The charged particle beam is configured to pass through a beam area 62 of the charged particle optics module 55. As shown in Figure 6, the beam area 62 can be in a central portion of the charged particle optics module 55. The beam area 62 is generally centrally located when viewed in a direction parallel to at least one beam path. The beam area 62 is centrally located when viewed in a direction perpendicular to the plane of the planar element.

[0068]

[0077] In one embodiment, the charged particle optics module 55 is included within a charged particle optical device 40, such as the charged particle optical device 40 illustrated in or described with reference to Figures 2, 3, and / or 5. In one embodiment, the charged particle optics module 55 is field replaceable. The charged particle optics module 55 can be removed from and / or inserted into the charged particle optical device 40 without substantially disassembling other portions of the charged particle optical device 40. That is, the charged particle optics module 55 can be removable from and / or insertable into the charged particle optical device 40.

[0069]

[0078] In one embodiment, the charged particle optics module 55 includes an objective lens assembly including an objective lens array 241. The charged particle optics module 55 may further include a control lens array 250, a detector 240, and / or a deflector array. In an alternative embodiment, the charged particle optics module 55 may be a condenser lens assembly. The charged particle optics module 55 may include the condenser lens array 231. The charged particle optics module 55 may further include one or more of a deflector array and / or a beam-limiting aperture array.

[0070]

[0079] Figures 7 and 8 are schematic cross-sectional side views of an exemplary charged particle optical element 60. Figure 9 is a schematic plan view of an element 60 of the type illustrated in Figure 8. For clarity of illustration, the relative dimensions and / or aspect ratios in Figures 7-9 have been exaggerated. The element 60 may be configured to be suitable for incorporation into a charged particle optical module 55, such as the charged particle optical module 55 illustrated in Figure 6. The charged particle optical module 55 is configured to direct charged particles along at least one beam path toward a sample 208.

[0071]

[0080] In one embodiment, the charged particle optical element 60 includes a chip. The chip includes an integrated circuit 64. The integrated circuit 64 is formed on a semiconductor substrate 61. The substrate 61 includes or is composed of a semiconductor material such as silicon. The chip is formed by cutting the substrate 61 from a larger substrate, such as a silicon wafer, after the integrated circuit has been formed using a lithographic manufacturing process. The lithographic manufacturing process uses a lithographic imaging system to define the patterns to be formed in one or more layers of the integrated circuit. The substrate 61 may be substantially flat.

[0072]

[0081] In one embodiment, the integrated circuit 64 includes multiple layers. These layers can define one or more circuit layers. For example, the layers can define a complementary metal-oxide semiconductor (CMOS) circuit. As such, the integrated circuit 64 can include CMOS elements. In one embodiment, the CMOS circuit includes a metal layer or multiple metal layers. In one embodiment, the integrated circuit is configured to detect signal particles emitted from a sample. For example, the metal layer includes one or more electrodes that can provide a surface of the CMOS circuit on the substrate 61 that can face the sample 208 during operation. The metal layer can include a detector element configured to detect the signal particles. The detector element can also be referred to as a capture electrode. The capture electrode is an example of a sensor unit for detecting signal particles. Power and control signals for the CMOS circuit can be connected to the CMOS circuit by electrical connections running from areas outside the integrated circuit 64 to the integrated circuit 64. The CMOS circuit can include a logic layer. The logic layer can be on a different layer than the one or more electrodes. The logic layer may include amplifiers, such as transimpedance amplifiers (TIAs), filters, analog-to-digital converters (ADCs), and / or readout logic. In other embodiments, the integrated circuit may be formed using SiGe or GaAs technology. Thus, the integrated circuit may alternatively or additionally include SiGe or GaAs circuitry.

[0073]

[0082] In one embodiment, as illustrated in FIGS. 7 and 8 , the substrate 61 includes (e.g., defines) at least one aperture 63. The or each aperture 63 passes through the tip 61. The or each aperture 63 is configured to allow at least one beam path to pass therethrough. As such, each aperture 63 provides a route for at least one beam of charged particles to pass through the substrate 61. In the example of FIGS. 7 and 8 , the substrate 61 includes multiple apertures 63. Each aperture 63 may allow one charged particle beam or a group of charged particle beams to pass through the aperture 63. FIGS. 7 and 8 schematically show four apertures 63. The number of apertures 63 can be increased beyond four. As shown in FIGS. 7 and 8 , the aperture 63 is provided within the beam area 62 of the charged particle optical element 60. In an alternative embodiment, only one aperture 63 may be present. For example, the charged particle optical device 40 including the charged particle optical element 60 may be configured to direct a single charged particle beam towards the sample 208. Alternatively, the single aperture 63 may be for multiple sub-beams (or beam grids) of a multi-beam to pass therethrough. In this case, the charged particle optical element 60 with the single aperture 63 may be a macro element configured to act on all sub-beams of the multi-beam.

[0074]

[0083] 7 and 8, in one embodiment, the integrated circuit 64 is disposed adjacent to one or more of the apertures 63. In one embodiment, the integrated circuit 64 surrounds each of one or more of the apertures 63. In one embodiment, the integrated circuit 64 defines one or more electrodes in each aperture 63. In one embodiment, the integrated circuit 64 may include one or more electrodes that define one or more of the apertures 63. The electrodes may act on a charged particle beam passing through the aperture 63.

[0075]

[0084] In one embodiment, the integrated circuit includes and / or controls one or more deflectors. Each deflector may be configured to act on a charged particle beam (or group of charged particle beams) passing through a respective aperture 63. The deflectors may be configured to control the direction of the charged particle beams of the down-beam of the charged particle optical element 60. For example, the deflectors may be configured to control where the charged particles are incident on the down-beam charged particle optical element 60 or the sample 208. The deflectors may be configured to control whether one or more charged particle beams pass through an aperture of the down-beam planar element or whether one or more charged particle beams are blocked by the down-beam planar element.

[0076]

[0085] In one embodiment, the integrated circuit 64 includes and / or controls a multipole element. The multipole element may include multiple electrodes for each aperture 63. The multipole element may be configured to correct one or more parameters of the charged particle beam passing through the aperture 63. For example, in one embodiment, the multipole element may be an astigmatism corrector configured to adjust the shape of the charged particle beam passing through the aperture 63.

[0077]

[0086] In one embodiment, integrated circuit 64 includes and / or controls one or more aberration compensators or correctors. The aberration compensators may be formed into an aberration compensator array. In one embodiment, the aberration compensators may be configured to act on individual apertures 63. For example, the aberration compensators may be configured to control the field curvature and / or astigmatism of the charged particle beam.

[0078]

[0087] As mentioned in the introduction to this description, the charged particle optical element 60 may experience significant heating during use. Heating may occur particularly within and / or near the beam area 62. Sources of heating include the charged particle beam and active electronics, such as the integrated circuit 64. Embodiments of the present disclosure facilitate temperature control by configuring the substrate 61 to have a size (e.g., defined by the area of ​​its major surfaces) that exceeds the die size (e.g., processable area) of a lithographic imaging system used during the fabrication of the integrated circuit 64. As such, the substrate 61 is significantly larger laterally than substrates 61 containing integrated circuits 64 typically are. The substrate 61 may be described as extending laterally. By extending the substrate 61 laterally, additional space is provided in the peripheral region. The additional space can be utilized to improve temperature control of the substrate 61. The additional space can be used to provide more effective cooling configurations and / or position other heat sources further away from the beam area 62. Alternatively or additionally, the increased size may provide design freedom to improve mechanical support for the substrate 61. The improved mechanical support may be configured to contribute to temperature control of the substrate 61, for example, by providing a low thermal resistance path for heat to be efficiently conducted away from the substrate 61.

[0079]

[0088] In one embodiment, the size of substrate 61 is larger than the maximum die size of the lithographic imaging system. The maximum die size is the largest die area that the lithographic imaging system can process. The die size of the lithographic imaging system may also be referred to as the field size of the lithographic imaging system. In one embodiment, substrate 61 is at least 1.5 times, at least 2 times, at least 3 times, at least 4 times, or at least 5 times larger than the maximum die size of the lithographic imaging system. As a result of being larger than the die size, substrate 61 may include one or more scribe line structures 67, such as scribe line alignment marks. The one or more scribe line structures 67 may be formed in scribe lines that are located outside of integrated circuits 64 when viewed perpendicular to the major surface of substrate 61. In one embodiment, the one or more scribe line structures 67 are located between integrated circuits 64 and at least a portion of peripheral region 83 when viewed perpendicular to the major surface of substrate 61. After the integrated circuit 64 is formed by a lithographic manufacturing process and the chip is cut from a larger semiconductor substrate (e.g., a silicon wafer), such scribe line structures 67 are typically not present in the chip. Therefore, the presence of scribe line structures 67 indicates that the size of the substrate 61 is larger than the die size of the lithographic imaging system used during the fabrication of the integrated circuit 64.

[0080]

[0089] Thus, a method for manufacturing a charged particle optical element 60 may be provided. The method includes fabricating an integrated circuit 64 within a die of a semiconductor wafer. The die size of the die is defined by a lithographic imaging system (e.g., by a field size of the lithographic imaging system). Any of various known types of lithographic imaging systems may be used. The integrated circuit 64 may take any of the forms described above. The method further includes cutting a chip from the wafer. The chip includes the integrated circuit 64 within a substrate 61 derived from the wafer. The method includes forming at least one aperture 63 in the substrate 61. The at least one aperture 63 may be formed, for example, by etching. The at least one aperture 63 may take any of the forms described above. The at least one aperture 63 is configured to allow at least one beam path of the charged particle beam to pass through the substrate 61. The method is configured such that the size of the substrate 61 exceeds the die size of the lithographic imaging system.

[0081]

[0090] In one embodiment, the substrate 61 includes an inner region 82 and a peripheral region 83. The integrated circuits 64 are formed in the inner region 82. The peripheral region 83 is free of functional integrated circuits. Therefore, no portion of a functional integrated circuit is formed in the peripheral region 83. The peripheral region 83 is laterally outward of the inner region 82 when viewed perpendicularly to a major surface of the substrate 61 (e.g., the largest surface of the substrate 61, such as the top or bottom surface). The peripheral region 83 may extend to the outer boundary or outer edge of the substrate 61. The peripheral region 83 may surround the inner region 82 when viewed perpendicularly to the major surface of the substrate 61. The peripheral region 83 is integrally connected to the inner region 82. Therefore, the material of the substrate 61 extends continuously from the inner region 82 to the peripheral region 83 without any interface or structural mismatch separating the inner region 82 from the peripheral region 83. Inner region 82 and peripheral region 83 may, for example, originate from the same silicon wafer and represent a single, contiguous portion of the silicon wafer. In one embodiment, inner boundary 81 of peripheral region 83 defines an area equal in size (surface area) to the die size of a lithographic imaging system used during the fabrication of integrated circuits (when viewed perpendicular to the plane of substrate 61). Inner region 81 is illustrated by a dashed line in Figures 7-9.

[0082]

[0091] In one embodiment, elements 60 are configured to provide multiple conductive paths from peripheral region 83 to integrated circuit 64. The conductive paths may include one or more redistribution layers and one or more through-substrate vias (TSVs). The conductive paths allow elements positioned laterally outside of inner region 82 to be electrically connected to integrated circuit 64.

[0083]

[0092] In one embodiment, as illustrated in Figures 7-9, at least a subset of the conductive paths connect the integrated circuit 64 to the electronics unit 68. The electronics unit 68 may include a printed circuit board (PCB). In one embodiment, the electronics unit 68 is located on the opposite side of the substrate 61 from the integrated circuit 64. As shown in Figures 7 and 8, in some embodiments, the electronics unit 68 is provided on the up-beam side of the substrate 61 (above the substrate 61 in the orientation shown), and the integrated circuit 64 is provided on the down-beam side of the substrate 61 (below the substrate 61 in the orientation shown). In an alternative embodiment, the electronics unit 68 is provided on the down-beam side of the substrate 61.

[0084]

[0093] In one embodiment, the electronics unit 68 (e.g., a PCB) is fixed to the substrate 61. The electronics unit 68 may be coupled to the substrate 61. The electronics unit 68 may be fixed to a major surface of the substrate 61. The electronics unit 68 may overlap a portion of the major surface of the substrate 61. As shown in FIGS. 7 and 8 , in one embodiment, the electronics unit 68 extends laterally beyond the peripheral outer edge of the substrate 61. In one embodiment, the electronics unit 68 is configured to conduct power to the integrated circuit 64. For example, the electronics unit 68 may be electrically connected to a power supply configured to provide power to the integrated circuit 64. Additionally or alternatively, the electronics unit 68 may be configured to conduct signals to the integrated circuit 64. For example, in one embodiment, the electronics unit 68 is configured to provide control signals to the integrated circuit 64. The control signals may be, for example, control signals for controlling the gain and / or offset of an analog-to-digital converter (ADC) included within the integrated circuit 64. In one embodiment, the electronics unit 68 is configured to conduct signals from the integrated circuit 64. For example, in one embodiment, electronics unit 68 is configured to transmit a signal indicative of the flow of signal particles emitted from sample 208 and detected at substrate 61 .

[0085]

[0094] 7 and 8, the conductive path may include one or more TSVs 65. Each TSV passes through the substrate 61 from the up beam side of the substrate 61 to the down beam side of the substrate 61. The TSVs allow an electrical connection to be made between one side of the substrate 61 and the other side of the substrate 61.

[0086]

[0095] In one embodiment, the charged particle optical element 60 may be the most down-beam charged particle optical element of the charged particle optical device 40. There may be only a small clearance from the down-beam of the charged particle optical element 60 to the sample 208. Alternatively, there may be only a small clearance from the down-beam of the charged particle optical element 60 to the next component in the charged particle optical device 40. Thus, the up-beam side of the substrate 61 may be more accessible than the down-beam side of the substrate 61. The TSVs 65 provide electrical connection from the down-beam side of the substrate 61 to the more accessible up-beam side.

[0087]

[0096] In one embodiment, as shown in FIGS. 7 and 8 , the conductive paths may include one or more conductive tracks in layer 69 extending parallel to the plane of substrate 61. Layer 69 may include a coating on substrate 61 or a layer (e.g., an insulating layer) formed on substrate 61. The conductive paths in layer 69 may be defined by applying a patterning process to a metal layer to selectively remove portions of the metal layer. Multiple patterned metal sublayers separated from each other by insulating sublayers can be formed to provide more complex wiring configurations. Conductive tracks in different sublayers may be selectively connected to each other by appropriately positioned metal vias. Thus, layer 69 may include one or more sublayers containing conductive tracks configured to laterally distribute electrical signals or power. Layer 69 may also be referred to as a redistribution layer.

[0088]

[0097] 7 , layer 69 including conductive tracks is provided on the same side of substrate 61 as integrated circuit 64 (i.e., below substrate 61 in the orientation shown). Layer 69 extends from at least a region laterally overlapping integrated circuit 64 to a region laterally outside integrated circuit 64, and optionally laterally overlaps peripheral region 83 of substrate 61. In the example of FIG. 7 , layer 69 laterally overlaps the location of electronics unit 68 (e.g., PCB). One or more TSVs 65 provide electrical connection between layer 69 and electronics unit 68. In other embodiments, additional layer 69 may be provided on the side of substrate 61 where electronics unit 68 is located, to enable laterally directing electrical signals or power to appropriate electrical connection points on electronics unit 68.

[0089]

[0098] 8, a layer 69 containing conductive tracks is provided on the side of the substrate 61 opposite the integrated circuit 64 (i.e., above the substrate 61 in the orientation shown). The layer 69 extends through the substrate 61 to the integrated circuit 64 from a region that laterally overlaps at least one or more TSVs 65 configured to provide a direct or indirect electrical connection. In the example of FIG. 8, the TSVs 65 are shown providing a direct connection from the integrated circuit 64 to the layer 69 above the substrate 61. In other embodiments, the layer 69 may connect to one or more TSVs 65 and redistribute signals or power laterally away from the integrated circuit 64 before providing an electrical connection through the substrate 61 to the layer 69 above the substrate 61.

[0090]

[0099] In one embodiment, layer 69 is configured to carry power and / or communication signals (e.g., control signals) between electronics unit 68 and integrated circuit 64. Conductive tracks in layer 69 may be soldered or wire bonded to electronics unit 68, for example.

[0091]

[0100] FIG. 9 is a view from the beam-up side of the substrate 61. The beam area 62 is circular in the illustrated example, but may include any other shape, including, for example, a square, a rectangle, a hexagon, or any other regular or irregular polygon. In one embodiment, the charged particle optical element 60 includes one or more connector regions 75. A connector region 75 is an area in which multiple TSVs 65 are located. The TSVs may be positioned relatively close to each other within the connector region 75. In the example of FIG. 9, the element 60 includes three connector regions 75. In one embodiment, the number of connector regions 75 is one, two, four, or more than four. Each connector region 75 is connected to the electronics unit 68 by a conductive track in a respective layer 69.

[0092]

[0101] In one embodiment, a cooling element 86 may be provided to cool the substrate 61, as shown schematically in FIGS. 7-9 . In one embodiment, the cooling element 86 is mounted to a peripheral region 83 of the substrate 61. In the illustrated example, the cooling element 86 is mounted on the up-beam side of the substrate 61. The cooling element 86 is mounted in a manner that provides a high thermal conductivity connection to the substrate 61. Having a high thermal conductivity connection improves the efficiency with which heat can be transferred away from the substrate 61, thereby improving cooling performance. In one embodiment, the cooling element 86 is connected to the substrate 61 over a relatively large contact area. Providing a relatively large contact area promotes high thermal conduction. As explained above, configuring the size of the substrate 64 to exceed the die size of a lithographic imaging system used during the fabrication of the integrated circuit 64 facilitates providing a large contact area. For example, in one embodiment, the contact area is greater than 10%, optionally greater than 20%, optionally greater than 30%, optionally greater than 40%, and optionally greater than 50% of the die size. In one embodiment, the cooling element 86 includes a heat sink body (e.g., a block of material having a relatively high heat capacity and thermal conductivity). The heat sink body defines one or more internal channels 88 for directing the flow of a heat exchange fluid through the body. The increased space provided by configuring the size of the substrate 64 to exceed the die size facilitates configuring the cooling element 86 to have higher performance. This may be achieved, for example, by increasing the size of the cooling element 86 to improve its function as a heat sink. Alternatively or additionally, the increased space may allow for configuring the cooling channels to provide greater flow and / or forming more effective internal channels 88 within the heat sink body, for example, by increasing the surface contact area between the heat exchange fluid and the walls of the internal channels 88. In one embodiment, a liquid management system may be provided to drive the flow of the heat exchange fluid through the one or more internal channels 88.

[0093]

[0102] In one embodiment, as shown in FIG. 9 , mechanical support elements 84 may be provided to mechanically support the substrate 61. In the example of FIG. 9 , two mechanical support elements 85 are provided. Each mechanical support element 84 is configured to mechanically support the substrate 61 via a peripheral region 83 of the substrate 61. As such, each mechanical support element 84 may be mechanically connected, partially or entirely, to the substrate 61 at the peripheral region 83. Each mechanical support element 84 may be rigidly connected, directly or indirectly, to the substrate 61. Each mechanical support element 84 may rigidly connect the substrate 61 to another element in the module 55 or to one or more elements outside the module 55. The increased space provided by configuring the size of the substrate 61 to exceed the die size facilitates configuring each mechanical support element 84 to have high performance. Each mechanical support element 84 contacts the substrate 61 over a larger area, for example, thereby distributing forces applied to the substrate 61 and reducing potentially damaging pressures and / or torques. Additionally, the large contact area may allow the mechanical support element 84 to contribute to improved cooling of the substrate 61 by providing a high thermal conductivity path for heat to flow away from the substrate 61.

[0094]

[0103] Configurations of the present disclosure may be embodied in an evaluation apparatus for evaluating a sample 208 using charged particles. The evaluation apparatus may take any of the forms described above with reference to FIG. 1 . The evaluation apparatus may include a charged particle optical device 40. The charged particle optical device may take any of the forms described above with reference to FIGS. 2-5 . In one embodiment, the evaluation apparatus includes a sample support configured to support the sample 208. In one embodiment, the evaluation apparatus includes a charged particle optical module 55 configured to direct charged particles toward the sample 208 along at least one beam path. The charged particle module 55 may take any of the forms described above with reference to, for example, FIGS. 6-9 .

[0095]

[0104] In one embodiment, a chip assembly is provided. The chip assembly includes a chip including an integrated circuit 64 formed on a semiconductor substrate 61. The substrate 61 may include an aperture 63 for a beam path to pass therethrough. As such, the chip may take any of the forms described above with reference to FIGS. 7-9. Alternatively, the substrate 61 of the chip assembly may be provided without the aperture 63 for a beam path. As such, the chip of the chip assembly may be applied in contexts other than as part of a charged particle optical element. In this case, the chip may take any of the forms described above with reference to FIGS. 7-9, except for having the aperture 63. In one embodiment, the size of the substrate 61 exceeds the die size of a lithographic imaging system used during fabrication of the integrated circuit 64. As described above, configuring the substrate 61 to have a size that exceeds the die size of a lithographic imaging system used during fabrication of the integrated circuit 64 may facilitate temperature control of the chip by providing additional space in a peripheral region 83 of the substrate 61. In one embodiment, a cooling element is mounted in the peripheral region 83. The peripheral region 83 is laterally outward of the inner region 82 in which the integrated circuits 64 are formed. The cooling element 86 may include a heat sink and / or may define one or more internal channels 88 for directing the flow of a heat exchange fluid. The cooling element 86 and / or the internal channels 88 may take any of the forms described above with reference to Figures 7 and 8 or other forms. In one embodiment, a liquid management system is provided to drive the flow of the heat exchange fluid through the one or more internal channels 88. In one embodiment, the chip includes one or more scribe line structures located between the integrated circuits 64 and the peripheral region 83.

[0096]

[0105] In one embodiment, the charged particle optical elements 60 and / or the charged particle optical module 55 may be formed using microelectromechanical systems (MEMS) fabrication techniques and / or may be referred to as MEMS elements. One or more of such elements may be controlled to be set to a high potential difference relative to a reference potential (e.g., ground) during use. Such elements may be electrically connected to one or more voltage supplies for supplying voltages to the elements. In one embodiment, a controller is configured to control the voltages applied to the elements.

[0097]

[0106] Embodiments are provided according to the following numbered clauses: Clause 1: A charged particle optical element for a charged particle optics module configured to direct charged particles toward a sample along at least one beam path, the charged particle optical element comprising: a chip including an integrated circuit formed in a semiconductor substrate, the substrate defining at least one aperture for passage of at least one beam path therethrough; Charged particle optical elements, where the size of the substrate exceeds the die size of the lithographic imaging system used during the manufacture of integrated circuits. Clause 2. The device of clause 1, wherein the integrated circuit is configured to detect signal particles emitted from the sample. Clause 3. The device of clause 1 or 2, wherein the integrated circuit comprises a complementary metal oxide semiconductor (CMOS) circuit, a SiGe circuit, and / or a GaAs circuit. Clause 4. The substrate includes an inner region and a peripheral region; An integrated circuit is formed within the interior region; The peripheral area does not have any functional integrated circuits. 4. The device of any one of clauses 1-3, wherein the peripheral region is laterally outward of the inner region when viewed perpendicular to the main surface of the substrate. Clause 5. The element of clause 4, wherein the inner boundary of the peripheral region defines an area equal in size to a die size of a lithographic imaging system used during the manufacture of the integrated circuit, when viewed perpendicular to the major surface of the substrate. Clause 6. A device according to clause 4 or 5, configured to provide multiple conductive paths from a peripheral region to an integrated circuit. Clause 7. One or more of the conduction paths: one or more redistribution layers; and 7. The device of clause 6, comprising one or more through substrate vias (STVs). Clause 8. The device of any one of clauses 4 to 7, wherein the substrate includes one or more scribe line structures formed in scribe lines located outside the integrated circuit when viewed perpendicular to a major surface of the substrate. Clause 9. The device of clause 8, wherein the one or more scribe line structures are located between the integrated circuit and at least a portion of the peripheral region when viewed perpendicular to the major surface of the substrate. Clause 10. The element of clause 8 or 9, wherein the one or more scribe line structures include one or more alignment marks. Clause 11. A charged particle optical module comprising an element described in any one of clauses 1 to 10, wherein the substrate includes an inner region and a peripheral region, the integrated circuit is formed in the inner region, the peripheral region is free of functional integrated circuits, and the peripheral region is laterally outside the inner region when viewed perpendicular to the main surface of the substrate. Clause 12. The module of clause 11, further comprising a cooling element mounted in the peripheral region and configured to extract heat from the substrate. Clause 13. The module of clause 12, wherein the cooling element includes a heat sink body defining one or more internal channels for directing the flow of a heat exchange fluid through the body. Clause 14. The module of clause 12 or 13, wherein the contact area between the cooling element and the substrate is greater than 10% of the die size of a lithographic imaging system used during the manufacture of the integrated circuit. Clause 15. The module described in clauses 11 to 14, further comprising a mechanical support element configured to mechanically support the substrate, the mechanical support element configured to support the substrate via a peripheral region of the substrate. Clause 16. An evaluation device for evaluating a sample using charged particles, the device comprising: a sample support configured to support a sample; and 16. An evaluation apparatus comprising a module according to any one of clauses 11 to 15 configured to direct charged particles towards a sample along at least one beam path. Clause 17. A chip assembly comprising: A chip including an integrated circuit formed in a semiconductor substrate, the size of the substrate exceeding the die size of a lithographic imaging system used during the manufacture of the integrated circuit; and A chip assembly comprising a cooling element mounted in a peripheral region laterally outward of an inner region in which an integrated circuit is formed, the cooling element including a heat sink body, the heat sink body defining one or more inner channels for directing the flow of a heat exchange fluid through the body. Clause 18. The chip assembly of clause 17, wherein the chip includes one or more scribe line structures formed in scribe lines located outside the integrated circuits when viewed perpendicular to the major surface of the substrate. Clause 19. A method for manufacturing a charged particle optical element, comprising: Fabricating an integrated circuit within a die of a semiconductor wafer, the die size of the die being defined by a lithographic imaging system used during fabrication of the integrated circuit; Slicing chips from the wafer, the chips including integrated circuits formed on a substrate derived from the wafer; forming at least one aperture in the substrate for at least one beam path of the charged particle beam to pass through the substrate; The method wherein the size of the substrate exceeds the die size of the lithographic imaging system.

[0098]

[0107] While the present invention has been described in terms of various embodiments, other embodiments of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. For example, as noted above, in one embodiment, the substrate has portions of varying thickness, and the electrical connector extends through the thinner portions. However, the thickness of the substrate may alternatively be uniform. The electrical connections for the electronic components may be closer to the outer edge of the substrate than the electronic components, and the conductive layer may be electrically connected to the electrical connections. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

[0099]

[0108] The above description is intended to be illustrative rather than limiting, and as such, it will be apparent to one skilled in the art that modifications may be made as described herein without departing from the scope and provisions of the claims set out below.

[0100]

[0109] While the invention has been described in connection with various embodiments, other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

1. 1. A charged particle optical element for a charged particle optics module configured to direct charged particles toward a sample along at least one beam path, the charged particle optical element comprising: a chip including an integrated circuit formed in a semiconductor substrate, the substrate defining at least one aperture for passage of the at least one beam path therethrough; A charged particle optical element, wherein the size of the substrate exceeds a maximum die size of a lithographic imaging system used during the manufacture of the integrated circuit.

2. The device of claim 1 , wherein the integrated circuit is configured to detect signal particles emitted from the sample.

3. 3. The device of claim 1 or 2, wherein the integrated circuit comprises a complementary metal oxide semiconductor (CMOS) circuit, a SiGe circuit, and / or a GaAs circuit.

4. the substrate includes an inner region and a peripheral region; the integrated circuit is formed within the inner region; the peripheral region is free of any functional integrated circuit; The device of claim 1 , wherein the peripheral region is laterally outward of the inner region when viewed perpendicular to a major surface of the substrate.

5. 5. The device of claim 4, wherein an inner boundary of the peripheral region defines an area equal in size to the die size of the lithographic imaging system used during fabrication of the integrated circuit when viewed perpendicular to the major surface of the substrate.

6. The device of claim 4 configured to provide multiple conductive paths from the peripheral region to the integrated circuit.

7. One or more of the conductive paths are one or more redistribution layers; and The device of claim 6 , comprising one or more through-substrate vias (TSVs).

8. The device of claim 4 , wherein the substrate includes one or more scribe line structures formed in scribe lines located outside the integrated circuits when viewed perpendicular to the main surface of the substrate.

9. The device of claim 8 , wherein the one or more scribe line structures are located between the integrated circuit and at least a portion of the peripheral region when viewed perpendicular to the major surface of the substrate.

10. A charged particle optical module including an element described in any one of claims 1 to 9, wherein the substrate includes an inner region and a peripheral region, the integrated circuit is formed in the inner region, the peripheral region is free of functional integrated circuits, and the peripheral region is laterally outside the inner region when viewed perpendicular to the main surface of the substrate.

11. The module of claim 10 further comprising a cooling element mounted in the peripheral region and configured to extract heat from the substrate.

12. 12. The module of claim 11, wherein a contact area between the cooling element and the substrate is greater than 10% of the die size of a lithographic imaging system used during fabrication of the integrated circuit.

13. The module of claim 10 , further comprising a mechanical support element configured to mechanically support the substrate, the mechanical support element configured to support the substrate via the peripheral region of the substrate.

14. 1. An evaluation device for evaluating a sample using charged particles, said device comprising: a sample support configured to support a sample; and Characterization apparatus comprising a module according to any one of claims 10 to 13 configured to direct charged particles towards the sample along at least one beam path.

15. 1. A chip assembly comprising: A chip including an integrated circuit formed in a semiconductor substrate, the size of the substrate exceeding a maximum die size of a lithographic imaging system used during the manufacture of the integrated circuit; and A chip assembly comprising: a cooling element mounted in a peripheral region laterally outward of an inner region in which the integrated circuits are formed, the cooling element including a heat sink body, the heat sink body defining one or more inner channels for directing the flow of a heat exchange fluid through the body.

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