Method for etching features in a stack - Patent application

Abstract

A method is provided for etching a feature in a stack including a silicon oxide layer beneath a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0°C. An etching gas including a halogen-containing component and a phosphorus-containing component is provided. A plasma is generated from the etching gas. A bias is provided to accelerate ions from the plasma into the stack. The feature is etched in the stack selectively with respect to the mask.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Application No. 63 / 448,049, filed February 24, 2023, which is incorporated herein by reference for all purposes. [Background technology]

[0002] FIELD OF THE DISCLOSURE The present disclosure relates to methods of forming semiconductor devices on semiconductor wafers, and in particular to etching stacks in the formation of memory or other semiconductor devices.

[0003] In the formation of semiconductor devices, etching layers may be etched to form memory holes or memory lines. Some semiconductor devices may be formed by etching a double-layer stack of silicon oxide and silicon nitride (ONON). Such stacks may be used in memory applications such as forming dynamic random access memory (DRAM) and three-dimensional "NAND" gates (3D NAND).

[0004] The Background Art set forth herein is intended to present the contents of the present disclosure generally, and the inventions of the presently named inventors are not admitted expressly or impliedly as prior art to the present disclosure to the extent described in this Background Art section and in aspects of the description that are not prior art at the time of filing. Summary of the Invention

[0005] To achieve the foregoing in accordance with the objectives of the present disclosure, a method is provided for etching a feature in a stack comprising a silicon oxide layer beneath a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0° C. An etching gas is provided that includes a halogen-containing component and a phosphorus-containing component. A plasma is generated from the etching gas. A bias is applied to accelerate ions from the plasma into the stack. The feature is etched in the stack selectively with respect to the mask.

[0006] In another embodiment, an apparatus for processing a stack on a substrate including at least one silicon oxide layer is provided. The etching chamber has a substrate support for supporting the substrate therein. A temperature regulator controls the temperature of the substrate support. A gas source provides an etching gas to the etching chamber. The gas source includes a halogen-containing component source and a phosphorus-containing component source. An electrode provides power to the etching gas. A power source provides power to the electrode.

[0007] In another embodiment, a method is provided for etching a feature in a stack including a silicon oxide layer under a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0° C. An etching gas including a halogen-containing component and a phosphorus-containing component is provided. A multi-state power source having at least three states is provided. The multi-state power source generates a plasma from the etching gas and provides a bias to accelerate ions from the plasma into the stack. The feature is etched in the stack selectively with respect to the mask.

[0008] These and other features of the present disclosure are described in more detail in the following detailed description and in conjunction with the following figures. [Brief explanation of the drawings]

[0009] The present disclosure is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements and in which:

[0010] [Figure 1] 1 is a high-level flowchart that may be used in some embodiments.

[0011] [Figure 2A] 1A and 1B are schematic cross-sectional views of stacks processed according to embodiments. [Figure 2B] 1A and 1B are schematic cross-sectional views of stacks processed according to embodiments.

[0012] [Figure 3] 1 is a schematic diagram of an etching chamber that can be used in embodiments.

[0013] [Figure 4] FIG. 1 is a schematic diagram of a computer system that may be used to implement embodiments.

[0014] [Figure 5] 1 is a high-level flowchart that may be used in some embodiments.

[0015] [Figure 6A] A clock signal used in some embodiments.

[0016] [Figure 6B] 4 is a graph of a digital pulse signal used in some embodiments.

[0017] [Figure 6C] 4 is a graph illustrating an RF signal used in some embodiments.

[0018] [Figure 7] 1 is a schematic diagram of another etching chamber used in some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present disclosure will now be described in detail with reference to several preferred embodiments thereof, as illustrated in the accompanying drawings. In the following description, several specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0020] Controlling the profile during low-temperature etching of ultra-high aspect ratio contact dielectric etch, especially for 3D NAND pillar structures (large bowing CDs with small bottom CDs), presents significant challenges. This can be attributed to increased by-product accumulation close to the etch front, which slows down SiO2 reactive ion etching (RIE). The most common way to increase the etch rate (ER) for high aspect ratios is to increase ion energy and ion flux, which results in poorer bowing CD control (larger bowing). Another common way to increase the bottom CD and ER is to change the plasma chemistry. This approach can lead to other omissions, such as bowing widening, capping, or excessive contact twisting.

[0021] In some embodiments, the etch front surface is modified to improve etching of silicon oxide (SiO2 (also known as SiO)) and silicon nitride (Si3N4 (also known as SiN)). Some embodiments add a phosphorus (P)-containing precursor to the plasma. The P-containing precursor is believed to cause P-doping of the SiO2 and Si3N4 materials. The doped SiO2 material will have a reduced activation energy for RIE. Therefore, even low-energy ions from the plasma can contribute to the etching. Phosphine (PH3) and phosphorus trifluoride (PF3) are two primary compounds that can be used as P-containing precursors in some embodiments. Some embodiments may use other compounds that are difficult to commercialize because they are liquids or solids at room temperature (e.g., phosphorus trichloride (PCl3), phosphorus tribromide (PBr3), phosphorus oxyfluoride (POF3), or phosphorus triiodide (PI3)). Some embodiments may use phosphorus pentafluoride (PF5).

[0022] Reducing the etch activation energy of SiO2 and Si3N4 by phosphorus doping for RIE may help maintain high ONON pillar ER even at high aspect ratios. This may result in more efficient use of reactive ions supplied to the etch front. Some embodiments may make the silicon oxide etch more chemical in nature, closer to the silicon nitride etch, providing a more uniform ONON etch. In some embodiments, boron may be used to provide boron doping for RIE.

[0023] FIG. 1 is a high-level flowchart that may be used in some embodiments for ease of understanding. In some embodiments, a stack is placed on a substrate support in an etch chamber (step 104). In some embodiments, the stack is placed under a carbon-containing patterned mask. In some embodiments, the carbon-containing mask is an amorphous carbon mask. FIG. 2A is a schematic cross-sectional view of a stack 200 used in embodiments. In some embodiments, the stack includes a substrate 208 below a plurality of bilayers 212 that are placed under a carbon-containing patterned mask 216. One or more layers may be placed between the substrate 208 and the plurality of bilayers 212 or between the plurality of bilayers 212 and the carbon-containing patterned mask 216. However, some embodiments do not have a silicon-containing mask above the plurality of bilayers 212 or above the carbon-containing patterned mask 216. The carbon-containing patterned mask 216 may be amorphous carbon. In some embodiments, the pattern of the patterned mask provides mask features 220 for high aspect ratio contacts. In some embodiments, the mask features are formed before the substrate is placed in the etch chamber. In other embodiments, the mask features 220 are formed while the substrate is in the etch chamber. In some embodiments, the plurality of bilayers 212 is a bilayer of a silicon oxide layer 224 and a silicon nitride layer 228.

[0024] After stack 200 is installed in the etching chamber, the stack is cooled (step 108) by providing a chiller temperature below 0° C. The chiller cools a coolant that cools stack 200. In some embodiments, the chiller is cooled to a temperature below −40° C.

[0025] An etching gas including a halogen-containing component and a phosphorus-containing component is provided (step 112). In some embodiments, the etching gas is flowed into an etching chamber. In some embodiments, the etching gas includes a halogen-containing component, a phosphorus-containing component, a hydrogen-containing component, a hydrocarbon-containing component, and a fluorocarbon-containing component. In some embodiments, the halogen-containing component is a bromofluorocarbon C x Br y F z , chlorofluorocarbon C x Cl y F z , chlorinated hydrocarbons C x H y Cl z , bromohydrocarbon C x H y Br z , Fluorinated hydrocarbons C x H y F z , Fluorocarbon C x F yIn some embodiments, the halogen-containing component is a metal halide. In some embodiments, the etching gas further comprises at least one of methane (CH), hydrogen fluoride (HF), and hydrogen gas (H). In some embodiments, the etching gas further comprises an inert gas, such as argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), or nitrogen (N). In some embodiments, the inert gas may be an inert collision gas to provide ions for ion collision and facilitate etching. In some embodiments, the etching gas does not include oxygen and does not include octafluorocyclobutane (CF) or hexafluorocyclobutane (CF). In some embodiments, the etching gas further comprises at least one of methane (CH) and hydrogen gas (H). In some embodiments, the phosphorus-containing component is at least one of PF, PH, PF, PCl, PBr, POF, and PI. In some embodiments, an example etching gas is 5-120 sccm NF, 50-400 sccm H, 0-100 sccm CHF, 1-100 sccm PH, 0-100 sccm Cl, 0-100 sccm HBr, and 20-200 sccm CHF. In this example, a pressure of 5-60 mTorr is applied. In some embodiments, the halogen-containing component may include a fluorine-containing component, a chlorine-containing component, or a bromine-containing component.

[0026] The etching gas is converted into an etching plasma (step 116). This may be accomplished by providing excitation RF power at a frequency of 60 megahertz (MHz) at 200 to 15,000 watts. In some embodiments, the RF power is 0 to 25,000 watts at a frequency of 60 MHz. The stack 200 is exposed to the plasma (step 120). A bias of a magnitude of 200 to 15,000 volts is provided (step 124). In some embodiments, the bias power is at least 200 volts. In some embodiments, RF power, either continuous or pulsed RF power with a peak power of 3 kW to 150 kW, may be used for both the excitation RF power using a high frequency and the bias RF power using a low frequency. The bias accelerates ions into the stack 200, causing etching of high aspect ratio etch features in the stack 200 that are selective to (through) the carbon-containing patterned mask (step 128). In some embodiments, if the bias source is a pulsed bias source, the bias is provided by at least two states of pulsed bias. The bias source may include a primary pulsed bias source and a secondary pulsed bias source. In some embodiments, the bias is provided by an RF power source. The plasma is maintained for 180 to 3600 seconds. The etch can etch both the silicon oxide layer and the silicon nitride layer. After the etch is completed, the substrate is removed from the etch chamber (step 132).

[0027] 2B is a cross-sectional view of stack 200 after contact 232 has been etched. The contact is a high aspect ratio contact. Preferably, the contact has an aspect ratio of etch depth to feature CD width greater than 30:1. More preferably, the high aspect ratio contact has a height to CD width ratio greater than 40:1. Even more preferably, the high aspect ratio contact has a height to CD width ratio greater than 100:1.

[0028] The etching process can etch silicon oxide and silicon nitride layers selectively to amorphous carbon with a selectivity of greater than 3:1 while etching high aspect ratio features. The resulting features also have reduced bowing, striations, distortion, capping, and tapering. The present embodiments also enable the use of carbon-containing pattern masks, such as amorphous carbon, without the need for silicon-containing masks, such as polysilicon, resulting in reduced cost and defects.

[0029] Previous processes using etching, in which the stack is processed at temperatures above 0°C, relied on fluorocarbon chemistries to etch and provide sidewall protection. Such processes resulted in masks with silicon oxide and silicon nitride etch selectivities of less than 3:1. Sidewall protection is provided by polymer deposition and oxygen, controlled by the carbon concentration. High concentrations of carbon increase sidewall deposition, while high concentrations of oxygen consume the deposited polymer. High concentrations of oxygen also increase mask consumption. Some previous processes used silicon-containing masks.

[0030] Some embodiments increase etch rates and improve contact geometry / striation compared to conventional techniques. Without being bound by theory, the addition of a phosphorus-containing component to the etching gas is believed to deposit phosphorus dopants in silicon oxide-containing and silicon nitride-containing layers. The phosphorus dopants reduce the activation energy required to etch silicon oxide-containing layers, making silicon oxide more easily etched and lower-energy ions more efficient. Providing lower-energy ions for etching reduces bowing and other etching problems caused by higher-energy ions. The phosphorus dopant may also reduce the activation energy required to etch silicon nitride. However, the phosphorus dopant reduces the activation energy for silicon oxide more than it reduces the activation energy for silicon nitride. In prior art techniques, silicon oxide etches slower than silicon nitride, causing non-uniform etching of the ON-ON stack. Providing a phosphorus dopant allows for more uniform etching of the ON-ON layers.

[0031] In some embodiments, the electrostatic chuck is cooled to a temperature below 0° C. In some embodiments, the chuck is cooled to a temperature below −10° C. In some embodiments, the chuck is cooled to a temperature below −20° C. In some embodiments, the chuck is cooled to a temperature between −80° C. and 0° C. to provide enhanced processing. In some embodiments, the stack is cooled to a temperature between −60° C. and −20° C.

[0032] In some embodiments, the stack includes one or more layers of silicon oxide and / or silicon nitride. In some embodiments, the stack is a single layer of silicon oxide or silicon nitride. In some embodiments, the silicon oxide and / or silicon nitride layers are doped. In some embodiments, the silicon oxide and / or silicon nitride layers are undoped. In some embodiments, the stack includes alternating layers of silicon oxide and polysilicon (OPOP).

[0033] In some embodiments, ONON stacks may be etched to form contact holes, channel holes, or trenches in the fabrication of 3D NAND memory devices. Other embodiments may etch OPOP (alternating layers of SiO2 and polysilicon) stacks to form contact holes, channel holes, or trenches in the fabrication of 3D NAND memory devices. Other embodiments may be used to etch DRAM capacitors. The capacitor etch may provide high aspect ratio features in silicon oxide with a small CD of 1.5 microns. Some embodiments provide etch features with height-to-width ratios greater than 10:1. Some embodiments provide CDs of less than 50 nm with etch depths greater than 20 microns, providing features with a depth-to-width aspect ratio of at least 4000:1. In some embodiments, the etch depth is greater than 3 microns. Some embodiments enable etching of at least 192 or 256 bilayers of silicon oxide and silicon nitride in a single etch step using a single amorphous carbon mask less than 1 micron thick.

[0034] In some embodiments, the etching gas may include Cl2 and / or HBr as the halogen-containing component and PF5 as the phosphorus-containing component.

[0035] In some embodiments, providing the etching gas and the ion etching may be provided as successive steps of a cyclical process. Providing the etching gas simultaneously with the ion etching may provide a faster process than a successive cyclical process.

[0036] FIG. 3 is a schematic diagram of an etching reactor that can be used in embodiments. In one or more embodiments, the etching reactor 300 includes a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 308 within an etching chamber 349 surrounded by a chamber wall 352. Within the etching chamber 349, the stack 200 is disposed on top of the ESC 308, which functions as a substrate support. The ESC 308 may receive a bias from an ESC source 348. An etching gas source 310 is connected to the etching chamber 349 through the gas distribution plate 306. In some embodiments, the etching gas source 310 includes a phosphorus-containing component source 312, a halogen-containing component source 316, and other gas sources 318 (e.g., a hydrogen-containing component source and a fluorocarbon-containing component source). An ESC temperature controller 350 is connected to a chiller 314. The chiller 314 can cool the ESC 308 to a temperature below 0° C. In this embodiment, chiller 314 provides coolant to channels 313 in or near ESC 308. Radio frequency (RF) power supply 330 provides RF power to the lower electrode and / or upper electrode, which in this embodiment are ESC 308 and gas distribution plate 306. In an exemplary embodiment, 400 kilohertz (kHz), 60 megahertz (MHz), and, optionally, 2 MHz and 27 MHz power supplies constitute at least the primary and secondary power sources for RF power supply 330 and ESC source 348. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, the generators may be in separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. In other embodiments, other arrangements of RF sources and electrodes may be used. RF power may be continuous or pulsed. Some or all of the RF power may be supplied using a non-sinusoidal waveform. The controller 335 is controllably connected to the RF power supply 330 , the ESC source 348 , the exhaust pump 320 , and the etching gas source 310 .Examples of such etch chambers are the Exelan Flex® Dielectric Etch System or the Vantex® Dielectric Etch System manufactured by Lam Research Corporation of Fremont, Calif. The etch chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor, in which the electrode may be a coil.

[0037] FIG. 4 is a high-level block diagram illustrating a computer system 400 suitable for implementing the controller 335 used in embodiments. Computer systems may take many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to large supercomputers. The computer system 400 includes one or more processors 402 and may further include an electronic display device 404 (for displaying images, text, and other data), a main memory 406 (e.g., random access memory (RAM)), storage devices 408 (e.g., hard disk drives), removable storage devices 410 (e.g., optical disk drives), user interface devices 412 (e.g., keyboards, touch screens, keypads, mice, or other pointing devices), and a communications interface 414 (e.g., wireless network interfaces). The communications interface 414 allows software and data to be transferred between the computer system 400 and external devices via links. The system may also include a communications infrastructure 416 (e.g., a communications bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0038] Information transmitted through communications interface 414 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals that can be received by communications interface 414 over a communications link carrying the signals, which may be implemented using electrical wire or cable, fiber optics, telephone line, cellular phone link, radio frequency link, and / or other communications channels. It is contemplated that such communications interfaces enable one or more processors 402 to receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, method embodiments may be performed solely on a processor, or may be performed over a network, such as the Internet, in cooperation with a remote processor that shares some of the processing.

[0039] The term "non-transitory computer-readable medium" is used generally to refer to media (e.g., main memory, secondary memory, removable storage, storage devices (e.g., hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory)) and is not to be construed to include transitory objects such as carrier waves or carrier signals. Examples of computer-readable code include machine code (such as produced by a compiler) and files containing high-level code that are executed by a computer using an interpreter. The computer-readable medium may also be computer code embodied in a carrier wave and transmitted by a computer data signal representing a sequence of instructions executable by a processor.

[0040] In some embodiments, liquid nitrogen is used as the coolant that is flowed through the ESC 308 to provide cooling. In other embodiments, Vertel Sinera™ liquid, manufactured by DuPont Corporation of Wilmington, Delaware, may be used as the coolant.

[0041] In some embodiments, the RF power is provided using a multi-state pulse having at least three states. The multi-state pulse generates a plasma from the etching gas and provides a bias. In some embodiments, the multi-state pulse has at least a primary RF signal in a first frequency range and a secondary RF signal in a second frequency range, both of which are pulsed between at least a first state, a second state, and a third state. In some embodiments, one or more of the RF signals has a non-sinusoidal waveform.

[0042] In some embodiments, in a first state, the primary RF signal is at a first primary power level and the secondary RF signal is at a first secondary power level, in a second state, the primary RF signal is at a second primary power level and the secondary RF signal is at a second secondary power level, and in a third state, the primary RF signal is at a third primary power level and the secondary RF signal is at a third secondary power level. In some embodiments, in the first state, the primary RF signal is at a first primary power level and the secondary RF signal is at a first secondary power level, in the second state, the primary RF signal is at a second primary power level and the secondary RF signal is at a second secondary power level, and in the third state, no RF power is supplied. In some embodiments, the first primary power level is greater than the first secondary power level, the second primary power level is less than the second secondary power level, and the absolute value of the difference between the third primary power level and the third secondary power level is less than both the absolute value of the difference between the first primary power and the first secondary power and the absolute value of the difference between the second primary power and the second secondary power.

[0043] 5 is a flowchart of a process using multi-state pulses that can be used in some embodiments. A stack is placed in a chamber (step 504). In some embodiments, the stack can be stack 200 shown in FIG. 2A. After stack 200 is placed in the etch chamber, the stack is cooled to a temperature below 0° C. (step 508). In some embodiments, the stack is cooled to a temperature below −40° C.

[0044] An etching gas containing a halogen-containing component and a phosphorus-containing component is flowed into the etching chamber (step 112). In some embodiments, the etching gas contains a halogen-containing component, a phosphorus-containing component, a hydrogen-containing component, a hydrocarbon-containing component, and a fluorocarbon-containing component. In some embodiments, the halogen-containing component is a bromofluorocarbon C x Br y F z , chlorofluorocarbon C x Cl y F z , chlorinated hydrocarbons C x H y Cl z , bromohydrocarbon C x H y Br z , Fluorinated hydrocarbons C x H y F z , Fluorocarbon C x F yThe etching gas may include at least one of silicon tetrachloride (SiCl), bromine trichloride (BCl), nitrogen trifluoride (NF), C4F8, octafluoropropane (C3F8), hexafluoro-1,3-butadiene (C4F6), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), chlorine (Cl2), hydrogen bromide (HBr), trifluoroiodomethane (CF3I), fluoromethane (CH3F), difluoromethane (CH2F2), hydrochloric acid (HCl), and trifluoromethane (CHF3). In some embodiments, the halogen-containing component is a metal halide. In some embodiments, the etching gas further includes an inert gas, such as argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), or nitrogen (N2). In some embodiments, the inert gas may be an inert collision gas to provide ions for ion collision to facilitate etching. In some embodiments, the etching gas is oxygen-free and does not include octafluorocyclobutane (CF) or hexafluorocyclobutane (CF). In some embodiments, the etching gas is oxygen-free and carbon-free. In some embodiments, the etching gas further includes at least one of methane (CH), hydrogen fluoride (HF), and hydrogen gas (H). In some embodiments, the phosphorus-containing component is at least one of PF, PH, PF, PCl, PBr, POF, and PI. In some embodiments, example etching gases are 0-120 sccm NF, 0-400 sccm H, 1-100 sccm PF, 0-100 sccm Cl, 0-100 sccm HBr, 0-250 sccm HF, and 0-200 sccm CHF. In this example, a pressure of 5-60 mTorr is applied. In some embodiments, the halogen-containing component may include a fluorine-containing component, a chlorine-containing component, or a bromine-containing component. In some embodiments, boron trifluoride (BF3) or boron trichloride (BCl3) may be used.

[0045] A multi-state pulse is provided (step 516). In some embodiments, the multi-state pulse of any state may have a duty cycle between 1% and 99%. FIG. 6A is a graph 602 of a clock signal 604 used to provide the multi-state pulse in some embodiments. Graph 602 represents logic levels on the y-axis and time t on the x-axis. The y-axis of graph 602 includes logic level 0 and logic level 1. The x-axis of graph 602 includes multiple times t0, t1, t2, t3, t4, and t5.

[0046] The time interval between any two consecutive times on the x-axis of graph 602 is the same. For example, the time interval between times t0 and t1 is equal to the time interval between times t1 and t2, and the time interval between times t1 and t2 is equal to the time interval between times t2 and t3. The time interval between times t3 and t4 is equal to the time interval between times t2 and t3, and the time interval between times t4 and t5 is equal to the time interval between times t3 and t4. Time t1 is consecutive to time t0. Similarly, time t2 is consecutive to time t1, time t3 is consecutive to time t2, time t4 is consecutive to time t3, and time t5 is consecutive to time t4.

[0047] Clock signal 604 periodically transitions between logic level 0 and logic level 1. For example, during the first half of cycle 1 of clock signal 604, clock signal 604 is at logic level 1. At time t1, clock signal 604 transitions from logic level 1 to logic level 0. During the second half of cycle 1 of clock signal 604, clock signal 604 has logic level 0. At time t2, clock signal 604 transitions from logic level 0 to logic level 1. During the first half of cycle 2 of clock signal 604, clock signal 604 is at logic level 1. At time t3, clock signal 604 transitions from logic level 1 to logic level 0. During the second half of cycle 2 of clock signal 604, the clock signal is at logic level 0. At time t4, clock signal 604 transitions from logic level 0 to logic level 1.

[0048] Cycle 2 of clock signal 604 is consecutive to cycle 1 of clock signal 604. For example, there are no other clock cycles between cycle 1 and cycle 2 of clock signal 604. Cycle 1 occurs from time t0 to time t2, and cycle 2 occurs from time t2 to time t4.

[0049] 6B is a diagram of an embodiment of a graph 606 to illustrate an embodiment of a digital pulse signal 608 used in some embodiments. Graph 606 represents the logic levels of digital pulse signal 608 on the y-axis and time t on the x-axis. The y-axis of graph 606 includes logic levels 0, 1, and 2. The x-axis of graph 606 includes time t0, time t0a, time t0b, time t1, time t2, time t2a, time t2b, time t3, and time t4. Time t0a occurs between time t0 and time t0b, time t0b occurs between time t0a and time t1, time t2a occurs between time t2 and time t2b, and time t2b occurs between time t2a and time t3.

[0050] The digital pulse signal 608 periodically transitions between a first state (S1), a second state (S2), and a third state (S0). For example, the digital pulse signal 608 has state S1 defined by a logic level 0 from time t0 to time t0a. For example, in state S1 of the digital pulse signal 608, the digital pulse signal 608 is at logic level 0. The digital pulse signal 608 transitions from logic level 0 to logic level 1 at time t0a. State S2 of the digital pulse signal 608 is defined by a logic level 1. For example, in state S2 of the digital pulse signal 608, the digital pulse signal 608 is at logic level 1.

[0051] Digital pulse signal 608 has state S2 from time t0a to time t0b. At time t0b, digital pulse signal 608 transitions from state S2 to state S0, which is defined by logic level 2. For example, in state S0 of digital pulse signal 608, digital pulse signal 608 is at logic level 2. Digital pulse signal 608 has state S0 from time t0b to time t2. At time t2, digital pulse signal 608 transitions from state S0 to state S1.

[0052] The digital pulse signal 608 has state S1 from time t2 to time t2a. The digital pulse signal 608 transitions from state S1 to state S2 at time t2a. The digital pulse signal 608 has state S2 from time t2a to time t2b. At time t2b, the digital pulse signal 608 transitions from state S2 to state S0. The digital pulse signal 608 has state S0 from time t2b to time t4. At time t4, the digital pulse signal 608 transitions from state S0 to state S1.

[0053] Note that multiple instances of each of states S1, S2, and S0 of digital pulse signal 608 occur. For example, a first instance of state S1 of digital pulse signal 608 occurs between time t0 and time t0a, and a second instance of state S1 of digital pulse signal 608 occurs between time t2 and time t2a. As another example, a first instance of state S2 of digital pulse signal 608 occurs between time t0a and time t0b, and a second instance of state S2 of digital pulse signal 608 occurs between time t2a and time t2b. As yet another example, a first instance of state S0 of digital pulse signal 608 occurs between time t0b and time t2, and a second instance of state S0 of digital pulse signal 608 occurs between time t2a and time t4. As another example, a first instance of state S2 of digital pulse signal 608 is consecutive to a first instance of state S1 of digital pulse signal 608, and a first instance of state S0 of digital pulse signal 608 is consecutive to a first instance of state S2 of digital pulse signal 608. A second instance of state S1 of digital pulse signal 608 is consecutive to a first instance of state S0 of digital pulse signal 608. Also, a second instance of state S2 of digital pulse signal 608 is consecutive to a second instance of state S1 of digital pulse signal 608, and a second instance of state S0 of digital pulse signal 608 is consecutive to a second instance of state S2 of digital pulse signal 608.

[0054] 6C is an embodiment of a graph 610 of a primary RF signal 612 and a secondary RF signal 616 used in some embodiments. The primary RF signal 612 and the secondary RF signal 614 are synchronized to the digital pulse signal 608. For example, the primary RF signal 612 and the secondary RF signal 614 each begin a transition from state S1 to state S2 at time t0a when the digital pulse signal 608 transitions from state S1 to state S2. As another example, the primary RF signal 612 and the secondary RF signal 614 each begin a transition from state S2 to state S0 at time t0b when the digital pulse signal 608 transitions from state S2 to state S0. As yet another example, the primary RF signal 612 and the secondary RF signal 614 each begin a transition from state S0 to state S1 at time t2 when the digital pulse signal 608 transitions from state S0 to state S1.

[0055] Graph 610 represents the power levels of primary RF signal 612 and secondary RF signal 614. For example, the y-axis of graph 610 includes power levels P0, P1, P2, P3, and P4. Power level P1 is greater than power level P0. Power level P2 is greater than power level P1, and power level P3 is greater than power level P2. Power level P4 is greater than power level P3. Graph 610 also represents time t on the x-axis. For example, the x-axis of graph 610 includes times t0, t0a, t0b, t1, t2, t2a, t2b, t3, and t4.

[0056] As used herein, a power level is the envelope (e.g., peak-to-peak amplitude) of an RF signal. For example, the power level includes one or more peak-to-peak power values ​​within a predetermined range from the power level (e.g., peak-to-peak power values ​​greater than or less than the value of the power level). As yet another example, the power level is a statistical value (e.g., an average or median value) of all of the peak-to-peak power values. As yet another example, the power level is the highest value of all of the peak-to-peak power values. As yet another example, the power level is the lowest value of all of the peak-to-peak power values.

[0057] In an example used in some embodiments, the first state (S1) is from t0 to t0a, during which the primary RF signal 612 is provided at a first primary power level of P4 and the secondary RF signal 614 is provided at a first secondary power level of P1, where P4 is greater than P1 as shown. The second state (S2) is from t0a to t0b, during which the primary RF signal 612 is provided at a second primary power level of P2 and the secondary RF signal 614 is provided at a second secondary power level of P3, where P3 is greater than P2 as shown. The third state (S0) is from t0b to t2, during which the primary RF signal 612 is provided at a third primary power level of 0 and the secondary RF signal 614 is provided at a third secondary power level of 0 as shown. In this example, the power level of the primary RF signal 612 during S0 is equal to the power level of the secondary RF signal 614, which is 0. More generally, in some embodiments, the third primary power level is approximately equal to the third secondary power level. More generally, in some embodiments, the absolute value of the difference between the third primary power level and the third secondary power level is less than both the absolute value of the difference between the first primary power and the first secondary power and the absolute value of the difference between the second primary power and the second secondary power.

[0058] It should be noted that in some embodiments, the RF signals described herein do not transition from one state to the successive state instantaneously. For example, the transition of the primary RF signal 612 from state S1 to state S2 is not instantaneous. For example, the transition of the primary RF signal 612 from state S1 to state S2 occurs within a time window. As another example, the time window for a transition from a time described herein is the period occurring between states after that time. For example, the time window from time t0a is the period occurring between state S2 of the digital pulse signal 608 after time t0a. The period after time t0a occurs between state S2 of the digital pulse signal 608 from time t0a to a time between times t0a and t0b.

[0059] State S1 of primary RF signal 612 between times t0 and t0a is a first instance of state S1 of primary RF signal 612, and state S1 of primary RF signal 612 between times t2 and t2a is a second instance of state S1 of primary RF signal 612. Similarly, state S2 of primary RF signal 612 between times t0a and t0b is a first instance of state S2 of primary RF signal 612, and state S2 of primary RF signal 612 between times t2a and t2b is a second instance of state S2 of primary RF signal 612. Also, state S0 of primary RF signal 612 between times t0b and t2 is a first instance of state S0 of primary RF signal 612, and state S0 of primary RF signal 612 between times t2b and t4 is a second instance of state S0 of primary RF signal 612.

[0060] Similarly, state S1 of primary RF signal 612 between times t0 and t0a is a first instance of state S1 of primary RF signal 612, and state S1 of primary RF signal 612 between times t2 and t2a is a second instance of state S1 of primary RF signal 612. Similarly, state S2 of primary RF signal 612 between times t0a and t0b is a first instance of state S2 of primary RF signal 612, and state S2 of primary RF signal 612 between times t2a and t2b is a second instance of state S2 of primary RF signal 612. Also, state S0 of primary RF signal 612 between times t0b and t2 is a first instance of state S0 of primary RF signal 612, and state S0 of primary RF signal 612 between times t2b and t4 is a second instance of state S0 of primary RF signal 612.

[0061] In some embodiments, providing high power for the primary RF signal 612 during state S1 allows for increased bias, which provides higher aspect ratio etching. However, high bias power can result in adverse effects such as increased bowing, reduced selectivity, clogging or necking, and faceting. To reduce or eliminate some of the adverse effects of increased bias power, state S2 is provided, in which the bias power provided by the primary RF signal 612 is reduced and the plasma source power provided by the secondary RF signal 614 is increased. In some embodiments, the power level of the secondary RF signal 614 is increased to be greater than the power level of the primary RF signal 612. To eliminate some of the adverse effects not eliminated by state S2, a third state S0 is provided. Thus, providing an etch of a stack having a silicon oxide layer under a mask with an etch gas including a halogen-containing component and a phosphorus-containing component using a multi-state RF power having at least three states provides improved, more selective etching with reduced adverse effects. In some embodiments, the etch gas does not include a metal-containing component.

[0062] In some embodiments, in State S1, with a primary power level higher than the secondary power level, a high bias power is applied to provide a high-rate, high-aspect-ratio etch. In some embodiments, the high-bias etch can also cause sputtering, which removes portions of the mask and redeposits them on the sides of the feature, creating necking that can lead to clogging. In some embodiments, State S2, with a high secondary power level and a low primary power level, allows for increased plasma density at a low bias, allowing for removal of formed necking and clogging. In some embodiments, State S2, with a low primary power level, allows for a low bias, allowing for removal of formed necking and clogging. In some embodiments, four or more states are used, with two States S1 and S2 having substantially higher primary and secondary powers than State S3, including a zero-power State S0. In some embodiments, the power level of the primary RF signal 612 during State S0 is approximately equal to the power level of the secondary RF signal 614. In some embodiments, the power levels of the primary RF signal 612 and the secondary RF signal 614 during State S0 are each less than 300 Watts. In some embodiments, the power level of the primary RF signal 612 and the power level of the secondary RF signal 614 during state S0 are zero watts. In some embodiments, the low power levels of the primary RF signal 612 and the secondary RF signal 614 cause neutral deposition on the mask, allowing for increased etch selectivity by adding to the mask. In some embodiments, the duty cycle of the third state S0 is greater than the duty cycle of the first state S1 and the duty cycle of the second state S2 to provide a longer period for deposition on the mask, thereby increasing selectivity. In some embodiments, the duty cycle of the third state S0 is between 25% and 94%. In some embodiments, state S0 may precede state S1. In some embodiments, state S0 may be between state S1 and state S2. In some embodiments, state S2 may precede state S1.

[0063] In some embodiments, a fourth state (S3) is used in a multi-state pulse. State S3 may precede or follow state S1, state S2, or state S0. Some embodiments have more than four states. In some embodiments, one or more states have zero RF power.

[0064] In some embodiments, the first state (S1) has a high RF power, the second state (S2) has an intermediate RF power, and the third state (S0) has a low RF power lower than the intermediate RF power. In some embodiments, the high RF power in the first state (S1) has a first primary power and a first secondary power, the intermediate RF power in the second state (S2) has a second primary power and a second secondary power, and the low RF power in the third state (S0) has a third primary power and a third secondary power. In some embodiments, the first primary power is greater than the second primary power, the second primary power is greater than the third primary power, the first secondary power is greater than the second secondary power, and the second secondary power is greater than the third secondary power. In some embodiments, the low RF power is 0 watts, such that the third primary power and the third secondary power are 0 watts.

[0065] In some embodiments, the parameters of states S1, S2, and S0 may be varied during the etching process, where the etch feature is etched deeper such that the height-to-width aspect ratio increases. For example, in some embodiments, the bias during S1 may increase over time. In some embodiments, the duty cycle of state S0 may increase over time. In some embodiments, the duty cycle of S2 may increase over time.

[0066] FIG. 7 is a schematic diagram of an etching reactor that can be used in some embodiments. In some embodiments, the etching reactor 700 includes a gas distribution plate 706 that provides a gas inlet into an etching chamber 749 surrounded by chamber walls 752, and an electrostatic chuck (ESC) 708. Within the etching chamber 749, the stack 200 is placed on top of the ESC 708, which functions as a substrate support. An etching gas source 710 is connected to the etching chamber 749 through the gas distribution plate 706. In some embodiments, the etching gas source 710 includes a phosphorus-containing component source 712, a halogen-containing component source 716, and other gas sources (e.g., a hydrogen-containing component source and a fluorocarbon-containing component source) 718. The ESC temperature regulator 750 is connected to a chiller 714. The chiller 714 can cool the ESC 708 to a temperature below 0° C. In this embodiment, the chiller 714 provides coolant to channels 713 in or near the ESC 708. A primary radio frequency (RF) power supply 780 provides a primary RF signal to the lower electrode, which in this embodiment is the ESC 708. A secondary RF power supply 784 provides a secondary RF signal to the ESC 708. A gas distribution plate 706 forms the upper electrode, which is grounded. In some embodiments, a 400 kilohertz (kHz) power supply and / or a 2 MHz power supply may comprise the primary RF power supply 780. In some embodiments, a 60 MHz power supply and / or a 27 MHz power supply comprise the secondary RF power supply 784. In other embodiments, other arrangements of RF sources and electrodes may be used. A controller 735 is controllably connected to the primary RF power supply 780, which provides the primary signal, the secondary RF power supply 784, which provides the secondary signal, the ESC source 748, the exhaust pump 720, and the etching gas source 710. Examples of such etching chambers are the Exelan Flex® Dielectric Etch System and the Vantex® Dielectric Etch System manufactured by Lam Research Corporation of Fremont, California. The etching chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor, in which the electrode may be a coil.

[0067] In some embodiments, the controller 735 is configured to cool the substrate support to a temperature below 0° C., provide an etching gas including a halogen-containing component from a halogen-containing component source and a phosphorus-containing component from a phosphorus-containing component source, generate a plasma from the etching gas, and provide a bias to accelerate ions from the plasma into the stack.

[0068] While the present disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, substitutions, and various substitute equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Therefore, it is intended that the following appended claims be construed to include all such alterations, modifications, substitutions, and various substitute equivalents that fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be construed to mean a logic using a non-exclusive logical "OR" ("A OR B OR C"), and not to mean "only one of A and B and C." Each step in a process may be optional and not required. Different embodiments may omit one or more steps or provide steps in a different order. Also, various embodiments may provide different steps simultaneously rather than sequentially.

Claims

1. 1. A method for etching features in a stack comprising a silicon oxide layer under a mask, the method comprising: cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0°C; providing an etching gas comprising a halogen-containing component and a phosphorus-containing component; generating a plasma from the etching gas; providing a bias to accelerate ions from the plasma into the stack; selectively etching features in the stack with respect to the mask; A method comprising:

2. 10. The method of claim 1, The method, wherein the etching gas further comprises a hydrogen-containing component.

3. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask.

4. 4. The method of claim 3, The method wherein the carbon-containing mask is amorphous carbon.

5. 10. The method of claim 1, The etching gas does not contain oxygen and 4 F 8 and C 4 F 6 A method that does not include any of the above.

6. 10. The method of claim 1, The halogen-containing component may be a chlorinated hydrocarbon, a bromofluorocarbon, a chlorofluorocarbon, SiCl 4 , BCl 3 , N.F. 3 , C 4 F 8 , C 3 F 8 , C 4 F 6 , SF 6 , C.F. 4 , Cl 2 , HBr, CF 3 I, CH 3 F, CH 2 F 2 , CHF 3 and HCl.

7. 10. The method of claim 1, The etching gas may further include HF, H 2 , O 2 , C.H. 4 The method includes at least one of the following:

8. 10. The method of claim 1, The method, wherein cooling the substrate support for supporting the stack in an etching chamber to the temperature below 0°C further comprises cooling the substrate support to a temperature below -10°C.

9. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack includes multiple alternating layers of silicon oxide or silicon nitride.

10. 10. The method of claim 1 further comprising:

1. A method comprising: providing RF power having a peak power between 3 kW and 150 kW.

11. 10. The method of claim 1, The phosphorus-containing component is PF 5 , P.H. 3 , P.F. 3 , PCl 3 , PBr 3 , POF 3 , and P.I. 3 The method includes at least one of the following:

12. 10. The method of claim 1, The phosphorus-containing component is 3 and P.F. 3 A method comprising at least one of the following.

13. 10. The method of claim 1, The etching gas may further include He, Ne, Ar, Kr, Xe, and N 2 The method includes an inert gas comprising at least one of:

14. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack includes multiple alternating layers of silicon oxide and polysilicon.

15. 10. The method of claim 1, The method wherein the features have a height to width ratio greater than 10:

1.

16. 10. The method of claim 1, The phosphorus-containing component is PF 5 A method comprising:

17. 10. The method of claim 1, The phosphorus-containing component is PF 3 and P.F. 5 and further comprising providing continuous RF power.

18. 10. The method of claim 1, The method, wherein providing a bias provides a bias greater than 200 volts.

19. 10. The method of claim 1, The method wherein the bias is provided by a pulsed bias with at least two states.

20. 10. The method of claim 1, The method wherein the bias is provided by an RF power source.

21. 1. An apparatus for processing a stack on a substrate comprising at least one silicon oxide layer, comprising: an etching chamber; a substrate support for supporting a substrate within the etching chamber; a temperature regulator for controlling the temperature of the substrate support; a gas source for providing an etching gas, a source of halogen-containing components; a gas source comprising a source of a phosphorus-containing component; an electrode for providing power to the etching gas; a power source for providing power to the electrodes; An apparatus comprising:

22. 22. The apparatus of claim 21 further comprising: a controller controllably connected to the gas source, the power source, and the temperature regulator, the controller comprising: cooling the substrate support to a temperature below 0°C; providing the etching gas comprising a halogen-containing component from the halogen-containing component source and a phosphorus-containing component from the phosphorus-containing component source; generating a plasma from the etching gas; providing a bias to accelerate ions from the plasma into the stack The apparatus is configured to:

23. 23. The apparatus of claim 22, The apparatus wherein the gas source further comprises a source of a hydrogen-containing component.

24. 24. The apparatus of claim 23, The apparatus, wherein the controller is further configured to provide a hydrogen-containing component from the hydrogen-containing component source.

25. 23. The apparatus of claim 22, The power supply a primary power source providing a primary signal in a first frequency range; a secondary power source providing a secondary signal in a second frequency range; The controller further comprises: pulsing the primary signal between at least three states including a first state, a second state, and a third state; The apparatus is configured to pulse the secondary signal between the first state, the second state, and the third state.

26. 26. The apparatus of claim 25, During the first state, the primary signal has a first primary power level and the secondary signal has a first secondary power level; During the second state, the primary signal has a second primary power level and the secondary signal has a second secondary power level; During the third state, the primary signal has a third primary power level and the secondary signal has a third secondary power level; the first primary power level is greater than the second primary power level, the second primary power level is greater than the third primary power level, the first secondary power level is greater than the second secondary power level, and the second secondary power level is greater than the third secondary power level.

27. 26. The apparatus of claim 25, The apparatus, wherein the primary signal is a primary RF signal and the secondary signal is a secondary RF signal.

28. 26. The apparatus of claim 25, The apparatus, wherein the primary signal is a primary pulsed bias signal and the secondary signal is a secondary pulsed bias signal.

29. 22. The apparatus of claim 21, The apparatus, wherein the power source is an RF power source.

30. 22. The apparatus of claim 21, The apparatus, wherein the power source is a pulsed bias source.

31. 1. A method for etching features in a stack including a silicon oxide layer under a mask, comprising: cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0°C; providing an etching gas comprising a halogen-containing component and a phosphorus-containing component; providing a multi-state power source having at least three states, the multi-state power source providing a bias to generate a plasma from the etching gas and accelerate ions from the plasma into the stack; selectively etching features in the stack with respect to the mask; A method comprising:

32. 32. The method of claim 31 , providing the multi-state power supply comprises: generating a primary signal that pulses between at least three states including a first state, a second state, and a third state; generating a secondary signal that pulses between the first state, the second state, and the third state; A method comprising:

33. 33. The method of claim 32, During the first state, the primary signal has a first primary power level and the secondary signal has a first secondary power level; During the second state, the primary signal has a second primary power level and the secondary signal has a second secondary power level; During the third state, the primary signal has a third primary power level and the secondary signal has a third secondary power level; the first primary power level is greater than the second primary power level, the second primary power level is greater than the third primary power level, the first secondary power level is greater than the second secondary power level, and the second secondary power level is greater than the third secondary power level.

34. 34. The method of claim 33, The method, wherein the third primary power level and the third secondary power level are equal to 0 watts.

35. 34. The method of claim 33, A method wherein the duty cycle of the third state is greater than both the duty cycle of the first state and the duty cycle of the second state.

36. 33. The method of claim 32, The method, wherein the etching gas further comprises a hydrogen-containing component.

37. 33. The method of claim 32, The method, wherein the mask is a carbon-containing mask.

38. 33. The method of claim 32, The etching gas does not contain oxygen and 4 F 8 and C 4 F 6 A method that does not include any of the above.

39. 33. The method of claim 32, The etching gas may further include HF, H 2 , O 2 , and C.H. 4 The method includes at least one of the following:

40. 33. The method of claim 32, The method, wherein cooling the substrate support for supporting the stack in an etching chamber to a temperature below 0°C further comprises cooling the substrate support to a temperature below -10°C.

41. 33. The method of claim 32, The method, wherein the mask is a carbon-containing mask and the stack includes multiple alternating layers of silicon oxide or silicon nitride.

42. 33. The method of claim 32, The phosphorus-containing component is PF 5 , P.H. 3 , P.F. 3 , PCl 3 , PBr 3 , POF 3 , and P.I. 3 The method includes at least one of the following:

43. 33. The method of claim 32, The etching gas may further include He, Ne, Ar, Kr, Xe, and N 2 The method includes an inert gas comprising at least one of:

44. 33. The method of claim 32, The method, wherein the mask is a carbon-containing mask and the stack includes multiple alternating layers of silicon oxide and polysilicon.

45. 32. The method of claim 31 , The method, wherein the multi-state power provides RF power.

46. 32. The method of claim 31 , The method wherein the multi-state power provides bias power.

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