Treatment for improving the surface roughness of etched silicon and germanium containing materials

Abstract

An exemplary semiconductor processing method may include providing a process precursor to a remote plasma system of a semiconductor processing chamber. The method may include generating plasma effluents of the process precursor within the remote plasma system. The method may include flowing the plasma effluents of the process precursor into a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be disposed within the processing region. The alternating layers of material may include a silicon- and germanium-containing material. The method may include contacting the substrate with the plasma effluents of the process precursor. The contacting may remove residue from the surface of the silicon- and germanium-containing material.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 18 / 112,252, filed February 21, 2023, entitled "Treatments to Improve ETCHed Silicon-And-Germanium-Containing Material Surface Roughness," which is incorporated herein by reference in its entirety.

[0002] The present technology relates to semiconductor processes and devices, and more particularly to lateral etching of silicon and germanium containing materials in vertical structures. [Background technology]

[0003] Integrated circuits are made possible by processes that fabricate intricately patterned layers of material on a substrate surface. Fabricating patterned materials on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring a photoresist pattern to an underlying layer, thinning a layer, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches one material faster than another, for example, to facilitate the pattern transfer process. Such an etching process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etching processes that are selective to a variety of materials have been developed.

[0004] Etching processes are sometimes referred to as wet or dry based on the materials used in the process. Wet HF etching preferentially removes silicon oxide over other dielectrics and materials. However, wet processes can have difficulty penetrating some confined trenches and can sometimes deform the remaining material. Dry etches, generated within a local plasma formed within the substrate processing region, can penetrate more confined trenches and reduce deformation of delicate remaining structures. However, local plasmas can damage the substrate by creating electric arcs when they discharge.

[0005] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0006] An exemplary semiconductor processing method may include providing a process precursor to a remote plasma system of a semiconductor processing chamber. The method may include generating plasma effluents of the process precursor within the remote plasma system. The method may include flowing the plasma effluents of the process precursor into a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be disposed within the processing region. The alternating layers of material may include a silicon- and germanium-containing material. The method may include contacting the substrate with the plasma effluents of the process precursor. The contacting may remove residue from the surface of the silicon- and germanium-containing material.

[0007] In some embodiments, the process precursor may be or may include a hydrogen-containing precursor, a nitrogen-containing precursor, or an oxygen-containing precursor. While generating plasma effluents of the process precursor, plasma power in the remote plasma system may be maintained at about 5,000 W or less. The method may include providing an inert precursor to the remote plasma system containing the process precursor. The inert precursor may be or may include argon or helium. The alternating layers of material further include a silicon-containing material. The residue may be or may include a carbon-containing material. The temperature in the semiconductor processing chamber may be maintained at about 350° C. or less. The pressure in the semiconductor processing chamber may be maintained at about 5 Torr or less. The method may then include contacting the substrate with plasma effluents of the process precursor to etch the silicon- and germanium-containing material. The 3σ average surface roughness (R a ) can be about 5 nm or less.

[0008] Some embodiments of the present technology may include a semiconductor processing method. The method may include providing a process precursor to a remote plasma system of a semiconductor processing chamber. The method may include generating a plasma effluent of the process precursor in the remote plasma system. The method may include flowing the plasma effluent of the process precursor into a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be disposed in the processing region. The alternating layers of material include a material containing silicon and germanium. The material containing silicon and germanium has a first average surface roughness (R a ) The method may include contacting the substrate with plasma effluents of the treatment precursor. The contacting may remove residue from the surface of the silicon and germanium containing material. The method may include etching the silicon and germanium containing material. The silicon and germanium containing material may be characterized by an average surface roughness (R a ) is the first average surface roughness (R a ) can be improved by about 10% or more.

[0009] In some embodiments, the plasma power of the remote plasma system can be maintained between about 1,000 W and about 5,000 W. The temperature within the semiconductor processing chamber can be maintained at about 100° C. or higher. The pressure within the semiconductor processing chamber can be maintained at about 5 Torr or lower. The process precursor can include one or more of diatomic hydrogen (H), water vapor (H O), diatomic nitrogen (N), ammonia (NH), or molecular oxygen (O). The method can include providing an inert precursor to a remote plasma system containing the process precursor. The method can include removing native oxide from the silicon and germanium containing material prior to etching the silicon and germanium containing material.

[0010] Some embodiments of the present technology may include a semiconductor processing method. The method may include providing a process precursor to a remote plasma system of a semiconductor processing chamber. The method may include generating plasma effluents of the process precursor in the remote plasma system. The method may include flowing the plasma effluents of the process precursor into a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be placed in the processing region. The alternating layers of material may include a silicon- and germanium-containing material. The method may include contacting the substrate with the plasma effluents of the process precursor. The contacting may remove residue from a surface of the silicon- and germanium-containing material. The method may include stopping the flow of the process precursor. The method may include etching the silicon- and germanium-containing material.

[0011] In some embodiments, the method can include transferring the substrate to a second processing region of a second semiconductor processing chamber after stopping the flow of the processing precursor.The method can include removing native oxide from the silicon and germanium containing material before etching the silicon and germanium containing material.

[0012] Such a technique can provide many advantages over conventional systems and techniques. For example, the process can remove residue from silicon- and germanium-containing materials prior to the etching step. Additionally, removing residue from silicon- and germanium-containing materials can result in more uniform etching and an etched silicon- and germanium-containing material with a desirable surface roughness. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the description and accompanying drawings.

[0013] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a top view of one embodiment of an exemplary processing system in accordance with embodiments of the present technique; [Figure 2A] 1 is a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technique; [Figure 2B] 2B is a detailed view of a portion of the processing chamber shown in FIG. 2A in accordance with an embodiment of the present technique; [Figure 3] 1 is a bottom view of an exemplary showerhead in accordance with embodiments of the present technique; [Figure 4] FIG. 1 illustrates exemplary steps of a method according to an embodiment of the present technology. [Figure 5A] 1 is a cross-sectional view of a substrate being processed in accordance with an embodiment of the present technique; [Figure 5B] 1 is a cross-sectional view of a substrate being processed in accordance with an embodiment of the present technique; [Figure 5C] 1 is a cross-sectional view of a substrate being processed in accordance with an embodiment of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0015] Some figures are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically and explicitly stated to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include unnecessary or exaggerated material for illustrative purposes.

[0016] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numerals, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0017] The transition to gate-all-around (GAA) transistors involves many process step changes from traditional fin field-effect (FinFET) transistors. Furthermore, as structures continue to shrink, the thickness of material layers decreases and the aspect ratios of memory holes and other structures increase, sometimes dramatically.

[0018] During the GAA process, alternating layers of materials, such as alternating layers of silicon-containing material and silicon- and germanium-containing material, are deposited on a substrate. In forming a transistor, memory holes or trenches can be formed in the alternating layers of materials. During the GAA process, the silicon- and germanium-containing material can be removed from within the memory holes or trenches to form material that acts as a nanowire / nanosheet.

[0019] Because these memory holes or trenches have a high aspect ratio, forming the memory holes or trenches can leave residue on the sidewalls. In embodiments in which the precursor used to etch the memory holes or trenches includes a carbon-containing precursor, some carbon-containing material can deposit on the exposed surfaces of the alternating layers of material. Specifically, the carbon-containing material can form as residue on the exposed surface of the silicon- and germanium-containing material. This residue can interfere with subsequent removal of the silicon- and germanium-containing material. The residue can act as a mask that prevents the etch precursor from uniformly removing the silicon- and germanium-containing material. Therefore, with conventional techniques, the presence of residue on the exposed surface of the silicon- and germanium-containing material can make it difficult to uniformly remove the silicon- and germanium-containing material. Non-uniform removal can lead to an increase in the average surface roughness (Ra) of the etched silicon- and germanium-containing material. This increased average surface roughness (Ra) of the etched silicon and germanium containing material can have undesirable effects on the electrical and / or mechanical properties of the silicon and germanium containing material.

[0020] The present technology overcomes these problems by performing a treatment after forming memory holes or trenches in the alternating layers of material. The treatment may include forming a plasma effluent of a treatment precursor and contacting a substrate with the treatment precursor. The treatment precursor and its plasma effluent, when formed, can selectively remove residue from the silicon- and germanium-containing material being removed. By removing residue from the silicon- and germanium-containing material, a more uniform etch can be achieved to remove the silicon- and germanium-containing material. Thus, the etched silicon- and germanium-containing material may be characterized by a reduced average surface roughness (Ra) compared to prior art techniques.

[0021] While the remaining disclosure routinely identifies specific etching processes that utilize the techniques of the present disclosure, it will be readily understood that the present systems and methods are equally applicable to etching processes that may occur in the chambers described. Thus, the techniques should not be considered limited to use with only etching processes or chambers. Furthermore, while an exemplary chamber is described to provide a foundation for the techniques, it should be understood that the techniques may be applied to any semiconductor processing chamber that may enable the steps described.

[0022] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to an embodiment. In this illustration, a pair of front-opening unified pods (FOUPs) 102 provide substrates of various sizes, which are received by a robot arm 104 and placed in a low-pressure holding area 106, and then placed into one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robot arm 110 can be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform many substrate processing steps, including cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, degassing, orientation, and other substrate processes, as well as the dry etch processes described herein.

[0023] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit a dielectric material on a substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to etch a dielectric film on a substrate. Any one or more of the described processes may be performed in a separate chamber(s) from the fabrication system shown in different embodiments. It will be appreciated that system 100 also contemplates additional configurations of deposition, etching, annealing, and curing chambers for dielectric films.

[0024] 2A shows a cross-sectional view of an exemplary processing chamber system 200 with partitioned plasma generation regions within the processing chamber. For example, during etching of films such as titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, process gases can be flowed through a gas inlet assembly 205 into a first plasma region 215. A remote plasma system (RPS) 201 can optionally be included in the system to subsequently process the first gas traveling through the gas inlet assembly 205. The inlet assembly 205 can include two or more separate gas supply channels, and a second channel (not shown), if included, can bypass the RPS 201.

[0025] The cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, and substrate support 265 on which substrate 255 is disposed are shown and may each be included depending on the embodiment. The pedestal 265 may have heat exchange channels through which heat exchange fluid flows to control the temperature of the substrate and may operate to heat and / or cool the substrate or wafer during processing. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated using embedded resistive heating elements to achieve relatively high temperatures, such as from about 100° C. or less to about 1100° C. or more.

[0026] The face plate 217 can be pyramidal, conical, or another similar structure that is narrow at the top and widens toward the bottom. The face plate 217 can also be flat, as shown, and can include multiple through-channels used to distribute process gases. Depending on the use of RPS 201, plasma-generating gases and / or plasma-excited species can pass through multiple holes in the face plate 217, as shown in FIG. 2B, for more uniform delivery to the first plasma region 215.

[0027] An exemplary configuration can include a gas inlet assembly 205 opening into a gas feed region 258 separated from the first plasma region 215 by the faceplate 217 such that gases / species flow through holes in the faceplate 217 into the first plasma region 215. Structural and operational features can be selected to prevent significant backflow of plasma from the first plasma region 215 into the feed region 258, the gas inlet assembly 205, and the fluid delivery system 210. The faceplate 217 or conductive top of the chamber and the showerhead 225 are shown with an insulating ring 220 positioned between the features, which allows an AC potential to be applied to the faceplate 217 relative to the showerhead 225 and / or ion suppressor 223. The insulating ring 220 can be positioned between the faceplate 217 and the showerhead 225 and / or ion suppressor 223, thereby allowing a capacitively coupled plasma (CCP) to form in the first plasma region. Baffles (not shown) may additionally be positioned in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid into the region through the gas inlet assembly 205.

[0028] The ion suppressor 223 may include a plate or other geometric shape defining a plurality of apertures throughout its structure configured to suppress the migration of ionic charged species from the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 and into the activated gas supply region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may include a perforated plate having various aperture configurations. These uncharged species may include highly reactive species that are transported from the apertures with a less reactive carrier gas. As noted above, migration of ionic species through the apertures may be reduced and, in some cases, completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 advantageously provides greater control over the gas mixture contacting the underlying wafer substrate, thereby providing greater control over the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture can affect its etch selectivity, e.g., SiGe. x :SiO x Etch ratio, SiGe x :Si etch ratios, etc. can be varied significantly. In alternative embodiments where deposition is performed, the balance can also be shifted from conformal to flowable deposition of dielectric material.

[0029] The plurality of apertures in the ion suppressor 223 can be configured to control the passage of the activated gas, i.e., ionic, radical, and / or neutral species, through the ion suppressor 223. For example, the aspect ratio of the apertures, or the diameter to length of the apertures, and / or the geometry of the apertures can be controlled to reduce the flow of ionic charged species in the activated gas through the ion suppressor 223. The apertures in the ion suppressor 223 can include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and dimensioned to control the flow of ionic species through the showerhead 225. An adjustable electrical bias can also be applied to the ion suppressor 223 as an additional means of controlling the flow of ionic species through the suppressor.

[0030] The ion suppressor 223 can function to reduce or eliminate the amount of ionic charged species that travel from the plasma generation region to the substrate. Uncharged neutral and radical species can still pass through the openings in the ion suppressor and react with the substrate. It should be noted that complete elimination of ionic charged species in the reaction region surrounding the substrate may not be achieved in some embodiments. In certain cases, ionic species are intended to reach the substrate to perform etching and / or deposition processes. In these cases, the ion suppressor can help control the concentration of ionic species in the reaction region at a level that is process-supportive.

[0031] The showerhead 225 in combination with the ion suppressor 223 prevents the plasma present in the first plasma region 215 from directly exciting gases in the substrate processing region 233, while still allowing excited species to migrate from the chamber plasma region 215 into the substrate processing region 233. In this manner, the chamber can be configured to prevent the plasma from contacting the substrate 255 being etched. This can advantageously protect various intricate structures and films patterned on the substrate that could be damaged, misaligned, or otherwise distorted if the generated plasma were to directly contact them. Additionally, the rate at which the plasma etches the material can increase when it contacts or approaches the substrate level. Therefore, by keeping the plasma away from the substrate, exposed areas of the material can be further protected.

[0032] The processing system may further include a power supply 240 electrically coupled to the processing chamber to supply power to the faceplate 217, the ion suppressor 233, the showerhead 225, and / or the pedestal 265 to generate a plasma in the first plasma region 215 or processing region 233. The power supply may be configured to supply an adjustable amount of power to the chamber depending on the process being performed. Such a configuration allows for the use of an adjustable plasma in the process being performed. Unlike remote plasma units, which often provide an on or off function, an adjustable plasma may be configured to supply a specific amount of power to the plasma region 215. This allows for the development of specific plasma characteristics that can dissociate precursors in specific ways to enhance the etch profile produced by those precursors.

[0033] A plasma can be ignited either in the chamber plasma region 215 above the showerhead 225 or in the substrate processing region 233 below the showerhead 225. A plasma may exist in the chamber plasma region 215, for example, to generate radical precursors from an inflow of a fluorine-containing precursor or other precursor. An AC voltage, typically in the radio frequency (RF) range, can be applied between a conductive top portion of the processing chamber, such as the faceplate 217, and the showerhead 225 and / or ion suppressor 223 to ignite a plasma in the chamber plasma region 215 during deposition. The RF power source can generate a high RF frequency of 13.56 MHz, although other frequencies can also be generated alone or in combination with the 13.56 MHz frequency.

[0034] 2B shows a detailed view 253 of features that affect the distribution of process gas through face plate 217. As shown in FIGS. 2A and 2B, face plate 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas delivery region 258 to which process gas can be supplied from gas inlet 205. Gas fills gas delivery region 258 and can flow through apertures 259 in face plate 217 to first plasma region 215. Apertures 259 can be configured to direct flow substantially in one direction so that process gas can flow into processing region 233 but can partially or completely prevent backflow into gas delivery region 258 after traversing face plate 217.

[0035] A gas distribution assembly, such as the showerhead 225, for use in the processing chamber section 200 may be referred to as a dual channel showerhead (DCSH), and is further detailed in the embodiment depicted in Figure 3. A dual channel showerhead can accommodate an etching process that allows for separation of etchants outside the processing region 233, thereby providing limited interaction with chamber components and each other before being delivered into the processing region.

[0036] The showerhead 225 can include an upper plate 214 and a lower plate 216. The plates can be coupled together to define a volume 218 between the plates. The coupling of the plates can provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216. The formed channels can be configured to provide fluid access from the volume 218 through the lower plate 216 only via the second fluid channel 221, and the first fluid channel 219 can be fluidly isolated from the volume 218 between the plates and the second fluid channel 221. The volume 218 can be fluidly accessible through a side of the gas distribution assembly 225.

[0037] 3 is a bottom view of a showerhead 325 for use with a processing chamber, according to an embodiment. The showerhead 325 may correspond to the showerhead 225 shown in FIG. 2A. The through-holes 365, showing a view of the first fluid channel 219, may have multiple shapes and configurations to control and influence the flow of precursors through the showerhead 225. The small holes 375, showing a view of the second fluid channel 221, may provide a substantially even distribution over the surface of the showerhead, even among the through-holes 365, which may help to provide a more uniform mixing of the precursors as they exit the showerhead than other configurations.

[0038] The chambers described above can be used to perform exemplary methods, including etching methods. Turning to FIG. 4 , exemplary steps in a method 400 according to an embodiment of the present technology are shown. Prior to the first step of the method, a substrate can be processed with one or more methods and then placed in a processing region of a chamber where the method 400 can be performed. For example, alternating layers of materials can be formed on the substrate, followed by forming one or more memory holes or trenches in the alternating layers. The alternating layers can include any number of materials and can include alternating layers of silicon-containing materials and silicon- and germanium-containing materials. While the remaining disclosure discusses silicon-containing materials and silicon- and germanium-containing materials, any other known materials used for these two layers can be used in place of one or more layers. Some or all of these steps can be performed in a chamber or system tool, as described above, or can be performed in different chambers on the same system tool, which may include the chamber in which the steps of the method 400 are performed.

[0039] Method 400 may include providing a process precursor to a remote plasma region of a semiconductor processing chamber in step 405. In some embodiments, an inert precursor may be provided along with the process precursor. An exemplary chamber may be chamber 200, described above, and may include one or both of the RPS unit 201 or first plasma region 215. Either or both of these regions may be the remote plasma region used in step 405. In step 410, a plasma may be generated in the remote plasma region, thereby generating plasma effluents of the process precursor. In step 415, the plasma effluents may flow into a processing region of the chamber. In step 420, the plasma effluents may interact with and contact a substrate in the processing region, which may include one or more memory holes or trenches formed through alternating layers of silicon-containing material and silicon- and germanium-containing material. Contact of the precursor with the substrate may remove residue from the surface of the silicon- and germanium-containing material. For example, substrate development processes, such as etching processes to form one or more memory holes or trenches through alternating layers of material, may leave any number of residues on the material. For example, etching to form one or more memory holes or trenches may leave carbon-containing material on the silicon- and germanium-containing material. This carbon-containing material on the silicon- and germanium-containing material may affect subsequent processes, such as laterally etching the silicon- and germanium-containing material. Thus, the contacting in step 420 may remove at least a portion of the residue on the silicon- and germanium-containing material, which may result in better etching of the silicon- and germanium-containing material. In embodiments, after removing the residue in step 420, optional step 425 may include removing native oxide from the substrate, e.g., the silicon- and germanium-containing material. The method 400 may also include, in optional step 430, etching the silicon and germanium containing material to remove the silicon and germanium containing material from the one or more memory holes or trenches.

[0040] The method 400 may include removing residue from exposed surfaces of the silicon- and germanium-containing material in the one or more memory holes or trenches to more uniformly etch the silicon- and germanium-containing material in the alternating layers of material and reduce etch roughness. As discussed above, forming the one or more memory holes or trenches can leave residue on exposed surfaces due to precursors used to etch the alternating layers of material. In embodiments, the precursors used to etch the alternating layers of material can include a carbon-containing precursor that can leave carbon-containing material on the sidewalls of the one or more memory holes or trenches, such as on the exposed surfaces of the silicon- and germanium-containing material. In some semiconductor structures, such as GAA transistors, the silicon- and germanium-containing material may be removed relative to other materials in the alternating layers, such as silicon-containing materials. However, the presence of residue, such as carbon-containing material, can inhibit etching to remove the silicon- and germanium-containing material. The carbon-containing material may act as a discontinuous mask, causing the silicon- and germanium-containing material to be non-uniformly etched, resulting in a rough surface. Method 400 may include removing residue from the exposed surface of the silicon- and germanium-containing material, thereby improving the uniformity of subsequent etching to remove the silicon- and germanium-containing material. Thus, method 400 may improve the 3σ average surface roughness (R a ) can be maintained at or below about 5 nm.

[0041] The diameter or width of an exemplary memory hole or trench may be tens of nanometers or less, while the height of the memory hole or trench may be on the order of several micrometers or more. This may result in aspect ratios, or height to width ratios, of greater than 20:1, greater than 50:1, greater than 75:1, greater than 100:1, or even greater. The present technology may be applied to, for example, memory applications, GAA transistors, and logic applications. Thus, in embodiments, there may be more than 2, 3, 4, 5, 10, 15, 20, 25, 50, 75, or 100 alternating layers of material within each memory hole trench. In embodiments, prior to method 400, the 3σ average surface roughness (R a ) can be about 4.5 nm or greater, can be about 5 nm or greater, about 5.5 nm or greater, about 6 nm or greater, about 6.5 nm or greater, about 7 nm or greater, about 7.5 nm or greater, about 8 nm or greater, about 8.5 nm or greater, or greater.

[0042] Precursors used in this method can include a process precursor and, optionally, an inert precursor. Exemplary process precursors can be hydrogen-containing precursors, nitrogen-containing precursors, oxygen-containing precursors, or combinations thereof, which can be flowed into a remote plasma region that can be separate from the process region but fluidly connected to the process region. The hydrogen-containing precursor can be or include, for example, molecular hydrogen (H), ammonia (NH), or any other hydrogen-containing precursor used or useful in semiconductor processing. The nitrogen-containing precursor can be or include, for example, molecular nitrogen (N), ammonia (NH), or any other nitrogen-containing precursor used or useful in semiconductor processing. The oxygen-containing precursor can be or include, for example, molecular oxygen (O), or any other oxygen-containing precursor used or useful in semiconductor processing. In some embodiments, the process precursor can be provided along with an inert precursor. The inert precursor can be or include, for example, argon, helium, xenon, or other noble metal, inert, or useful precursor. An inert precursor can be used to dilute the process precursor, further reducing the etch rate and allowing for proper diffusion through the trench, or to aid in the distribution of the process precursor throughout the process area.

[0043] The flow rates of the treatment precursor and the inert precursor, if present, can be sufficient to provide adequate distribution to process the entire substrate. In embodiments, the flow rate of the treatment precursor to the remote plasma system can be about 1 sccm or greater, about 10 sccm or greater, about 50 sccm or greater, about 100 sccm or greater, about 250 sccm or greater, about 500 sccm or greater, about 1,000 sccm or greater, about 1,500 sccm or greater, about 2,000 sccm or greater, about 2,500 sccm or greater, about 3,000 sccm or greater, about 3,500 sccm or greater, about 4,000 sccm or greater, or more. Additionally, the flow rate of the inert precursor, which can dilute and / or distribute the treatment precursor or its plasma effluents, can be about 100 sccm or greater, about 250 sccm or greater, about 500 sccm or greater, about 750 sccm or greater, about 1,000 sccm or greater, about 2,500 sccm or greater, about 5,000 sccm or greater, about 7,500 sccm or greater, about 10,000 sccm or greater, or even greater.

[0044] Plasma effluent of the treatment precursor and inert precursor, if present, can be generated at a plasma power of about 5,000 W or less, and can be generated at about 4,750 W or less, about 4,500 W or less, about 4,250 W or less, about 4,000 W or less, about 3,750 W or less, about 3,500 W or less, about 3,250 W or less, about 3,000 W or less, about 2,750 W or less, about 2,500 W or less, about 2,250 W or less, about 2,000 W or less, about 1,750 W or less, about 1,500 W or less, about 1,250 W or less, about 1,000 W or less, about 750 W or less, about 500 W or less, about 250 W or less, or less. By generating the plasma effluent with a remote plasma system, a portion of the ions present in the generated plasma effluent can be filtered before entering the processing region. This filtration can limit impact and damage to the substrate and the materials deposited thereon.

[0045] The substrate can be contacted with the plasma effluent of the treatment precursor for a time sufficient to treat residues, such as carbon-containing materials, on the silicon- and germanium-containing material. In embodiments, this time can be about 3 seconds or more, about 5 seconds or more, about 10 seconds or more, about 20 seconds or more, about 30 seconds or more, about 40 seconds or more, about 50 seconds or more, about 1 minute or more, about 2 minutes or more, about 3 minutes or more, about 5 minutes or more, or longer. A time of about 3 seconds or more can remove about 85% or more of the residue from the silicon- and germanium-containing material, and about 90% or more, about 95% or more, about 97% or more, about 99% or more, about 99.9% or more, or even all of the residue from the silicon- and germanium-containing material.

[0046] As discussed above, method 400 may include, in optional step 425, removing native oxide from a material on the substrate, such as a silicon- and germanium-containing material. Optional step 425 may be performed in the same semiconductor processing chamber as steps 405-420, or the substrate may be transferred to a second processing region of a second semiconductor processing chamber to remove the native oxide. However, the second semiconductor processing chamber may be on the same processing system, such as processing system 100, as the semiconductor processing chamber used during steps 405-420. Additionally, method 400 may include, in optional step 430, etching the silicon- and germanium-containing material. Etching the silicon- and germanium-containing material may be performed as a step in the formation of a gate-area transistor. Optional step 430 may be performed in the same semiconductor processing chamber as steps 405-420 and / or optional step 425, or the substrate may be transferred to a third processing region of the second semiconductor processing chamber to remove the native oxide. However, the third semiconductor processing chamber may be on the same processing system, such as processing system 100, as the semiconductor processing chamber used during steps 405-420 and / or the semiconductor processing chamber used during optional step 425.

[0047] Removing residue from the exposed surface of the silicon- and germanium-containing material in one or more memory holes or trenches makes etching of the silicon- and germanium-containing material in alternating layers of material more uniform and reduces etch roughness. In embodiments, the average surface roughness (R a ) can improve by about 5% or more, can improve by about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, or more. For example, after subsequent etching of the silicon and germanium containing material, the 3σ average surface roughness (R a ) can be about 5 nm or less, and can be about 4.9 nm or less, about 4.8 nm or less, about 4.7 nm or less, about 4.6 nm or less, about 4.5 nm or less, about 4.3 nm or less, about 4.2 nm or less, about 4.1 nm or less, about 4 nm or less, about 3.9 nm or less, about 3.8 nm or less, about 3.7 nm or less, about 3.6 nm or less, about 3.5 nm or less, about 3.3 nm or less, about 3.2 nm or less, about 3.1 nm or less, about 3 nm or less, or even less. Conventional techniques for removing residue from exposed surfaces of silicon and germanium containing materials prior to etching can result in a 3σ average surface roughness (R a ) can be about 5 nm or greater, or even larger.

[0048] Process conditions can affect the steps performed in method 400, as well as other etching methods according to the present technique. While each step of method 400 can be performed at a constant temperature in embodiments, the temperature can be adjusted during different steps in some embodiments. For example, in embodiments, the substrate, pedestal, or chamber temperature while contacting the substrate with plasma effluents can be maintained between about 25° C. and about 350° C. The temperature may also be maintained at about 340° C. or less, about 330° C. or less, about 320° C. or less, about 310° C. or less, about 300° C. or less, about 280° C. or less, about 260° C. or less, about 240° C. or less, about 220° C. or less, about 200° C. or less, about 180° C. or less, about 160° C. or less, about 140° C. or less, about 120° C. or less, about 100° C. or less, or lower. In embodiments, the temperature may be maintained at about 100°C or higher, about 120°C or higher, about 140°C or higher, about 160°C or higher, about 180°C or higher, about 200°C or higher, about 220°C or higher, about 240°C or higher, about 260°C or higher, about 280°C or higher, about 300°C or higher, or higher. Temperature can affect the etching process itself; higher temperatures can increase the reactivity between the processing precursors and residues on the silicon- and germanium-containing materials. Similarly, lower temperatures can slow the removal of residues on the silicon- and germanium-containing materials due to poor reactivity. Thus, in some embodiments, maintaining a temperature of about 100°C or higher can result in more uniform residue removal from the silicon- and germanium-containing materials.

[0049] The pressure within the chamber can affect the process being performed, and in embodiments, the pressure within the semiconductor processing chamber can be maintained at less than about 5 Torr, about 4.5 Torr or less, about 4 Torr or less, about 3.5 Torr or less, about 3 Torr or less, about 2.5 Torr or less, about 2 Torr or less, about 1.5 Torr or less, about 1 Torr or less, about 0.5 Torr or less, about 0.3 Torr or less, about 0.2 Torr or less, about 0.1 Torr or less, about 0.85 Torr or less, or even lower. In embodiments, a pressure of about 3 Torr or less allows the precursor or its plasma effluent to easily flow into the trench or memory hole. Therefore, lower pressures can improve residue removal rates on silicon- and germanium-containing materials by reducing recombination of plasma radicals within the processing region.

[0050] 5A-5C, cross-sectional views of a structure 500 being processed in accordance with embodiments of the present technology are shown. As shown in FIG. 5A, a substrate 505 can have multiple stacked layers overlying it, which can be silicon-containing materials, silicon- and germanium-containing materials, or other substrate materials. The alternating layers of material can include materials suitable for GAA transistors, such as silicon-containing material 510 alternating with silicon- and germanium-containing material 520. Silicon- and germanium-containing material 520 can be or include material that is removed to create nanowires / nanosheets in a GAA transistor. While only seven layers of material are shown, the exemplary structure can include any number of layers discussed above. A memory hole or trench 530 can be defined through the stacked structure down to the level of the substrate 505. The memory hole or trench 530 may be defined by sidewalls 532, which may be composed of alternating layers of silicon-containing material 510 and silicon- and germanium-containing material 520. After forming the memory hole or trench 530, a residue 525 may be present on the silicon- and germanium-containing material 520. The residue 525 may be a carbon-containing material and may be a result of the precursors used to form the memory hole or trench 530.

[0051] Figure 5B may show a structure after some steps of a method according to the present technology have been performed, as discussed above with respect to Figure 4. As shown in Figure 5A, residue 525 present on silicon and germanium containing material 520 may be removed to expose the underlying silicon and germanium containing material 520. Although Figure 5B shows all of residue 525 removed, it is understood that not all of residue 525 is removed and some of residue 525 may still be present.

[0052] 5C shows the structure after further steps of a method according to the present technology have been performed, as discussed above with respect to FIG. 4. An etching step may be performed to remove the silicon- and germanium-containing material 520. The etching may remove portions of the silicon- and germanium-containing material 520 to form nanowires / nanosheets of the silicon- and germanium-containing material 520 between adjacent silicon-containing materials 510, which may be useful for gate-all-around applications. In embodiments, less than about 10 nm or less of the silicon- and germanium-containing material 520 may be removed. The substrate 505 may exhibit minimal etching at the bottom of the trench 530.

[0053] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0054] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. In addition, while a method or process may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in an order different from that described.

[0055] Where a range of values ​​is presented, unless the context clearly dictates otherwise, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value within that stated range is also encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded from the range, and each range where either, neither, or both limits are included in the smaller range is also encompassed within the scope, subject to any specifically excluded limits in the stated range. When one or both limits are included in a stated range, ranges excluding either or both of those included limits are also included.

[0056] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors; a reference to "the material" includes a reference to one or more such materials and equivalents thereof known to those skilled in the art, and so forth.

[0057] Additionally, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and the appended claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a process precursor to a remote plasma system of a semiconductor processing chamber; generating a plasma effluent of the treatment precursor within the remote plasma system; flowing plasma effluents of the process precursor into a processing region of the semiconductor processing chamber, wherein a substrate including alternating layers of material is disposed in the processing region, and the alternating layers of material include a silicon and germanium containing material; and contacting the substrate with the plasma effluents of the treatment precursor, wherein the contacting removes residue from the surface of the silicon and germanium containing material. A semiconductor processing method comprising:

2. The semiconductor processing method of claim 1 , wherein the process precursor comprises a hydrogen-containing precursor, a nitrogen-containing precursor, or an oxygen-containing precursor.

3. 10. The semiconductor processing method of claim 1, wherein plasma power within said remote plasma system is maintained at about 5,000 W or less while generating plasma effluent of said process precursor.

4. providing an inert precursor to the remote plasma system containing the treatment precursor; 10. The semiconductor processing method of claim 1, further comprising:

5. The semiconductor processing method of claim 4 , wherein the inert precursor comprises argon or helium.

6. The semiconductor processing method of claim 1 , wherein the alternating layers of material further comprise a silicon-containing material.

7. The semiconductor processing method of claim 1 , wherein the residue comprises a carbon-containing material.

8. 10. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained at about 350[deg.] C. or less.

9. 10. The semiconductor processing method of claim 1, wherein the pressure within the semiconductor processing chamber is maintained at about 5 Torr or less.

10. thereafter contacting the substrate with the plasma effluents of the treatment precursor to etch the silicon and germanium containing material.

10. The semiconductor processing method of claim 1, further comprising:

11. The 3σ average surface roughness (R ａ 11. The semiconductor processing method of claim 10, wherein the thickness of the first and second electrodes is about 5 nm or less.

12. 1. A semiconductor processing method comprising: providing a process precursor to a remote plasma system of a semiconductor processing chamber; generating a plasma effluent of the treatment precursor within the remote plasma system; flowing plasma effluents of the process precursor into a processing region of the semiconductor processing chamber, wherein a substrate comprising alternating layers of material is disposed in the processing region, the alternating layers of material comprising a material containing silicon and germanium, and the silicon and germanium containing material has a first average surface roughness (R ａ ) flowing the plasma effluent; contacting the substrate with the plasma effluents of the treatment precursor, wherein the contacting removes residue from a surface of the silicon and germanium containing material; and Etching the silicon and germanium containing material, wherein the average surface roughness (R ａ ) is the first average surface roughness (R ａ ) is improved by about 10% or more compared to A semiconductor processing method comprising:

13. 13. The semiconductor processing method of claim 12, wherein the plasma power of the remote plasma system is maintained between about 1,000 W and about 5,000 W.

14. the temperature within the semiconductor processing chamber is maintained at or above about 100°C; and the pressure within the semiconductor processing chamber is maintained at about 5 Torr or less; 13. The semiconductor processing method of claim 12.

15. The treatment precursor is diatomic hydrogen (H ２ ), water vapor (H ２ O), diatomic nitrogen (N ２ ), ammonia (NH ３ ), or molecular oxygen (O ２ 13. The semiconductor processing method of claim 12, comprising one or more of:

16. providing an inert precursor to the remote plasma system containing the treatment precursor; 13. The semiconductor processing method of claim 12, further comprising:

17. removing native oxide from the silicon and germanium containing material prior to etching the silicon and germanium containing material; 13. The semiconductor processing method of claim 12, further comprising:

18. 1. A semiconductor processing method comprising: providing a process precursor to a remote plasma system of a semiconductor processing chamber; generating a plasma effluent of the treatment precursor within the remote plasma system; flowing plasma effluents of the process precursor into a processing region of the semiconductor processing chamber, wherein a substrate comprising alternating layers of material is disposed in the processing region, and the alternating layers of material comprise a silicon and germanium containing material; contacting the substrate with the plasma effluents of the treatment precursor, wherein the contacting removes residue from a surface of the silicon and germanium containing material; stopping the flow of the treatment precursor; and Etching the silicon and germanium containing material. A semiconductor processing method comprising:

19. transferring the substrate to a second processing region of a second semiconductor processing chamber after stopping the flow of the processing precursor.

20. The semiconductor processing method of claim 18, further comprising:

20. removing native oxide from the silicon and germanium containing material prior to etching the silicon and germanium containing material; 20. The semiconductor processing method of claim 18, further comprising:

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