Compressing Translation Lookaside Buffer (TLB) Tags Using TLB Metadata Buffers in Processor-Based Devices

Abstract

Disclosed herein is a method for compressing TLB tags using a translation lookaside buffer (TLB) metadata buffer in a processor-based device. In some aspects, the processor-based device provides a memory management unit (MMU) including a TLB and a TLB metadata buffer including a plurality of TLB metadata buffer entries that store corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for use in accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request including a virtual address (VA), the MMU creates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of the TLB tag of the TLB entry in place of the TLB metadata of the TLB metadata buffer entry.

Description

[Technical Field]

[0001] (Priority application)

[0001] This application claims priority to U.S. patent application Ser. No. 18 / 168,871, entitled "COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB METADATA BUFFER IN PROCESSOR-BASED DEVICES," filed February 14, 2023, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] I. Field of the Disclosure The techniques of this disclosure generally relate to translation lookaside buffers (TLBs) in processor-based devices.

[0003]

[0003] II. Background technology Microprocessors, also referred to herein as "processors," perform computational tasks for a wide variety of applications. Traditional processors utilize virtual memory, which refers to a memory management mechanism that maps memory addresses referenced by executing processes (i.e., virtual addresses or VAs) to physical addresses (PAs) in system memory. By using virtual memory, processor-based systems can provide access to a virtual memory space that is larger than the actual physical memory space and enhance inter-process security through memory isolation. The mapping of VAs to their corresponding PAs is achieved using a data structure known as a page table. To further improve performance, page table entries retrieved from the page table during VA-to-PA translations are cached in a data structure called a translation lookaside buffer or TLB.

[0004] While the use of a TLB can be effective in reducing memory access latency within a processor, the TLB can require a significant portion of the processor's physical area. This problem may be encountered more frequently as instruction set architectures (ISAs) increase the size of data such as VAs, application space identifiers (ASIDs), and virtual machine identifiers (VMIDs), which may traditionally be stored as part of the tag of each TLB entry. Therefore, it may be desirable to reduce the area occupied by a TLB while minimizing TLB invalidations without adversely affecting TLB lookup latency. Summary of the Invention

[0005]

[0005] Aspects disclosed in the detailed description include compressing TLB tags using a translation lookaside buffer (TLB) metadata buffer in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some example aspects disclosed herein, a processor of a processor-based device provides a memory management unit (MMU) including a TLB and a TLB metadata buffer. The TLB metadata buffer includes multiple TLB metadata buffer entries, each of which stores corresponding TLB metadata. The TLB metadata may include any data that is traditionally stored as part of a TLB entry's tag and that may be replicated across multiple TLB entries during execution of a software process. Thus, by way of non-limiting example, the TLB metadata in some aspects may include an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context, while some aspects may provide that the TLB metadata includes multiple high-order bits of a virtual address (VA) of a memory region being used by a processor pipeline of the processor.

[0006] In exemplary operation, an MMU of a processor-based device selects a TLB metadata buffer entry for use in accessing the TLB of the processor-based device, for example, by selecting a TLB metadata buffer entry that stores, as TLB metadata, the ASID and VMID of a new processor context, or by selecting a TLB metadata buffer entry that stores, as TLB metadata, the upper bits of the VA of a memory region being used by the processor pipeline in which the memory access request is received. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request that includes the VA, the MMU creates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of the TLB entry's tag in place of the TLB metadata of the TLB metadata buffer entry. Some aspects may further provide that when the MMU receives another memory request that includes the VA, the MMU accesses the TLB entry based on the active TLB metadata pointer (e.g., by matching the TLB tag of the TLB entry with the active TLB metadata pointer). In this manner, the embodiments disclosed herein allow for a smaller tag size for each TLB entry without impacting TLB latency, with the added benefit of simplified TLB content addressable memory (CAM) logic.

[0007] In aspects where the TLB metadata stored in a TLB metadata buffer entry includes the ASID and VMID of a processor context, the MMU is configured to detect a processor context switch to a new context associated with the ASID and VMID. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata including the ASID and VMID of the new context, the MMU may allocate a TLB metadata buffer entry for such. The MMU then selects a TLB metadata buffer entry that stores corresponding TLB metadata including the ASID and VMID of the new context for use in accessing the TLB, and stores a pointer to the TLB metadata buffer entry in an active pointer table entry of an active pointer table. Some such aspects provide that the TLB metadata buffer entry further includes a translation regime indicator, and the MMU stores a pointer to the TLB metadata buffer entry in an active pointer table entry that corresponds to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry. Some aspects further provide that the TLB metadata buffer entry further includes a global indicator that, when set, indicates that any associated TLB entry can be used across multiple applications (i.e., only the VMID of the TLB entry needs to match). In these aspects, the MMU stores a pointer to the TLB metadata buffer entry as a global active TLB metadata pointer in an active pointer table entry.

[0008] In an aspect in which the TLB metadata stored in a TLB metadata buffer entry includes multiple most significant bits of a VA of a memory region being used by a processor pipeline of a processor, an MMU is configured to receive a memory access request, the memory access request including the VA and associated with one of multiple processor pipelines of a processor-based device. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata including the multiple most significant bits of the VA, the MMU may allocate a TLB metadata buffer entry for such. The MMU selects a TLB metadata buffer entry that stores corresponding TLB metadata including the multiple most significant bits of the VA for use in accessing the TLB, and stores a pointer to the TLB metadata buffer entry in one of the active pointer table entries of an active pointer table that corresponds to the processor pipeline.

[0009]

[0009] In another aspect, a processor-based device is disclosed. The processor-based device includes a TLB including a plurality of TLB entries, and a TLB metadata buffer including a plurality of TLB metadata buffer entries, each configured to store corresponding TLB metadata. The processor-based device further includes an MMU configured to select a TLB metadata buffer entry from the plurality of TLB metadata buffer entries for use in accessing the TLB. The MMU is further configured to store a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The MMU is also configured to receive a first memory access request including a first VA. In response to receiving the first memory access request, the MMU is additionally configured to create a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0010] In another aspect, a processor-based device is disclosed. The processor-based device includes means for selecting one TLB metadata buffer entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for use in accessing a TLB of the processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata. The processor-based device further includes means for storing a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The processor-based device also includes means for receiving a first memory access request including a first VA. The processor-based device additionally includes means for, in response to receiving the first memory access request, creating a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0011] In another aspect, a method for compressing TLB tags using a TLB metadata buffer in a processor-based device is disclosed. The method includes selecting, by an MMU of the processor-based device, one TLB metadata buffer entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for use in accessing a TLB of the processor-based device, the plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata. The method further includes storing, by the MMU, a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The method also includes receiving, by the MMU, a first memory access request including a first VA. In response to receiving the first memory access request, the method additionally includes generating, by the MMU, a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry.

[0012] In another aspect, a non-transitory computer-readable medium is disclosed. The non-transitory storage medium stores computer-executable instructions that, when executed, cause a processor of a processor-based device to select one TLB metadata buffer entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for use in accessing a TLB of the processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata. The computer-executable instructions further cause the processor to store a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. The computer-executable instructions also cause the processor to receive a first memory access request including a first VA. The computer-executable instructions additionally cause the processor to generate a TLB entry in the TLB for the first VA in response to receiving the first memory access request, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry. [Brief explanation of the drawings]

[0013] [Figure 1]

[0013] A block diagram of an exemplary processor-based device including a memory management unit (MMU) and a translation lookaside buffer (TLB) configured to compress TLB tags using a TLB metadata buffer in accordance with some aspects. [Figure 2]

[0014] 2 is a block diagram of an exemplary embodiment of the MMU of FIG. 1 in which a TLB metadata buffer stores TLB metadata including application space identifiers (ASIDs) and virtual machine identifiers (VMIDs) for multiple translation regimes in response to a processor context switch, according to some embodiments. [Figure 3]

[0015] 2 is a block diagram of an example embodiment of the MMU of FIG. 1 in which a TLB metadata buffer stores TLB metadata including high-order bits of virtual addresses (VAs) for multiple processor pipelines, according to some embodiments. [Figure 4]

[0016] 1 provides a flowchart illustrating an exemplary operation of the MMU and TLB of FIGS. 1-3 to compress TLB tags using a TLB metadata buffer, according to some aspects. [Figure 5A]

[0017] A flowchart illustrating an example operation of the MMU and TLB of FIGS. 1 and 2 to store TLB metadata including ASIDs and VMIDs for multiple translation regimes in response to a processor context switch, according to some aspects, is provided. [Figure 5B] A flowchart illustrating an example operation of the MMU and TLB of FIGS. 1 and 2 to store TLB metadata including ASIDs and VMIDs for multiple translation regimes in response to a processor context switch, according to some aspects, is provided. [Figure 6]

[0018] 1 and 3 to store TLB metadata including the most significant bits of the VA for multiple processor pipelines, according to some aspects. [Figure 7]

[0019] FIG. 3 is a block diagram of an exemplary processor-based device that can include the MMU and TLB of FIGS. 1 and 2. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0020] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0015]

[0021] Aspects disclosed in the detailed description include compressing TLB tags using a translation lookaside buffer (TLB) metadata buffer in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some example aspects disclosed herein, a processor of a processor-based device provides a memory management unit (MMU) including a TLB and a TLB metadata buffer. The TLB metadata buffer includes multiple TLB metadata buffer entries, each of which stores corresponding TLB metadata. The TLB metadata may include any data that is traditionally stored as part of a TLB entry's tag and that may be replicated across multiple TLB entries during execution of a software process. Thus, by way of non-limiting example, the TLB metadata in some aspects may include an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context, while some aspects may provide that the TLB metadata includes multiple high-order bits of a virtual address (VA) of a memory region being used by a processor pipeline of the processor.

[0016]

[0022] In exemplary operation, an MMU of a processor-based device selects a TLB metadata buffer entry for use in accessing the processor-based device's TLB, for example, by selecting a TLB metadata buffer entry that stores, as TLB metadata, the ASID and VMID of a new processor context, or by selecting a TLB metadata buffer entry that stores, as TLB metadata, the upper bits of the VA of a memory region being used by the processor pipeline in which the memory access request is received. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request that includes the VA, the MMU creates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of the TLB entry's tag in place of the TLB metadata of the TLB metadata buffer entry. Some aspects may further provide that when the MMU receives another memory request that includes the VA, the MMU accesses the TLB entry based on the active TLB metadata pointer (e.g., by matching the TLB entry's TLB tag with the active TLB metadata pointer). In this manner, the embodiments disclosed herein allow for a smaller tag size for each TLB entry without impacting TLB latency, with the added benefit of simplified TLB content addressable memory (CAM) logic.

[0017]

[0023] In aspects where the TLB metadata stored in the TLB metadata buffer entry includes the ASID and VMID of the processor context, the MMU is configured to detect a processor context switch to a new context associated with the ASID and VMID. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata including the ASID and VMID of the new context, the MMU may allocate a TLB metadata buffer entry for such. The MMU then selects a TLB metadata buffer entry that stores corresponding TLB metadata including the ASID and VMID of the new context for use in accessing the TLB and stores a pointer to the TLB metadata buffer entry in an active pointer table entry of an active pointer table. Some such aspects provide that the TLB metadata buffer entry further includes a translation regime indicator, and the MMU stores a pointer to the TLB metadata buffer entry in an active pointer table entry that corresponds to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry. Some aspects further provide that the TLB metadata buffer entry further includes a global indicator that, when set, indicates that any associated TLB entry can be used across multiple applications (i.e., only the VMID of the TLB entry needs to match). In these aspects, the MMU stores a pointer to the TLB metadata buffer entry as a global active TLB metadata pointer in an active pointer table entry.

[0018]

[0024] In an aspect in which the TLB metadata stored in a TLB metadata buffer entry includes multiple most significant bits of a VA of a memory region being used by a processor pipeline of the processor, an MMU is configured to receive a memory access request, the memory access request including the VA and associated with one processor pipeline of the processor-based device. According to some aspects, if no TLB metadata buffer entry stores corresponding TLB metadata including the multiple most significant bits of the VA, the MMU may allocate a TLB metadata buffer entry for such. The MMU selects a TLB metadata buffer entry that stores corresponding TLB metadata including the multiple most significant bits of the VA for use in accessing the TLB, and stores a pointer to the TLB metadata buffer entry in one of the active pointer table entries of an active pointer table that corresponds to the processor pipeline.

[0019]

[0025] In this regard, FIG. 1 is a diagram of an exemplary processor-based device 100 that includes a processor 102. The processor 102, which may also be referred to as a "processor core" or "central processing unit (CPU) core," may be an in-order or out-of-order processor (OoP) and / or may be one of multiple processors 102 provided by the processor-based device 100. In the example of FIG. 1, the processor 102 includes instruction processing circuitry 104 that includes one or more processor pipelines 106(0)-106(P) for processing instructions 108 fetched by fetch circuitry 112 from an instruction memory (labeled "INSTR memory" in FIG. 1) 110 for execution. The instruction memory 110 may be provided within or as part of a system memory within the processor-based device 100, as a non-limiting example. An instruction cache (labeled "INSTR cache" in FIG. 1) 114 may also be provided in the processor 102 for caching instructions 108 fetched from the instruction memory 110 to reduce latency in the fetch circuitry 112.

[0020]

[0026] 1 is configured to provide instructions 108 as fetched instructions 108F to one or more processor pipelines 106(0)-106(P) within instruction processing circuitry 104 for preprocessing before the fetched instructions 108F reach execution circuitry (labeled "EXEC circuitry" in FIG. 1) 116 for execution. The processor pipelines 106(0)-106(P) are provided across different processing circuits or stages of instruction processing circuitry 104 to preprocess and process the fetched instructions 108F in a series of steps that may be performed simultaneously to increase throughput before execution of the fetched instructions 108F by execution circuitry 116.

[0021]

[0027] 1, instruction processing circuit 104 includes decode circuit 120 configured to decode fetched instruction 108F, fetched by fetch circuit 112, into decoded instruction 108D to determine the required instruction type and action. The required instruction type and action encoded in decoded instruction 108D may also be used to determine which processor pipeline 106(0)-106(P) the decoded instruction 108D should be placed in. In this example, decoded instruction 108D is placed in one or more of processor pipelines 106(0)-106(P) and then provided to rename circuit 122 within instruction processing circuit 104. Renaming circuit 122 is configured to determine whether any register names in decoded instruction 108D should be renamed to decouple any register dependencies that would prevent parallel or out-of-order processing.

[0022]

[0028] 1 also includes a register access circuit (labeled "RACC circuit" in FIG. 1) 124. The register access circuit 124 is configured to access physical registers in a physical register file (PRF) (not shown) based on mapping entries of source register operands of the decoded instruction 108D mapped to logical registers in a register mapping table (RMT) (not shown) to obtain generated values ​​from the executed instruction 108E in the execution circuit 116. The register access circuit 124 is also configured to provide the generated values ​​obtained from the executed instruction 108E as source register operands of the decoded instruction 108D to be executed.

[0023]

[0029] Also provided in the instruction processing circuitry 104 is a scheduler circuit (labeled "SCHED circuitry" in FIG. 1) 126 that is provided to the processor pipelines 106(0)-106(P) and configured to store the decoded instruction 108D in a reservation entry until all source register operands for the decoded instruction 108D are available. The scheduler circuitry 126 issues the decoded instruction 108D ready for execution to the execution circuitry 116. A write circuitry 128 is also provided in the instruction processing circuitry 104 for writing or committing values ​​generated from the executed instruction 108E back to memory (such as a PRF), cache memory, or system memory.

[0024]

[0030] 1, processor-based device 100 further includes memory system 130 providing MMU 132 configured to manage memory accesses. MMU 132 provides TLB 134, which is a cache of recently executed translations of virtual addresses to physical addresses (PAs) performed by MMU 132 for memory pages containing retrieved instructions or data. MMU 132 of FIG. 1 is also communicatively coupled to memory controller 136 configured to perform memory read and write operations on system memory 138. System memory 138 in some aspects may include, by way of non-limiting example, double data rate (DDR) synchronous dynamic random access memory (SDRAM).

[0025]

[0031] 1 is responsible for performing VA-to-PA address translation operations that support the virtual memory functionality of processor-based device 100. In this regard, MMU 132, according to some aspects, may include multiple hierarchical page tables (not shown), each including page table entries that represent mappings for subdivisions of addressable virtual memory space having a particular size (i.e., memory pages). The mappings stored by the page table entries of the hierarchical page tables of MMU 132 may be cached in multiple TLB entries 140(0)-140(B) of TLB 134, each of which includes a corresponding TLB tag (labeled “tag” in FIG. 1 ) 142(0)-142(B) and data element (labeled “data” in FIG. 1 ) 144(0)-144(B). Each of TLB tags 142(0)-142(B) may include a virtual page address and may also include an ASID (not shown) for enabling a processor context switch without requiring TLB 134 to be invalidated and a VMID (not shown) for enabling a hypervisor virtual machine (VM) switch without requiring TLB 134 to be invalidated. Each data element 144(0)-144(B) may include a corresponding PA for TLB entry 140(0)-140(B). TLB entries 140(0)-140(B) may further include additional metadata not shown in FIG. 1 , such as a validity indicator, a global indicator, and / or memory properties such as type and access permissions.

[0026]

[0032] As mentioned above, TLB 134 can require a significant portion of processor 102's physical area, a problem that can be exacerbated as the size of data, such as the VA, ASID, and VMID, that are traditionally stored as part of the TLB tags 142(0)-142(B) of TLB entries 140(0)-140(B) increases. In this regard, MMU 132 provides TLB metadata buffer 146, which includes multiple TLB metadata buffer entries (labeled "TMB entries" in FIG. 1) 148(0)-148(T). Each of TLB metadata buffer entries 148(0)-148(T) stores corresponding TLB metadata (denoted "META" in FIG. 1 ) 150(0)-150(T), which may include any data that is traditionally stored as part of the TLB tags 142(0)-142(B) of TLB entries 140(0)-140(B) and that may be replicated within multiple TLB entries 140(0)-140(B) during execution of a software process by processor 102. Thus, in embodiments such as those discussed below with respect to FIG. 2 , TLB metadata 150(0)-150(T) may include the ASID and VMID of a processor context, while some embodiments such as those discussed below with respect to FIG. 3 may provide that TLB metadata 150(0)-150(T) include multiple high-order bits of the VA of a memory region being used by processor pipelines 106(0)-106(P) of processor 102.

[0027]

[0033] In exemplary operation, MMU 132 selects a TLB metadata buffer entry, such as TLB metadata buffer entry 148(0), for use in accessing TLB 134 of processor-based device 100 (e.g., based on a processor context switch or a memory access request from processor pipelines 106(0)-106(P)). MMU 132 then stores a pointer to TLB metadata buffer entry 148(0) (i.e., the index of TLB metadata buffer entry 146(0) within TLB metadata buffer 148) as active TLB metadata pointer (denoted in FIG. 1 as “ACT TLB META PTR”) 152. When MMU 132 receives memory access request (denoted in FIG. 1 as “MEM ACC REQ”) 154 that includes VA 156, MMU 132 generates a TLB entry (e.g., TLB entry 140(0)) in TLB 134 for VA 156 as part of the address translation operation. MMU 132 stores active TLB metadata pointer 152 as part of TLB tag 142(0) instead of TLB metadata 150(0) for TLB metadata buffer entry 148(0), which would traditionally be stored as part of TLB tag 142(0). When MMU 132 receives another memory access request 158 ​​that includes VA 156, MMU 132 may access TLB entry 140(0) based on active TLB metadata pointer 152 (e.g., by matching TLB tag 142(0) of TLB entry 140(0) with active TLB metadata pointer 152).

[0028]

[0034] As discussed above, processor 102 may simultaneously fetch and process instructions in processor pipelines 106(0)-106(P), allowing multiple processes (not shown) to be executed in parallel by processor 102. Such processes are assigned an ASID by an operating system (OS) executed by processor 102 and are also assigned their own set of translation tables for use by MMU 132 in performing VM-to-PA translation operations. Upon a processor context switch (i.e., a transfer of execution from a first process to a second process), processor 102 saves the execution state of the first process and restores the execution state of the second process. Processor 102 also switches translation table entries to the translation table entries of the second process as part of the processor context switch. To eliminate the need to flush a conventional TLB with each processor context switch, conventional TLBs store the ASID of a particular process as part of the TLB tag of each TLB entry, allowing multiple TLB entries for a given memory page used by different processes to exist in the TLB. Similarly, when a process is running within a VM that is itself running within a hypervisor, a traditional TLB also stores the VM's VMID as part of the TLB tag of each TLB entry to eliminate the need to flush the TLB on a VM switch.

[0029]

[0035] To compress the size of TLB tags while providing ASIDs and VMIDs to different processes, some aspects of MMU 132 of FIG. 1 provide support for storing TLB metadata including ASIDs and VMIDs. In this regard, FIG. 2 illustrates an exemplary aspect of MMU 132 of FIG. 1. As seen in FIG. 2, MMU 132 includes TLB metadata buffer 200, which corresponds in function to TLB metadata buffer 146 of FIG. 1. TLB metadata buffer 200 stores a plurality of TLB metadata buffer entries 202(0) through 202(T), which correspond in function to TLB metadata buffer entries 148(0) through 148(T) of FIG. 1. In the example of Figure 2, TLB metadata buffer entries 202(0)-202(T) include respective validity indicators (labeled "valid" in Figure 2) 204(0)-204(T) and respective least-recently-used (LRU) data (labeled "LRU" in Figure 2) 206(0)-206(T). TLB metadata buffer entries 202(0)-202(T) of Figure 2 also include global indicators (labeled "global" in Figure 2) 208(0)-208(T) that indicate whether associated TLB entries 140(0)-140(B) of TLB 134 of Figure 1 are available to multiple processes. TLB metadata buffer entries 202(0)-202(T) also include respective TLB metadata 210(0)-210(T), which include ASIDs 212(0)-212(T) and VMIDs 214(0)-214(T). Because different translation regimes (e.g., EL2, EL2&0, EL1&0, etc.) may be used during a given processor context, TLB metadata 210(0)-210(T) also include respective translation regime indicators (labeled "TRANS REG" in FIG. 2) 216(0)-216(T).

[0030]

[0036] MMU 132 further provides an active pointer table 218 that stores a plurality of active pointer table entries 220(0)-220(A). Each of active pointer table entries 220(0)-220(A) stores a respective active TLB metadata pointer 222(0)-222(A), which corresponds in function to active TLB metadata pointer 152 of Figure 1. Active pointer table entries 220(0)-220(A) are each associated with a translation regime and store the active TLB metadata pointer 222(0)-222(A) for inclusion within the TLB tag 142(0)-142(B) of the TLB entry 140(0)-140(A) corresponding to that translation regime. Thus, for example, active pointer table entry 220(0) may be associated with translation regime EL1&0 such that active TLB metadata pointer 222(0) is stored as part of the TLB tag 142(0)-142(B) of TLB entry 140(0)-140(B) corresponding to translation regime EL1&0. Active pointer table entries 220(0)-220(A) may also store respective global active TLB metadata pointers 224(0)-224(A) that may be used to point to TLB metadata buffer entries 202(0)-202(T) for which corresponding global indicators 208(0)-208(T) are set.

[0031]

[0037] 2 detects a processor context switch to a new context 226 associated with an ASID 228 and a VMID 230. To ensure that there are TLB metadata buffer entries 202(0)-202(T) available for use with the new context 226, the MMU 132 may invalidate one or more of the least recently used TLB metadata buffer entries 202(0)-202(T) of the TLB metadata buffer 200. The MMU 132 may then store TLB metadata 210(0)-210(T) including the ASID 228 and the VMID 230 of the new context 226, or store the VMID 230 of the new context 226 and determine whether there are one or more TLB metadata buffer entries 202(0)-202(T) with the corresponding global indicator 208(0)-208(T) set. Otherwise, MMU 132 allocates a TLB metadata buffer entry, such as TLB metadata buffer entry 202(0), stores ASID 228 and VMID 230 of new context 226 as ASID 212(0) and VMID 214(0) of TLB metadata 210(0) for TLB metadata buffer entry 202(0), and, in some aspects, sets global indicator 208(0) appropriately.

[0032]

[0038] Upon identifying a TLB metadata buffer entry, such as TLB metadata buffer entry 202(0), that stores corresponding TLB metadata 210(0) including ASID 228 and VMID 230 of new context 226 (or that stores corresponding TLB metadata 210(0) including VMID 230 of new context 226 and has global indicator 208(0) set), MMU 132 selects TLB metadata buffer entry 202(0) for use in accessing TLB 134 of Figure 1. MMU 132 then stores a pointer to TLB metadata buffer entry 202(0) in an active pointer table entry, such as active pointer table entry 220(0), that corresponds to the translation regime indicated by translation regime indicator 216(0) of TLB metadata buffer entry 202(0). 2, if translation regime indicator 216(0) indicates that TLB metadata buffer entry 202(0) corresponds to translation regime EL1&0, which is represented by active pointer table entry 220(0), MMU 132 stores a pointer to TLB metadata buffer entry 202(0) as active TLB metadata pointer 222(0) in active pointer table entry 220(0). When MMU 132 subsequently generates a TLB entry, such as TLB entry 140(0) in TLB 134, for a memory access request made during new context 226 under translation regime EL1&0, MMU 132 obtains active TLB metadata pointer 222(0) from active pointer table entry 220(0) corresponding to translation regime EL1&0 and stores it as part of TLB tag 142(0) of TLB entry 140(0) instead of ASID 228 and VMID 230. In some aspects, if global indicator 208(0) of TLB metadata buffer entry 202(0) is set, MMU 132 stores a pointer to TLB metadata buffer entry 202(0) as global active TLB metadata pointer 224(0) in active pointer table entry 220(0).

[0033]

[0039] To compress the size of the TLB tag while providing the most significant bits of the VA for memory pages being accessed by processor pipelines 106(0)-106(P) of Figure 1, some aspects of MMU 132 of Figure 1 provide support for storing TLB metadata including the most significant bits of an implementation-specific number of VAs. In this regard, Figure 3 illustrates an example aspect of MMU 132 of Figure 1 that provides a TLB metadata buffer 300 that corresponds in function to TLB metadata buffer 146 of Figure 1. TLB metadata buffer 300 of Figure 3 stores a number of TLB metadata buffer entries 302(0)-302(T) that correspond in function to TLB metadata buffer entries 148(0)-148(T) of Figure 1. 3, TLB metadata buffer entries 302(0)-302(T) include respective validity indicators (labeled "valid" in FIG. 3) 304(0)-304(T) and respective LRU data (labeled "LRU" in FIG. 3) 306(0)-306(T). TLB metadata buffer entries 302(0)-302(T) also include respective TLB metadata (labeled "META" in FIG. 3) 308(0)-308(T), each of which includes a number of upper VA bits 310(0)-310(T) of the VA of a memory page.

[0034]

[0040] 3 further provides an active pointer table 312 that stores a plurality of active pointer table entries 314(0)-314(A), each of which stores a respective active TLB metadata pointer 316(0)-316(A), corresponding in function to active TLB metadata pointer 152 of FIG. 1. Active pointer table entries 314(0)-314(A) also store corresponding pipeline identifiers (denoted "pipeline IDs" in FIG. 3) 318(0)-318(A), each identifying a processor pipeline within processor pipelines 106(0)-106(P) with which the respective active pointer table entry 314(0)-314(A) is associated.

[0035]

[0041] 3 receives a memory access request 320 that includes a VA 322 having a plurality of upper VA bits 324 and that is associated with one of processor pipelines 106(0)-106(P) of processor-based device 100, such as processor pipeline 106(0). MMU 132 may determine whether a TLB metadata buffer entry 302(0)-302(T) exists that stores corresponding TLB metadata 308(0)-308(T) that includes the plurality of upper bits 324 of VA 322. If not, MMU 132 may allocate a TLB metadata buffer entry, such as TLB metadata buffer entry 302(0), and store the plurality of upper bits 324 of VA 322 as TLB metadata 308(0) for TLB metadata buffer entry 302(0).

[0036]

[0042] After identifying TLB metadata buffer entry 302(0) that stores corresponding TLB metadata 308(0) including multiple high-order bits 324 of VA 322, MMU 132 selects TLB metadata buffer entry 302(0) for use in accessing TLB 134 of Figure 1. MMU 132 then stores a pointer to TLB metadata buffer entry 302(0), for example, as active TLB metadata pointer 316(0) in active pointer table entry 314(0), and also stores an identifier for processor pipeline 106(0) as pipeline identifier 318(0) in active pointer table entry 314(0). When MMU 132 subsequently generates a TLB entry, such as TLB entry 140(0) in TLB 134, for a memory access request to VA 322 in processor pipeline 106(0), MMU 132 obtains active TLB metadata pointer 316(0) from active pointer table entry 314(0) corresponding to processor pipeline 106(0) and stores it as part of TLB tag 142(0) of TLB entry 140(0) instead of the full VA 322.

[0037]

[0043] To illustrate an example operation of the MMU 132 and TLB 134 of Figure 1 for compressing TLB tags using the TLB metadata buffer 146, according to some aspects, Figure 4 provides a flowchart illustrating an example operation 400. For clarity, reference will be made to elements of Figure 1 when describing Figure 4. Operation 400 begins by MMU 132 of processor-based device 100 selecting one TLB metadata buffer entry (e.g., TLB metadata buffer entry 148(0) of FIG. 1 ) from among multiple TLB metadata buffer entries (e.g., TLB metadata buffer entries 148(0)-148(T) of FIG. 1 ) in a TLB metadata buffer (e.g., TLB metadata buffer 146 of FIG. 1 ) for use in accessing a TLB (e.g., TLB 134 of FIG. 1 ) in processor-based device 100, where TLB metadata buffer entries 148(0)-148(T) are each configured to store corresponding TLB metadata (e.g., TLB metadata 150(0)-150(T) of FIG. 1 ) (block 402). MMU 132 stores a pointer to TLB metadata buffer entry 148(0) as an active TLB metadata pointer (e.g., active TLB metadata pointer 152 of FIG. 1 ) (block 404).

[0038]

[0044] MMU 132 subsequently receives a first memory access request (e.g., memory access request 154 of FIG. 1 ) that includes a first VA (e.g., VA 156 of FIG. 1 ) (block 406). In response to receiving first memory access request 154, MMU 132 generates a TLB entry in TLB 134 for first VA 156 (e.g., TLB entry 140(0) of FIG. 1 ), the TLB entry including a TLB tag (e.g., TLB tag 142(0) of FIG. 1 ) that stores active TLB metadata pointer 152 in place of TLB metadata 150(0) of TLB metadata buffer entry 148(0) (block 408). In some aspects, MMU 132 receives a second memory access request (e.g., memory access request 158 ​​of FIG. 1 ) that includes first VA 156 (block 410). In response to receiving the second memory access request 158, the MMU 132 accesses TLB entry 140(0) based on the active TLB metadata pointer 152 (e.g., by matching the TLB tag 142(0) of TLB entry 140(0) using the active TLB metadata pointer 152) (block 412).

[0039]

[0045] 5A-5B provide a flowchart illustrating an example operation 500 of the MMU 132 of FIGS. 1 and 2 for storing TLB metadata including ASIDs and VMIDs for multiple translation regimes in response to a processor context switch, according to some aspects. In describing FIGS. 5A and 5B, reference is made to elements of FIGS. 1 and 2 for clarity. It should be understood that portions of the operation 500 illustrated in FIGS. 5A and 5B correspond to the operations described above with respect to FIG. 4. In FIG. 5A, the operation 500 begins with the MMU 132 detecting a processor context switch to a new context (e.g., context 226 of FIG. 2) associated with an ASID (such as ASID 228 of FIG. 2) and a VMID (e.g., VMID 230 of FIG. 2) (block 502). In some aspects, MMU 132 may invalidate one or more least recently used TLB metadata buffer entries (e.g., TLB metadata buffer entries 202(0) through 202(T) of FIG. 2 ) of a plurality of TLB metadata buffer entries of a TLB metadata buffer (e.g., TLB metadata buffer 200 of FIG. 2 ) (block 504). In this manner, MMU 132 may ensure in advance that at least one or more least recently used TLB metadata buffer entries will be available for use within new context 226.

[0040]

[0046] Some aspects may provide for MMU 132 determining that no TLB metadata buffer entry 202(0)-202(T) exists among the plurality of TLB metadata buffer entries 202(0)-202(T) that stores corresponding TLB metadata (e.g., TLB metadata 210(0)-210(T) of FIG. 2 ) including ASID 228 and VMID 230 of new context 226 (block 506). In response to determining that no TLB metadata buffer entry 202(0)-202(T) exists among the plurality of TLB metadata buffer entries 202(0)-202(T) that stores corresponding TLB metadata 210(0)-210(T) including ASID 228 and VMID 230 of new context 226, MMU 132 performs a series of operations (block 508). MMU 132 first allocates a TLB metadata buffer entry (e.g., TLB metadata buffer entry 202(0) of FIG. 2) (block 510). MMU 132 then stores ASID 228 and VMID 230 of new context 226 as TLB metadata 210(0) in TLB metadata buffer entry 202(0) (block 512). Operation 500 then proceeds to block 514 of FIG. 5B.

[0041]

[0047] 5B, MMU 132 selects (block 514) TLB metadata buffer entry 202(0) that stores corresponding TLB metadata 210(0) including ASID 228 and VMID 230 of new context 226 for use in accessing TLB 134. Thus, the operations of block 502 to detect a processor context switch to new context 226 and the operations of block 514 to select TLB metadata buffer entry 202(0) that stores corresponding TLB metadata 210(0) including ASID 228 and VMID 230 of new context 226 correspond in some aspects to the operations of block 402 of FIG. MMU 132 then stores a pointer to TLB metadata buffer entry 202(0) in one active pointer table entry (such as active pointer table entry 220(0) of FIG. 2 ) of multiple active pointer table entries 220(0)-220(A) of active pointer table 218 that corresponds to the translation regime indicated by the translation regime indicator of TLB metadata buffer entry 202(0) (e.g., translation regime indicator 216(0) of FIG. 2 ) (block 516). Thus, the operation of block 516 for storing a pointer to TLB metadata buffer entry 202(0) in active pointer table entry 220(0) that corresponds to the translation regime indicated by the translation regime indicator 216(0) of TLB metadata buffer entry 202(0) corresponds, in some aspects, to the operation of block 404 of FIG. 4 .

[0042]

[0048] In some aspects, the operation of block 516 to store a pointer to TLB metadata buffer entry 202(0) in active pointer table entry 220(0) corresponding to the translation regime indicated by translation regime indicator 216(0) of TLB metadata buffer entry 202(0) may include MMU 132 determining that a global indicator of TLB metadata buffer entry 202(0) (e.g., global indicator 208(0) of FIG. 2) is set (block 518). In response to determining that global indicator 208(0) of TLB metadata buffer entry 202(0) is set, MMU 132 stores the pointer to TLB metadata buffer entry 202(0) as a global active TLB metadata pointer in active pointer table entry 220(0) (e.g., global active TLB metadata pointer 224(0) of FIG. 2) (block 520).

[0043]

[0049] 1 and 3 for storing TLB metadata including upper bits of VAs for multiple processor pipelines according to some aspects, FIG. 6 provides a flowchart illustrating exemplary operations 600. For clarity, reference is made to elements of FIGS. 1 and 3 when describing FIG. 6. It should be understood that some of the operations 600 illustrated in FIG. 6 correspond to the operations described above with respect to FIG. 4. The operations 600 of FIG. 6 include the MMU 132 receiving a third memory access request (e.g., memory access request 320 of FIG. 3) that includes a second VA (e.g., VA 322 of FIG. 3) and that is associated with one processor pipeline (e.g., processor pipeline 106(0) of FIG. 1) among multiple processor pipelines (e.g., processor pipelines 106(0)-106(P) of FIG. 1) of processor-based device 100 (block 602). According to some aspects, MMU 132 may determine that a TLB metadata buffer entry (such as TLB metadata buffer entries 302(0)-302(T) in FIG. 3 ) that stores corresponding TLB metadata (such as TLB metadata 308(0)-308(T) in FIG. 3 ) that includes multiple most significant bits (e.g., multiple most significant bits 324 in FIG. 3 ) of second VA 322 does not exist among multiple TLB metadata buffer entries 302(0)-302(T) in FIG. 3 . In response to determining that a TLB metadata buffer entry (such as TLB metadata buffer entries 302(0)-302(T) that stores corresponding TLB metadata 308(0)-308(T) that includes multiple most significant bits 324 in second VA 322 does not exist among multiple TLB metadata buffer entries 302(0)-302(T), MMU 132 performs a series of operations (block 606). MMU 132 first allocates a TLB metadata buffer entry (e.g., TLB metadata buffer entry 302(0) in FIG. 3) (block 608). MMU 132 then stores the upper bits 324 of second VA 322 as TLB metadata 308(0) for TLB metadata buffer entry 302(0) (block 610).

[0044]

[0050] MMU 132 selects TLB metadata buffer entry 302(0) that stores corresponding TLB metadata 308(0) that includes the plurality of most significant bits 324 of second VA 322 for use in accessing a TLB (such as TLB 134 of FIG. 1) (block 612). Thus, the operation of block 612 to select TLB metadata buffer entry 302(0) that stores corresponding TLB metadata 308(0) that includes the plurality of most significant bits 324 of second VA 322 corresponds in some aspects to the operation of block 402 of FIG. 4. MMU 132 then stores a pointer to TLB metadata buffer entry 302(0) in one active pointer table entry (e.g., active pointer table entry 314(0) of FIG. 3 ) that corresponds to processor pipeline 106(0) among multiple active pointer table entries (e.g., active pointer table entries 314(0)-314(A) of FIG. 3 ) in an active pointer table (e.g., active pointer table 312 of FIG. 3 ) (block 614). Thus, the operation of block 614 for storing a pointer to TLB metadata buffer entry 302(0) in active pointer table entry 314(0) that corresponds to processor pipeline 106(0) corresponds, in some aspects, to the operation of block 404 of FIG. 4 .

[0045]

[0051] The MMU and TLB according to the aspects disclosed herein and discussed with reference to Figures 1-4, 5A-5B, and 6 may be provided in or incorporated into any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile position unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopters.

[0046]

[0052] In this regard, FIG. 7 illustrates an example of a processor-based device 700 including an MMU and a TLB such as those illustrated and described with respect to FIGS. 1-4, 5A-5B, and 6. In this example, the processor-based device 700, which corresponds in function to the processor-based device 100 of FIG. 1, includes a processor 702 having one or more CPUs 704 coupled to a cache memory 706. The CPU(s) 704 are also coupled to a system bus 708, which may interconnect the devices included within the processor-based device 700. As is well known, the CPU(s) 704 communicate with these other devices by exchanging address, control, and data information via the system bus 708. For example, the CPU(s) 704 may communicate bus transaction requests to a memory controller 710. Although not illustrated in FIG. 7, multiple system buses 708 may be provided, with each system bus 708 constituting a different fabric.

[0047]

[0053] Other devices may also be connected to the system bus 708. As illustrated in FIG. 7, these devices may include, by way of example, a memory system 712, one or more input devices 714, one or more output devices 716, one or more network interface devices 718, and one or more display controllers 720. The input device(s) 714 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output device(s) 716 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 718 may be any device configured to enable the exchange of data with a network 722. The network 722 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 718 may be configured to support any type of communication protocol desired. The memory system 712 may include a memory controller 710 coupled to one or more memory arrays 724 and an MMU 726 (e.g., MMU 132 of FIGS. 1-3 ), which may be coupled to a TLB 728 (e.g., TLB 134 of FIG. 1 ).

[0048]

[0054] The CPU(s) 704 may also be configured to access display controller(s) 720 via the system bus 708 to control information sent to one or more displays 730. The display controller(s) 720 send information to be displayed to the display(s) 730 via one or more video processors 732, which process the displayed information into a format suitable for the display(s) 730. The display(s) 730 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0049]

[0055] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The master and slave devices described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip, by way of example. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0050]

[0056] The various illustrative logic blocks, modules, and circuits described in connection with aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0051]

[0057] Aspects disclosed herein may be embodied in hardware and / or instructions stored in the hardware and may reside in, for example, a Random Access Memory (RAM), a flash memory, a Read Only Memory (ROM), an Electrically Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0052]

[0058] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps described in the exemplary aspects may be combined. It should be understood that numerous and varied modifications may be made to the operational steps depicted in the flowchart diagrams, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also appreciate that information and signals may be represented using any of a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0053]

[0059] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0054]

[0060] The following numbered clauses describe example implementations. Article 1. a translation lookaside buffer (TLB) containing a plurality of TLB entries; a TLB metadata buffer including a plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata; a memory management unit (MMU); The MMU is Selecting one TLB metadata buffer entry from among the multiple TLB metadata buffer entries for use in accessing the TLB; storing a pointer to the TLB metadata buffer entry as the active TLB metadata pointer; receiving a first memory access request including a first virtual address (VA); In response to receiving the first memory access request, create a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores an active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry; A processor-based device that is configured to: Article 2. The MMU: receiving a second memory access request including the first VA; In response to receiving the second memory access request, accessing the TLB entry based on the active TLB metadata pointer. 10. The processor-based device of claim 1, further configured to: Article 3. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; MMU, Detecting a processor context switch to a new context associated with the ASID and VMID; selecting a TLB metadata buffer entry that stores corresponding TLB metadata including the ASID and VMID of the new context for use in accessing the TLB; and wherein the TLB metadata buffer entry is configured to select a TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for use in accessing the TLB. 2. A processor-based device according to clause 1 or 2. Clause 4. Before the MMU selects a TLB metadata buffer entry that stores the ASID and VMID of the new context as corresponding TLB metadata for use in accessing the TLB, determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and VMID of the new context; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and VMID of the new context, Allocate a TLB metadata buffer entry, Store the ASID and VMID of the new context as TLB metadata in the TLB metadata buffer entry; 4. The processor-based device of claim 3, further configured to: Article 5. the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding translation regime; each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata further including a translation regime indicator; the MMU is configured to store a pointer to the TLB metadata buffer entry in one active pointer table entry of a plurality of active pointer table entries of the active pointer table, the active pointer table entry corresponding to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry, thereby storing the pointer to the TLB metadata buffer entry as an active TLB metadata pointer; 10. A processor-based device according to clause 3 or 4. Article 6. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata further including a global indicator; each active pointer table entry of the plurality of active pointer table entries further including a global active TLB metadata pointer; MMU, determining that the global indicator in the TLB metadata buffer entry is set; responsive to determining that the global indicator of the TLB metadata buffer entry is set, storing a pointer to the TLB metadata buffer entry as a global active TLB metadata pointer in the active pointer table entry; and configured to store a pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry. 2. A processor-based device as described in clause 5. Clause 7. The processor-based device of any one of clauses 3 to 6, wherein the MMU is further configured to invalidate one or more least recently used TLB metadata buffer entries of the plurality of TLB metadata buffer entries following detecting a processor context switch to a new context associated with the ASID and VMID. Article 8. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata including a plurality of most significant bits of the VA; the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding processor pipeline among the plurality of processor pipelines; MMU, receiving a third memory access request including a second VA and associated with one of the processor pipelines of the processor-based device; selecting a TLB metadata buffer entry that stores corresponding TLB metadata including the plurality of most significant bits of the second VA for use in accessing the TLB; configured to select a TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for use in accessing the TLB; 3. The processor-based device of claim 1 or 2, wherein the MMU is configured to store a pointer to a TLB metadata buffer entry in one active pointer table entry of a plurality of active pointer table entries in an active pointer table that corresponds to the processor pipeline, thereby storing the pointer to the TLB metadata buffer entry as an active TLB metadata pointer. Clause 9. Before the MMU selects a TLB metadata buffer entry that stores corresponding TLB metadata including the plurality of most significant bits of the second VA for use in accessing the TLB, determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA, Allocate a TLB metadata buffer entry, storing the plurality of most significant bits of the second VA as TLB metadata in a TLB metadata buffer entry; 9. The processor-based device of claim 8, further configured to: Clause 10. The processor-based device of any one of clauses 1 to 9 integrated within a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a mobile phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopters. Article 11. means for selecting a translation lookaside buffer (TLB) entry from a plurality of TLB metadata buffer entries for use in accessing a translation lookaside buffer (TLB) of a processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata; means for storing a pointer to a TLB metadata buffer entry as an active TLB metadata pointer; means for receiving a first memory access request including a first virtual address (VA); , means for generating a TLB entry in the TLB for the first VA in response to receiving a first memory access request, the TLB entry including a TLB tag that stores an active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry; 2. A processor-based device, including Clause 12. A method for compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer, comprising: selecting, by a memory management unit (MMU) of the processor-based device, one TLB metadata buffer entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for use in accessing a TLB of the processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata; storing, by the MMU, a pointer to a TLB metadata buffer entry as an active TLB metadata pointer; receiving, by the MMU, a first memory access request including a first virtual address (VA); generating, by the MMU in response to receiving a first memory access request, a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores an active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry; A method comprising: Article 13. receiving, by the MMU, a second memory access request including the first VA; accessing, by the MMU, the TLB entry based on the active TLB metadata pointer in response to receiving the second memory access request; 13. The method of clause 12, further comprising: Article 14. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; Selecting a TLB metadata buffer entry from among a plurality of TLB metadata buffer entries for use in accessing the TLB detecting, by the MMU, a processor context switch to a new context associated with the ASID and VMID; selecting, by the MMU, a TLB metadata buffer entry that stores corresponding TLB metadata including the ASID and VMID of the new context for use in accessing the TLB; 14. The method of claim 12 or 13, comprising: Clause 15. Before selecting a TLB metadata buffer entry that stores the ASID and VMID of the new context as corresponding TLB metadata for use in accessing the TLB, determining, by the MMU, that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and VMID of the new context; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and VMID of the new context, allocating, by the MMU, a TLB metadata buffer entry; storing, by the MMU, the ASID and VMID of the new context as TLB metadata in a TLB metadata buffer entry; 15. The method of clause 14, further comprising: Article 16. the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding translation regime; each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata further including a translation regime indicator; storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in one active pointer table entry of a plurality of active pointer table entries of an active pointer table that corresponds to a translation regime indicated by the translation regime indicator of the TLB metadata buffer entry; 16. The method according to clause 14 or 15. Article 17. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata that further corresponds to the global indicator; each active pointer table entry of the plurality of active pointer table entries further including a global active TLB metadata pointer; storing a pointer to the TLB metadata buffer entry in an active pointer table entry corresponding to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry; determining, by the MMU, that a global indicator in the TLB metadata buffer entry is set; storing, by the MMU, a pointer to the TLB metadata buffer entry as a global active TLB metadata pointer in an active pointer table entry in response to determining that the global indicator of the TLB metadata buffer entry is set; 17. The method according to clause 16, comprising: Article 18. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store corresponding TLB metadata including a plurality of most significant bits of the VA; the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding processor pipeline among the plurality of processor pipelines; Selecting a TLB metadata buffer entry from among a plurality of TLB metadata buffer entries for use in accessing the TLB receiving, by the MMU, a third memory access request including a second VA and associated with one processor pipeline of a plurality of processor pipelines of the processor-based device; selecting, by the MMU, a TLB metadata buffer entry storing corresponding TLB metadata including the plurality of most significant bits of the second VA for use in accessing the TLB; Including, storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in one active pointer table entry of a plurality of active pointer table entries in an active pointer table corresponding to the processor pipeline; 14. The method according to clause 12 or 13. Clause 19. before selecting a TLB metadata buffer entry that stores corresponding TLB metadata including the plurality of most significant bits of the second VA for use in accessing the TLB; determining, by the MMU, that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA, allocating, by the MMU, a TLB metadata buffer entry; storing, by the MMU, the plurality of most significant bits of the second VA as TLB metadata in a TLB metadata buffer entry; 19. The method of clause 18, further comprising: Clause 20. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to: selecting a translation lookaside buffer (TLB) entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for use in accessing a TLB of the processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata; storing a pointer to the TLB metadata buffer entry as the active TLB metadata pointer; receiving a first memory access request including a first virtual address (VA); In response to receiving the first memory access request, creating a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores an active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry; Non-transitory computer-readable medium.

Claims

1. a translation lookaside buffer (TLB) containing a plurality of TLB entries; a TLB metadata buffer including a plurality of TLB metadata buffer entries each configured to store corresponding TLB metadata; a memory management unit (MMU); wherein the MMU comprises: selecting a TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for use in accessing the TLB; storing a pointer to said TLB metadata buffer entry as an active TLB metadata pointer; receiving a first memory access request including a first virtual address (VA); in response to receiving the first memory access request, creating a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry; It is configured as follows: Processor-based devices.

2. The MMU is receiving a second memory access request including the first VA; in response to receiving the second memory access request, accessing the TLB entry based on the active TLB metadata pointer; and further configured as follows: The processor-based device of claim 1 .

3. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; The MMU is Detecting a processor context switch to a new context associated with the ASID and VMID; selecting the TLB metadata buffer entry that stores the corresponding TLB metadata including the ASID and the VMID of the new context for use in accessing the TLB; thereby selecting the TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for use in accessing the TLB. The processor-based device of claim 1 .

4. before the MMU selects the TLB metadata buffer entry that stores the ASID and the VMID of the new context as the corresponding TLB metadata for use in accessing the TLB; determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and the VMID of the new context; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and the VMID of the new context, Allocating the TLB metadata buffer entry; storing the ASID and the VMID of the new context as the TLB metadata in the TLB metadata buffer entry; and further configured as follows: The processor-based device of claim 3 .

5. the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding translation regime; each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata further including a translation regime indicator; the MMU is configured to store the pointer to the TLB metadata buffer entry in one active pointer table entry of the plurality of active pointer table entries of the active pointer table that corresponds to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry, thereby storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer; The processor-based device of claim 3 .

6. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata further including a global indicator; each active pointer table entry of the plurality of active pointer table entries further including a global active TLB metadata pointer; The MMU is determining that the global indicator in the TLB metadata buffer entry is set; responsive to determining that the global indicator of the TLB metadata buffer entry is set, storing the pointer to the TLB metadata buffer entry as the global active TLB metadata pointer in the active pointer table entry. thereby storing the pointer to the TLB metadata buffer entry in the active pointer table entry corresponding to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry. The processor-based device of claim 5 .

7. 4. The processor-based device of claim 3, wherein the MMU is further configured to invalidate one or more least recently used TLB metadata buffer entries of the plurality of TLB metadata buffer entries following detecting the processor context switch to the new context associated with the ASID and the VMID.

8. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata including a plurality of most significant bits of a VA; the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding one of a plurality of processor pipelines; The MMU is receiving a third memory access request including a second VA and associated with one of a plurality of processor pipelines of the processor-based device; selecting the TLB metadata buffer entry that stores the corresponding TLB metadata including the most significant bits of the second VA for use in accessing the TLB; configured to select the TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for use in accessing the TLB; the MMU is configured to store the pointer to the TLB metadata buffer entry in one active pointer table entry of the plurality of active pointer table entries of the active pointer table corresponding to the processor pipeline, thereby storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer; The processor-based device of claim 1 .

9. before the MMU selects the TLB metadata buffer entry storing the corresponding TLB metadata including the plurality of most significant bits of the second VA for use in accessing the TLB; determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA, Allocating the TLB metadata buffer entry; storing the plurality of most significant bits of the second VA as the TLB metadata in the TLB metadata buffer entry; and further configured as follows: The processor-based device of claim 8 .

10. set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cell phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters 10. The processor-based device of claim 1, wherein the processor-based device is integrated within a device selected from the group consisting of:

11. 1. A processor-based system comprising: means for selecting a translation lookaside buffer (TLB) entry from a plurality of TLB metadata buffer entries for use in accessing a translation lookaside buffer (TLB) of the processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata; means for storing a pointer to said TLB metadata buffer entry as an active TLB metadata pointer; means for receiving a first memory access request including a first virtual address (VA); means for generating a TLB entry in the TLB for the first VA in response to receiving the first memory access request, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry; 1. A processor-based device comprising:

12. 1. A method for compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer, comprising: selecting, by a memory management unit (MMU) of a processor-based device, a TLB metadata buffer entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for use in accessing a TLB of the processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata; storing, by the MMU, a pointer to the TLB metadata buffer entry as an active TLB metadata pointer; receiving, by the MMU, a first memory access request including a first virtual address (VA); in response to receiving the first memory access request, creating, by the MMU, a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry; A method comprising:

13. receiving, by the MMU, a second memory access request including the first VA; accessing, by the MMU, the TLB entry based on the active TLB metadata pointer in response to receiving the second memory access request; The method of claim 12 further comprising:

14. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata including an application space identifier (ASID) and a virtual machine identifier (VMID) of a processor context; selecting a TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for use in accessing the TLB; Detecting, by the MMU, a processor context switch to a new context associated with an ASID and a VMID; selecting, by the MMU, the TLB metadata buffer entry that stores the corresponding TLB metadata including the ASID and the VMID of the new context for use in accessing the TLB; 13. The method of claim 12, comprising:

15. before selecting the TLB metadata buffer entry that stores the ASID and the VMID of the new context as the corresponding TLB metadata for use in accessing the TLB; determining, by the MMU, that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and the VMID of the new context; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the ASID and the VMID of the new context, allocating, by the MMU, the TLB metadata buffer entry; storing, by the MMU, the ASID and the VMID of the new context as the TLB metadata in the TLB metadata buffer entry; The method of claim 14 further comprising:

16. the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding translation regime; each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata further including a translation regime indicator; storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in one active pointer table entry of the plurality of active pointer table entries of the active pointer table that corresponds to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry.

15. The method of claim 14.

17. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata further corresponding to a global indicator; each active pointer table entry of the plurality of active pointer table entries further including a global active TLB metadata pointer; storing the pointer to the TLB metadata buffer entry in the active pointer table entry corresponding to the translation regime indicated by the translation regime indicator of the TLB metadata buffer entry; determining, by the MMU, that the global indicator in the TLB metadata buffer entry is set; storing, by the MMU, the pointer to the TLB metadata buffer entry as the global active TLB metadata pointer in the active pointer table entry in response to determining that the global indicator of the TLB metadata buffer entry is set; 17. The method of claim 16, comprising:

18. each TLB metadata buffer entry of the plurality of TLB metadata buffer entries configured to store the corresponding TLB metadata including a plurality of most significant bits of a VA; the MMU further includes an active pointer table, the active pointer table including a plurality of active pointer table entries, each of which associates an active TLB metadata pointer with a corresponding one of a plurality of processor pipelines; selecting a TLB metadata buffer entry from among the plurality of TLB metadata buffer entries for use in accessing the TLB; receiving, by the MMU, a third memory access request including a second VA and associated with one processor pipeline of a plurality of processor pipelines of the processor-based device; selecting, by the MMU, the TLB metadata buffer entry storing the corresponding TLB metadata including a plurality of most significant bits of the second VA for use in accessing the TLB; Including, storing the pointer to the TLB metadata buffer entry as the active TLB metadata pointer includes storing, by the MMU, the pointer to the TLB metadata buffer entry in one active pointer table entry of the plurality of active pointer table entries in the active pointer table corresponding to the processor pipeline. The method of claim 12.

19. before selecting the TLB metadata buffer entry that stores the corresponding TLB metadata including the plurality of most significant bits of the second VA for use in accessing the TLB; determining, by the MMU, that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA; In response to determining that no TLB metadata buffer entry exists among the plurality of TLB metadata buffer entries that stores corresponding TLB metadata including the plurality of most significant bits of the second VA, allocating, by the MMU, the TLB metadata buffer entry; storing, by the MMU, the plurality of most significant bits of the second VA as the TLB metadata in the TLB metadata buffer entry; 20. The method of claim 18, further comprising:

20. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, when executed, cause a processor of a processor-based device to: selecting a translation lookaside buffer (TLB) entry from a plurality of TLB metadata buffer entries of a TLB metadata buffer for use in accessing a TLB of the processor-based device, the TLB metadata buffer entries each configured to store corresponding TLB metadata; storing a pointer to said TLB metadata buffer entry as an active TLB metadata pointer; receiving a first memory access request including a first virtual address (VA); in response to receiving the first memory access request, creating a TLB entry in the TLB for the first VA, the TLB entry including a TLB tag that stores the active TLB metadata pointer in place of the TLB metadata of the TLB metadata buffer entry. Non-transitory computer-readable medium.

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