Coreless interposer manufacturing method

Abstract

Disclosed herein is a method for interconnect structures and systems in package manufacturing of interconnect structures configured to electrically communicate / couple one or more integrated circuit packages / semiconductor dies to a circuit substrate. The method includes forming one or more conductive lines, filling one or more gaps between the one or more conductive lines with an electrically insulating material, removing excess electrically insulating material to obtain a first layer of the interconnect structure, and repeating the above steps to produce one or more additional layers of the interconnect structure. The additional one or more layers are stacked on top of the first layer, thereby enabling on-the-fly formation of vertical electrical connections between the conductive lines / patterns.

Description

[Technical Field]

[0001] TECHNICAL FIELD The present disclosure relates generally to semiconductor devices, and more particularly to methods for fabricating interconnect structures and electrical interfaces. [Background technology]

[0002] Reducing the size of semiconductor devices improves device performance by reducing interconnect lengths, thus leading to increased signal transfer speeds and reduced device power consumption. Existing manufacturing methods for semiconductor devices are generally based on packaging a semiconductor die / chip and mounting it on a substrate. To enable electrical interconnections between devices, an interposer is attached between the substrate and the package. Therefore, the interposer should match the small pads and fine-pitch interconnects of the semiconductor die / chip with the relatively large pads and coarse-pitch interconnects of the substrate.

[0003] Currently, interposers are made with a silicon, glass, or organic core with vertical and horizontal electrical connections. The vertical electrical connections (vias) are typically formed by drilling holes through the substrate and plating the holes with a conductive material, which limits the aspect ratio that can be achieved.

[0004] Recent approaches to achieving shorter interconnect lengths include 2.5D or 3D interposers. However, forming electrical connections in 2.5D or 3D interposers requires drilling, which leads to manufacturing difficulties and poor reliability, and limits the design and complexity of via patterns. A further approach is to fabricate ultra-thin coreless interposers made from organic materials. However, these have high warpage, via cracking, and limited line / spatial resolution. Summary of the Invention

[0005] Aspects of the present disclosure, according to some embodiments thereof, relate to semiconductor devices. More particularly, but not exclusively, aspects of the present disclosure, according to some embodiments thereof, relate to coreless interposers and methods of manufacturing the same.

[0006] According to some embodiments, a coreless interposer interconnect structure is provided herein. The interposer includes one or more layers, each of which includes one or more conductive lines (e.g., regions, patterns, pads, etc.) configured to pass electrical signals and an electrically insulating material configured to fill voids between each of the one or more conductive lines. According to some embodiments, the one or more conductive lines are arranged in a predetermined pattern. In some embodiments, the predetermined patterns of each of the one or more layers may be different. According to some embodiments, the one or more layers are stacked substantially vertically, thereby enabling on-the-fly formation of vertical electrical connections between the conductive regions.

[0007] Advantageously, in some embodiments, the vertical electrical connections (ie, vias) of each of one or more layers are formed substantially simultaneously.

[0008] Advantageously, in some embodiments, the vertical electrical connections are formed without drilling and are therefore not limited by the aspect ratio (i.e., height to diameter ratio) of the vertical electrical connections. As a result, in some embodiments, the formation of vias with high density, complex patterns, and virtually unlimited via heights is facilitated and achieved.

[0009] According to some embodiments, the coreless interposer may be flexible. According to some embodiments, the coreless interposer may be semi-rigid. According to some embodiments, the coreless interposer may be rigid. Each possibility is a separate embodiment.

[0010] According to some embodiments, the aspect ratio of the vertical electrical connections is substantially infinite / unlimited.

[0011] According to some embodiments, a method is provided herein for a system in package manufacturing of an interconnect structure (e.g., a coreless interposer) configured to electrically communicate / couple one or more integrated circuit packages / semiconductor dies to a circuit substrate. The method includes forming one or more conductive lines (e.g., areas, pads, patterns, etc.), filling one or more gaps between the one or more conductive lines with an electrically insulating material, and removing the remaining electrically insulating material to obtain a first layer of the interconnect structure. The additional one or more layers are stacked on top of the first layer, thereby enabling on-the-fly formation of vertical electrical connections between the conductive lines.

[0012] According to some embodiments, the one or more conductive lines may be formed by photolithography.

[0013] According to some embodiments, photolithography may include forming a seed layer, applying a resist onto the seed layer, irradiating and developing the resist, filling one or more gaps between the developed resist with a conductive material, removing the developed resist, and removing residue of the seed layer such that one or more conductive lines of the conductive material are formed.

[0014] According to some embodiments, the one or more conductive lines may be formed by selective laser sintering.

[0015] According to some embodiments, removing the residue of the electrically insulating material may include planarizing using a surface planarization tool / machine, thereby forming a substantially flat surface of the first layer and / or the additional layer or layers of the interconnect structure.

[0016] According to some embodiments, excess electrically insulating material may be removed until a portion of the first layer and / or additional layer or layers of the interconnect structure is exposed.

[0017] According to some embodiments, the method may lack a drilling step. According to some embodiments, the method may lack an etching step.

[0018] According to some embodiments, the aspect ratio of vertical electrical connections formed according to the disclosed methods can be virtually unlimited.

[0019] According to some embodiments, the method can include curing and / or firing the electrically insulating material. According to some embodiments, the method can include heat treating the electrically insulating material.

[0020] According to some embodiments, filling the one or more voids may include pouring / spreading an electrically insulating material over the one or more conductive lines and the voids therebetween.

[0021] According to some embodiments, the method may include forming at least a first layer of an interconnect structure on a temporary carrier.

[0022] According to some embodiments, the electrically insulating material may be a dielectric.

[0023] According to some embodiments, the electrically insulating material may include one or more polymers.

[0024] According to some embodiments, the line / spatial resolution of the conductive line structures may be at least about 5 / 5 um.

[0025] According to some embodiments, the vertical electrical connections may include through-chip vertical electrical connections.

[0026] According to some embodiments, the interconnect structure may be configured to allow electrical coupling between conductive pads measuring approximately 100x100 um and conductive pads measuring approximately 5x5 um or less.

[0027] Particular embodiments of the present disclosure may include some, all, or any of the advantages described above. One or more other technical advantages will be readily apparent to those skilled in the art from the drawings, descriptions, and claims contained herein. Furthermore, while certain advantages have been enumerated above, various embodiments may include all, some, or none of the enumerated advantages.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. In case of conflict, the patent specification, including definitions, shall prevail. As used herein, the indefinite articles "a" and "an" mean "at least one" or "one or more" unless the context clearly dictates otherwise. [Brief explanation of the drawings]

[0029] Some embodiments of the present disclosure are described herein with reference to the accompanying drawings. The description, together with the drawings, will make apparent to those skilled in the art how some embodiments can be implemented. The drawings are for illustrative purposes and are not intended to show structural details of the embodiments in more detail than is necessary for a basic understanding of the present disclosure. For clarity, some objects shown in the drawings are not drawn to scale. Furthermore, two different objects in the same figure may be drawn to different scales. In particular, the scale of some objects may be greatly exaggerated compared to other objects in the same figure. [Figure 1A] FIG. 1A schematically illustrates a side view of an interconnect structure, according to some embodiments. [Figure 1B] FIG. 1B schematically illustrates a top view of the interconnect structure of FIG. 1A, according to some embodiments. [Figure 1C] FIG. 1C schematically illustrates a top view of each of one or more layers of the interconnect structure of FIG. 1A, according to some embodiments. [Figure 2] FIG. 2 illustrates a flowchart of a method for fabricating an interconnect structure, such as a coreless interposer, according to some embodiments. [Figure 3] FIG. 3 illustrates a schematic diagram of an example additive manufacturing process for forming conductive regions of an interconnect structure, according to some embodiments. [Figure 4] FIG. 4 schematically illustrates an example of a semi-additive manufacturing method for forming conductive regions of an interconnect structure, according to some embodiments. [Figure 5] FIG. 5 schematically illustrates an example of a semi-additive process for forming conductive regions of an interconnect structure, according to some embodiments. [Figure 6] FIG. 6 illustrates, in schematic form, an example of a method for fabricating an interconnect structure, such as a coreless interposer, according to some embodiments. [Figure 7] FIG. 7 shows an example cross-sectional view of an experimentally fabricated coreless interposer having four layers, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0030] The principles, uses, and implementations of the teachings herein may be better understood with reference to the accompanying description and drawings, which, upon review, will enable those skilled in the art to practice the teachings herein without undue effort or experimentation.

[0031] In the description and claims of this application, the words "include" and "have" and forms thereof are not limited to the members in a list with which the words may be associated.

[0032] As used herein, the term "about" may be used to specify a quantity or parameter value (e.g., the length of a member) within a continuous range of values ​​near (and including) a given (stated) value. According to some embodiments, "about" may specify a parameter value to be 80% to 120% of the given value. For example, the statement "the length of the member is equal to about 1 m" is equivalent to the statement "the length of the member is between 0.8 m and 1.2 m." According to some embodiments, "about" may specify a parameter value to be 90% to 110% of the given value. According to some embodiments, "about" may specify a parameter value to be 95% to 105% of the given value.

[0033] As used herein, according to some embodiments, the terms "substantially" and "about" may be interchangeable.

[0034] As used herein, according to some embodiments, the terms “interface,” “interposer,” and “interconnect structure” may be interchangeable and refer to an electrical interface configured to enable electrical interconnection between devices or components thereof. According to some embodiments, the electrical interface may be configured to route and / or reroute electrical interconnections, e.g., to spread electrical interconnections between large pads to smaller pads. According to some embodiments, an interposer may be configured to enable electrical interconnection between large pads formed on a printed circuit board (PCB) and small pads (e.g., having a small size / diameter and / or small pitch size) formed on a package, die, or any other component of an integrated circuit.

[0035] According to some embodiments, large pads may refer to pads having large sizes, such as, but not limited to, about 500×500 μm or larger, about 400×400 μm or larger, about 300×300 μm or larger, etc. Each possibility is a separate embodiment. According to some embodiments, large pads may refer to pads having large pitch sizes, such as, but not limited to, about 4 mm or larger, about 3 mm or larger, about 2 mm or larger, about 1.4 mm or larger, etc. Each possibility is a separate embodiment. According to some embodiments, small pads may refer to pads having small sizes, such as, but not limited to, about 4×4 μm or smaller, about 5×5 μm or smaller, about 7×7 μm or smaller, about 10×10 μm or smaller, about 12×12 μm or smaller, about 15×15 μm or smaller, about 20×20 μm or smaller, about 25×25 μm or smaller, about 30×30 μm or smaller, about 40×40 μm or smaller, about 50×50 μm or smaller, etc. Each possibility is a separate embodiment. According to some embodiments, small pads may refer to pads having small / fine pitch sizes (i.e., distance between each conductive region / line), such as, but not limited to, about 500 um or less, about 200 um or less, about 100 um or less, about 50 um or less, about 40 um or less, about 30 um or less, about 20 um or less, about 10 um or less, about 8 um or less, about 5 um or less, about 4 um or less, about 3 um or less, about 2.5 um or less, etc. Each possibility is a separate embodiment.

[0036] According to some embodiments, the interposer may be used, among other things, in integrated circuits to provide electrical communication between an integrated circuit die and a package / package substrate, such as a ball grid array (BGA) package, a multi-chip module, etc. According to some embodiments, the interposer may be integrated into a 3D integrated circuit die stack.

[0037] According to some embodiments, an interposer may refer to a logic interposer. According to some embodiments, an interposer may refer to a logic interposer and a memory interposer. According to some embodiments, an interposer may refer to an image sensor interposer, such as a complementary metal oxide semiconductor (CMOS) image interposer. According to some embodiments, an interposer may refer to a memory stack interposer. According to some embodiments, an interposer may refer to a power, RF, or analog integrated passive interposer. Each possibility is a separate embodiment.

[0038] As used herein, the term "coreless" may refer to a substrate-less structure, i.e., an interposer that does not have an interposer substrate. According to some embodiments, the term "coreless interposer" may refer to an interposer that lacks a core / substrate layer.

[0039] As used herein, the term "package" may refer to any package type that houses one or more semiconductor devices, dies, integrated circuits, memory devices, passive and / or active component elements, etc., or any combination thereof.

[0040] As used herein, the terms “conductive line,” “conductive material region,” “conductive region,” “contact pad,” and “conductive pattern” may be used interchangeably and refer to any conductive portion, such as a conductive portion, of a coreless interposer, according to some embodiments. According to some embodiments, the conductive line may be made of or include a metal, such as copper, gold, silver, nickel, etc., or any combination thereof. According to some embodiments, the conductive region is configured to electrically interconnect, route, and / or reroute integrated circuit devices and / or components thereof, such as, but not limited to, a microprocessor, a memory device, a chipset, a graphics device, one or more dies, etc., or any combination thereof. According to some embodiments, the conductive line may refer to an electrical trace. Additionally or alternatively, in some embodiments, the conductive line may form a conductive path (vertical electrical connection) between one or more layers of a coreless interposer, as further detailed elsewhere herein. According to some embodiments, the conductive lines can form various types of vias, including, but not limited to, through vias, tented vias, blind vias, buried vias, stacked vias, etc., or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, in contrast to traditionally formed vias, the vias disclosed herein are formed without drilling. According to some embodiments, in contrast to traditionally formed vias, the vias disclosed herein are formed without etching.

[0041] Reference is now made to Figure 1A, which schematically illustrates a side view of interconnect structure 100, Figure 1B, which schematically illustrates a top view thereof, and Figure 1C, which schematically illustrates a top view of each of one or more layers of interconnect structure 100, according to some embodiments.

[0042] According to some embodiments, the interconnect structure 100 includes a coreless interposer 102. According to some embodiments, the coreless interposer 102 is configured to enable electrical interconnection of packages (e.g., chip packages), modules, systems, etc., or any combination thereof. According to some embodiments, the coreless interposer 102 may be used to electrically interconnect a chip package to a printed circuit board (PCB), such as a motherboard, a central processing unit (CPU), etc.

[0043] Advantageously, in some embodiments, the line / spatial resolution of the coreless interposer 102 may be at least about 5 / 5 um. According to some embodiments, the contact pitch (spatial separation between nearest vias) of the coreless interposer 102 may be less than about 5 um. According to some embodiments, the contact pitch (spatial separation between nearest vias) of the coreless interposer 102 may be less than about 4 um. According to some embodiments, the contact pitch (spatial separation between nearest vias) of the coreless interposer 102 may be less than about 3 um. According to some embodiments, the contact pitch (spatial separation between nearest vias) of the coreless interposer 102 may be less than about 2.5 um.

[0044] According to some embodiments, the coreless interposer 102 has a substrateless structure. According to some embodiments, the conductive lines of the coreless interposer 102 are formed without drilling, etching, or otherwise penetrating it. This minimizes / prevents cracks or deformations while allowing for increased density and resolution of the conductive lines (and vias formed by the conductive lines, as further detailed elsewhere herein).

[0045] According to some embodiments, the coreless interposer 102 is a three-dimensional (3D) interposer. According to some embodiments, the coreless interposer 102 may include a plurality of high-density conductive lines defined therein. According to some embodiments, the coreless interposer 102 may include a plurality of ultra-thin and high-density vertical electrical interconnects formed therein. Advantageously, in some embodiments, the coreless interposer 102 enables miniaturization of electronic devices while improving interconnections, thereby improving performance and reducing power consumption of the electronic devices.

[0046] According to some embodiments, the interconnect structure 100 can be an ultra-thin structure, e.g., about 50 μm or less in thickness. According to some embodiments, the interconnect structure 100 can be an ultra-thin structure, e.g., about 40 μm or less in thickness. According to some embodiments, the interconnect structure 100 can be an ultra-thin structure, e.g., about 30 μm or less in thickness. According to some embodiments, the interconnect structure 100 can be an ultra-thin structure, e.g., about 20 μm or less in thickness. According to some embodiments, the interconnect structure 100 can be an ultra-thin structure, e.g., about 10 μm or less in thickness. According to some embodiments, the interconnect structure 100 can be an ultra-thin structure, e.g., about 5 μm to about 500 μm in thickness. Each possibility is a separate embodiment. In some embodiments, the interconnect structure 100 can have any desired thickness (i.e., a virtually unlimited height).

[0047] According to some embodiments, the interconnect structure 100 can have a multi-layer structure (e.g., two, three, four, five, six, seven, or more layers). Each possibility is a separate embodiment. According to some embodiments, the thickness of each layer can be substantially the same. In some embodiments, each layer can have a different thickness.

[0048] According to some embodiments, the interconnect structure 100 is configured to electrically interconnect various types of packaging to a substrate, such as, but not limited to, a ball grid array (BGA), a land grid array (LGA), a multi-chip module (MCM), a quad flat non-leaded package (QFN), a system-in-package (SiP), a package-on-package (PoP), a fan-out wafer-level package (WLP), or any other type of packaging.

[0049] According to some embodiments, the interconnect structure 100 may be used to electrically interconnect a single package to a substrate. According to some embodiments, the interconnect structure 100 may be used to electrically interconnect multiple packages to a substrate.

[0050] According to some embodiments, the interconnect structure 100 is configured to electrically interconnect microprocessors (e.g., single-core and / or multi-core processors), microcontrollers, memory chips (volatile memory, non-volatile memory, etc.), logic chips, integrated circuits, any passive and / or active components or devices, or any other electrical components, semiconductor devices, etc., or any combination thereof.

[0051] According to some embodiments, the coreless interposer 102 includes one or more layers. According to some embodiments, each of the one or more layers is stacked on top of the previous (bottom) layer. According to some embodiments, each of the multiple layers includes an electrically insulating region and a conductive region.

[0052] According to some embodiments, each insulating region is disposed between each conductive region, thereby preventing (horizontal) current flow (i.e., short-circuiting) between each of the conductive regions in a particular one or more layers. In other words, the one or more layers are stacked substantially vertically, forming vertical electrical connections between the insulating regions, thereby enabling vertical current flow through the one or more layers according to a predetermined pattern / path.

[0053] Advantageously, in some embodiments, the structure of the coreless interposer 102 enables on-the-fly formation of vertical electrical connections between electrically insulating materials. According to some embodiments, the vertical electrical connections of each of one or more layers may be formed simultaneously. Advantageously, in some embodiments, the vertical electrical connections are formed without drilling. Advantageously, in some embodiments, the vertical electrical connections are formed without etching (e.g., chemical etching). Advantageously, the vertical electrical connections may be formed in any desired pattern and / or height to facilitate routing of electrical signals. Advantageously, in some embodiments, the aspect ratio of the vertical electrical connections of the coreless interposer 102 may be substantially infinite / unlimited.

[0054] According to some embodiments, as shown in FIGS. 1A-C, one or more layers of the coreless interposer 102 may include four layers. According to some embodiments, as shown in FIG. 1A, a first layer 110 of the one or more layers includes a plurality of electrically conductive material regions 110a and a plurality of electrically insulating material regions 110b. According to some embodiments, as shown in FIG. 1A, a second layer 112, a third layer 114, and a fourth layer 116 of the one or more layers each include a plurality of electrically conductive material regions 112a, 114a, and 116a and a plurality of electrically insulating material regions 112b, 114b, and 116b, respectively. It will be understood that the number of one or more layers of the coreless interposer 102 may vary and may include virtually any desired number. According to some embodiments, the number of one or more layers may include 3, 4, 5, 6, 7, 8, 9, 10, 15, 20, 25, 30, or more layers, among others. According to some embodiments, as described in more detail in FIG. 2, there is virtually no upper limit to the number of one or more layers.

[0055] According to some embodiments, as shown in FIGS. 1A-C, the plurality of conductive material regions 110a of the first layer 110 may include a first plurality of contact pads configured to electrically interconnect to a substrate. According to some embodiments, the dimensions of each of the first plurality of contact pads may be approximately 100 um x 100 um. According to some embodiments, the dimensions of each of the first plurality of contact pads may be in the range of approximately 100-500 um x 100-500 um. According to some embodiments, the dimensions of each of the first plurality of contact pads may be in the range of approximately 50-500 um x 50-500 um. Each possibility is a separate embodiment.

[0056] According to some embodiments, the plurality of conductive material regions 112a of the second layer 112 can be configured to form vertical electrical connections of a desired pattern and / or size. According to some embodiments, the plurality of conductive material regions 114a of the third layer 114 can optionally include and / or serve as a redistribution layer (RDL) configured to reroute vertical electrical connections to desired locations. According to some embodiments, the plurality of conductive material regions 116a of the fourth layer 116 can include a second plurality of contact pads. The second plurality of contact pads are configured to interconnect the interposer 102 to a package. According to some embodiments, the dimensions of each of the second plurality of contact pads can be approximately 10 x 10 um or less. According to some embodiments, the dimensions of each of the second plurality of contact pads can be approximately 8 x 8 um or less. According to some embodiments, the dimensions of each of the second plurality of contact pads can be approximately 6 x 6 um or less. According to some embodiments, the dimensions of each of the second plurality of contact pads can be approximately 5 x 5 um or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be approximately 4 x 4 um or less. According to some embodiments, the dimensions of each of the second plurality of contact pads may be approximately 2.5 x 2.5 um or less. Each possibility is a separate embodiment.

[0057] According to some embodiments, the conductive material regions lines and / or contact pads may have a thickness of about 5-7 um or 3-6 um. According to some embodiments, the lines and / or pads may have a thickness of less than about 5 um.

[0058] According to some embodiments, the conductive material regions 110a / 112a / 114a / 116a may include or be in the form of contact pads. According to some embodiments, the form / shape of the conductive material regions 110a / 112a / 114a / 116a may include or be in the form of, among others, a circle, a square, a rectangle, a rounded rectangle, a chamfered rectangle, an octagon, a donut, an n-sided polygon, etc. (when viewed from above), or any combination thereof. Each possibility is a separate embodiment. According to some embodiments, the conductive material regions 110a / 112a / 114a / 116a may include or be in the form of electrical lines.

[0059] According to some embodiments, the vertical electrical connections may be in the form of or include through vias, tented vias, blind vias, buried vias, stacked vias, etc., among others, or any combination thereof. Each possibility is a separate embodiment.

[0060] According to some embodiments, the coreless interposer 102 may be flexible. According to some embodiments, the coreless interposer 102 may be semi-rigid. According to some embodiments, the coreless interposer 102 may be rigid. Each possibility is a separate embodiment. According to some embodiments, the rigid coreless interposer may have a Shore D hardness value in the range of approximately 90D to 100D. According to some embodiments, the rigid coreless interposer may have a Shore D hardness value in the range of approximately 85D to 96D. According to some embodiments, the flexible coreless interposer may have a Shore D hardness value in the range of approximately 55D to 75D. According to some embodiments, the flexible coreless interposer may have a Shore D hardness value in the range of approximately 60D to 70D. According to some embodiments, the semi-rigid coreless interposer may have a combined Shore D hardness value of the rigid coreless interposer and the flexible coreless interposer. That is, it may include a combination of rigid Shore D hardness and flexible Shore D hardness values ​​of the coreless interposer. As a non-limiting example, a semi-flexible coreless interposer may have an area of ​​Shore D hardness of about 96D and an area of ​​about 65D. Alternatively, in some embodiments, the semi-rigid coreless interposer may have a substantially uniform hardness, such as, but not limited to, a Shore D hardness value ranging from about 65D to 85D.

[0061] Reference is made to FIG. 2, which illustrates a flowchart 200 of a method for fabricating an interconnect structure, such as a coreless interposer, according to some embodiments.

[0062] According to some embodiments, in step 202, the method may include forming one or more conductive regions. According to some embodiments, the one or more conductive regions may include or be in the form of one or more conductive lines. According to some embodiments, the one or more conductive regions may include or be in the form of contact pads. According to some embodiments, the one or more conductive regions may be configured to form vias. According to some embodiments, the one or more conductive regions may be formed according to a predetermined pattern.

[0063] According to some embodiments, one or more conductive regions may be made of or include a metal. According to some embodiments, one or more conductive regions may include copper, gold, silver, etc. Each possibility is a separate embodiment. According to some embodiments, each of one or more layers of the interposer may be made of or include different materials. According to some embodiments, each of one or more layers of the interposer may be made of or include the same material (e.g., made of or include the same metal in each of one or more layers).

[0064] According to some embodiments, one or more conductive regions may be made from or include a mixture of conductive materials. According to some embodiments, one or more conductive lines may be made from or include a mixture of metals.

[0065] According to some embodiments, in step 202, the method may include forming one or more conductive regions on a temporary carrier substrate. According to some embodiments, the temporary carrier substrate may be made from an inert material, such as, but not limited to, glass, stainless steel, SiC, AlN, polyimide, polyimide on glass, etc. According to some embodiments, the temporary carrier substrate may be rigid, semi-rigid, or flexible. Each possibility is a separate embodiment.

[0066] According to some embodiments, one or more conductive regions may be formed by performing an additive manufacturing process (step 202a), such as, but not limited to, selective laser sintering, as detailed in FIG. 3.

[0067] According to some embodiments, the one or more conductive regions may be formed by performing semi-additive processes (step 202b), such as, but not limited to, photolithography and / or electroplating, as further detailed in Figures 4 and 5.

[0068] According to some embodiments, the method may include filling one or more gaps between one or more conductive regions with an electrically insulating material in step 204. According to some embodiments, filling may include pouring / spreading the electrically insulating material over the one or more conductive regions and the one or more gaps therebetween.

[0069] According to some embodiments, the electrically insulating material may include a dielectric material. According to some embodiments, the electrically insulating material may include one or more polymers. According to some embodiments, the electrically insulating material may be made from or include a polyimide. According to some embodiments, the electrically insulating material may be photosensitive. By way of non-limiting example, the electrically insulating material may be made from or include a photo-definable epoxy. According to some embodiments, the electrically insulating material may be non-photosensitive. According to some embodiments, the electrically insulating material may include a thickness to diameter ratio of at least about 5:1. According to some embodiments, the thickness of the electrically insulating material layer is in the range of about 5-30 μm. According to some embodiments, the electrically insulating material has a coefficient of thermal expansion of about 15-20 ppm / °C.

[0070] According to some embodiments, the CTE of the conductive region may be substantially matched to the CTE of the electrically insulating material, thereby facilitating heat management and dissipation generated by the electronic device away from it. Those skilled in the art will appreciate that insufficient heat transfer can result in reduced performance of the electronic device or its components. Furthermore, thermal expansion mismatch can lead to increased mechanical stress, which in turn can lead to reduced performance.

[0071] According to some embodiments, each of the one or more layers of the coreless interposer may be made from or include a different electrically insulating material. According to some embodiments, each of the one or more layers of the coreless interposer may be made from or include the same electrically insulating material.

[0072] According to some embodiments, in step 206, the method may optionally include heat treating, curing, and / or polymerizing the electrically insulating material that fills one or more gaps between the one or more conductive regions.

[0073] According to some embodiments, in step 208, the method may include removing excess electrically insulating material, thereby obtaining a first layer of one or more layers of an interconnect structure.

[0074] According to some embodiments, removing / scraping away excess electrically insulating material may include planarizing using a surface planarizing device / machine to form a substantially flat surface of the first layer (and / or each of the additional one or more layers) of the interconnect structure. According to some embodiments, excess portions of electrically insulating material may be removed until a portion of the conductive material region (e.g., a surface or top layer of the conductive material region) is exposed.

[0075] According to some embodiments, in step 210, the method may include repeating the above steps (e.g., steps 202-208) to generate one or more additional layers of the interconnect structure. In other words, the above steps may be repeated until a desired number of one or more layers is obtained (e.g., until a desired height / depth of the vertical electrical connection is achieved).

[0076] According to some embodiments, the iteration may include aligning conductive regions of a previous / bottom layer of one or more layers with one or more additional layers of the interconnect structure. According to some embodiments, the alignment may be performed according to fiducials / landmarks on the previous / bottom layer. According to some embodiments, the alignment between each conductive region of one or more layers may be about 1 um or less. According to some embodiments, the alignment between each conductive region of one or more layers may be about 0.5 um or less. Each possibility is a separate embodiment. In some embodiments, the methods disclosed herein enable the fabrication of coreless interposers with mismatch losses of less than about 10% or less than about 5%.

[0077] According to some embodiments, the method may include a step 212 of removing the temporary carrier from the interconnect structure, if desired.

[0078] According to some embodiments, the method may optionally include performing electrical measurements to test / verify at least a portion of one or more layers during and / or after fabrication of the interconnect structure (step not shown).

[0079] According to some embodiments, the method provides for "on the fly" formation of vertical electrical connections between electrically insulating materials.

[0080] In some embodiments, the methods disclosed herein lack any drilling steps. In some embodiments, the methods lack mechanical and / or laser drilling. Advantageously, therefore, the disclosed methods are not limited by the aspect ratio of via height to diameter, as opposed to methods involving via drilling, which tend to crack the interposer or portions thereof. In other words, in some embodiments, the aspect ratio can be virtually infinite.

[0081] Advantageously, because there is no limitation on the height-to-diameter aspect ratio, in some embodiments there is virtually no upper limit to the number of one or more layers that can be stacked on top of each other, thereby enabling the formation of vertical electrical connections (e.g., vias) between electrically insulating materials having virtually unlimited height / depth.

[0082] According to some embodiments, the predetermined patterns of each of the one or more layers may be different. According to some embodiments, complex and dense patterns can be achieved regardless of the number of one or more layers of the interposer. Advantageously, in some embodiments, the methods disclosed herein incorporate additive manufacturing techniques to produce coreless interposer interconnect structures. As a result, the interposer is produced by either semi-additive or additive (e.g., fully additive) methods. This allows for a wide range of patterns (e.g., interconnect schemes) and via architectures to be achieved in some embodiments. Therefore, necessary signal routing, signal integrity, and power delivery can be achieved while facilitating thermal management. In some embodiments, complex patterns of vertical electrical connections can be achieved substantially without reducing or limiting the resolution (i.e., density of conductive regions) of the interposer. According to some embodiments, the line / spatial resolution of the interconnect structure may be at least about 5 / 5 μm.

[0083] In some embodiments, coreless interposers manufactured according to the methods disclosed herein meet military standard testing for 1000 cycles from −45° C. to +145° C. In some embodiments, coreless interposers manufactured according to the methods disclosed herein meet Joint Electron Device Engineering Council (JEDEC) standards, including testing for 1000 cycles from −25° C. to +125° C.

[0084] In some embodiments, the methods disclosed herein enable fabrication of coreless interposers with mismatch losses of less than about 10% or less than about 5%. In some embodiments, the methods disclosed herein enable fabrication of coreless interposers with conductive material thickness variations of less than about 1 um or less than about 0.5 um. In some embodiments, the methods disclosed herein enable fabrication of coreless interposers with interlayer contact resistivities of less than about 1×10 -6 Ω / cm 2This makes it possible to manufacture coreless interposers with a size of less than 1000mm.

[0085] Reference is made to FIG. 3 , which schematically illustrates an example of an additive manufacturing method 302a for forming the conductive region (i.e., in step 202a of FIG. 2 ), according to some embodiments. According to some embodiments, the additive manufacturing method may include, among others, a selective laser sintering (SLS) method, such as, but not limited to, direct SLS, direct metal laser sintering (DMLS), selective laser melting (SLM), metal wire 3D printing, or any other additive manufacturing method. According to some embodiments, the additive manufacturing method may include any type of directed energy deposition method, powder-based fusion additive manufacturing, or the like, or any combination thereof. According to some embodiments, the additive manufacturing method may include micro metal additive manufacturing (MMAM). Each possibility is a separate embodiment.

[0086] According to some embodiments, in step 302a-1, the additive manufacturing process can include cleaning the carrier 304. According to some embodiments, the carrier 304 can be a temporary carrier. Alternatively, in some embodiments, the carrier can be a non-temporary carrier.

[0087] According to some embodiments, cleaning the carrier 304 may include performing a plasma surface treatment. According to some embodiments, the plasma surface treatment may be performed by atmospheric pressure plasma. According to some embodiments, cleaning the carrier 304 may include chemical etching (i.e., wet etching or dry etching) of the surface of the carrier. According to some embodiments, cleaning the carrier 304 may include dry etching of the surface of the carrier 304. According to some embodiments, cleaning the carrier 304 may include ultrasonic cleaning. According to some embodiments, cleaning the carrier 304 may include ozone treatment of the surface of the carrier. According to some embodiments, cleaning the carrier 304 may include any combination of the cleaning methods described above, or any other surface treatment / cleaning.

[0088] According to some embodiments, in step 302a-2, the additive manufacturing process may include coating a surface of the carrier 304 with a conductive material. According to some embodiments, the conductive material may be made of or may include one or more metals. According to some embodiments, the conductive material may include copper. According to some embodiments, the conductive material may include gold, silver, etc.

[0089] According to some embodiments, in step 302a-2, the additive manufacturing process may include spreading / coating the carrier 304 with an ink coating 308, such as, but not limited to, a copper ink coating. According to some embodiments, the ink coating 308 may include a structural powder (i.e., a high-melting-point powder such as a metal) and a binder / solvent (i.e., a powder with a lower melting point than the structural powder). In other words, in some embodiments, the ink coating 308 may be made from or include a mixture of two or more powders. According to some embodiments, the ink coating 308 may include a mixture of conductive materials (e.g., a mixture of metals). It will be understood by those skilled in the art that different binders and / or solvents will produce metal inks with different viscosities, thereby affecting their filling capabilities. According to some embodiments, the solvent may include, among others, water, ethylene glycol, diethylene glycol monomethyl ether, etc. Each possibility is a separate embodiment.

[0090] According to some embodiments, coating the carrier 304 with the conductive material may be performed by, among others, an ink spy coater, a slot die coater, an ultrasonic spin spy coater, or the like, or any combination thereof. According to some embodiments, coating the carrier 304 may include doctor blade coating to facilitate the formation of a well-defined coating thickness.

[0091] According to some embodiments, step 302a-2 may include drying the ink coating 308. According to some embodiments, drying may be performed by a blower, an oven, or the like, among others.

[0092] According to some embodiments, in step 302a-3, the additive manufacturing process may include performing selective laser sintering to form the conductive regions 310a according to a predetermined pattern. According to some embodiments, a direct laser writer may be used to perform the selective laser sintering.

[0093] According to some embodiments, in step 302a-4, the additive manufacturing process may include washing or otherwise removing the non-sintered material (e.g., non-sintered copper ink), thereby obtaining a pattern of conductive regions 310a. According to some embodiments, the pattern may include conductive lines having a required width, length, and distance between them, essentially as disclosed herein.

[0094] According to some embodiments, the method 302a may lack a material removal step.

[0095] Reference is now made to FIG. 4, which schematically illustrates an example of a semi-additive process 402b for forming conductive regions (ie, step 202a of FIG. 2), according to some embodiments.

[0096] According to some embodiments, the semi-additive manufacturing method may be based on or include a lithographic manufacturing method. According to some embodiments, the lithographic method may include, among other things, a maskless lithographic method. According to some embodiments, the lithography may include, among other things, see-through, e-beam and / or optical lithography (i.e., photolithography), etc. Each possibility is a separate embodiment. According to some embodiments, the lithography may include, among other things, nanolithography, plasmon-assisted lithography, laser interference lithography, nanosphere lithography, etc. Each possibility is a separate embodiment.

[0097] According to some embodiments, the semi-additive process 402b can include photolithography.

[0098] According to some embodiments, in step 404b-1, the semi-additive manufacturing process may include cleaning the carrier 404. According to some embodiments, cleaning the carrier 404 may include performing a plasma surface treatment. According to some embodiments, the plasma surface treatment may be performed by atmospheric pressure plasma. According to some embodiments, cleaning may include chemical etching (i.e., wet etching) of the surface of the carrier 404. According to some embodiments, cleaning the carrier may include dry etching of the surface of the carrier 404. According to some embodiments, cleaning the carrier may include ultrasonic cleaning (e.g., in different solutions such as acetone, methanol, etc.). According to some embodiments, cleaning the carrier may include ozone treatment of the surface of the carrier 404. According to some embodiments, cleaning the carrier may include any combination of the cleaning methods described above or any other surface treatment / cleaning.

[0099] According to some embodiments, in step 402b-2, the semi-additive process may include applying a radiation sensitive compound onto the carrier 404. According to some embodiments, the radiation sensitive compound may include a resist, such as a positive resist (i.e., the pattern formed in the positive resist is the same as the pattern on the mask) or a negative resist (i.e., the pattern formed is the inverse of the mask pattern). According to some embodiments, the resist may include a photoresist 408.

[0100] According to some embodiments, the carrier 404 may be maintained in a spin coater to apply / spread photoresist thereon. According to some embodiments, the carrier 404 may be placed on a vacuum spindle to apply / spread photoresist 408 thereon. According to some embodiments, the carrier 404 may be rotated (e.g., for about 15 seconds, about 30 seconds, about 60 seconds, etc.) to facilitate obtaining a uniform photoresist 408 coating. According to some embodiments, the carrier 404 may optionally undergo a pre-patterning heat treatment (e.g., soft baking) to remove solvent from the photoresist 408 and / or to strengthen adhesion to the carrier 404.

[0101] According to some embodiments, in step 402b-3, the semi-additive process may include pattern transfer. According to some embodiments, step 402b-3 may be performed in a clean room illuminated with yellow light. According to some embodiments, step 402b-3 may include exposing the photoresist 408 to radiation, such as ultraviolet radiation, to transfer the desired pattern.

[0102] According to some embodiments, after the pattern transfer is completed, the photoresist 408 may be removed from the unpatterned portions such that a pattern of one or more insulating regions 410b is formed on the carrier 404. According to some embodiments, a developer solution (e.g., a developer solution that does not contain metal ions) may be used to remove the unexposed portions of the negative photoresist and expose the positive photoresist 408.

[0103] According to some embodiments, step 402b-3 may include performing a post-exposure bake before developing the pattern of one or more insulating regions 410b on the carrier 404.

[0104] According to some embodiments, step 402b-3 may include performing a hard bake of the one or more insulating regions 410b to facilitate solidification of the pattern of the one or more insulating regions 410b.

[0105] According to some embodiments, step 402b-3 may include removing photoresist residue.

[0106] According to some embodiments, in step 402b-4, the semi-additive process may include applying a conductive material between one or more gaps between one or more insulating regions 410b. According to some embodiments, the conductive material may be applied by electroplating (e.g., copper electroplating).

[0107] According to some embodiments, the one or more gaps between the one or more insulating regions 410b define the area and dimensions of the conductive material (i.e., conductive regions 410a, such as lines, pads, vias, etc.) on the carrier. As a non-limiting example, in semi-additive processes, the resolution of the conductive lines of the interconnect structure is defined by the resolution of the photoresist pattern obtained by photolithography (i.e., the smallest dimensions that can be accurately transferred into the resist coated on the carrier).

[0108] According to some embodiments, in step 402b-6, the semi-additive process may optionally include removing one or more insulating regions 410b. According to some embodiments, removing the photoresist may include any suitable removal method, such as wet and / or dry etching, stripping, cleaning, etc., or any combination thereof.

[0109] Reference is made to FIG. 5, which illustrates a schematic example of a semi-additive process 502b for obtaining conductive regions (ie, of step 202b of FIG. 2), according to some embodiments.

[0110] According to some embodiments, the semi-additive manufacturing method 502b may be based on or include a lithographic manufacturing method. According to some embodiments, the lithographic method may include, among other things, a maskless lithographic method. According to some embodiments, the lithography may include, among other things, see-through, e-beam and / or optical lithography (i.e., photolithography), etc. Each possibility is a separate embodiment. According to some embodiments, the lithography may include, among other things, nanolithography, plasmon-assisted lithography, laser interference lithography, nanosphere lithography, etc. Each possibility is a separate embodiment.

[0111] According to some embodiments, the semi-additive process 502b can include photolithography.

[0112] According to some embodiments, in step 502b-1, the semi-additive manufacturing process may include providing / obtaining a carrier substrate 504. According to some embodiments, the carrier 504 may be a temporary carrier.

[0113] According to some embodiments, step 502b-1 may include cleaning the carrier 504. According to some embodiments, the carrier cleaning may include performing a plasma surface treatment. According to some embodiments, the carrier cleaning may include chemical etching (i.e., wet etching) of the surface of the carrier 504. According to some embodiments, the carrier cleaning may include dry etching of the surface of the carrier 504. According to some embodiments, the carrier cleaning may include ultrasonic cleaning. According to some embodiments, the carrier cleaning may include ozone treatment, plasma treatment, etc. of the surface of the carrier. According to some embodiments, the carrier cleaning may include any combination of the cleaning methods described above, or any other suitable surface treatment / cleaning.

[0114] According to some embodiments, in step 502b-2, the semi-additive process may include forming a seed layer 506 on the carrier 504. According to some embodiments, the seed layer 506 may be made of or may include one or more metals. According to some embodiments, the seed layer 506 may include TiW and copper (Cu).

[0115] According to some embodiments, the seed layer 506 can be formed by a metallization process. According to some embodiments, the seed layer 506 can be formed by a physical vapor deposition (PVD) method, such as sputtering or thermal evaporation. According to some embodiments, the seed layer 506 can be formed by a chemical vapor deposition (CVD) method, such as atomic layer deposition (ALD). Each possibility is a separate embodiment.

[0116] According to some embodiments, in step 502b-3, the semi-additive process may include applying a radiation sensitive compound onto the seed layer 506. According to some embodiments, the radiation sensitive compound may include a resist, such as a positive resist (i.e., the pattern formed in the positive resist is the same as the pattern on the mask) or a negative resist (i.e., the pattern formed is the inverse of the mask pattern). According to some embodiments, the resist may include a photoresist 508.

[0117] According to some embodiments, the carrier 504 may be placed on a vacuum spindle while the photoresist is applied. According to some embodiments, the carrier 504 may then be spun (e.g., for about 15 seconds, about 30 seconds, about 60 seconds, etc.) to facilitate obtaining a uniform coating of the photoresist 506. According to some embodiments, the coated carrier 504 may optionally undergo a pre-patterning heat treatment (e.g., baking) to remove solvent from the photoresist 508 and / or to strengthen adhesion of the photoresist 508 to the seed layer 506.

[0118] According to some embodiments, in step 502b-4, the semi-additive process may include photoresist illumination and development (pattern transfer). According to some embodiments, step 502b-4 may be performed in a clean room illuminated with yellow light. According to some embodiments, step 502b-4 may include irradiating with radiation, such as ultraviolet light, to transfer a desired pattern into the photoresist 508, forming one or more electrically insulating regions 510b (i.e., photoresist pattern 510b).

[0119] According to some embodiments, after the pattern transfer is complete, the photoresist 508 may be removed from the unpatterned portions, thereby exposing the pattern of one or more electrically insulating regions 510 formed on the seed layer 506. According to some embodiments, the unpatterned photoresist may be removed by washing, sonication, etching, and / or rinsing in a solution, plasma oxidation, etc., or any combination thereof.

[0120] According to some embodiments, a second heat treatment (e.g., post-baking) may optionally be performed after developing the pattern on the carrier 504. According to some embodiments, the carrier 504 and the developed pattern may be dried in an ambient environment.

[0121] According to some embodiments, in step 502b-5, the semi-additive process may include filling one or more gaps between the regions of electrically insulating material 510b with a conductive material to form one or more conductive regions 510a. According to some embodiments, the one or more conductive regions 510a may be formed by electroplating. As a non-limiting example, step 504b-5 may include copper electroplating.

[0122] According to some embodiments, in step 502b-6, the semi-additive process may include removing the photoresist pattern 510b. According to some embodiments, the photoresist pattern 510b may be removed by wet chemical techniques. According to some embodiments, AZ 100 remover may be used to remove the photoresist pattern 510b. According to some embodiments, AZ 920 remover may be used to remove the photoresist pattern 510b. According to some embodiments, 1-methyl-2-pyrrolidone (NMP) remover may be used to remove the photoresist pattern 510b. According to some embodiments, dimethyl sulfoxide (DMSO) may be used to remove the photoresist pattern 510b (e.g., by ultrasonic cleaning).

[0123] According to some embodiments, in step 502b-7, the semi-additive process may include removing the remaining seed layer 506 between the one or more conductive regions 510a to prevent horizontal current flow between each of the one or more conductive regions 510a through each of the one or more layers of the interconnect structure, thereby allowing vertical current flow (i.e., between each of the one or more layers of the coreless interposer).

[0124] According to some embodiments, the remainder of the seed layer 506 may be removed by etching or any other suitable removal technique.

[0125] Reference is made to FIG. 6, which schematically illustrates an example of a method 600 for manufacturing a coreless interposer, according to some embodiments.

[0126] According to some embodiments, in step 602, the method may include forming a seed layer 601 on a carrier 603. According to some embodiments, step 602 may include sputtering one or more metals to obtain the seed layer 601.

[0127] According to some embodiments, in step 604, the method may include applying photoresist 605 onto carrier 603. According to some embodiments, photoresist 605 may be applied by using a spin coater to facilitate a uniform coating of photoresist 605. According to some embodiments, coated carrier 603 may optionally undergo a soft bake to remove solvent from photoresist 605 and / or to enhance adhesion to carrier 603.

[0128] According to some embodiments, in step 606, the method may include irradiating and developing (i.e., pattern transfer) the photoresist 605. According to some embodiments, after the pattern transfer is complete, the photoresist 605 may be removed from its unexposed portions by, for example, washing, rinsing, and / or using a developer. According to some embodiments, step 606 may optionally include a post-exposure bake before developing the photoresist pattern 607. According to some embodiments, step 606 may optionally include a hard bake of the photoresist pattern to facilitate solidification of the photoresist pattern 607. According to some embodiments, step 606 may optionally include a step of removing residue of the photoresist 605.

[0129] According to some embodiments, in step 608, the method may include applying a conductive material between one or more gaps in the photoresist pattern 607. According to some embodiments, the conductive material may be applied by electroplating (e.g., copper electroplating), thereby forming one or more conductive regions 609.

[0130] According to some embodiments, in step 610, the method may include removing the photoresist pattern 607, for example, by rinsing, wet and / or dry etching, cleaning, etc., or any combination thereof.

[0131] According to some embodiments, in step 612, the method may include removing the seed layer 601 remaining between one or more conductive regions 609.

[0132] According to some embodiments, in step 614, the method may include filling one or more gaps between one or more conductive regions with an electrically insulating material 611.

[0133] According to some embodiments, in step 616, the method may include heat treating, curing, and / or polymerizing the electrically insulating material 611 that fills the one or more voids.

[0134] According to some embodiments, in step 618, the method may include removing excess electrically insulating material 611, thereby obtaining a first layer of one or more layers of a coreless interposer.

[0135] According to some embodiments, each of steps 620, 622, 624, 626, 628, 630, 632, 634, and 636 may be similar or identical to each of steps 602, 604, 606, 608, 610, 612, 614, 616, and 618, thereby obtaining a second layer of one or more layers of a coreless interposer.

[0136] According to some embodiments, each of steps 638, 640, 642, 644, 646, 648, 650, 652, and 654 may be similar or identical to each of steps 602, 604, 606, 608, 610, 612, 614, 616, and 618, thereby obtaining a third layer of one or more layers of a coreless interposer.

[0137] Similarly, according to some embodiments, each of steps 656, 658, 660, 662, 664, 666, 668, 670, and 672 may be similar to or identical to each of steps 602, 604, 606, 608, 610, 612, 614, 616, and 618, thereby obtaining a fourth layer of one or more layers of a coreless interposer. It will be understood by those skilled in the art that the disclosed method enables manufacturing a coreless interposer having any required number of one or more layers.

[0138] According to some embodiments, the photoresist patterns 607 for each of the first, second, third, and fourth layers may be different.

[0139] According to some embodiments, in step 674, the method may include removing the carrier from the coreless interposer.

[0140] [Example] Example 1 According to some embodiments, a coreless interposer 700 has been experimentally prepared by using copper to form one or more conductive lines and by using SU-8 (GLM2060 SU8 by Gersteltec) to form one or more electrically insulating regions.

[0141] FIG. 7 shows a cross-sectional side view obtained from a high-resolution scanning electron microscope (HR-SEM) using a focused ion beam (FIB) in a dual beam tool of a coreless interposer 700 fabricated according to the processes disclosed herein, particularly using the semi-additive approach disclosed herein.

[0142] 7, the coreless interposer 700 has four layers. A first layer 710 includes a plurality of conductive lines 710a and a plurality of regions of electrical insulating material 710b. As shown in FIG. 7, a second layer 712, a third layer 714, and a fourth layer 716 of the one or more layers of the coreless interposer 700 each include a plurality of conductive lines 712a, 714a, and 716a and a plurality of regions of electrical insulating material 712b, 714b, and 716b, respectively.

[0143] 7, the thickness of each of the plurality of conductive lines 710a, 712a, and 714a is substantially uniform and is about 5 um, and the thickness of the conductive line 716a of the fourth layer 716 is about 7 um.

[0144] It will be understood that certain features of the disclosure that are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, for brevity, various features of the disclosure that are described in the context of a single embodiment may also be provided separately or in any suitable combination, or as appropriate, in any other embodiment of the disclosure. A feature described in the context of an embodiment should not be considered an essential feature of that embodiment unless expressly designated as such.

[0145] Although method steps may be described in a particular order according to some embodiments, methods of the present disclosure may include some or all of the described steps performed in a different order. In particular, it should be understood that the order of any stages and substages of a described method may be reordered unless the context clearly dictates otherwise, e.g., where a later stage requires as input the output of a previous stage, or where a later stage requires the product of a previous stage. Methods of the present disclosure may include some of the described stages or all of the described stages. A particular step in a disclosed method should not be considered an essential step of the method unless expressly designated as such.

[0146] While the present disclosure has been described in conjunction with specific embodiments thereof, it is evident that there may be numerous alternatives, modifications, and variations that will be apparent to those skilled in the art. Accordingly, the present disclosure embraces all such alternatives, modifications, and variations that fall within the scope of the appended claims. It is to be understood that the present disclosure is not necessarily limited in its application to the details of construction and arrangement of parts and / or methods set forth herein. Other embodiments may be implemented and the embodiments may be carried out in various ways.

[0147] The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. A citation or identification of a citation in this application shall not be construed as an admission that such citation is available as prior art to the disclosure. Section headings are used herein to facilitate understanding of the specification and should not be construed as necessarily limiting.

Claims

1. 1. A method for a system in package manufacturing of an interconnect structure configured to electrically communicate / couple one or more integrated circuit packages / semiconductor dies to a circuit substrate, comprising: forming one or more conductive lines; filling one or more gaps between the one or more conductive lines with an electrically insulating material; removing excess electrically insulating material, thereby obtaining a first layer of the interconnect structure; A method in which the above steps are repeated to create one or more additional layers of the interconnect structure, with the additional one or more layers being stacked on top of the first layer, thereby enabling on-the-fly formation of vertical electrical connections between conductive lines / patterns.

2. The method of claim 1 , wherein the one or more conductive lines are formed by photolithography.

3. 3. The method of claim 2, wherein the photolithography comprises forming a seed layer, applying a resist to the seed layer, irradiating and developing the resist, filling one or more gaps between the developed resist with a conductive material, removing the developed resist, and removing residue of the seed layer as formed.

4. The method of claim 1 , wherein the one or more conductive lines are formed by selective laser sintering.

5. 5. The method of claim 1, wherein removing excess portions of the electrically insulating material comprises planarizing using a surface planarizing tool / machine, thereby forming a substantially flat surface of the first layer and / or the additional layer or layers of the interconnect structure.

6. 6. The method of claim 1, wherein excess portions of the electrically insulating material are removed until a portion of the first layer and / or the additional layer or layers of the interconnect structure is exposed.

7. The method according to any one of claims 1 to 6, wherein the method is devoid of a perforation step.

8. The method of claim 7 , wherein the aspect ratio of the vertical electrical connection is substantially unlimited.

9. The method according to any one of claims 1 to 8, wherein the method comprises curing and / or baking the electrically insulating material.

10. 10. The method of any one of claims 1 to 9, wherein filling the one or more voids comprises pouring / spreading the electrically insulating material over the one or more conductive lines and voids therebetween.

11. The method according to any one of claims 1 to 10, wherein the electrically insulating material is a dielectric.

12. The method of claim 11 , wherein the electrically insulating material comprises one or more polymers.

13. The method of any one of claims 1 to 12, wherein the line / spatial resolution of the interconnecting conductive lines is at least about 5 / 5 um.

14. The method of any one of claims 1 to 13, wherein the method comprises forming at least the first layer of the interconnect structure on a temporary carrier.

15. The method of claim 14 further comprising removing the temporary carrier.

16. The method of any one of claims 1 to 15, wherein the vertical electrical connection comprises a through-chip vertical electrical connection.

17. 17. The method of any one of claims 1 to 16, wherein the interconnect structure is configured to enable electrical coupling between conductive pads of about 100x100um size and conductive pads of about 5x5um size or less.

18. 1. A coreless interposer interconnect structure, comprising: The interposer comprises one or more layers, each of the one or more layers comprising: one or more conductive lines configured to pass electrical signals and arranged in a predetermined pattern; an electrically insulating material configured to fill voids between each of the one or more conductive lines; each of said one or more layers being stacked substantially vertically to enable on-the-fly formation of vertical electrical connections between conductive lines; Coreless interposer interconnect structure.

19. 20. The coreless interposer of claim 18, wherein the predetermined pattern of each of the one or more layers is different.

20. 20. The coreless interposer of claim 18 or 19, wherein the electrically insulating material comprises a photocurable epoxy.

21. The coreless interposer of any one of claims 18 to 20, wherein the aspect ratio of the vertical electrical connection is substantially infinite.

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