Stripline wafers for wafer-based connector systems

Abstract

A multilayer stripline wafer for use in an electrical connector. The multilayer stripline wafer includes multiple layers. A signal transmission path is disposed on at least one inner layer of the multiple layers. The signal transmission path may be an uncoupled or loosely coupled single-ended signal transmission path or a differentially coupled signal transmission path. A conductive planar member is disposed on one or more of the multiple layers. The conductive planar member is spaced apart from the signal transmission path. The one or more conductive planar members control the impedance of the signal transmission path.

Description

[Technical Field]

[0001] The present invention relates generally to electrical connectors and connector systems, and more particularly to wafer-based electrical connectors comprising stripline-based wafers. [Background technology]

[0002] Electrical connectors for interconnecting circuit board backplanes with daughterboards typically include two mating connector halves. One of the mating halves typically contains multiple wafers or circuit boards containing signal-carrying and ground traces. These connectors are required to have high contact densities and operate at relatively high electrical speeds. The electronics industry's ongoing trend toward miniaturization and improved electrical performance is driving ever-increasing demands for increased contact density and higher electrical speeds. These demands create design conflicts because increasing contact density places traces and contacts in close proximity to one another, which creates signal integrity issues between the traces and contacts. Summary of the Invention [Problem to be solved by the invention]

[0003] Therefore, it would be beneficial to provide an electrical connector with a stripline wafer that can provide several signal integrity advantages, including, but not limited to, increased current carrying capacity and improved skew, impedance, and shielding performance. [Means for solving the problem]

[0004] The solution is provided by a connector system that includes one or more multilayer stripline wafers that provide several signal integrity advantages, including, but not limited to, improved skew, impedance, and shielding. The connector's one or more multilayer stripline wafers also provide increased current carrying capacity for power wafer applications. Additionally, the one or more multilayer stripline wafers are typically thicker than known wafers, providing a mechanical advantage to the electrical connector.

[0005] The invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a top view of an exemplary circuit board or wafer according to the prior art, the wafer having grounded coplanar waveguide transmission lines. [Figure 2] 1 is a perspective view of an exemplary circuit board or wafer according to the prior art; [Figure 3] 1 is a perspective view of an exemplary embodiment of a multilayer circuit board or wafer according to the present invention; [Figure 4] 4 is a diagram of an exemplary embodiment of a representative layer of the multilayer circuit board or wafer of FIG. 3. [Figure 5] 4 is a diagram of another exemplary layer of a representative layer of the multilayer circuit board or wafer of FIG. 3. [Figure 6] 6 is a cross-sectional view of the multilayer circuit board or wafer taken along line 6-6 of FIG. 3. [Figure 7] FIG. 4 is a partial perspective view of a mating area of ​​the multilayer circuit board or wafer of FIG. 3. [Figure 8] FIG. 4 is a side view of the multilayer circuit board or wafer of FIG. 3 showing the various layers. [Figure 9]FIG. 1 is a perspective view of an exemplary electrical connector assembly comprising multiple wafers according to the present invention, the wafers having slots that engage with keys on the housing of the backplane connector to ensure accurate contact and pad alignment and to achieve a robust backplane housing. [Figure 10] FIG. 1 is a graph showing a comparison between two simulated wafers with five signal pairs, the plots showing significantly lower far end crosstalk (FEXT) in the stripline wafer of the present invention compared to the prior art grounded coplanar waveguide wafer. [Figure 11] FIG. 1 is a schematic diagram of a first exemplary layer of a four-layer circuit board or wafer configured for high-speed signal integrity, where layers (a) and (d) are ground planes and layers (b) and (c) are wiring layers. [Figure 12] FIG. 1 is a schematic diagram of a second exemplary layer of a four-layer circuit board or wafer configured to accommodate high current / power, with layers (a), (b), (c), and (d) being conductive plane layers. [Figure 13] FIG. 1 is a diagram of an exemplary alternative embodiment of a representative layer of a multilayer circuit board or wafer, with the upper layer shown in transparency and illustrating vias placed along the trace routing of the representative layer. [Figure 14] FIG. 14 is a cross-sectional view of the representative view of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] The connector system includes one or more multi-layer stripline wafers that provide several signal integrity advantages, including, but not limited to, improved skew, impedance, and shielding. The connector's one or more multi-layer stripline wafers also provide increased current carrying capacity for power wafer applications. Additionally, the one or more multi-layer stripline wafers are typically thicker than known wafers, providing a mechanical advantage to the electrical connector.

[0008] One embodiment is directed to a multi-layer stripline wafer for use in an electrical connector. The multi-layer stripline wafer includes a plurality of layers. Single-ended signal transmission paths are disposed on at least one interior layer of the plurality of layers. The single-ended signal transmission paths are spaced apart from one another to maintain an uncoupled state. A conductive planar member is disposed on one or more of the plurality of layers. The conductive planar member is spaced apart from the single-ended signal transmission paths. One or more of the interior conductive planar members controls the impedance of the single-ended signal transmission paths.

[0009] One embodiment is directed to a multilayer stripline wafer for use in an electrical connector. The multilayer stripline wafer includes a plurality of layers. A differentially coupled signal transmission path is disposed on at least one inner layer of the plurality of layers. A conductive planar member is disposed on one or more of the plurality of layers. The conductive planar member is spaced apart from the differentially coupled signal transmission path. The one or more conductive planar members control the impedance of the differentially coupled signal transmission path.

[0010] One embodiment is directed to a multi-layer stripline wafer for use in an electrical connector, the multi-layer stripline wafer including multiple layers of spaced apart conductive material configured to enable high current transmission across the multi-layer stripline wafer.

[0011] As shown in FIG. 1, a known wafer-based connector system 10 uses a grounded coplanar waveguide signal transmission line, trace, or path 12. The wafer-based connector system 10 uses skew compensation techniques that extend traces 14 near the pincer area and / or mating area 16. These techniques are complex, tedious to design, and difficult to adjust from an impedance perspective. Also, in known systems, the grounded coplanar waveguide transmission line, trace, or path 12 is constructed on a two-layer wafer 18, as shown in FIG. 2. Typically, the beam region 22 of a two-layer wafer-based connector system 10 has a high, undesirable impedance. In a two-layer wafer 18, the beam region 22 of the mating signal contact 20 is located in a portion of the wafer 18 that does not have a copper or ground layer, resulting in a high impedance in the beam region 22. As a result, the beam region 22 is farther from the ground plane 24. To solve this, the thickness of the wafer 18 can be reduced. However, the wafer 18 cannot be made too thin in consideration of durability.

[0012] In contrast, the exemplary multilayer stripline wafer 30 of the present invention shown in Figures 3-6 allows signals to be routed in a single-ended manner. However, the present invention and wafer are not limited to single-ended routing. For example, signals may be routed in differential signal transmission lines, traces, or paths.

[0013] The single-ended signal transmission lines, traces, or paths 32 may be spaced apart from one another to maintain an uncoupled or loosely coupled state. When the signal transmission lines, traces, or paths 32 are uncoupled, no mode conversion occurs. Therefore, for successful skew correction, it is only necessary to match the lengths of the signal transmission lines, traces, or paths 32. The wafer 30 may be a printed circuit board, which may be, but is not limited to, microstrip (two layers) or stripline (three or more layers) with or without a coplanar ground.

[0014] 3-9 illustrate an electrical connector system 40 formed in accordance with an exemplary embodiment. The electrical connector system 40 includes a backplane connector 42 and a daughtercard connector 44 that are used to electrically connect a backplane circuit board (not shown) and a daughtercard circuit board (not shown). Although the electrical connector system 40 is described herein with reference to the backplane connector 42 and the daughtercard connector 44, it is understood that the subject matter herein may be utilized with different types of electrical connectors other than backplane connectors and daughtercard connectors, such as, but not limited to, mezzanine-style connector systems in which the wafer is essentially an interposer. Backplane connector 42 and daughtercard connector 44 are merely illustrative of an exemplary embodiment of electrical connector system 40 for interconnecting particular types of circuit boards, namely, backplane circuit boards with daughtercard circuit boards.

[0015] In the exemplary embodiment shown, the daughtercard connector 44 comprises a right-angle connector in which the mating interface 46 and the mounting interface 48 are oriented perpendicular to one another. The daughtercard connector 44 may be attached to a daughtercard circuit board at the mounting interface 48 and mated to the backplane connector 42 at the mating interface 46. In alternative embodiments, other orientations of the interfaces 46, 48 are possible.

[0016] The daughter card connector 44 includes a housing 50 that holds multiple stripline wafers 30. The housing 50 may be constructed from one or more pieces without departing from the scope of the present invention.

[0017] Each stripline wafer 30 has individual signal transmission lines, traces, or paths 32 extending between conductive pads 52 located adjacent to the mating interface 46 and conductive pads 54 located adjacent to the mounting interface 48, although the specific configuration of the individual signal transmission lines, traces, or paths 32 may vary from wafer to wafer 30. The signal conductive pads 52 are configured to make electrical connection to the signal transmission lines, traces, or paths 32 by known methods such as, but not limited to, vias or through-holes. The signal conductive pads 52 are configured to mate with and electrically connect to signal contacts 20 of the backplane connector 42.

[0018] A floating pad 53 is provided proximate to the mating interface 46. The floating pad 53 extends between the mating interface 46 and the conductive pad 52. The floating pad 53 does not physically contact the conductive pad 52. In the illustrated embodiment, the floating pad 53 is disposed proximate to but spaced apart from the second internal ground layer 72, which is disposed on an adjacent layer of the wafer 30. However, in other embodiments, the floating pad 53 may be further spaced apart from any ground members. In the illustrated embodiment, the floating pad 53 is in close proximity to the ground plane member 72. In the illustrated exemplary embodiment, the floating pad 53 is capacitively coupled to the second internal ground layer 72 and the beam region 22 of the contact 20. However, the floating pad 53 may be capacitively coupled to other layers.

[0019] As shown in FIGS. 6 and 8, an exemplary wafer 30 includes a first conductive layer 70, a second inner conductive layer 72, a third inner conductive layer 74, and a fourth conductive layer 76. In this embodiment, the first conductive layer 70 is a top ground layer. The fourth conductive layer 76 is a bottom ground layer. The second layer 72 includes signal transmission lines, traces, or paths 32. The third conductive layer 74 includes several ground coppers or paths. However, the purpose and use of each conductive layer may vary depending on the specific configuration required. For example, the signal transmission lines, traces, or paths 32 may be routed on the third inner conductive layer 74. As shown in FIGS. 13 and 14, ground stitching vias 75 may also be provided in the ground layers. Vias 75 are placed along the routing of the signal transmission lines, traces, or paths 32 to further facilitate noise reduction. Additionally, in various embodiments, ground and power may be shared on any layer. While this embodiment shows four layers, any number of layers may be used.

[0020] An opening 62 is provided in the first layer 70 to expose the conductive pad 52 and the floating pad 53. An opening 63 (FIG. 3) is also provided to expose the conductive pad 54. A fourth conductive ground plane layer 76 is disposed on the opposite side of the wafer 30. The ground layers 70 and 76 are configured to mate with and be electrically connected to the ground contacts or ground plates of the backplane connector 42.

[0021] When used in a wafer configuration, stripline signal transmission lines, traces, or paths 32 significantly reduce the complexity associated with skew correction compared to known wafer connectors. The stripline wafer 30 allows signals to be routed single-ended through the stripline signal transmission lines, traces, or paths 32, rather than differentially coupled as is done in the prior art. The single-ended stripline signal transmission lines, traces, or paths 32 can be spaced apart to maintain an uncoupled state. Because the stripline signal transmission lines, traces, or paths 32 are uncoupled, no mode conversion occurs. Therefore, successful skew correction only requires that the lengths of the stripline signal transmission lines, traces, or paths 32 be matched.

[0022] The stripline wafer 30 also allows for increased wiring density. With a typical printed circuit board stackup, the stripline signal transmission lines, traces, or paths 32 can be significantly narrower compared to grounded coplanar waveguides while meeting the same impedance targets. The increased wiring density allows for a denser electrical connector system 40.

[0023] Stripline wafer 30 allows printed circuit board manufacturers to more reliably consistently meet required impedance targets, resulting in fewer scrapped printed circuit boards. In contrast, prior art grounded coplanar waveguides are susceptible to under-etching / over-etching, which can adversely affect impedance.

[0024] In the illustrated exemplary embodiment, the multilayer stripline wafer 30 has a second internal conductive planar member 72 and a third internal conductive planar member 74 disposed in the beam region 22. In this embodiment, the second internal conductive planar member 72 is a ground member. The second internal conductive planar member 72 is used as a reference and is capacitively coupled to the floating pad 53 in the beam region 22 of the contact 20, allowing the floating pad 53 to cooperate with the beam region 22 to reduce the impedance of the beam region 22. In one embodiment, the ground plane member 72 may be spaced approximately 0.004 inches from the floating pad 53.

[0025] The stripline wafer 30 of the present invention allows for finer control of impedance in the signal transmission lines, traces or paths 32. As shown in Figures 6 and 8, the multi-layer stripline wafer 30 can use internal planar members 72, 74 to reduce impedance in the signal transmission lines, traces or paths 32, minimize noise resonance and improve connector performance.

[0026] In other embodiments, the inner conductive planar members 72, 74 may be located in other locations and may be used for different purposes, such as, but not limited to, multiple voltage planes.

[0027] The multi-layer stripline wafer 30 has a larger copper volume than known grounded coplanar waveguides. The larger copper volume allows the multi-layer stripline wafer 30 to be an effective heat sink, allowing more current to flow across the wafer 30 while maintaining a temperature equal to or lower than that of a grounded coplanar waveguide wafer.

[0028] Although the exemplary embodiment shown in Figures 2-8 has been described in detail, the multilayer stripline wafer 30 can have a variety of configurations. For example, as shown in Figure 11, the multilayer stripline wafer 30 can have a top ground plane 70' and a bottom ground plane 76' with wiring layers 72', 74' disposed therebetween for high-speed signal integrity. Another example shown in Figure 12 illustrates a multilayer stripline wafer 30 having conductive surface layers, such as, but not limited to, copper surface layers, on all layers 70", 72", 74", 76" to accommodate high current / power transmission throughout the multilayer stripline wafer. Furthermore, as previously mentioned, the signal transmission lines, traces, or paths 32 on any of these layers can be single-ended or differentially coupled transmission lines, traces, or paths.

[0029] Additionally, stripline signal transmission lines, traces, or paths 32 are significantly less susceptible to noise than prior art grounded coplanar waveguide wafers. In ultra-high speed applications, noise is one of the major factors that degrade performance. Because stripline signal transmission lines, traces, or paths 32 can be designed to be narrow, stripline signal transmission lines, traces, or paths 32 can be spaced far enough apart to substantially eliminate electromagnetic coupling. This dramatically reduces near-end crosstalk (NEXT) and far-end crosstalk (FEXT). Stripline signal transmission lines, traces, or paths 32 also have a high tolerance to FEXT. The equation for FEXT can be as follows: In a stripline configuration, the mutual inductance and inductance per unit length are the same, and the mutual capacitance and capacitance per unit length are the same. This means that in a stripline configuration, the terms in the parentheses are zero. Therefore, there should be no FEXT in the region where the stripline signal transmission lines, traces, or paths 32 couple. Figure 10 shows a comparison between two simulated wafers with five pairs. The graph shows that the stripline wafer 30, represented by plot 86, has significantly lower FEXT compared to the known grounded coplanar waveguide wafer, represented by plot 88. The stripline configuration of the present invention also reduces electromagnetic interference (EMI) compared to the prior art grounded coplanar waveguide wafer.

[0030]

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[0031] The multi-layer stripline wafer 30 allows for versatility and a variety of routing options for isolating the stripline signal transmission lines, traces, or paths 32 from one another. For example, in various embodiments, transmit signals can be routed on one layer and receive signals on another layer. In another embodiment, ground planes can be placed between layers to isolate them from one another. In another embodiment, multiple voltage planes can be used within the same wafer, as shown in FIG. 8. For example, the first inner planar member 70 can be used for, but is not limited to, 12 volts, and the second inner planar member 72 can be used for, but is not limited to, 24 volts. In another embodiment, the ground return and power return can be designed into the same wafer. In another embodiment, three different voltage planes and three ground return planes may be provided on a six-layer wafer. In another exemplary embodiment, stripline signal transmission lines, traces, or paths may be routed on layer 2, with layers 1 and 4 used as ground references, allowing the stripline signal transmission lines, traces, or paths to be wider and less lossy. Many other wafer configurations may also be used. These are some of the many applications in which stripline wafers can be used, although none of these applications can be realized with grounded coplanar waveguide wafers.

[0032] Because stripline wafers are thicker than known grounded coplanar waveguide wafers, stripline wafers are more durable. This allows for the inclusion of slots 80 in the stripline wafer 30. As shown in FIG. 9 , the slots 80 extend from the mating interface 46. The slots 80 are aligned and cooperate with stiffening members or ribs 82 on the backplane connector 42. The stiffening members 82 reinforce the backplane connector 42, allowing it to be more robust. When the daughtercard connector 44 is inserted into the backplane connector 42, the stiffening members 82 are inserted into the slots 80. The stiffening members 82 cooperate with the slots 80 to properly position and align the daughtercard connector 44 with the backplane connector 42. The slots 80 and stiffeners 82 act as a key to ensure precise alignment between the conductive pads 52 of the stripline wafer 30 of the daughtercard connector 44 and the signal contacts 20 of the backplane connector 42 .

Claims

1. 1. A multi-layer stripline wafer for use in an electrical connector, said multi-layer stripline wafer comprising: A plurality of layers; a signal transmission path disposed in at least one inner layer of the plurality of layers; a conductive planar member disposed on one or more of the plurality of layers, the conductive planar member being spaced apart from the signal transmission path; Equipped with A multi-layer stripline wafer, wherein one or more conductive planar members control the impedance of the signal transmission path.

2. 2. The multi-layer stripline wafer of claim 1, wherein the signal transmission paths are single-ended signal transmission paths that are separated from one another to maintain a non-coupled state.

3. The multi-layer stripline type wafer of claim 1 , wherein the signal transmission paths are differentially coupled signal transmission paths.

4. The multi-layer stripline wafer of claim 1 , wherein the multi-layer stripline wafer is a printed circuit board.

5. 10. The multi-layer stripline wafer of claim 1, wherein the signal transmission paths have conductive pads positioned proximate to but spaced from a mating interface of the wafer, and floating pads extend between the conductive pads and the mating interface.

6. 6. The multi-layer stripline wafer of claim 5, wherein the floating pad is capacitively coupled to an internal ground plane of the multi-layer stripline wafer and to a beam region of a mating contact.

7. The multi-layer stripline wafer of claim 1 , wherein a first ground plane member extends across the first side of the wafer.

8. 8. The multi-layer stripline wafer of claim 7, wherein openings are provided in the first ground plane member to expose the signal conductive pads.

9. 6. The multi-layer stripline wafer of claim 5, wherein a second ground plane member is disposed on one of the one or more layers that is disposed proximate to the floating pad.

10. The multi-layer stripline wafer of claim 1 , wherein the signal transmission paths are length-matched for skew compensation.

11. The multi-layer stripline wafer of claim 2 , wherein the transmission paths are narrowed to allow for increased wiring density.

12. The multi-layer stripline wafer of claim 1 , wherein the multi-layer stripline wafer comprises at least one internal conductive planar member.

13. The multi-layer stripline wafer of claim 12 , wherein at least one of the interior conductive planar members is disposed in a beam-receiving region of the multi-layer stripline wafer.

14. 13. The multi-layer stripline wafer of claim 12, wherein at least one of the interior conductive planar members is a ground planar member.

15. The multi-layer stripline wafer of claim 12 wherein at least one of the interior conductive planar members is a voltage planar member.

16. 3. The multi-layer stripline wafer of claim 2, wherein the single-ended signal transmission path is routed between two layers of the conductive planar member.

17. 10. The multi-layer stripline wafer of claim 1, wherein slots extend from a mating interface of the multi-layer stripline wafer, the slots configured to interact with stiffening members of a mating connector to achieve precise alignment between the multi-layer stripline wafer and the mating connector.

18. 10. The multi-layer stripline wafer of claim 1, wherein the conductive planar member includes ground stitching vias disposed along the routing of signal transmission lines, traces or paths to further facilitate noise reduction.

19. 10. The multi-layer stripline wafer of claim 1, wherein the conductive planar member is a ground plane member that functions as a heat sink for high current applications.

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