Passivation of metal structures in harsh environments

Abstract

A method for manufacturing a semiconductor structure includes the steps of: providing a substrate; forming an active region within the substrate; depositing and patterning a metal layer to form metal lines and one or more contacts connected to the active region; depositing a silicon oxide layer by PECVD (plasma-enhanced chemical vapor deposition) to cover at least a portion of the metal layer; and depositing a silicon nitride layer by low-pressure chemical vapor deposition (LPCVD) to cover at least a portion of the silicon oxide layer.

Description

Technical Field

[0001] The present invention relates to the passivation of metal structures in harsh environments, particularly passivation in semiconductor and MEMS structures.

Background Art

[0002] The passivation of metal structures, typically aluminum-based, is performed using silicon nitride. Silicon nitride may be required as a moisture barrier and a barrier in the passivation system. Conventionally, nitrides are deposited using plasma enhanced chemical vapor deposition (PECVD). This is because the process is performed at low temperature and thus has high compatibility with metal systems commonly used in microsystem technology to avoid diffusion and alloy formation.

Summary of the Invention

[0003] Aspects of the present invention provide semiconductor structures and methods of formation as described in the appended claims.

[0004] Embodiments of the present invention are described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0005] [Figure 1] Shows a schematic cross-section of at least a portion of a semiconductor structure according to one embodiment. [Figure 2] Shows a schematic cross-section of at least a portion of a semiconductor structure according to another embodiment including a noble metal. [Figure 3] Shows a schematic cross-section of at least a portion of a semiconductor structure according to one embodiment arranged for use in a harsh environment. [Figure 4] Is a flowchart showing steps of a method of forming a semiconductor structure according to one embodiment.

Mode for Carrying Out the Invention

[0006] Traditionally, PECVD nitride coatings have been used as passivation layers to protect underlying metal structures from corrosion. The disadvantages of PECVD nitride coatings are as follows: relatively low chemical stability; relatively high defect density within the layer (for example, the layer may contain a high density of so-called "pinholes"); and a very thick layer is required to achieve adequate passivation properties.

[0007] Under extreme operating conditions (high temperature, chemically aggressive substances, high pressure), the PECVD nitride layer can be damaged, allowing corrosive media and ions to penetrate the microsystem or IC, ultimately leading to system failure.

[0008] The embodiments described herein provide protection for integrated circuits and / or micromechanical structures (also referred to herein as MEMS structures), thereby enabling them to be used in aggressive / harsh environments or to be further processed by the use of aggressive chemicals such as etchants. Protection may be provided by high-density silicon nitride deposited by LPCVD (low-pressure chemical vapor deposition) with high chemical resistance. This is due to the strong bonding of silicon nitride molecular structures resulting from deposition from the gas phase at high temperatures (e.g., above 600°C). Several embodiments may be particularly suitable as sensors (e.g., pressure and / or temperature sensors) for harsh environments (e.g., in fuel, combustion engine exhaust systems, or in hot oil).

[0009] LPCVD is a process for depositing layers onto a substrate (typically a semiconductor substrate such as silicon). It is a chemical process performed at high temperature and reduced pressure. The temperature range for LPCVD is 500°C to 1000°C, and the pressure of the LPCVD process is in the range of 0.01 mbar to 10 mbar. The temperature during the deposition process provides energy for the chemical reactions of several gases that form the material being deposited. This reduced pressure assists the actual deposition process on the substrate surface and prevents the generation of particles in the internal space of the deposition furnace. To deposit silicon nitride, ammonia and dichlorosilane are reacted with the silicon nitride, which is formed as a high-density layer on the wafer surface. The chemical reaction depends on the actual deposition temperature and pressure and is not always perfectly stoichiometric.

[0010] Traditionally, high temperatures (e.g., >600°C) have been considered too high to use for depositing LPCVD silicon nitride at the end of the manufacturing process (wafer process) for integrated circuits or micromechanical structures. If LPCVD deposition is implemented without special additional measures, the metallized structures of the back-end-of-line wiring process, which ultimately need to be protected for their application, can be destroyed by temperature-related diffusion and alloying. The same applies to contacts between silicon structures and metals, which can be damaged by alloying at high deposition temperatures and long process times.

[0011] The embodiments described herein can solve at least some of these problems by providing an industrially applicable process for depositing high-density LPCVD silicon nitride on pre-processed integrated circuits and micromechanical structures, including metallization, without adverse effects on the metal during the deposition of the LPCVD nitride layer. The integrated circuits and micromechanical structures thus protected can be used safely and with long-term stability under the most extreme conditions, such as those common in exhaust systems or high-temperature media (e.g., oil).

[0012] Conventional PECVD (plasma-enhanced chemical vapor deposition) silicon nitride or silicon oxide layers (and combinations thereof) deposited at temperatures below 450°C may not provide this protection due to weak internal bonding ratios and layer defects (e.g., pinholes) that occur in this type of deposition. Furthermore, LPCVD layers can be thinner than PECVD layers and offer even better protection, resulting in a significant reduction in mechanical stress, particularly on micromechanical structures (lower thermomechanical stress). The thin thickness and characteristics of the LPCVD deposition process (batch process with parallel deposition on up to 200 wafers) also enable more economical processing.

[0013] In addition to improved protection against aggressive operating conditions, the arrangement of a layer with a embedded metal can also be used, for example, as an etching mask for etching silicon in a high-temperature potassium hydroxide (KOH) solution. Subsequently, the LPCVD silicon nitride layer can also provide the necessary protection against the embedded metal.

[0014] The LPCVD deposition temperature can range from 500°C to 750°C. Preferably, deposition temperatures above 600°C are used to provide sufficiently improved protection. The specific deposition temperature is determined by additional target layer parameters (mechanical layer stress, residual conductivity, etc.). The entire structure to be protected must withstand this deposition temperature of the LPCVD nitride layer. This applies particularly to metallization and silicon structures and their contacts. Furthermore, the metallic structure should be prevented from oxidizing when the wafer is introduced into the LPCVD system. Here, high temperatures are already prevalent due to the process, and in the presence of oxygen in the air, this can lead to undesirable and significant oxidation of the metal. Therefore, several embodiments may consist of special layer systems produced in a special process sequence such that the protective LPCVD layer is produced as the final layer (top passivation layer).

[0015] Compared to conventional PECVD nitrides, LPCVD nitride layers have a denser structure, fewer impurities from the formation process, and are closer to the stoichiometric ratio of Si3N4, making them more chemically stable. Furthermore, LPCVD nitride layers exhibit higher thermal and mechanical stability during the wiring-to-equipment (BEOL) and assembly processes. This makes it possible to distinguish nitride layers deposited by LPCVD from nitride layers formed by other processes (e.g., PECVD).

[0016] According to one embodiment, this method includes the following process sequence. a) Use of temperature-stable metals (e.g., including tungsten) and, optionally, chemically very stable metals (e.g., including gold or platinum) as conductive path materials and (wire) bond pads. Specifically, deposit and photolithography patterning of the metal or lift-off patterning of the metal is performed on an integrated circuit or micromechanical structure. The metal is typically a metal layer stack comprising a first metal, an adhesive layer and a diffusion barrier layer. For example, the stable metal may be a metal layer stack comprising tungsten, titanium (Ti), and titanium nitride (TiN), where Ti is the adhesive layer and TiN is the diffusion barrier layer. Alternatively, instead of the Ti-based adhesive and barrier layers, the metal layer stack may include tantalum (Ta)-based layers in combination with, for example, chromium (Cr) and nickel (Ni). In some embodiments, tungsten can be replaced with, for example, aluminum (Al) or gold (Au). b) The metal is coated with a PECVD silicon oxide layer. This deposition can be carried out at low temperatures (e.g., below 450°C) and in a complete vacuum (e.g., <1 Torr). Since the entire deposition process is carried out in a vacuum, the risk of metal oxidation is eliminated or significantly reduced. c) The PECVD silicon oxide is densified and annealed at a temperature higher than the subsequent LPCVD nitride deposition temperature (e.g., in the range of 800°C to 1000°C). Steps b) and c) form a very high-density, high-temperature stable silicon oxide layer, which acts as effective oxidation protection during subsequent LPCVD nitride deposition, especially when the wafer is placed in the corresponding apparatus. Densification can reduce the thickness of the PECVD silicon oxide layer by 10% to 40%. The PECVD layer is thick enough to protect the metal layer during densification and prevent the diffusion of origin when handling the wafer in the furnace. A nitrogen atmosphere is used in the furnace. d) Deposit LPCVD nitride at high temperatures (e.g., above 600°C). c) Form contacts or openings for bond pads to the top metal layer. These contacts are preferably resistant to aggressive / harsh media or are positioned so as not to come into direct contact with aggressive media during use.

[0017] Because the overall temperature budget can be kept low, significant or critical alloy formation does not occur at electrical contacts, especially with single-crystal and polycrystalline silicon. This means that the deposition temperature and process time can be adjusted as appropriate. This is made possible, in particular, by the fact that even very thin PECVD oxide layers and very thin LPCVD nitride layers provide very good protection.

[0018] The PECVD oxide layer is typically a TEOS layer. The TEOS layer is a silicon oxide layer deposited using a PECVD process with TEOS tetraethyl orthosilicate, also known as tetraethoxysilane, as the reaction gas or precursor. At medium temperatures (e.g., 300°C to 450°C), the plasma output converts the TEOS gas to SiO2 via several intermediate states, forming a layer on the substrate. This layer is not very dense. All silicon oxide layers and the SiO2 tetraeters forming the glass are relatively far apart, and not all oxygen atoms are bonded to adjacent tetraeters. Hydrogen atoms and organic residues (at the molecular level) are present between the tetraeters. This makes the deposited TEOS oxide layer rather unstable. In densification bakes at temperatures in the 800 to 1000°C range, hydrogen and organic residues are degassed, and the SiO2 tetraeters bond directly to each other (via oxygen atoms). This results in a structure with a density nearly identical to that of fused silica or thermally grown oxides. This means that the TEOS oxide layer is much denser and has much better properties (chemically and mechanically). The densification process reduces the thickness of the TEOS oxide layer. The TEOS layer may be doped (i.e., containing a doped precursor) or undoped. In doped TEOS, boron and / or phosphorus are added. In other embodiments, the PECVD layer may be silane-based.

[0019] Multiple embodiments may include structures for protecting the metal structure and / or micromechanical structure of an integrated circuit from aggressive media / environments, comprising a protected metal structure (single or multilayer), a high-density PECVD silicon oxide layer, and a final LPCVD silicon nitride layer.

[0020] The semiconductor structure may be formed by photolithography or by lift-off (monolayer or multilayer) deposition and structure formation of a high-temperature stable, and possibly chemically stable, metal. As a process performed entirely in vacuum, a silicon oxide layer is deposited at a low temperature (e.g., below 450°C) by PECVD. This method further includes densifying this PECVD oxide layer at a temperature higher than the subsequent LPCVD deposition temperature, preparing this layer for subsequent higher temperatures, and LPCVD nitride deposition at a temperature above 600°C to achieve a high-density, protective silicon nitride layer. Furthermore, this method may include openings for contact or bond pads to the upper metal layer.

[0021] This process can have a low temperature budget due to its low annealing time and low layer thickness, in order to avoid significant alloy formation in metal contact with single-crystal or polycrystalline silicon. In some applications, it may be necessary to etch the silicon to release the mechanical structure by undercut etching with a highly aggressive wet chemical (e.g., KOH or TMAH) that would attack the metal. The metal may then be embedded, and the LPCVD nitride layer may be used as a masking layer for wet etching.

[0022] FIG. 1 shows a schematic cross-section of at least a part of a semiconductor structure 2, which may be part of a sensor for harsh environments. The structure 2 has a silicon substrate 4 having an active region 6 that includes elements of an integrated circuit or a microelectromechanical system (MEMS) structure. The active region 6 typically includes doped regions that form semiconductor devices of an integrated circuit or a micro-mechanical structure. An intermediate insulator layer 8 is disposed on the substrate 4 and is arranged to electrically insulate the metal layer 10 from the substrate 4. The metal layer 10 includes metal lines connected to the active region 6 via contacts 12. A PECVD silicon oxide layer 14 covers the metal layer 10. A passivation layer, which is an LPCVD nitride layer 16, covers the oxide layer 14. Openings 18 in the PECVD oxide layer 14 and the LPCVD nitride layer 16 provide access to the metal layer 10. An external wire (not shown) may be directly bonded to the metal layer 10 within the openings 18 to provide input and output signals. For example, the external wire may be soldered to the metal layer 10 or bonded in other ways to provide an electrical connection to the metal layer 10.

[0023] Figure 2 shows a schematic cross-sectional view of at least a portion of another semiconductor structure 2. For the sake of understanding, the same reference numerals are used in different figures for the same or similar features and are not intended to limit the illustrated embodiments. Structure 2 has a silicon substrate 4 having an active region 6 containing elements of an integrated circuit or micromechanical structure. The active region 6 typically includes a doped region that forms a semiconductor device of an integrated circuit or micromechanical structure. An intermediate insulator layer 8 is placed on the substrate 4 and is positioned to electrically insulate the substrate 4 from the metal layer 10. The metal layer 10 includes metal lines connected to the active region 6 via contacts 12. A PECVD silicon oxide layer 14 covers the metal layer 10. A passivation layer, which is an LPCVD nitride layer 16, covers the oxide layer 14. Openings 18 in the PECVD oxide layer 14 and the LPCVD nitride layer 16 provide access to the metal layer 10. To provide additional protection, a noble metal layer 20 is placed within the openings 18. The noble metal layer 20 may include, for example, gold or platinum. For example, the precious metal layer may provide improved chemical protection and prevent oxidation or other degradation of the metal layer 10, which would otherwise be exposed by the opening 18. External wires (not shown) may be joined to the precious metal layer 20 within the opening 18 to provide input and output signals. For example, the external wires may be soldered to the precious metal layer 20 or otherwise joined to provide an electrical connection to the metal layer 20.

[0024] FIG. 3 shows a schematic cross-sectional view of a part of another semiconductor structure 2, such as sensors for sensing in a harsh environment 22. The structure 2 has a silicon substrate 4 having an active region 6 that includes elements of an integrated circuit or a micro-mechanical structure. The active region 6 typically includes doped regions that form semiconductor devices of an integrated circuit or a micro-mechanical structure. An intermediate insulator layer 8 is disposed on the substrate 4 and is arranged to electrically insulate the metal layer 10 from the substrate 4. The metal layer 10 includes metal lines connected to the active region 6 via contacts 12. A PECVD silicon oxide layer 14 covers the metal layer 10. A passivation layer, which is an LPCVD nitride layer 16, covers the oxide layer 14. Openings 18 in the PECVD oxide layer 14 and the LPCVD nitride layer 16 provide access to the metal layer 10 outside the harsh environment 22. A portion 23 of the structure 2 that is exposed to the harsh environment 22 includes a continuous passivation layer 16a to completely cover the metal layer 10 within the harsh environment 22. A wire 24 is bonded to the metal layer 10 within the opening 18. The wire 24 can be arranged to provide input and / or output signals to an integrated circuit or a micro-mechanical system within the active region 6. The openings 18 and the wire 24 are shielded from the harsh environment by a containment structure 26 that includes a lid 28 and a seal 30 between the semiconductor structure 2 and the lid 28. For example, the harsh environment 22 may include high-temperature oil 25 contained by the containment structure 26, and the semiconductor structure 2 may be a pressure sensor for measuring the pressure within the high-temperature oil 25.

[0025] The substrate 4 may include a plurality of semiconductor layers, such as a bulk silicon layer (also referred to as a handling wafer) and an active layer (e.g., an epitaxial silicon layer) for forming semiconductor devices by doping.

[0026] Figure 4 shows a flowchart of a method for forming a semiconductor structure. This method includes the steps of: providing a substrate (S1, e.g., silicon); forming an active region within the substrate (S2, the active region may include an integrated circuit or MEMS structure); providing an insulating layer (e.g., silicon oxide) on the substrate and structuring the insulating layer to provide openings in the substrate (S3); and depositing and patterning a metal layer (e.g., tungsten) to form metal lines and one or more contacts connected to the active region (S4). Further layers, including adhesive layers and diffusion barrier layers, are also typically deposited to form a metal layer stack. This method further includes the steps of: depositing a silicon oxide layer on the metal layer by plasma-enhanced chemical vapor deposition (PECVD) (S5); densifying the silicon oxide layer by high-temperature annealing (S6); and depositing a silicon nitride layer on the silicon oxide layer by low-pressure chemical vapor deposition (LPCVD) (S7). The method further includes the step of structuring oxide and nitride layers to form contact openings in a metal layer (S8). Typically, the PECVD and LPCVD layers are etched to provide one or more openings in the metal layer so that they can be electrically connected to a semiconductor structure. The method further includes the step of providing a second (upper) metal layer for electrical connection to the metal layer (S9).

[0027] Generally, embodiments described herein may provide a semiconductor structure comprising a substrate, an active region within the substrate, a metal layer including metal lines and one or more contacts connected to the active region, a plasma-enhanced chemical vapor deposition (PECVD) silicon oxide layer disposed on the metal layer, and a low-pressure chemical vapor deposition (LPCVD) silicon nitride layer disposed on the PECVD silicon oxide layer. The semiconductor structure may be part of a sensor, such as a pressure sensor, suitable for use in harsh environments (at high temperatures and / or in contact with corrosive media). The structure typically includes an insulating layer between the substrate and the metal layer, the insulating layer including an opening for the metal layer to electrically connect to the active region.

[0028] The LPCVD silicon nitride layer may be formed at temperatures above 600°C to improve its protective properties. For example, the LPCVD silicon nitride layer may be formed at temperatures in the range of 600°C to 750°C.

[0029] The LPCVD silicon nitride layer may have a thickness ranging from approximately 0.1 μm to 1 μm. Preferably, the LPCVD silicon nitride layer has a thickness of less than 0.5 μm. The relative thinness of the passivation layer allows for a lower thermal budget and can protect the structure from degradation during manufacturing (e.g., due to diffusion or alloying).

[0030] The PECVD silicon oxide layer may have a thickness ranging from about 0.2 μm to 2 μm. Preferably, the PECVD silicon oxide layer has a thickness of less than 1 μm. Similarly, relative thinness allows for a lower thermal budget. The initially deposited oxide layer may have a greater thickness, which is reduced in the subsequent process step of densification annealing. The PECVD silicon oxide layer may be a TEOS layer, for example, a densified TEOS layer. The TEOS layer may be doped or undoped. Alternatively, the PECVD silicon oxide layer may be a silane-based oxide layer. Typically, the PECVD layer is formed directly on the metal layer, but in other embodiments, an intermediate layer may be present.

[0031] The active region may include at least a portion of a micro-electromechanical system (MEMS) structure, and the metal layer provides input and output to the MEMS structure. For example, the MEMS structure may be part of a sensor, such as a pressure sensor, for use in harsh environments. The pressure signal may be output from a semiconductor structure. For example, the active region may be formed by doping and / or patterning a silicon substrate.

[0032] The active region may include at least a portion of an integrated circuit (IC). The metal layer provides inputs and outputs to the IC. The active region may also include semiconductor devices such as transistors formed within the active region and connected to the metal layer.

[0033] Typically, the metal layer is made from a durable metal suitable for harsh environments. For example, the metal layer may contain tungsten. The metal layer may also be part of a metal layer stack that further includes an adhesive layer (e.g., Ti) and a diffusion barrier layer (e.g., TiN).

[0034] The PECVD silicon oxide layer and the LPCVD silicon nitride layer may include one or more openings for forming electrical connections with the metal layer. For example, the LPCVD layer may cover at least 90% of the surface area of ​​the metal layer. The structure may include a noble metal layer (e.g., gold or platinum) on the metal layer within the openings, which may further protect the metal layer in areas where the passivation layer is removed. Thick metallization may provide connections to the metal layer through the openings in the PECVD and LPCVD layers.

[0035] Other embodiments provide sensors (e.g., pressure and / or temperature sensors) that include the semiconductor structure described above.

[0036] Further embodiments provide a method for manufacturing a semiconductor structure. This method includes the steps of providing a substrate, forming an active region on the substrate (for example, by doping and / or patterning the substrate), and depositing and patterning a metal layer to form metal lines and one or more contacts connected to the active region. This method further includes the steps of depositing a silicon oxide layer on the metal layer by plasma-enhanced chemical vapor deposition (PECVD), which may be followed by a densification bake, and depositing a silicon nitride layer on the silicon oxide layer by low-pressure chemical vapor deposition (LPCVD). This method may also include the steps of depositing an insulating layer on the substrate before depositing the metal layer, and structuring the insulating layer to provide openings for the metal layer to electrically connect to the active region.

[0037] The step of depositing the silicon oxide layer may include depositing at a temperature below 450°C. Lower deposit temperatures help prevent oxidation of the metal layer and other structural degradation.

[0038] Preferably, deposition is carried out in a vacuum to prevent contamination or oxidation. For example, the step of PECVD deposition of a silicon oxide layer may include deposition at a pressure of less than 1 Torr. After deposition, densification may be performed. For example, the method may include densifying and annealing the silicon oxide layer before deposition of the silicon nitride layer. Densification increases the density and decreases the thickness of the PECVD silicon oxide layer. Densifying and annealing may include annealing at a temperature higher than the subsequent LPCVD deposition temperature, for example, in the range of 800°C to 1000°C.

[0039] The step of depositing the silicon nitride layer may include depositing at a temperature higher than 600°C. For example, the step of depositing the silicon nitride layer may include depositing at a temperature in the range of 600°C to 750°C. Deposition may be carried out at a pressure in the range of 0.01 mbar to 10 mbar.

[0040] Optionally, the step of depositing the PECVD silicon oxide layer may include depositing with tetraethyl orthosilicate (TEOS), with or without a doped precursor. The TEOS layer can particularly benefit from densification. Alternatively, the step of depositing the PECVD silicon oxide layer may include depositing with silane.

[0041] While specific embodiments have been described, it will be apparent to those skilled in the art that modifications can be made to the described embodiments without departing from the claims. Each feature disclosed or illustrated herein can be incorporated into an embodiment, either alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

1. A method for manufacturing a semiconductor structure, The steps include providing a substrate and The steps include forming an active region within the substrate, The steps include depositing and patterning a metal layer to form a metal line connected to the active region and one or more contacts, The steps include: depositing a silicon oxide layer by PECVD (plasma-enhanced chemical vapor deposition) so as to cover at least a portion of the metal layer; The steps include: depositing a silicon nitride layer by LPCVD (low-pressure chemical vapor deposition) so as to cover at least a portion of the silicon oxide layer; Methods that include...

2. The method according to claim 1, wherein the step of depositing the silicon oxide layer includes depositing it at a temperature of less than 450°C.

3. The method according to claim 1 or 2, wherein the step of depositing the silicon oxide layer includes depositing it at a pressure of less than 1 Torr.

4. The method according to any one of claims 1 to 3, further comprising the step of densifying and annealing the silicon oxide layer before depositing the silicon nitride layer.

5. The method according to claim 4, wherein the step of densifying and annealing reduces the thickness of the silicon oxide layer by PECVD by 10% to 40%.

6. The method according to claim 4 or 5, wherein the densification annealing step includes annealing at a temperature in the range of 800°C to 1000°C.

7. The method according to any one of claims 1 to 6, wherein the step of depositing the silicon nitride layer includes depositing it at a temperature exceeding 600°C.

8. The method according to any one of claims 1 to 7, wherein the step of depositing the silicon nitride layer includes depositing it at a temperature in the range of 600°C to 750°C.

9. The method according to any one of claims 1 to 8, wherein the step of depositing the silicon nitride layer includes depositing it at a pressure in the range of 0.01 mbar to 10 mbar.

10. The method according to any one of claims 1 to 9, wherein the step of depositing the silicon oxide layer by PECVD is carried out using tetraethyl orthosilicate (TEOS).

11. The method according to any one of claims 1 to 10, wherein the step of depositing the silicon oxide layer by PECVD includes depositing it using silane.

12. The method according to any one of claims 1 to 11, further comprising the step of depositing an insulating layer on the substrate and structuring the insulating layer such that it provides an opening for the metal layer to electrically connect to the active region.

13. circuit board and The active region within the substrate, A metal layer including a metal line connected to the active region and one or more contacts, A PECVD (plasma-enhanced chemical vapor deposition) silicon oxide layer covering at least a portion of the metal layer, An LPCVD (low-pressure chemical vapor deposition) silicon nitride layer covering at least a portion of the PECVD silicon oxide layer and A semiconductor structure comprising the features described above.

14. The semiconductor structure according to claim 13, wherein the LPCVD silicon nitride layer is formed at a temperature of 600°C or higher.

15. The semiconductor structure according to claim 13 or 14, wherein the LPCVD silicon nitride layer is formed at a temperature in the range of 600°C to 750°C.

16. The semiconductor structure according to any one of claims 13 to 15, wherein the LPCVD silicon nitride layer has a thickness in the range of 0.1 μm to 1 μm.

17. The semiconductor structure according to any one of claims 13 to 16, wherein the PECVD silicon oxide layer has a thickness in the range of 0.2 μm to 2 μm.

18. The semiconductor structure according to any one of claims 13 to 17, wherein the PECVD silicon oxide layer is a TEOS layer.

19. The semiconductor structure according to any one of claims 13 to 18, wherein the PECVD silicon oxide layer is a silane-based oxide layer.

20. The semiconductor structure according to any one of claims 13 to 19, wherein the PECVD silicon oxide layer is a densified oxide layer.

21. The active region includes at least a part of a MEMS (micro-electromechanical system) structure or an IC (integrated circuit), The semiconductor structure according to any one of claims 13 to 20, wherein the metal layer provides input and output to the MEMS structure or IC.

22. The semiconductor structure according to any one of claims 13 to 21, wherein the metal layer contains tungsten.

23. The semiconductor structure according to any one of claims 13 to 22, wherein the PECVD silicon oxide layer and the LPCVD silicon nitride layer include one or more openings for forming an electrical connection with the metal layer.

24. An insulating layer is further provided between the substrate and the metal layer, The semiconductor structure according to any one of claims 13 to 23, wherein the insulating layer includes an opening for the metal layer to electrically connect to the active region.

25. A sensor comprising the semiconductor structure described in any one of claims 13 to 24.

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