Manufacturing of high aspect ratio electronic devices with minimal sidewall spacer loss.

Abstract

The method includes forming a planarization layer to a position lower than the transistor device region above the base structure of an electronic device and higher than the transistor device region below the base structure. The base structure includes several features. The method further includes forming a spacer material along the base structure and the planarization layer, modifying the spacer material formed along the bottom trench of the base structure to obtain a modified spacer material, and forming a spacer layer by removing the modified spacer material using a wet etching process. Modifying the spacer material formed along the bottom trench of the base structure to obtain a modified spacer material includes performing a dry etching process targeting the spacer material formed along the bottom trench of the base structure.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the manufacture of electronic devices. Specifically, embodiments of the present disclosure relate to the manufacture of high aspect ratio electronic devices with minimized loss of sidewall spacers.

Background Art

[0002] An electronic device manufacturing apparatus may include a plurality of chambers such as a process chamber and a load lock chamber. Such an electronic device manufacturing apparatus can use a robot device in a transfer chamber configured to transfer a substrate between the plurality of chambers. In some examples, a plurality of substrates are transferred together. The process chamber may be used within an electronic device manufacturing apparatus to perform one or more processes such as a deposition process and an etching process on a substrate. For many processes, gas is flowed into the process chamber. Electronic devices such as semiconductor devices are manufactured by performing a series of operations that may include deposition, oxidation, photolithography, ion implantation, etching, etc. to form many patterned layers.

Summary of the Invention

[0003] According to one embodiment, a method is provided. The method includes forming a planarization layer to a position lower than the upper transistor device region of the base structure of an electronic device and higher than the lower transistor device region of the base structure. The base structure includes a plurality of features. The method further includes forming a spacer material along the base structure and the planarization layer, modifying the spacer material formed along the bottom trench of the base structure to obtain a modified spacer material, and forming a spacer layer by removing the modified spacer material using a wet etching process. Modifying the spacer material formed along the bottom trench of the base structure to obtain a modified spacer material includes performing a dry etching process targeting the spacer material formed along the bottom trench of the base structure.

[0004] According to another embodiment, a method is provided. The method comprises obtaining a base structure for an electronic device having an upper transistor device region and a lower transistor device region, comprising several features; forming a planarization layer from the base structure to a position lower than the upper transistor device region and higher than the lower transistor device region; forming a spacer material along the base structure and the planarization layer; modifying the spacer material formed along a bottom trench of the base structure to obtain a modified spacer material; forming a spacer layer by removing the modified spacer material using a wet etching process; removing the planarization layer; forming a set of epitaxial layers within the lower transistor device region; and removing the spacer layer. Modifying the spacer material formed along a bottom trench of the base structure to obtain a modified spacer material comprises performing a dry etching process targeting the spacer material formed along the bottom trench of the base structure.

[0005] In the drawings attached to this disclosure, the figures are shown as examples and not as limitations. In these drawings, similar reference numerals refer to similar elements. Different references to “one” embodiment or “one” embodiment in this disclosure do not necessarily refer to the same embodiment, but rather such references mean at least one. [Brief explanation of the drawing]

[0006] [Figure 1A-1D] This is a cross-sectional view illustrating an exemplary method for manufacturing an electronic device according to several embodiments. [Figure 2A-2F] This is a perspective view illustrating an exemplary method for manufacturing an electronic device according to several embodiments. [Figure 3] This is a flowchart illustrating an exemplary method for manufacturing an electronic device according to several embodiments. [Modes for carrying out the invention]

[0007] Embodiments described herein relate to the manufacture of electronic devices with minimized sidewall spacer losses. Some electronic devices may include one or more transistors. Examples of transistors include field-effect transistors (FETs). Spacers may be used during the manufacture of some electronic devices. For example, spacers may be formed to protect the sidewalls of an electronic device while the bottom of the device (e.g., the bottom of a trench) is exposed during processing. More specifically, spacer material may be formed on the sidewalls and bottom surface of a feature, and the portion of the spacer material formed on the bottom surface of the feature may be removed to expose the bottom.

[0008] Some spacers are etched using dry etching processes such as reactive ion etching (RIE). However, radicals and deflection ions generated during the dry etching process can damage the sidewall spacer material. This can be particularly noticeable as the distance between adjacent features (e.g., "critical dimension") decreases and the corresponding aspect ratio increases, according to more advanced technology nodes. The aspect ratio of a feature can be defined as the ratio of the feature's height or depth to its critical dimension. This difficulty can be exacerbated by forming very thin spacers (e.g., less than about 3 nanometers (nm)) on the sidewalls of features. Therefore, due to the radicals and / or deflection ions generated during dry etching processes (e.g., RIE), it is becoming increasingly difficult to fabricate high aspect ratio electronic devices using such dry etching processes by removing bottom spacer material while maintaining the thickness of the spacer material formed on the sidewalls of features.

[0009] To address these and other drawbacks, embodiments described herein can be used to manufacture electronic devices with minimal sidewall spacer loss. Manufacturing an electronic device may include obtaining a base structure, the base structure comprising an upper transistor device region and a lower transistor region. For example, obtaining a base structure may include forming a base structure.

[0010] The base structure may include multiple features. Each feature may have substantially the same height or depth, and pairs of features may be separated by substantially the same limiting dimension. In some embodiments, the electronic device is a high aspect ratio electronic device. More specifically, a high aspect ratio electronic device is an electronic device that includes features having a high aspect ratio with respect to the height or depth of the features and the limiting dimension. In some embodiments, a high aspect ratio is an aspect ratio of about 8:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 10:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 15:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 20:1 or greater. In some embodiments, the limiting dimension is in the range of about 10 nm to about 30 nm. In some embodiments, the limiting dimension is in the range of about 15 nm to about 20 nm.

[0011] In some embodiments, the electronic device includes a three-dimensional (3D) transistor device. In some embodiments, the 3D transistor device is a 3D complementary metal-oxide-semiconductor (CMOS) device. The CMOS device includes a first transistor device having a first type and a second transistor device having a second type complementary to the first type. For example, the CMOS device may include an n-type metal-oxide-semiconductor (NMOS) transistor device and a p-type metal-oxide-semiconductor (PMOS) transistor device. In some embodiments, the NMOS transistor device is an n-type FET (nFET) including a source / drain region formed from an n-type doped semiconductor material and a substrate formed from a p-type doped semiconductor material. In some embodiments, the PMOS transistor device is a p-type FET (pFET) including a source / drain region formed from a p-type doped semiconductor material and a substrate formed from an n-type doped semiconductor material. In some embodiments, the 3D transistor device is a complementary FET (cFET) device. The cFET device includes an upper FET having a first type, which is vertically stacked on a lower FET having a second type complementary to the first type. In this case, the upper and lower FETs share a gate structure. For example, the upper FET may be an nFET and the lower FET may be a pFET. Another example is that the upper FET may be a pFET and the lower FET may be an nFET. An insulating layer can separate the upper and lower FETs. In some embodiments, the upper FET includes a first nanowire and the lower FET includes a second nanowire.

[0012] Manufacturing an electronic device may further include forming a planarization layer. More specifically, the planarization layer may be formed to a position higher than the lower transistor device region and lower than the upper transistor device region. For example, the planarization layer may be formed to a position adjacent to an insulating layer. Forming a planarization layer may include forming the planarization layer material to a certain height higher than the upper transistor device region, and recessing the planarization layer material to a position lower than the upper transistor device region (e.g., adjacent to an insulating layer). In some embodiments, the planarization layer includes a carbon (C) material (e.g., amorphous carbon material). The planarization layer material can be formed using any suitable process. For example, the planarization layer may include a spin-on carbon (SoC) material. In some embodiments, recessing the planarization layer material includes performing a diimide or diazene (H2N2) recess.

[0013] Manufacturing an electronic device may further include forming a spacer layer on a base structure. More specifically, forming a spacer layer may include conformally depositing spacer material along the upper transistor device region up to a planarization layer. The spacer material can uniformly cover the sidewalls of multiple features and the bottom of trenches in the base structure. In some embodiments, atomic layer deposition (ALD) is used to conformally deposit the spacer material.

[0014] The spacer material may include any suitable dielectric material according to the embodiments described herein. In some embodiments, the spacer material includes a silicon (Si)-based material. For example, the spacer material may include a silicon nitride material. An example of a silicon nitride material is silicon nitride (Si x N yThis includes silicon oxynitride (SiON), silicon oxycarbonite (SiOCN), and the like. The spacer material can be formed to have any suitable thickness. In some embodiments, the spacer layer has a thickness between about 2 nm and about 8 nm. In some embodiments, the spacer layer has a thickness between about 3 nm and about 6 nm.

[0015] Manufacturing an electronic device may further involve performing a two-step etching process to remove spacer material formed along the bottom of a trench. The two-step etching process may include a first step of damaging spacer material formed along the bottom of a trench while minimizing damage to spacer material formed along the side walls of a feature, and a second step of removing spacer material formed along the bottom of a trench while minimizing loss of spacer material formed along the side walls of a feature.

[0016] More specifically, performing a two-step etching process may include modifying the spacer material formed along the bottom of the trench. In some embodiments, modifying the spacer material formed along the bottom of the trench may include using a dry etching process with a plasma etchant. For example, the dry etching process may be an ion bombardment process. Directional high-energy ions can bombard the spacer material formed along the bottom of the trench, and the bombardment damages the spacer material formed along the bottom of the trench. The damage may include physical damage caused by the ion bombardment and / or chemical damage caused by the plasma. Due to the directionality of the ion bombardment against the bottom of the trench, the spacer material formed along the side walls of the feature may suffer relatively little damage. The dry etching process can be performed using any suitable plasma etchant that is non-reactive to the spacer material. For example, the plasma etchant may include one or more non-reactive or inert gas species such as noble gases (e.g., helium (He), neon (Ne), argon (Ar), krypton (Kr), and / or xenon (Xe)), nitrogen gas (N2), etc.

[0017] Performing a two-step etching process may further include using a wet etching process to remove damaged spacer material along the bottom of the trench. In this step, the electronic device is immersed in a wet etchant for a certain amount of time. Damage to the spacer material along the bottom of the trench increases the selectivity of wet etching compared to the spacer material along the side walls of the feature, so that within the amount of time the electronic device is immersed in the wet etchant, only the smallest amount of spacer material along the side walls of the feature is removed. The wet etching process can be performed according to the embodiments described herein using any suitable wet etchant. In some embodiments, the wet etchant contains dilute hydrofluoric acid (dHF). For example, the dHF may have a ratio of 100:1 or greater, and the electronic device can be immersed for about 60 seconds. Thus, a spacer layer is formed after the spacer material has been removed from the bottom of the trench using the wet etching process.

[0018] Manufacturing an electronic device may further involve removing the planarization layer and forming an epitaxial layer within the lower transistor device region. More specifically, the spacer material along the sidewalls of the feature acts to prevent the formation of an epitaxial layer on the upper transistor device region. After forming the epitaxial layer within the lower transistor device region, the remaining spacer material can be removed from the electronic device, allowing for further device processing. Further details regarding manufacturing electronic devices while minimizing sidewall spacer losses are described below with reference to Figures 1A to 3.

[0019] Figures 1A to 1D are cross-sectional views illustrating exemplary methods for manufacturing an electronic device ("device") 100 according to several embodiments. For example, Figure 1A shows the step of obtaining a base structure of device 100. More specifically, device 100 may be a 3D CMOS device, and the base structure may include an upper transistor device region 110-1 corresponding to an upper transistor device having a first type, and a lower transistor device region 110-2 corresponding to a lower transistor device having a second type complementary to the first type. As shown, an insulating layer 120 can separate the upper transistor device region 110-1 and the lower transistor device region 110-2. In some embodiments, the upper transistor device region 110-1 corresponds to an NMOS transistor device, and the lower transistor device region 110-2 corresponds to a PMOS transistor device. In some embodiments, the upper transistor device region 110-1 corresponds to a PMOS transistor device, and the lower transistor device region 110-2 corresponds to an NMOS transistor device. In some embodiments, device 100 includes a cFET device, in which case the NMOS transistor device is an nFET and the PMOS transistor device is a pFET. In some embodiments, the upper transistor device region 110-1 includes a first nanowire and the lower transistor device region 110-2 includes a second nanowire. In some embodiments, obtaining a base structure includes forming a base structure.

[0020] As will be described in more detail below with reference to Figure 2, the base structure may include multiple features. Each feature may have substantially the same height or depth, and pairs of features may be separated by substantially the same limiting dimension. In some embodiments, device 100 is a high aspect ratio electronic device. More specifically, each feature may have a high aspect ratio with respect to the feature's height or depth and limiting dimension. In some embodiments, a high aspect ratio is an aspect ratio of about 8:1 or higher. In some embodiments, a high aspect ratio is an aspect ratio of about 10:1 or higher. In some embodiments, a high aspect ratio is an aspect ratio of about 15:1 or higher. In some embodiments, a high aspect ratio is an aspect ratio of about 20:1 or higher. In some embodiments, the limiting dimension is in the range of about 10 nm to about 30 nm. In some embodiments, the limiting dimension is in the range of about 15 nm to about 20 nm.

[0021] Figure 1B shows the step of forming the planarization layer 130 to a position lower than the upper transistor device region 110-1 and higher than the lower transistor device region 110-2. More specifically, the planarization layer 130 can be formed to a position adjacent to the insulating layer 120. Forming the planarization layer 130 may include forming the planarization layer material to a certain height higher than the upper transistor device region 110-1, and recessing the planarization layer material to a position lower than the upper transistor device region 110-1 and higher than the lower transistor device region 110-2 (e.g., adjacent to the insulating layer 120). In some embodiments, the planarization layer 130 includes a carbon (C) material. The planarization layer material can be formed using any suitable process. For example, the planarization layer 130 may include an SoC material. In some embodiments, recessing the planarization layer material includes performing a diimide or diazene (H2N2) recess.

[0022] FIG. 1C shows the step of forming a spacer layer 140 on a base structure. More specifically, forming the spacer layer 140 can include conformally depositing a spacer material up to the planarization layer 120 along the upper transistor device region 110-1. The spacer material can uniformly cover the sidewalls of a plurality of features and the bottom of the trench of the base structure. In some embodiments, ALD is used to conformally deposit the spacer material.

[0023] The spacer material can include any suitable dielectric material according to the embodiments described herein. In some embodiments, the spacer material includes a silicon (Si)-based material. For example, the spacer material can include a silicon nitride material. Examples of silicon nitride materials include silicon nitride (Si x N y ), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc. The spacer material can be formed to have any suitable thickness. In some embodiments, the spacer material is formed to have a thickness between about 2 nm and about 8 nm. In some embodiments, the spacer material is formed to have a thickness between about 3 nm and about 6 nm.

[0024] Forming the spacer layer 140 can further include modifying a portion of the spacer material formed along the bottom surface of the trench of the base structure. In some embodiments, modifying a portion of the spacer material formed along the bottom surface of the trench can include using a dry etching process with a plasma etchant. For example, the dry etching process can be an ion bombardment process. Highly directional energetic ions can impact the spacer material formed along the bottom surface of the trench, and the impact can damage the portion of the spacer material formed along the bottom surface of the trench. The damage can include physical damage caused by the ion bombardment and / or chemical damage caused by the plasma. Due to the directionality of the ion bombardment with respect to the bottom surface of the trench, a portion of the spacer material formed along the sidewalls of the feature can receive a relatively low degree of damage. The dry etching process can be performed using any suitable plasma etchant that is non-reactive with respect to the spacer material. For example, the plasma etchant can include one or more non-reactive or inert gas species such as noble gases (e.g., He, Ne, Ar, Kr, Xe), N2, etc.

[0025] Forming the spacer layer 140 may further include removing damaged spacer material along the bottom of the trench using a wet etching process. In this step, the device 100 is immersed in the wet etchant for a certain amount of time. Damage to the spacer material along the bottom of the trench increases the selectivity of wet etching compared to the spacer material formed along the side walls of the feature, so that within a certain amount of time the electronic device is immersed in the wet etchant, only the smallest amount of spacer material formed along the side walls of the feature is removed. The wet etching process can be carried out according to the embodiments described herein using any suitable wet etchant. In some embodiments, the wet etchant includes dHF. For example, the dHF may have a ratio of at least 100:1 and allow the electronic device to be immersed for about 60 seconds. Thus, the spacer layer 140 is formed after the spacer material has been removed from the bottom of the trench of the base structure using the wet etching process.

[0026] As further shown, the planarization layer 120 can be removed after the spacer layer 140 has been formed. The planarization layer 120 can be removed using any suitable process according to the embodiments described herein. In some embodiments, a plasma etching process is used to remove the planarization layer 120. For example, if the planarization layer 120 contains a carbon material, a hydrogen gas (H2) / N2 plasma can be used to remove the planarization layer 120.

[0027] Figure 1D shows the step of forming an epitaxial layer 150 within the bottom transistor device region 110-2. More specifically, the portion of the spacer layer 140 along the characteristic sidewalls functions to prevent the formation of the epitaxial layer 150 within the upper transistor device region 110-1. After forming the epitaxial layer 150 within the lower transistor device region 110-2, the remainder of the spacer layer 140 can be removed from the electronic device, and further device processing can be performed to complete the manufacturing of device 100. Further details regarding the manufacturing of device 100 are then described below with reference to Figures 2-3.

[0028] Figures 2A to 2F are perspective views illustrating exemplary methods for manufacturing an electronic device ("device") 200 according to several embodiments. For example, Figure 2A shows the steps for obtaining a base structure 202. More specifically, the device 100 may be a three-3D CMOS device, and the base structure 202 may include an upper transistor device region 210-1 corresponding to a first transistor device having a first type, and a lower transistor device region 210-2 corresponding to a second transistor device having a second type complementary to the first type. As shown, an insulating layer 220 can separate the upper transistor device region 210-1 and the lower transistor device region 210-2. In some embodiments, the upper transistor device region 210-1 corresponds to an NMOS transistor device, and the lower transistor device region 210-2 corresponds to a PMOS transistor device. In some embodiments, the upper transistor device region 210-1 corresponds to a PMOS transistor device, and the lower transistor device region 210-2 corresponds to an NMOS transistor device. In some embodiments, device 200 includes a cFET device, in which case the NMOS transistor device is an nFET and the PMOS transistor device is a pFET. In some embodiments, the upper transistor device region 210-1 includes a first nanowire and the lower transistor device region 210-2 includes a second nanowire. In some embodiments, obtaining a base structure includes forming a base structure 202.

[0029] The base structure 202 may include multiple features, including feature 205. Each feature may have substantially the same height or depth, and pairs of features may be spaced substantially by the same limiting dimension. In some embodiments, the device 200 is a high aspect ratio electronic device. More specifically, each feature may have a high aspect ratio with respect to the feature's height or depth and limiting dimension. In some embodiments, a high aspect ratio is an aspect ratio of about 8:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 10:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 15:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 20:1 or greater. In some embodiments, the limiting dimension is in the range of about 10 nm to about 30 nm. In some embodiments, the limiting dimension is in the range of about 15 nm to about 20 nm.

[0030] Figure 2B shows the step of forming the planarization layer 230 to a position lower than the upper transistor device region 210-1 and higher than the lower transistor device region 210-2. More specifically, the planarization layer 230 can be formed to a position adjacent to the insulating layer 220. Forming the planarization layer 230 may include forming the planarization layer material to a certain height higher than the upper transistor device region 210-1, and recessing the planarization layer material to a position lower than the upper transistor device region 210-1 and higher than the lower transistor device region 210-2 (e.g., adjacent to the insulating layer 220). In some embodiments, the planarization layer 230 includes a carbon (C) material. The planarization layer material can be formed using any suitable process. For example, the planarization layer 230 may include an SoC material. In some embodiments, recessing the planarization layer material includes performing a diimide or diazene (H2N2) recess.

[0031] Figure 2C shows the step of forming a spacer layer 240 on the base structure 202 and the planarization layer 220. More specifically, forming the spacer layer 240 may include conformally depositing spacer material along the upper transistor device region 210-1 up to the planarization layer 220. The spacer material can uniformly cover the sidewalls of multiple features, including feature 205, and the bottom of the trenches in the base structure 202. In some embodiments, ALD is used to conformally deposit the spacer material.

[0032] The spacer material may include any suitable dielectric material according to the embodiments described herein. In some embodiments, the spacer material includes a silicon (Si)-based material. For example, the spacer material may include a silicon nitride material. An example of a silicon nitride material is silicon nitride (Si x N y This includes silicon oxynitride (SiON), silicon oxycarbonite (SiOCN), and the like. The spacer material can be formed to have any suitable thickness. In some embodiments, the spacer material is formed to have a thickness between about 2 nm and about 8 nm. In some embodiments, the spacer material is formed to have a thickness between about 3 nm and about 6 nm.

[0033] Forming the spacer layer 240 may further include modifying the portion of the spacer material formed along the bottom surface of the trench in the base structure. In some embodiments, modifying the portion of the spacer material formed along the bottom surface of the trench may include using a dry etching process with a plasma etchant. For example, the dry etching process may be an ion bombardment process. Directional high-energy ions can bombard the spacer material formed along the bottom surface of the trench, and the bombardment damages the portion of the spacer material formed along the bottom surface of the trench. The damage may include physical damage caused by the ion bombardment and / or chemical damage caused by the plasma. Due to the directionality of the ion bombardment against the bottom surface of the trench, the portion of the spacer material formed along the feature sidewall may be subject to relatively low damage. The dry etching process can be carried out using any suitable plasma etchant that is non-reactive to the spacer material. For example, the plasma etchant may include one or more non-reactive or inert gas species such as noble gases (e.g., He, Ne, Ar, Kr and / or Xe), N2, etc.

[0034] Forming the spacer layer 240 may further include removing damaged spacer material along the bottom of the trench using a wet etching process. In this step, the device 200 is immersed in the wet etchant for a certain amount of time. Damage to the spacer material along the bottom of the trench increases the selectivity of wet etching compared to the spacer material formed along the side walls of the feature, so that within a certain amount of time the electronic device is immersed in the wet etchant, only the smallest amount of spacer material formed along the side walls of the feature is removed. The wet etching process can be carried out according to the embodiments described herein using any suitable wet etchant. In some embodiments, the wet etchant includes dHF. For example, dHF may have a ratio of at least 100:1 and allow the electronic device to be immersed for about 60 seconds. Thus, the spacer layer 240 is formed after the spacer material has been removed from the bottom of the trench of the base structure using the wet etching process.

[0035] Figure 2D shows the step of removing the planarization layer 220 after forming the spacer layer 240. The planarization layer 220 can be removed using any suitable process according to the embodiments described herein. In some embodiments, a plasma etching process is used to remove the planarization layer 220. For example, if the planarization layer 220 contains a carbon material, an H2 / N2 plasma can be used to remove the planarization layer 220.

[0036] Figure 2E shows the step of forming the epitaxial layer 250 within the bottom transistor device region 210-2. More specifically, the portion of the spacer layer 240 along the characteristic sidewalls functions to prevent the formation of the epitaxial layer 250 within the upper transistor device region 210-1.

[0037] Figure 2F shows the steps for removing the remainder of the spacer layer 240 after forming the epitaxial layer 250 within the lower transistor device region 210-2. In some embodiments, removing the remainder of the spacer layer 240 includes performing a wet etching process. For example, the wet etching process may be a thermal phosphoric acid (H3PO4) etching process, which may be selective for silicon oxide materials. As another example, the wet etching process may be a dHF etching process, which may be selective for silicon nitride materials. In some embodiments, removing the remainder of the spacer layer 240 includes performing a dry etching process (e.g., a plasma etching process). The dry etchant used may depend on the material of the spacer layer 240. Further device processing can then be performed to complete the fabrication of the device 200. Further details regarding the fabrication of the device 200 are described above with reference to Figure 2 and then below with reference to Figure 3.

[0038] Figure 3 shows an exemplary method 300 for manufacturing an electronic device using area-selective deposition, according to several embodiments. Method 300 can be performed within an electronic device processing system. More specifically, Method 300 can be performed within one or more process chambers of an electronic device processing system.

[0039] In step 310, a base structure is obtained that includes an upper device region and a lower device region. For example, the upper device region and the lower device region can be separated by an insulating layer. In some embodiments, obtaining the base structure includes forming the base structure.

[0040] More specifically, the electronic device can be a 3D CMOS device, the upper transistor device region can correspond to an upper transistor device having a first type, and the lower transistor device region can correspond to a lower transistor device having a second type complementary to the first type. In some embodiments, the upper transistor device is an NMOS transistor device and the lower transistor device is a PMOS transistor device. In some embodiments, the upper transistor device is a PMOS transistor device and the lower transistor device is an NMOS transistor device. In some embodiments, the electronic device is a cFET device, in which case the NMOS transistor device is an nFET and the PMOS transistor device is a pFET. In some embodiments, the upper transistor device region includes a first nanowire and the lower transistor device region includes a second nanowire.

[0041] The base structure may include multiple features. Each feature may have substantially the same height or depth, and pairs of features may be separated by substantially the same limiting dimension. In some embodiments, the electronic device is a high aspect ratio electronic device. More specifically, a high aspect ratio electronic device is an electronic device that includes features having a high aspect ratio with respect to the height or depth of the features and the limiting dimension. In some embodiments, a high aspect ratio is an aspect ratio of about 8:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 10:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 15:1 or greater. In some embodiments, a high aspect ratio is an aspect ratio of about 20:1 or greater. In some embodiments, the limiting dimension is in the range of about 10 nm to about 30 nm. In some embodiments, the limiting dimension is in the range of about 15 nm to about 20 nm.

[0042] In step 320, a planarization layer is formed. More specifically, the planarization layer can be formed to a position lower than the upper transistor device region and higher than the lower transistor device region. For example, the planarization layer can be formed to a position adjacent to the insulating layer. Forming the planarization layer can include forming the planarization layer material to a certain height higher than the upper transistor device region, and recessing the planarization layer material to a position lower than the upper transistor device region (for example, adjacent to the insulating layer). In some embodiments, the planarization layer includes a carbon (C) material. The planarization layer material can be formed using any suitable process. For example, the planarization layer can include an SoC material. In some embodiments, recessing the planarization layer material includes performing a diimide or diazene (H2N2) recess.

[0043] In step 330, spacer material is formed along the base structure and the planarization layer. More specifically, forming spacer material along the base structure may include conformally depositing spacer material along the first transistor device region up to the planarization layer. The spacer material can uniformly cover the sidewalls of multiple features and the bottom of the trenches in the base structure. In some embodiments, ALD is used to conformally deposit the spacer material.

[0044] The spacer material may include any suitable dielectric material according to the embodiments described herein. In some embodiments, the spacer material includes a silicon (Si)-based material. For example, the spacer material may include a silicon nitride material. An example of a silicon nitride material is silicon nitride (Si x N y This includes silicon oxynitride (SiON), silicon oxycarbonite (SiOCN), and the like. The spacer material can be formed to have any suitable thickness. In some embodiments, the spacer layer has a thickness between about 2 nm and about 8 nm. In some embodiments, the spacer layer has a thickness between about 3 nm and about 6 nm.

[0045] In step 340, the spacer material formed along the bottom of the trench in the base structure is modified. More specifically, the spacer material formed along the bottom of the trench in the base structure is damaged. To do this, a dry etching process is performed using a plasma etchant. More specifically, the dry etching process is a directional etching process that targets the spacer material formed along the bottom of the trench in the base structure.

[0046] In some embodiments, the dry etching process is an ion bombardment process. Directional high-energy ions can bombard the spacer material formed along the bottom of the trench, and the bombardment damages the spacer material formed along the bottom of the trench. The damage may include physical damage caused by the ion bombardment and / or chemical damage caused by the plasma. Due to the directionality of the ion bombardment against the bottom of the trench, the spacer material formed along the side walls of the feature may suffer relatively little damage. The dry etching process can be carried out using any suitable plasma etchant that is non-reactive to the spacer material. For example, the plasma etchant may include one or more non-reactive or inert gas species such as noble gases (e.g., He, Ne, Ar, Kr and / or Xe), N2, etc.

[0047] As an illustrative example, He / N2 plasma treatment can be used with appropriate arbitrary process parameters. Examples of process parameters include pressure, power (e.g., source power and bias power), gas flow, process time, etc. In some embodiments, He / N2 plasma treatment is performed at a pressure between about 1 milliliter and about 1 tor. In some embodiments, He / N2 plasma treatment is performed at a pressure between about 2 milliliters and about 10 milliliters. In some embodiments, the source power is in the range of about 100 watts (W) to about 500 watts (W). In some embodiments, the source power is in the range of about 200 watts (W) to about 400 watts (W). In some embodiments, the source power is in the range of about 250 watts (W) to about 350 watts (W). In some embodiments, the bias power is in the range of about 20 watts (W) to about 200 watts (W). In some embodiments, the source power is in the range of about 50 watts (W) to about 150 watts (W). In some embodiments, the source power is in the range of about 75 watts (W) to about 125 watts (W). In some embodiments, the He / N2 plasma treatment is performed using a He gas flow between about 10 standard cubic centimeters per minute (sccm) and about 500 sccm, and an N2 gas flow between about 10 sccm and about 500 sccm. In some embodiments, the He / N2 plasma treatment is performed using a He gas flow between about 100 sccm and about 300 sccm, and an N2 gas flow between about 50 sccm and about 200 sccm. In some embodiments, the He / N2 plasma treatment is performed using a He gas flow between about 175 sccm and about 215 sccm, and an N2 gas flow between about 75 sccm and about 150 sccm. In some embodiments, the process time is about 300 seconds or less. In some embodiments, the process time is about 240 seconds or less. In some embodiments, the process time is about 180 seconds or less. In some embodiments, the process time is about 120 seconds or less. In some embodiments, the process time is about 90 seconds or less. In some embodiments, the process time is about 80 seconds or less.

[0048] In step 350, a spacer layer is formed by removing the modified spacer material using a wet etching process. More specifically, the electronic device is immersed in the wet etchant for a certain amount of time. Damage to the spacer material along the bottom of the trench increases the selectivity of wet etching compared to the spacer material along the side walls of the feature, so that only the smallest amount of spacer material along the side walls of the feature is removed during the amount of time the electronic device is immersed in the wet etchant. The wet etching process can be performed according to the embodiments described herein using any suitable wet etchant. In some embodiments, the wet etchant includes dHF. For example, dHF can have a ratio of 100:1 or greater, allowing the electronic device to be immersed for about 60 seconds. Thus, the spacer layer is formed after the spacer material has been removed from the bottom of the trench using the wet etching process.

[0049] In step 360, the planarization layer is removed. The planarization layer can be removed using any suitable process according to the embodiments described herein. In some embodiments, a plasma etching process is used to remove the planarization layer. For example, if the planarization layer contains carbon material, an H2 / N2 plasma can be used to remove the planarization layer.

[0050] In step 370, a set of epitaxial layers is formed within the lower device region. More specifically, the spacer layer functions to prevent the formation of the set of epitaxial layers within the lower device region.

[0051] In step 380, remove the spacer layer.

[0052] In step 390, additional device processing is performed to complete the manufacturing of the electronic device.

[0053] To provide a full understanding of some embodiments of this disclosure, the above description includes numerous specific details, such as examples of particular systems, components, and methods. However, it will be apparent to those skilled in the art that at least some embodiments of this disclosure can be implemented without these specific details. As another example, to avoid unnecessarily obscuring this disclosure, well-known components or methods are not described in detail or are shown in the form of simple block diagrams. Thus, the specific details described are merely examples. Certain embodiments may differ from these exemplary details, yet are intended to be included within the scope of this disclosure.

[0054] Throughout this specification, any reference to “one embodiment” or “embodiment” means that the specific features, structure, or characteristics described in relation to that embodiment are included in at least one embodiment. Therefore, occurrences of the phrase “in one embodiment” or “in one embodiment” in various parts of this specification do not necessarily all refer to the same embodiment. In addition, the term “or” is intended to mean inclusive “or” rather than exclusive “or.” Where the terms “about” or “approximately” are used in this specification, the term is intended to mean that the presented nominal values ​​are accurate within a range of + / - 10%.

[0055] The operations of the methods described herein are shown and described in a particular order, but the order of operations of each method may be changed so that some operations are performed in the reverse order, or some operations are performed at least partially concurrently with other operations. In another embodiment, instructions or suboperations of different operations may be performed intermittently and / or alternately.

[0056] It should be understood that the above description is intended to be illustrative and not limiting. Many other embodiments will be obvious to those skilled in the art by reading and understanding the above description. Therefore, the scope of this disclosure should be determined in relation to the complete scope of the appended claims and the equivalent works to which such claims are claimed.

Claims

1. The planarization layer is formed to a position lower than the transistor device region above the base structure of the electronic device and higher than the transistor device region below the base structure, wherein the base structure includes a plurality of features. Forming a spacer material along the base structure and the planarization layer, Obtaining a modified spacer material by modifying the spacer material formed along the bottom trench of the base structure, wherein obtaining the modified spacer material by modifying the spacer material formed along the bottom trench of the base structure includes performing a dry etching process targeting the spacer material formed along the bottom trench of the base structure. The spacer layer is formed by removing the modified spacer material using a wet etching process. Methods that include...

2. The method according to claim 1, wherein forming the spacer material along the base structure and the planarization layer involves conformally depositing the spacer material using an atomic layer deposition (ALD) process.

3. The method according to claim 1, wherein the dry etching process is an ion bombardment process.

4. The method according to claim 1, wherein forming the spacer layer by removing the modified spacer material using the wet etching process comprises immersing the electronic device in dilute hydrofluoric acid (dHF).

5. The method according to claim 1, wherein the plurality of features have an aspect ratio of approximately 10:1 or greater.

6. The method according to claim 1, wherein the plurality of features have relevant limit dimensions between approximately 10 nanometers (nm) and approximately 30 nm.

7. The method according to claim 6, wherein the plurality of features have a related limit dimension between approximately 15 nm and approximately 20 nm.

8. After forming the spacer layer, the planarization layer is removed, Forming a set of epitaxial layers within the aforementioned lower transistor device region, After forming the set of epitaxial layers, the spacer layer is removed. The method according to claim 1, further comprising:

9. The method according to claim 1, wherein the spacer material includes a silicon-based dielectric material.

10. The method according to claim 1, wherein the electronic device includes a three-dimensional (3D) transistor device.

11. The method according to claim 10, wherein the electronic device includes a complementary field-effect transistor (cFET) device.

12. To obtain a base structure for an electronic device that includes multiple features and has an upper transistor device region and a lower transistor device region, From the base structure, a planarization layer is formed to a position lower than the upper transistor device region and higher than the lower transistor device region. Forming a spacer material along the base structure and the planarization layer, The process involves modifying the spacer material formed along the bottom trench of the base structure to obtain a modified spacer material, and obtaining the modified spacer material involves performing a dry etching process targeting the spacer material formed along the bottom trench of the base structure. The spacer layer is formed by removing the modified spacer material using a wet etching process, Removing the aforementioned planarization layer, Forming a set of epitaxial layers within the aforementioned lower transistor device region, Removing the aforementioned spacer layer A method that includes this.

13. The method according to claim 12, wherein forming the spacer material along the base structure and the planarization layer involves conformally depositing the spacer material using an atomic layer deposition (ALD) process.

14. The method according to claim 12, wherein the dry etching process is an ion bombardment process.

15. The method according to claim 12, wherein forming the spacer layer by removing the modified spacer material using the wet etching process comprises immersing the electronic device in dilute hydrofluoric acid (dHF).

16. The method according to claim 12, wherein the plurality of features have an aspect ratio of approximately 10:1 or greater.

17. The method according to claim 12, wherein the plurality of features have relevant limit dimensions between approximately 10 nanometers (nm) and approximately 30 nm.

18. The method according to claim 12, wherein the plurality of features have a relevant limit dimension between approximately 15 nm and approximately 20 nm.

19. The method according to claim 12, wherein the spacer material includes a silicon-based dielectric material.

20. The method according to claim 12, wherein the electronic device includes a complementary field-effect transistor (cFET) device.

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