Memory scheduling

Abstract

This paper describes methods, systems, and devices for memory scheduling. More specifically, it describes techniques related to memory interfaces between a host system and memory (e.g., tightly coupled memory). For example, a memory interface block (MIB) between a host system and a memory system can schedule access operations, error control operations, media management operations, and other operations performed by the memory system. The use of such MIBs can improve the memory system by reducing latency and increasing the efficiency of memory access, while mitigating the impact on the host system's architecture and design.

Description

Technical Field

[0001] Cross Reference This patent application claims priority to U.S. Patent Application No. 18 / 607,283, filed Mar. 15, 2024, by Liu et al. entitled "SCHEDULING FOR MEMORY", and U.S. Provisional Patent Application No. 63 / 457,703, filed Apr. 6, 2023, by Liu et al. entitled "SCHEDULING FOR MEMORY", each of which is assigned to the assignee of this application and is hereby expressly incorporated by reference in its entirety.

[0002] The following relates to one or more systems for memory, including scheduling for memory.

Background Art

[0003] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells may be programmed into one of two supported states, often represented by logic 1 or logic 0. In some embodiments, a single memory cell may support three or more states, and any one of them may be stored. To access the stored information, the memory device can read the state from the memory cell (e.g., sense, detect, retrieve, determine). To store information, the memory device can write a state to the memory cell (e.g., program, set, assign).

[0004] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technology, and NOR (not-or) and NAND (not-and) memory devices. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain their stored logical state for a long period of time even without an external power supply. Memory cells configured in a volatile configuration may lose their stored state when disconnected from an external power supply. [Brief explanation of the drawing]

[0005] [Figure 1] This figure shows an example of a system that supports memory scheduling according to the embodiments disclosed herein. [Figure 2] This figure shows an example of a system that supports memory scheduling according to the embodiments disclosed herein. [Figure 3] Figure 3A is a diagram showing an example of a device that supports memory scheduling according to the embodiments disclosed herein, Figure 3B is a diagram showing an example of a device that supports memory scheduling according to the embodiments disclosed herein, and Figure 3C is a diagram showing an example of a device that supports memory scheduling according to the embodiments disclosed herein. [Figure 4] This figure shows an example of a system that supports memory scheduling according to the embodiments disclosed herein. [Figure 5] This figure shows an example of a flowchart that supports memory scheduling according to the embodiments disclosed herein. [Figure 6]This is a block diagram of a memory system that supports memory scheduling according to the embodiments disclosed herein. [Figure 7] This flowchart shows one or more methods for supporting memory scheduling according to the embodiments disclosed herein. [Modes for carrying out the invention]

[0006] Memory systems may be configured to provide efficient and high-performance solutions for memory-centric logic such as graphics processing units (GPUs). In some embodiments, these memory systems may include tightly coupled dynamic random access memory (TCDRAM). TCDRAM may be tightly coupled (e.g., physically coupled) to the GPU as part of the memory system's physical memory map. Unlike cache-based memory, TCDRAM may not be supported by a level of external memory having the same physical addresses. Instead, TCDRAM may be associated with a dedicated base address and reside within that base address, and each part of the TCDRAM may not overlap in addresses.

[0007] The use of TCDRAM can reduce memory access latency by avoiding the use of memory caches, thereby avoiding the unpredictability of access times associated with cache usage. That is, since the code is not initially fetched from the cache or other external memory at the start of an access operation, the GPU (or other processing unit), for example, can immediately access the relevant memory system, thereby improving access latency. While this close relationship between the memory system and the relevant GPU can enable efficient memory access and other processes, it may be useful to incorporate a memory interface architecture that allows for even higher performance.

[0008] This paper describes techniques for memory interfaces between a host system (e.g., a GPU) and a memory system (e.g., TCDRAM). For example, a memory interface block (MIB) between the host system and the memory system can schedule access operations, error control operations, media management operations, and other operations performed by the memory system. In some embodiments, the MIB may be located on the host system die. The MIB can improve access operation latency by assisting (e.g., coordinating with) one or more memory controllers on the host system die in various scheduling operations. For example, the MIB can schedule operations that were previously performed by the host system. That is, the MIB can schedule error control operations, media management operations, test engines, and / or improve logic-to-memory I / O.

[0009] In some embodiments, MIBs may also help control the flow of commands to and from each memory bank. For example, each bank may be coupled to and share one or more channels configured to communicate data, C / A, and clock information with the memory die. Rather than leaving the efficient management of sharing these channels to the host system, the MIB can control the flow of data and commands on each channel between the host system die and the banks. Thus, the use of MIBs can enable improvements to the memory system by reducing latency and improving the efficiency of memory access, while mitigating the impact on the architecture and design of the host system.

[0010] First, the features of this disclosure are described in the context of the system, which is described with reference to Figures 1 and 2. The features of this disclosure are described in the context of the devices, systems, and flowcharts, which are described with reference to Figures 3A-35. These and other features of this disclosure are further illustrated and described with reference to the diagrams and flowcharts of the devices involved in memory scheduling, which are described with reference to Figures 6 and 7.

[0011] Figure 1 shows an example of a system 100 that supports memory scheduling according to embodiments disclosed herein. System 100 may include a portion of an electronic device such as a computing device, a mobile computing device, a wireless communication device, an image processing device, a vehicle, or other system. System 100 includes a host system 105, a memory system 110, and one or more channels 115 that connect the host system 105 to the memory system 110 (for example, to provide communication coupling). System 100 may include one or more memory systems 110, and embodiments of one or more memory systems 110 may be described in the context of a single memory system 110.

[0012] The host system 105 may be an example of a processor (e.g., circuit configuration, processing circuit configuration, processing component) that uses memory to perform processes, such as a computing device, mobile computing device, wireless communication device, image processing device, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or processing system for other fixed or portable electronic devices. The host system 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components (e.g., peripheral components, input / output controllers; not shown). The components of the host system 105 may be coupled to each other using a bus 135.

[0013] The external memory controller 120 may be configured to enable communication of information (e.g., data, commands, control information, configuration information) between components of the system 100 (e.g., between components of the host system 105, such as the processor 125, and the memory system 110). The external memory controller 120 can process (e.g., translate, translate) the communication exchanged between the host system 105 and the memory system 110. In some embodiments, the external memory controller 120, or other components of the system 100, or related functions described herein may be implemented by the processor 125, or may be part of the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software (e.g., instructions), or any combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is shown outside the memory system 110, in some embodiments the external memory controller 120, or its functions as described herein, may be implemented by one or more components of the memory system 110 (e.g., the memory system controller 155, the local memory controller 165), and vice versa. In various embodiments, the host system 105 or the external memory controller 120 may be referred to as the host.

[0014] The processor 125 may be capable of providing functions (e.g., control functions) relating to system 100 or host system 105. The processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. In some embodiments, the processor 125 may be, among other examples, a central processing unit (CPU), an image processing unit (GPU), a general-purpose GPU (GPGPU), or an example of a System of Central (SoC).

[0015] In some embodiments, system 100 or host system 105 may include input components, output components, or a combination thereof. Input components may include sensors, microphones, keyboards, another processor (e.g., on a printed circuit board), interfaces (e.g., user interfaces, interfaces between other devices), or peripherals that interface with system 100 via one or more peripheral components. Output components may include, among other examples, displays, audio speakers, printing devices, another processor on a printed circuit board, or peripherals that interface with system 100 via one or more peripheral components.

[0016] The memory system 110 may be a component of system 100 that is capable of operating to provide physical memory locations (e.g., addresses) that may be used or referenced by system 100. The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) to support data storage capacity. The memory system 110 may be configured to work with one or more different types of host systems 105 and can be executed in response to commands provided by the host systems 105 (e.g., via an external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive write commands indicating that the memory system 110 will store data received from the host system 105, or read commands indicating that the memory system 110 will provide data stored in the memory die 160 to the host system 105, or refresh commands indicating that the memory system 110 will refresh data stored in the memory die 160.

[0017] The memory system controller 155 may include components (e.g., circuitry, logic) that can operate to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with an external memory controller 120, one or more memory dies 160, or one or more processors 125. In some embodiments, the memory system controller 155 may cooperate with a local memory controller 165 of a memory die 160 to control the operation of the memory system 110.

[0018] Each memory die 160 may include a local memory controller 165 and a memory array 170. The memory array 170 may be a collection of memory cells, each of which is operable to store one or more data bits. The memory die 160 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some embodiments, the 2D memory die 160 may include a single memory array 170. In some embodiments, the 3D memory die 160 may include two or more memory arrays 170, which may be stacked or positioned side by side (for example, with respect to a substrate).

[0019] The local memory controller 165 may include components (e.g., circuitry, logic) that can operate to control the operation of the memory die 160. In some embodiments, the local memory controller 165 may be operable to communicate with the memory system controller 155 (e.g., to receive or send data or commands or both). In some embodiments, the memory system 110 may not include the memory system controller 155, and the local memory controller 165 or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, with other local memory controllers 165, or directly with an external memory controller 120 or processor 125, or with any combination thereof. Examples of components that may be included in the memory system controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from an external memory controller 120), a transmitter for sending signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, a sensing component for sensing the state of memory cells in the memory array 170, a writing component for writing states to memory cells in the memory array 170, or various other components capable of operating to support the aforementioned operations of the memory system 110.

[0020] The host system 105 (e.g., an external memory controller 120) and the memory system 110 (e.g., a memory system controller 155) can communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium for carrying information, and each channel 115 may include one or more signal paths (e.g., a transmission medium, a conductor, a conductive path) between terminals associated with components of the system 100. For example, channel 115 may be associated with a first terminal in the host system 105 (e.g., including one or more pins, including one or more pads) and a second terminal in the memory system 110. The terminal may be an example of a conductive input or output point of a device in the system 100, and the terminal may be operable to act as part of channel 115. In some embodiments, at least the channel 115 between the host system 105 and the memory system 110 includes, or may be referred to as, a host interface (e.g., a physical host interface). In some implementations, the host interface may include, or be associated with, interface circuits (e.g., signal drivers, signal latches) in the host system 105 (e.g., external memory controller 120), the memory system 110 (e.g., memory system controller 155), or both.

[0021] In some embodiments, channel 115 (e.g., the associated signal path and terminals) may be dedicated to the communication of one or more types of information. For example, channel 115 may include, among other channels, one or more command and address channels, one or more clock signal channels, one or more data channels, or combinations thereof. In some embodiments, signaling may be communicated over channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol of a signal (e.g., a signal level) may be registered for each clock cycle (e.g., at the rising edge or falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal may be registered for each clock cycle (e.g., at both the rising edge and the falling edge of a clock signal).

[0022] In some embodiments, one or more channels 115 may include one or more error detection code (EDC) channels. The EDC channels may be operable to communicate error detection signals, such as checksums, to improve the reliability of the system. The EDC channels can include any number of signal paths.

[0023] In some embodiments, a memory interface between a host system 105 (e.g., a GPU) and a memory system 110 (e.g., a TCDRAM). For example, a memory interface block between the host system 105 and the memory system 110 can schedule operations executed by the memory system 110, schedule error control operations, schedule media management operations, schedule a test engine, and / or improve the logic-to-memory I / O of the memory system 110. The use of such an interface block can enable the improvement of the memory system 110 by shortening latency and improving the efficiency of memory access while reducing the adverse impact on the architecture and design of the host system 105. Further, to further improve the performance of the system 100, the interface block can also be positioned in a die associated with the host system 105 rather than in a die associated with the memory system 110.

[0024] In addition to the applicability to the memory systems described herein, techniques for scheduling a memory interface can generally be implemented to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analytics, decision-making, or other related applications, there may be a desire for electronic devices that support artificial intelligence applications and processes. For example, artificial intelligence applications may be associated with access to relatively large amounts of data for analysis purposes and may benefit from memory devices that enable relatively efficient and efficient storage of relatively large amounts of data or relatively rapid access to stored data. Implementations of the techniques described herein can support artificial intelligence and / or machine learning techniques, among other benefits, by improving memory access speed and efficiency.

[0025] Figure 2 shows an example of a system 200 that supports memory scheduling according to an embodiment disclosed herein. The system 200 may include a memory die 210 and a host system die 205 (e.g., a GPU die), which may be one of the memory dies 160 and host system 105 described with reference to Figure 1. The memory die 210 may include one or more banks 230 of memory cells. The host system die 205 may include one or more processors 215, a memory controller 220 (e.g., an MC), and an MIB 225, which may be examples of the processors, controllers, and interfaces described with reference to Figure 1.

[0026] In some embodiments, the system 200 may include a memory die 210, which may include an example of a tightly coupled memory (TCM) architecture, such as tightly coupled dynamic random access memory (TCDRAM). Thus, the memory die 210 may include a bank 230 that can be accessed by the associated host system die 205 (e.g., the host system, the host system's processor) in a single data cycle. For example, the bank 230 of the memory die 210 may store time-critical routines and data. If the memory die 210 includes an example of a TCM architecture, the processor 215 of the host system die 205 can access the routines and data stored in the bank 230 within a single data cycle without waiting for various fetch codes and processes outside the system.

[0027] In some embodiments, the system 200 may include a host system die 205. The host system die 205 may include a processor 215, a memory controller 220, and other components that access and manipulate relevant data to enable simultaneous iterative calculations and processes. For example, the host system die 205 may receive and process graphics rendering requests sent by relevant host devices and then perform rapid calculations and other data manipulations to enable rendering of the requested graphics.

[0028] The host system die 205 may include one or more memory controllers 220. In some cases, the memory controllers 220 may be responsible for various power (e.g., power on, power off), access, and scheduling operations of the memory die 210. For example, the memory controller 220 can control power to various aspects of the host system die 205 so that performance can be maximized while adhering to constraints. The memory controller 220 may also connect various components of the host system die 205 to each other, connect to components of the memory die 210, or connect to another system outside the host system die 205. For example, the memory controller 220 may include a scheduler that can manage requests via deep queues. That is, the scheduler of the memory controller 220 can receive commands or requests, store them in a queue (e.g., a FIFO queue), and issue requests to various components of the host system die 205 so that latency is minimized. In some embodiments, for example, the memory controller 220 (or memory controller scheduler) may also be responsible for managing read and write aggregation requests, prioritization requests, ordering requests, and other requests.

[0029] In some embodiments, the use of a tightly coupled architecture included in the memory die 210 can improve the efficiency and high performance of the host system die 205. However, while the close relationship between the host system die 205 and the memory die 210 enables efficient memory access and other processes, it may be useful to incorporate a memory interface architecture (e.g., MIB225) that enables even higher performance.

[0030] In some embodiments, the host system die 205 may include one or more MIBs 225. For example, each MIB 225 may be an interface between the host system die 205 and the memory die 210 and may be located on the host system die 205. The MIBs 225 can enable improvements in access operation latency by assisting (e.g., coordinating with) the memory controllers 220 of the host system die 205 in various scheduling operations. For example, the MIBs 225 can schedule operations performed by the system 220, schedule error control operations, schedule media management operations, schedule a test engine, and / or improve logic-to-memory I / O. In some embodiments, each MIB 225 may include a command arbiter, one or more memory banks, and associated short queues (e.g., FIFO queues). Thus, each MIB 225 can control timing operations and refresh schedules associated with each bank 230 and can assign banks 230 to execute various commands and other operations received from one or more memory controllers 220.

[0031] In some embodiments, each MIB225 may help control the flow of commands to and from each designated bank 230. For example, each bank 230 may be coupled to one or more channels configured to communicate data, C / A, and clock information with the memory die 210. In some cases, each bank 230 may be coupled to one or more data pins (e.g., data channels), and one or more banks 230 may share C / A pins and clock pins (e.g., C / A channel, clock channel, CLK, RCLK). To enable efficient sharing of these pins, each MIB225 may control the flow of data and commands on each channel between the host system die 205 and the banks 230. For example, one or more MIB225s may receive commands from the memory controller 220, and then the memory banks and associated shallow queues (e.g., FIFO queues), as well as the command arbiter for each MIB225, can control which MIB225 can execute the commands. Therefore, MIB can enable improvements to the host system die 205 by reducing latency and improving memory access efficiency, while mitigating adverse effects on the host system architecture and design.

[0032] Figure 3A shows an example of a device 300-a that supports memory scheduling according to embodiments disclosed herein. Device 300-a may be an example of a device in which an ASIC 305 (e.g., another integrated circuit, die) is coupled to a memory device 310 using an interposer 315 (e.g., a silicon interposer, a glass interposer) and a package substrate 325. Device 300-a may be an example of the system 200 described with reference to Figure 2. The ASIC 305 may be an example of the host system die 205 and other host devices described with reference to Figures 1 and 2. Device 300-a may include an MIB 335, which may be an example of the MIB 225 described with reference to Figure 2, and may also include a physical interface 340. The memory device 310 may include one or more memory dies 320. Each memory die 320 may be an example of the memory die 210 described with reference to Figure 2. In some cases, the memory dies 320 may also be called a memory array, an array of memory cells, or a deck of memory cells.

[0033] In some embodiments, for improved power consumption and efficiency, MIB335 may be included in buffer layer 330-a and coupled to memory device 310 and ASIC305-a. For example, MIB335 may be included in buffer layer 330-a between memory device 310 and interposer 315. MIB335 may be coupled to ASIC305-a via one or more physical interfaces 340, and ASIC305-a may be physically connected via channels through interposer 315. As described with reference to Figure 2, MIB335 may help control the flow of commands and data between ASIC305-a and memory die 320 by providing temporary storage of commands received from ASIC305-a and specified to memory device 310, and scheduling for commands. One or more MIB335s can receive commands from the ASIC305-a (e.g., the memory controller of the ASIC305-a), temporarily store the commands in a memory bank managed by a shallow queue (e.g., a FIFO queue), and then determine when the commands should be sent to the memory device and through which channel (e.g., as described in Figure 2) the commands should be communicated.

[0034] Figure 3B shows an example of device 300-b that supports memory scheduling according to embodiments disclosed herein. Device 300-b may be an example of a device in which an ASIC 305-b is coupled to a memory device 310 above a package substrate 325. Device 300-b may be similar to device 300-a, except that the ASIC 305-b of device 300-b may be located between the buffer layer 330-b and the package substrate 325. Thus, one or more MIBs 335 and one or more physical interfaces 340 may be included within the buffer layer 330-b (for example, as an interface shim) to help control the flow of commands and data between the ASIC 305-b and one or more memory dies 320 of the memory device 310. This interface shim configuration can result in increased bandwidth and improved power efficiency of device 300-b.

[0035] Figure 3C shows an example of a device 300-c that supports memory scheduling according to an embodiment disclosed herein. Device 300-c may be an example of a device in which an ASIC 305-c is coupled to a memory device 310 via a package substrate 325. Device 300-c may be similar to device 300-b, except that one or more MIBs 335 and one or more physical interfaces 340 may be included in the ASIC 305-c. Furthermore, the ASIC 305-c of device 300-b may be located between the memory device 310 and the package substrate 325. Thus, one or more MIBs 335 and one or more physical interfaces 340 included in the ASIC 305-c may help control the flow of commands and data between the ASIC 305-c and one or more memory dies 320 of the memory device 310. This configuration, which includes MIB335 and physical interface 340 in ASIC305-c, can result in increased bandwidth, improved power efficiency, reduced latency, and faster access speeds for device 300-b.

[0036] Figure 4 shows an example of a system 400 that supports memory scheduling according to embodiments disclosed herein. The system 400 may include a host system die 402 and a memory die 430, which may be examples of the memory die 210 and host system 205 described with reference to Figure 2. The host system die 402 may include one or more processors 435, a memory controller 445 (e.g., MC), and an MIB 405, which may be examples of the processors, controllers, and interfaces described with reference to Figures 1-3. Each MIB 405 may include one or more bank controllers 410 and one or more queues 415 (e.g., shallow queues, FIFO queues) that can manage commands received from the memory controller 445 via a physical interface 425. Each MIB 405 may also be coupled to a bank 470 of the memory die 430 via one or more channels 459, each of which may include one or more data channels 460 and C / A channels 465.

[0037] The host system die 402 may include a memory controller 445. In some cases, the memory controller 445 may be firmware of the host system die 402 that is responsible for communicating commands to the memory die 430 (e.g., bank 470 of the memory die 430). For example, the memory controller 445 may include queues 450 (e.g., deep queues, priority queues) and a scheduler 455 that can temporarily store and manage commands to be sent to the memory die 430. In some embodiments, the memory controller 445 may store commands that may be destined for the memory die 430 in the queue 450. The scheduler 455 of the memory controller 445 can then determine when each queued command is buffered from the queue 450 via the physical interface 425.

[0038] System 400 may include one or more MIBs 405. Each MIB 405 may include one or more bank controllers 410. MIBs 405 can use the bank controllers 410 to execute commands using one or more associated banks 470. Each MIB 405 may include a command arbiter 420, which can determine which banks 470 may be available and assign one of the available bank controllers 410 to execute a command. MIBs 405 may also include a queue 415 that may control, in a FIFO manner, when commands stored in the bank controllers 410 are executed.

[0039] The system 400 may include one or more channels 459, each of which may include one or more data channels 460 and one or more C / A channels 465 coupled to a bank controller 410, a command arbiter 420, a bank 470, or a combination thereof. For example, channel 459-a may include data channels 460-a, 460-b, and 465 which may be coupled to MIB 405-a, bank 470-a, and bank 470-b (not shown). In such an embodiment, data channel 460-a may be coupled to bank 470-a, data channel 460-b may be coupled to bank 470-b, and C / A channel 465 may be coupled to both bank 470-a and bank 470-b (e.g., shared by them). For example, data channel 460-a may include four data pins (DQ0-DQ4), and data channel 460-b (not shown) may include four additional data pins (DQ5-DQ8). In some cases, for example, both data channels 460-a and 460-b (or another pair of data channels) may share a clock pin (CLK) and a read clock pin or return clock pin (RCLK). Thus, the clock pins (e.g., CLK and RCLK) may be coupled to two of the banks 470 (e.g., bank 470a and bank 470b), and each set of other pins of data channel 460 (e.g., DQ pins, ECC pins) may be coupled to one of the banks 470.

[0040] Each MIB405 may include one command arbiter 420. For example, the command arbiter 420 may perform arbitration operations relating to bank 470 and channel 459. For example, the command arbiter 420 may perform channel arbitration operations. Thus, the command arbiter 420 can use a round-robin or priority-based arbitration process to determine which commands to communicate over channel 459 and which channel 459 to use. That is, if MIB405-a may receive multiple column or row commands from the host system die 402, the command arbiter 420 can perform a round-robin or priority-based arbitration process to determine which column or row command is first transmitted to bank 470 over channel 459 (e.g., first executed). Furthermore, if both bank 470-a and bank 470-b have access to one or more of the channels 459 (e.g., C / A channel 465, shared CLK pin, or RCLK pin), the command arbiter 420 can determine which memory bank 470 will be able to access the channels first. The command arbiter 420 can also perform an arbitration process to determine which bank 470 may be available to execute a command (e.g., a column command, a row command). For example, the command arbiter 420 can determine which bank 470 should be assigned to a command by comparing the operation types of the columns in each bank 470 (e.g., read operations, write operations) with the operation type of the received command. In some cases, the command arbiter 420 may assign a write command to one of the banks 470.

[0041] The command arbiter may also perform a pre-bank arbitration process to prepare incoming commands and pending operations. During a pre-bank arbitration operation, the command arbiter 420 can determine whether each bank of bank 470 is ready to execute a command. For example, during pre-bank arbitration, the command arbiter 420 may determine that a row in bank 470-a is active and ready to receive a command (e.g., does not need to be refreshed or precharged), and then assign that command to bank 470-a and prepare the remaining banks for future commands (see Figure 5 for further details). In some embodiments, the pre-bank arbitration process may be an example of a round-robin arbitration process. If the command arbiter can utilize a round-robin arbitration process, the command arbiter may divide the command assignment (e.g., data associated with the command) among one or more banks of bank 470. In some other embodiments, the pre-bank arbitration process may be an example of a priority-based arbitration process. In other words, the command arbiter can compare the priorities of bank 470 and assign commands to the bank that may be characterized by a higher priority or availability among bank 470. If bank 470 has no relative priority or the priorities are the same, the command arbiter can perform round-robin arbitration by default. As a result of this pre-bank arbitration process, the command arbiter 420 can determine which bank 470 is ready to receive commands and then assign commands (particularly write commands) to the various banks.

[0042] In some embodiments, MIB405 may be included in the host system die 402. For example, to improve operating speed, MIB405 may be implemented on the silicon of the host system die 402. Thus, MIB405 can assist the memory controller 445 of the host system die 402 in scheduling and executing various commands, which may result in latency and a decrease in overall system efficiency. For example, MIB405 may be responsible for various access commands to the memory die 430 and operations that may be generated by one of the MIB405s.

[0043] In some embodiments, MIB405 may receive commands from memory controller 445. For example, memory controller 445 may transmit an access command to MIB405-a. Command arbiter 420 may determine that the received command can be assigned to bank 470-a. For example, command arbiter 420 may determine that bank 470a is available to assign the access command by accessing C / A channel 465. MIB405-a may then store the received command in queue 415a associated with bank controller 410a, and bank 470-a may execute the command. For example, the access command may be removed from queue 415-a and communicated to bank 470-a of memory die 430 via channel 459 (for example, via the C / A channel of C / A channel 465 associated with bank 470-a and the data channel of data channel 460; the other data channels of channel 459 are left for other uses).

[0044] In some cases, MIB405 may be responsible for performing various media management operations. For example, by including MIB405 on the host system die 402, MIB405 can perform operations that were previously performed by the memory controller 445 or another component of the host system die 402. Examples of operations that MIB405 may be responsible for include DRAM timing operations (see Figure 5) and various media management operations. For example, in addition to other operations, MIB405 may be responsible for low hammer mitigation, refresh operations, error control operations, and repair operations. In some cases, MIB405 (e.g., bank controller 410) may decide whether and when these operations should be performed, and may also assign one of the banks 470 to perform the determined operation (e.g., the host system die 402 may not send a request or instruction). For example, MIB405-a may detect an error caused by a low hammer occurrence or a row that has been repeatedly accessed over a period of time, and then perform a low hammer mitigation operation. In other embodiments, MIB405-a may detect a side of the memory die 430 (e.g., row, column, electrode) that needs repair and initiate a repair operation. Furthermore, in some embodiments, MIB405 may be responsible for refreshing each associated bank 470 after each bank 470 has performed an access operation or another type of operation, and in response to that. For example, MIB405 may perform refresh operations during scheduled idle times (e.g., between access operations, between management operations). Thus, MIB405 may transmit refresh commands instructing bank 470 to refresh (e.g., reset) the rows of memory cells in bank 470. MIB405 may continuously refresh the rows of bank 470 according to a schedule and transmit refresh commands accordingly.

[0045] In systems using MIB405, the host system may have little control over the exact timing of when an operation is performed. Such situations can make it difficult to ensure that certain commands are executed in a timely manner. In some embodiments, for example, the host system die 402 (or another host device) may transmit quality of service (QoS) indicators to one or more MIB405s. QoS indicators may indicate that one or more commands are priority commands and should take precedence over other commands already in the queue for various banks. For example, the host system die 402 may decide that a QoS operation should be performed on a memory die 430 (e.g., a memory array, its cells) and transmit that instruction to MIB405-a. The instruction for the QoS operation may include an instruction to MIB405-a to prioritize the command associated with the QoS indicator. In response to MIB405-a receiving that instruction, the command arbiter 420 may decide that bank 470a is available to perform the QoS operation and may select MIB405-a to perform the operation. Subsequently, MIB405-a may bypass the rest of the queued commands (for example, to prioritize QoS commands) and insert the QoS command at the beginning of queue 415a. MIB405-a may then perform the QoS operation.

[0046] By incorporating one or more MIB405s into the host system die 402, the adverse effects on the host system die 402 (or other host devices) as a whole can be mitigated. For example, implementing one or more MIB405s may result in faster low hammer mitigation operations and reduced access operation times, allowing the host system die 402 to focus on other operations. Furthermore, the MIB405 can be made operational through updates and generational changes of the host system die 402 or other host devices, enabling the MIB405's TCDRAM and memory die 430 to function. In other words, the use of MIB405 can make it possible to share scheduling responsibilities between the host system die 402 and MIB405, thereby reducing the overall complexity of the host system die 402 (from the host system die 402's perspective).

[0047] Figure 5 shows an example of a flowchart 500 supporting memory scheduling according to embodiments disclosed herein. Flowchart 500 may include an example of arbitration flows that may be performed by the MIB during the execution of an operation. The MIB may be an example of MIB225, MIB335, or MIB405 as described with reference to Figures 2-4. In some embodiments, flowchart 500 may be an example of arbitration flows that each memory bank of the MIB may perform before the MIB marks the memory bank as active. In some cases, arbitration of the MIB may be performed by the MIB's command arbiter.

[0048] Each MIB can perform various types of arbitration. For example, an MIB can perform bank arbitration and channel arbitration (e.g., pseudo-channel arbitration). In some embodiments, one or more MIBs may use a round-robin arbitration process to determine which commands should be communicated over a shared data channel (as described with reference to Figure 4). That is, if an MIB receives multiple column or row commands to be transmitted over the MIB's shared channel, the MIB may perform a round-robin or priority-based arbitration process to determine which column or row command will be transmitted and executed first. Similarly, one or more MIBs may perform an arbitration process to determine which of the relevant banks may be available for performing an operation. For example, an MIB may determine which bank to assign an operation to by comparing the operation type of the column in each bank (e.g., read operation, write operation) with the operation type of the received command. In some cases, an MIB may assign a write operation command, which involves consecutive write traffic on the relevant data channel, to a memory bank.

[0049] In some embodiments, each MIB may perform a pre-bank arbitration process. For example, each memory bank of an MIB may perform an arbitration process to prepare incoming commands and pending operations. As a result of this pre-bank arbitration process, the MIB can determine that a bank is ready to receive a command and can then assign the command (particularly a write command) to the respective bank.

[0050] At 505, the process may determine that the row is active (for example, by the MIB or other scheduler associated with the memory system). If the row is active, the process proceeds to 520, where it may determine whether the active row has been open for too long. If the row is not active, at 510, it may determine whether a refresh operation should be performed on the active row.

[0051] In step 510, it may be determined that the bank's active rows should undergo a refresh operation. If it is determined that refreshing the active rows would be beneficial, in step 535, an automatic refresh operation may be initiated. If it is determined that refreshing the active rows would not be beneficial, in step 525, it may be determined whether further requests have been received.

[0052] At 515, it may be determined that the request has been received. If the request has been received, it may be pending, and at 540, the request may be activated. If the request has not been received, at 545, the active row may wait for further action.

[0053] At 520, it may be determined that the active row has been open for too long. If the active row has been open for too long, at 560, a precharge operation may be initiated. If the active row has not been open for too long, at 525, it may be determined whether the request has been received.

[0054] At step 525, it may be determined that the request has been received. If the request has been received, at step 530, it may be determined that a previous request executed by the bank contained a different row than the active row of the current request. If the request has not been received, at step 545, the active row may wait for further operations.

[0055] At 530, it may be determined that a previous request executed by the bank contained a different row than the active row of the current request. If the previous request contained a different active row, the request may be executed at 555. If the previous request did not contain a different active row, the request may be executed at 550.

[0056] At step 535, an automatic refresh operation may be initiated. As part of initiating the automatic refresh command, a row command may be determined with respect to the bank (e.g., by the MIB or other scheduler associated with the memory system). For example, the MIB may determine that a column command is not used as part of the automatic refresh command, and that a row command is used as part of the automatic refresh command. Then, at step 565, it may be determined (e.g., by the MIB or other scheduler associated with the memory system) whether the command determined at step 535 is ready to communicate. If so, the command is transmitted to the bank (e.g., by the MIB or other scheduler associated with the memory system). Otherwise, the command may be canceled, and the arbitration process may be restarted.

[0057] In step 540, pending requests may be activated. As part of activating the requests, row commands may be determined with respect to the bank (e.g., by the MIB or other schedulers associated with the memory system). For example, the MIB may determine that column commands are not used as part of request activation, and that row commands are used as part of request activation. Then, in step 570, it may be determined (e.g., by the MIB or other schedulers associated with the memory system) whether the commands determined in step 540 are ready to communicate. If so, the commands are transmitted to the bank (e.g., by the MIB or other schedulers associated with the memory system). Otherwise, the commands may be canceled, and the arbitration process may restart.

[0058] In step 545, the active row may wait for a new request or a new arbitration process to begin. For example, it may be decided that neither column nor row commands will be used during this arbitration process. Therefore, the active row in the current bank may wait for a new arbitration process to begin.

[0059] In 550, pending requests may be executed. As part of the execution of the requests, column commands may be determined with respect to the bank (e.g., by the MIB or other schedulers associated with the memory system). For example, the MIB may determine that column commands will be used as part of an access operation (e.g., a read operation, a write operation), and that row commands will not be used as part of an operation. Then, in 575, it may be determined (e.g., by the MIB or other schedulers associated with the memory system) whether the commands determined in 550 are in a state where they can be communicated. If so, the commands are transmitted to the bank (e.g., by the MIB or other schedulers associated with the memory system). Otherwise, the commands may be canceled, and the arbitration process may restart.

[0060] In 555, pending requests may be executed. As part of the execution of the requests, column commands may be determined with respect to the bank (e.g., by the MIB or other schedulers associated with the memory system). For example, the MIB may determine that column commands will be used as part of access operations (e.g., read operations, write operations) and / or auto-precharge operations, and that row commands will not be used as part of operations. Then, in 580, it may be determined (e.g., by the MIB or other schedulers associated with the memory system) whether the commands determined in 555 are in a state where they can be communicated. If so, the commands are transmitted to the bank (e.g., by the MIB or other schedulers associated with the memory system). Otherwise, the commands may be canceled, and the arbitration process may restart.

[0061] In step 560, a precharge operation may be initiated. As part of the precharge command, a row command may be determined with respect to the bank (e.g., by the MIB or other scheduler associated with the memory system). For example, the MIB may determine that a column command is not used as part of the precharge command, and that a row command is used as part of the precharge command. Then, in step 585, it may be determined (e.g., by the MIB or other scheduler associated with the memory system) whether the command determined in step 560 is ready to communicate. If so, the command is transmitted to the bank (e.g., by the MIB or other scheduler associated with the memory system). Otherwise, the command may be canceled, and the arbitration process may be restarted.

[0062] Figure 6 is a block diagram 600 of a memory system 620 that supports memory scheduling according to embodiments disclosed herein. Memory system 620 may be an example of an embodiment of a memory system described with reference to Figures 1-5. Memory system 620 or its various components may be an example of means for performing various embodiments of memory scheduling described herein. For example, memory system 620 may include an interface block component 625, a command component 630, an access component 635, an operation component 640, a buffer component 645, a selection component 650, a detection component 655, or any combination thereof. Each of these components may communicate with one another directly or indirectly (e.g., via one or more buses).

[0063] The interface block component 625 is configured as a means for receiving commands from the controller to access a volatile memory device coupled to the controller, or may otherwise support such a means, the volatile memory device includes channels coupled to a bank set including a first bank and a second bank, the channels including a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first bank and the second bank. The command component 630 is configured as a means for assigning commands to the first bank of the volatile memory device, or may otherwise support such a means. In some embodiments, the command component 630 is configured as a means for determining a command sequence to be communicated over the control channel set based on commands assigned to the first bank associated with the channels and one or more other commands assigned to the second bank, or may otherwise support such a means. The access component 635 is configured as a means for accessing the first bank of the volatile memory device based on the determination of the command sequence, or may otherwise support such a means.

[0064] In some embodiments, the interface block component 625 is configured as a means for receiving instructions from the controller to prioritize one command over another, or may otherwise support such means, and command assignment is based on the receipt of instructions.

[0065] In some embodiments, the buffer component 645 is configured as a means for inserting a command at the head of a queue associated with a first bank based on the reception of an instruction, or may otherwise support such a means, and the determination of the command sequence is based on the insertion of the command at the head of the queue.

[0066] In some embodiments, the selection component 650 is configured as a means for selecting a first bank to execute a command based on the receipt of an instruction, or may support such means in other ways, and the assignment of the first bank is based on the selection of the first bank.

[0067] In some embodiments, the operational component 640 may be configured as a means for initiating media management operations for a volatile memory device based on access to a first bank, or may support such means in other ways.

[0068] In some embodiments, to support the initiation of a media management operation, the detection component 655 may be configured as a means for detecting the possibility of one or more errors caused by a low hammer event based on access to a first bank, or may otherwise support such a means. In some embodiments, to support the initiation of a media management operation, the operation component 640 may be configured as a means for initiating a low hammer mitigation operation based on the detection of the possibility, or may otherwise support such a means.

[0069] In some embodiments, to support the initiation of media management operations, the operation component 640 may be configured as a means for initiating a refresh operation on the first bank based on access to the first bank, or may support such a means in other ways.

[0070] In some embodiments, to support the initiation of a media management operation, the operation component 640 may be configured as a means for initiating a repair operation to repair rows, columns, or through-silicon electrodes via the first bank, based on access to the first bank, or may support such means in other ways.

[0071] In some embodiments, to support the initiation of media management operations, the operation component 640 may be configured as a means for initiating error control operations with respect to the first bank based on access to the first bank, or may support such means in other ways.

[0072] In some embodiments, media management operations are initiated without receiving instructions from the controller.

[0073] In some embodiments, the interface block component 625 is configured as a means for identifying a first performance parameter of a first bank and a second performance parameter of a second bank, or may support such means in other ways, and the assignment of commands to the first bank is based on the first and second performance parameters.

[0074] In some embodiments, to support the determination of the command sequence, the command component 630 may be configured as a means for determining the priority and hold periods of commands, or may support such means in other ways, and the determination of the command sequence is based on the priority and hold periods.

[0075] In some embodiments, to support the determination of a command sequence, the command component 630 may be configured as a means for determining a first command sequence relating to a first bank, including row and column commands associated with a first command sequence, or may otherwise support such a means. In some embodiments, to support the determination of a command sequence, the command component 630 may be configured as a means for determining a second command sequence relating to a second bank, including row and column commands associated with a second command sequence, or may otherwise support such a means, and the command sequence communicated over the channel's control channel set is based on the row and column commands associated with the first command sequence and the row and column commands associated with the second command sequence.

[0076] In some embodiments, the interface block component 625 may be configured as a means for determining whether column commands, row commands, or both should be communicated via a control channel set of channels as part of command execution, or may support such means in other ways, and the command sequence determination is based on the determination of whether column commands, row commands, or both should be communicated.

[0077] Figure 7 is a flowchart of Method 700 supporting memory scheduling according to embodiments disclosed herein. The operation of Method 700 may be implemented by a memory system or its components as described herein. For example, the operation of Method 700 may be performed by a memory system as described with reference to Figures 1-6. In some embodiments, the memory system may execute a set of instructions for controlling the functional elements of the device to perform the functions described above. As an addition or alternative, a wireless memory system may perform aspects of the functions described above using dedicated hardware.

[0078] In 705, the method may include receiving a command from a controller to access a volatile memory device coupled to the controller, the volatile memory device including channels coupled to a set of banks including a first bank and a second bank, the channels including a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first bank and the second bank. The operation of 705 may be performed according to embodiments disclosed herein. In some embodiments, the memory system may include one or more MIBs 405 that can receive a command from a controller (e.g., memory controller 445 in Figure 4) to access a volatile memory device coupled to the controller, the volatile memory device including channels coupled to a set of banks (e.g., bank 470) including a first bank and a second bank, the channels including a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first bank and the second bank. In some embodiments, aspects of the operation of 705 may be performed by the interface block component 625, as described with reference to Figure 6.

[0079] In 710, this method may include assigning commands to a first bank of volatile memory devices. The operation of 710 may be performed according to embodiments disclosed herein. In some embodiments, the memory system may include one or more command arbiters 420 that can assign commands to a first bank of volatile memory devices. In some embodiments, aspects of the operation of 710 may be performed by a command component 630, as described with reference to Figure 6.

[0080] In 715, this method may include determining a command sequence to be communicated over the control channel set based on commands assigned to a first bank associated with the channel and one or more other commands assigned to a second bank. The operation of 715 may be performed according to embodiments disclosed herein. In some embodiments, one of the command arbiters 420 of the memory system may determine a command sequence to be communicated over the control channel set based on commands assigned to a first bank associated with the channel and one or more other commands assigned to a second bank. In some embodiments, aspects of the operation of 715 may be performed by a command component 630 as described with reference to Figure 6.

[0081] In 720, this method may include accessing a first bank of volatile memory devices based on the determination of a command sequence. The operation of 720 may be performed according to embodiments disclosed herein. In some embodiments, the memory system may include one or more bank controllers 410 that can access a first bank of volatile memory devices based on the determination of a command sequence. In some embodiments, aspects of the operation of 720 may be performed by an access component 635 as described with reference to Figure 6.

[0082] In some embodiments, the apparatus described herein can perform one or more methods, such as method 700. The apparatus may include functions, circuit configurations, logic, means, or instructions (e.g., a non-temporary computer-readable medium for storing instructions executable by a processor), or any combination thereof, for performing the following embodiments of the disclosure.

[0083] Embodiment 1: A method, apparatus, or non-temporary computer-readable medium including operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for receiving a command from a controller to access a volatile memory device coupled to the controller, wherein the volatile memory device comprises a channel coupled to a bank set comprising a first bank and a second bank, the channel comprising a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first bank and the second bank; assigning a command to the first bank of the volatile memory device; determining a command sequence to be communicated via the control channel set based on the command assigned to the first bank and one or more other commands assigned to the second bank associated with the channel; and accessing the first bank of the volatile memory device based on the determination of the command sequence.

[0084] Embodiment 2: The method, apparatus, or non-temporary computer-readable medium of Embodiment 1, further comprising an operation, feature, circuit configuration, logic, means, or instruction, or any combination thereof, for receiving instructions from a controller to prioritize the above command over other commands, wherein the assignment of the command is based on the receipt of instructions.

[0085] Embodiment 3: The method, apparatus, or non-temporary computer-readable medium of Embodiment 2, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for performing operations, features, circuit configurations, logic, means, or instructions for performing operations, features, circuit configurations, logic, means, or instructions for performing operations, features, circuit configurations, logic, means, or instructions for performing operations, features, circuit configurations, means, or instructions for performing operations, features, configurations, or instructions for performing operations, features, configurations, means means, or instructions for performing operations, based on the receipt of instructions, wherein the determination of the command sequence is based on the insertion of a command into the queue.

[0086] Embodiment 4: Further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for selecting a first bank to execute a command based on the receipt of an instruction, wherein the assignment of the first bank is based on the selection of the first bank, the method, apparatus, or non-temporary computer-readable medium of Embodiment 2 or 3.

[0087] Embodiment 5: A method, apparatus, or non-temporary computer-readable medium of any one of Embodiments 1 to 4, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for initiating a media management operation for a volatile memory device based on access to a first bank.

[0088] Embodiment 6: The method, apparatus, or non-temporary computer-readable media according to Embodiment 5, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for initiating a media management operation, based on access to a first bank, detecting the possibility of one or more errors caused by a low hammer event, and initiating a low hammer mitigation operation based on the detection of the possibility.

[0089] Embodiment 7: The method, apparatus, or non-temporary computer-readable medium of Embodiment 5 or 6, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for initiating a media management operation, which in turn initiates a refresh operation relating to a first bank based on access to the first bank.

[0090] Embodiment 8: A method, apparatus, or non-temporary computer-readable medium according to any one of Embodiments 5 to 7, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for initiating a media management operation, which, based on access to the first bank, initiates a repair operation for repairing rows, columns, or through-silicon electrodes of the first bank.

[0091] Aspect 9: A method, apparatus, or non-temporary computer-readable medium according to any one of aspects 5 to 8, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for initiating a media management operation, which in turn initiates an error control operation relating to a first bank based on access to the first bank.

[0092] Embodiment 10: A method, apparatus, or non-transient computer-readable medium according to any one of Embodiments 5 to 9, wherein a media management operation is initiated without receiving instructions from a controller.

[0093] Embodiment 11: A method, apparatus, or non-temporary computer-readable medium according to any one of Embodiments 1 to 10, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for identifying a first performance parameter of a first bank and a second performance parameter of a second bank, wherein the assignment of a command to the first bank is based on the first and second performance parameters.

[0094] Embodiment 12: A method, apparatus, or non-temporary computer-readable medium by which determining a command sequence further includes operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for determining the priority of commands and the hold periods of commands, wherein the determination of a command sequence is based on priority and hold periods.

[0095] Embodiment 13: A method, apparatus, or non-temporary computer-readable medium by any one of Embodiments 1 to 12, wherein determining a command sequence involves determining a first command sequence relating to a first bank, including row and column commands associated with a first command sequence, and determining a second command sequence relating to a second bank, including row and column commands associated with a second command sequence, and further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for doing so, where the command sequence communicated via a control channel set of channels is based on the row and column commands associated with the first command sequence and the row and column commands associated with the second command sequence.

[0096] Embodiment 14: A method, apparatus, or non-temporary computer-readable medium by any one of Embodiments 1 to 13, further comprising operations, features, circuit configurations, logic, means, or instructions, or any combination thereof, for determining whether a column command or a row command or both should be communicated through a control channel set of channels as part of the execution of a command, wherein the determination of the command sequence is based on the determination of whether a column command or a row command or both should be communicated.

[0097] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, it is also possible to combine parts from two or more methods.

[0098] The apparatus will now be described. The following provides an overview of the embodiments of the apparatus described herein.

[0099] Embodiment 15: An apparatus comprising a first die, one or more controllers associated with the first die, an interface block coupled to the first die, a second die, and a volatile memory device coupled to the second die, wherein the volatile memory device comprises a first bank of memory cells, a second bank of memory cells, and a first channel coupled to the first and second banks, the first channel including a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first and second banks, and the interface block is configured to schedule access operations relating to the first and second banks of the volatile memory device based on commands received from one or more controllers.

[0100] The information and signals described herein may be represented using any of the various different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some drawings may show a signal as a single signal. However, a signal may also represent a bus of signals, and the bus may have varying bit widths.

[0101] The terms “electronic communication,” “conductive contact,” “connection,” and “coupling” may describe relationships between components that support the flow of signals between them. Components are considered to be electronically communicating with each other (e.g., conductive contact, connection, coupling) if there is an electrical path (e.g., a conductive path) between them that can always support the flow of signals (e.g., charge, current, voltage) between them. A conductive path between components that are electronically communicating with each other (e.g., conductive contact, connection, coupling) at any given time may be an open or closed circuit, based on the operation of the device containing the connected components. A conductive path between connected components may be a direct conductive path between components, or it may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some embodiments, the flow of signals between connected components may be temporarily interrupted by one or more intermediate components, such as switches or transistors.

[0102] The term "coupling" (e.g., "electrical coupling") can describe a transition from an open-circuit relationship between components, where signals cannot currently communicate with each other (e.g., via conductive paths), to a closed-circuit relationship between components, where signals can communicate with each other (e.g., via conductive paths). When a component such as a controller couples other components together, it initiates a change that allows signals to flow between those components via conductive paths that were previously not permitted.

[0103] The term "isolation" describes a relationship between components where signals cannot currently flow between them. Components are isolated from each other when there is an open circuit between them. For example, two components separated by a positioning switch are isolated from each other when the switch is open. When a controller isolates two components, it makes changes to the conductive paths that previously allowed signals to flow, so that signals cannot flow between the components.

[0104] As used herein, the terms “layer” and “level” refer to the geometric structure (e.g., layers, sheets) of a substrate. Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of the surface. For example, a layer or level may be a three-dimensional structure (e.g., a thin film) in which two dimensions are greater than the third dimension. A layer or level may contain various elements, components, or materials. In some embodiments, a single layer or level may consist of two or more sublayers or sublevels.

[0105] Devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a portion of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0106] The switching components (e.g., transistors) discussed herein may represent field-effect transistors (FETs), which may comprise a three-terminal component including a source (e.g., source terminal), a drain (e.g., drain terminal), and a gate (e.g., gate terminal). The terminals may be connected to other electronic components via a conductive material (e.g., metal, alloy). The source and drain may be conductive and may include doped (e.g., highly doped, degenerate) semiconductor regions. The source and drain may be separated by a doped (e.g., lightly doped) semiconductor region or channel. If the channel is n-type (e.g., majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (e.g., majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel may be controlled by applying a voltage to the gate. For example, the channel may become conductive by applying a positive or negative voltage to an n-type FET or a p-type FET, respectively. When a voltage above the transistor's threshold voltage is applied to the transistor's gate, the transistor can become "on" or "active." When a voltage below the transistor's threshold voltage is applied to the transistor's gate, the transistor can become "off" or "inactive."

[0107] The descriptions provided herein in relation to the accompanying drawings are illustrative and do not represent all possible embodiments or embodiments within the scope of the claims. The term “exemplary” as used herein means “serving as an example, case, or illustration,” and not “preferred” or “advantageous over other embodiments.” Detailed descriptions include specific details to facilitate understanding of the techniques described; however, these techniques can be practiced without these specific details. Furthermore, well-known structures and devices are shown in block diagram form to avoid ambiguity regarding the concepts of the embodiments described.

[0108] In the attached figures, similar components or functions may be given the same reference numeral. Furthermore, various components of the same type may be distinguished by adding a dash and a second label after the reference label to differentiate similar components. Where only the first reference label is used herein, the description is applicable to any similar component having the same first reference label, regardless of the second reference label.

[0109] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored in or transmitted via a computer-readable medium as one or more instructions (e.g., code). Other embodiments and implementations are within the scope of this disclosure and the accompanying claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various locations, including the distribution of some functions to be implemented in different physical locations.

[0110] For example, various exemplary blocks and modules described in connection with the disclosure herein may be implemented or run by processors such as DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, controller, microcontroller, state machine, or any other type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, a DSP core and one or more associated microprocessors, or any other such configuration).

[0111] When used herein, including in the claims, the word "or" used in an enumeration of items (for example, an enumeration of items with phrases such as "at least one" or "one or more") indicates an inclusive enumeration, for example, the enumeration "at least one of A, B, or C" means A, B, C, AB, AC, BC, or ABC (i.e., A, B, and C). Also, when used herein, the phrase "based on" is not to be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, when used herein, the phrase "based on" is to be interpreted similarly to the phrase "based on at least part of."

[0112] Computer-readable media include both non-temporary computer storage media and communication media, including any media that facilitates the transfer of computer programs from one location to another. Non-temporary storage media may be any available media that a computer can access. Examples, rather than limitations, include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD)ROM, or other optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other non-temporary media that can be used to carry or store desired program code means in the form of instructions or data structures and can be accessed by a computer or processor. Any connection is also appropriately called computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave are included in the definition of media. As used herein, "disk" and "disc" include CDs, laserdiscs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Typically, a "disk" reproduces data magnetically, while a "disc" reproduces data optically using a laser. Combinations of the above are also included in the scope of computer-readable media.

[0113] The descriptions herein are provided to enable those skilled in the art to implement or use the disclosure. Various modifications to the disclosure will be obvious to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the disclosure. Accordingly, the disclosure is not limited to the examples and designs described herein, but is given the broadest scope that is consistent with the principles and novel features disclosed herein.

Claims

1. Receiving a command from a controller to access a volatile memory device coupled to the controller, wherein the volatile memory device comprises channels coupled to a bank set comprising a first bank and a second bank, and the channels include a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first bank and the second bank. Assigning the command to the first bank of the volatile memory device, Determining a command sequence to be communicated via the control channel set based on the command assigned to the first bank associated with the channel and one or more other commands assigned to the second bank, Based on the determination of the command sequence, access the first bank of the volatile memory device. A method that includes this.

2. Receiving an instruction from the controller to prioritize the command over other commands, wherein the assignment of the command is based on the receipt of the instruction. The method according to claim 1, further comprising:

3. Based on the receipt of the instruction, insert the command at the beginning of the queue associated with the first bank, wherein the determination of the command sequence is based on the insertion of the command at the beginning of the queue. The method according to claim 2, further comprising:

4. Selecting the first bank to execute the command based on the receipt of the instruction, wherein the allocation of the first bank is based on the selection of the first bank. The method according to claim 2, further comprising:

5. Based on access to the first bank, media management operations for the volatile memory device are initiated. The method according to claim 1, further comprising:

6. Initiating the aforementioned media management operation Based on access to the first bank, the possibility of one or more errors caused by a low hammer event is detected, Based on the detection of the aforementioned possibility, a low hammer relaxation operation is initiated. The method according to claim 5, further comprising:

7. Initiating the aforementioned media management operation Based on access to the first bank, initiate a refresh operation on the first bank. The method according to claim 5, further comprising:

8. Initiating the aforementioned media management operation Based on access to the first bank, initiating a repair operation to repair a row, column, or through-silicon electrode of the first bank. The method according to claim 5, further comprising:

9. Initiating the aforementioned media management operation Based on access to the first bank, an error control operation relating to the first bank is initiated. The method according to claim 5, further comprising:

10. The method according to claim 5, wherein the media management operation is initiated without receiving instructions from the controller.

11. Identifying a first performance parameter of the first bank and a second performance parameter of the second bank, wherein the assignment of the command to the first bank is based on the first and second performance parameters. The method according to claim 1, further comprising:

12. Determining the aforementioned command sequence The priority of the command and the hold period for the command are determined such that the determination of the command sequence is based on the priority and the hold period. The method according to claim 1, further comprising:

13. Determining the aforementioned command sequence Determining the first command sequence relating to the first bank, which includes row commands and column commands associated with the first command sequence, Determining the second command sequence relating to the second bank, which includes row commands and column commands associated with the second command sequence, wherein the command sequence communicated over the control channel set of the channel is based on the row commands and column commands associated with the first command sequence and the row commands and column commands associated with the second command sequence. The method according to claim 1, further comprising:

14. As part of the execution of the command, a determination is made as to whether a column command, a row command, or both should be communicated via the control channel set of the channel, and the determination of the command sequence is based on the determination as to whether a column command, a row command, or both should be communicated. The method according to claim 1, further comprising:

15. The first die, One or more controllers associated with the first die, The interface block coupled to the first die, The second die, An apparatus comprising a volatile memory device coupled to the second die, wherein the volatile memory device is The first bank of memory cells, The second bank of memory cells, A first channel coupled to the first bank and the second bank, comprising a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first bank and the second bank. Equipped with, The interface block is configured to schedule access operations for the first and second banks of the volatile memory device based on commands received from one or more controllers. Device.

16. The aforementioned interface block, One of the commands received from the one or more controllers is assigned to the first bank of the volatile memory device. The controller receives instructions from one or more controllers to prioritize the command over other commands. The apparatus according to claim 15, further configured as follows.

17. The aforementioned interface block, Start media management operations related to the volatile memory device. The apparatus according to claim 15, further configured as follows.

18. The aforementioned interface block, Identification of the first performance parameter of the first bank and the second performance parameter of the second bank. The apparatus according to claim 15, further configured as follows.

19. The aforementioned interface block, Determines the priority of commands received from the one or more controllers and the hold period for those commands. The apparatus according to claim 15, further configured as follows.

20. A non-temporary computer-readable storage code, wherein the code is The controller receives a command to access a volatile memory device coupled to the controller, and the volatile memory device comprises channels coupled to a bank set comprising a first bank and a second bank, the channels comprising a first data channel set dedicated to the first bank, a second data channel set dedicated to the second bank, and a control channel set shared by the first bank and the second bank, The command is assigned to the first bank of the volatile memory device. Based on the command assigned to the first bank associated with the channel and one or more other commands assigned to the second bank, the command sequence to be communicated via the control channel set is determined. Based on the determination of the command sequence, access the first bank of the volatile memory device. Non-temporary computer-readable media storage code containing instructions that can be executed by a processor.

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