Aligned multichip devices

Abstract

Embodiments of this specification describe arranging TX and RX circuits within an IC such that rotated and mirrored ICs are aligned when connected in a multi-chip device. In one embodiment, the TX circuit (e.g., TX physical layer or PHY) is arranged in one row, while the RX circuit (e.g., RX physical layer or PHY) is arranged in another row. Thus, when the ICs are rotated or mirrored, at least one TX PHY is aligned with an RX PHY on another IC. This allows for the formation of non-intersecting inter-chip connections via an interposer.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to aligning transmit (TX) and receive (RX) circuits between integrated circuits (ICs) in a multi-chip device.

Background Art

[0002] Many devices include a plurality of ICs (or dies or chips) interconnected on a substrate or an interposer. That is, chip-to-chip connections can be used to form devices such as 1×2, 1×3, 1×4, etc. Typically, each of the ICs has a different tape-out (e.g., a different set of masks is used for each IC within the multi-chip device). One reason for this is to align the RX and TX circuits for chip-to-chip connections. That is, the chip-to-chip connections do not cross when navigating within the interposer. Thus, even if the ICs can have essentially the same hardware components (e.g., hardware modules), different tape-outs and mask sets are used, which is costly.

Summary of the Invention

[0003] One embodiment of this specification is a device comprising an interposer, a first IC disposed on the interposer and including a first row of transmit physical layers (TX PHY) parallel to the periphery of the first IC and a second row of receive physical layers (RX PHY) parallel to the periphery of the first IC, and a second IC disposed on the interposer and including a third row of TX PHY parallel to the periphery of the second IC and a fourth row of RX PHY parallel to the periphery of the second IC. The device also includes inter-chip connections in the interposer, where each RX PHY in the first IC is coupled to a TX PHY in the second IC, and each RX PHY in the second IC is coupled to a TX PHY in the first IC.

[0004] Another embodiment of this specification is a method comprising transmitting data from the first IC to the second IC and receiving data in the second IC, wherein the first and second ICs are arranged on an interposer, and using inter-chip connections within the interposer. The first IC includes a first row of transmit physical layer (TX PHY) parallel to the periphery of the first IC and a second row of receive physical layer (RX PHY) parallel to the periphery of the first IC, and the second IC includes a third row of TX PHY parallel to the periphery of the second IC and a fourth row of RX PHY parallel to the periphery of the second IC. Furthermore, the inter-chip connections couple each of the RX PHYs in the first IC to the TX PHY in the second IC, and each of the RX PHYs in the second IC to the TX PHY in the first IC.

[0005] Another embodiment of this specification is a device comprising an interposer, a first FPGA disposed on the interposer and including a first circuit design, and a second FPGA disposed on the interposer and including a second circuit design which is a mirror image of the first circuit design. Furthermore, the interposer provides a connection between the first FPGA and the second FPGA.

[0006] Another embodiment of this specification is a device comprising an interposer, a first FPGA disposed on the interposer and including a first circuit design, and a second FPGA disposed on the interposer and including the first circuit design, rotated relative to the first FPGA. Furthermore, the interposer provides a connection between the first FPGA and the second FPGA.

[0007] Other embodiments may be represented in the following non-limiting embodiments.

[0008] Example 1. A device comprising: an interposer; a first IC disposed on the interposer, comprising a first row of transmit physical layer (TX PHY) parallel to the periphery of the first IC and a second row of receive physical layer (RX PHY) parallel to the periphery of the first IC; a second IC disposed on the interposer, comprising a third row of TX PHY parallel to the periphery of the second IC and a fourth row of RX PHY parallel to the periphery of the second IC; and an inter-chip connection in the interposer, which couples each of the RX PHYs in the first IC to a TX PHY in the second IC, and couples each of the RX PHYs in the second IC to a TX PHY in the first IC.

[0009] Example 2. The device described in Example 1, wherein the inter-chip connections are not crossed.

[0010] Example 3. The device according to Example 2, wherein each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the second IC, and each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the first IC.

[0011] Example 4. The device according to Example 1, wherein the first column is different from the second column, and the third column is different from the fourth column.

[0012] Example 5. The device according to Example 1, wherein the first IC has a circuit layout that mirrors the circuit layout of the second IC.

[0013] Example 6. The device according to Example 5, wherein bit reordering is not performed by the first IC and the second IC on bits received by the inter-chip connection.

[0014] Example 7. The device according to Example 1, wherein the first IC has the same circuit layout as the second IC, and the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC.

[0015] Example 8. The device according to Example 7, wherein the first IC and the second IC are configured to perform bit sorting on bits received by the inter-chip connection.

[0016] Example 9. The device according to Example 1, further comprising a third IC disposed on an interposer, the third IC including a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, wherein the interchip connections couple each of the RX PHYs in the third IC to a TX PHY in the first IC, and each of the RX PHYs in the first IC to a TX PHY in the third IC.

[0017] Example 10. The device according to Example 9, further comprising a fourth IC disposed on an interposer, the fourth IC including a seventh row of TX PHYs parallel to the periphery of the fourth IC and an eighth row of RX PHYs parallel to the periphery of the fourth IC, wherein the first, second, third and fourth ICs are disposed in a 2x2 configuration, and the inter-chip connections are such that each RX PHY in the fourth IC is coupled to a TX PHY in the second IC, and each RX PHY in the second IC is coupled to a TX PHY in the fourth IC, and the inter-chip connections are such that each RX PHY in the fourth IC is coupled to a TX PHY in the third IC, and each RX PHY in the third IC is coupled to a TX PHY in the fourth IC.

[0018] Example 11. A method comprising transmitting data from the first IC to the second IC and receiving data in the second IC using inter-chip connections within the interposer, wherein the first IC includes a first row of transmit physical layer (TX PHY) parallel to the periphery of the first IC and a second row of receive physical layer (RX PHY) parallel to the periphery of the first IC, and the second IC includes a third row of TX PHY parallel to the periphery of the second IC and a fourth row of RX PHY parallel to the periphery of the second IC, and the inter-chip connections couple each of the RX PHYs in the first IC to the TX PHY in the second IC and each of the RX PHYs in the second IC to the TX PHY in the first IC.

[0019] Example 12. The method according to Example 11, wherein the inter-chip connections are not crossed.

[0020] Example 13. The method according to Example 11, wherein each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the second IC, and each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the first IC.

[0021] Example 14. The method according to Example 11, wherein the first IC has a circuit layout that mirrors the circuit layout of the second IC.

[0022] Example 15. The method according to Example 14, wherein bit sorting is not performed by the first IC and the second IC on bits received by the inter-chip connection.

[0023] Example 16. The method according to Example 11, wherein the first IC has the same circuit layout as the second IC, and the circuit layout of the first IC is rotated 180 degrees relative to the circuit layout of the second IC.

[0024] Example 17. The method according to Example 16, further comprising performing a bit sort on data received by a second IC.

[0025] Example 18. The method according to Example 11, further comprising transmitting data from a first IC disposed on an interposer to a third IC, wherein the third IC includes a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, and the inter-chip connection couples each of the RX PHYs in the third IC to a TX PHY in the first IC, and each of the RX PHYs in the first IC to a TX PHY in the third IC.

[0026] Example 19. A device comprising an interposer, a first FPGA disposed on the interposer and including a first circuit design, and a second FPGA disposed on the interposer and including a second circuit design which is a mirror image of the first circuit design, wherein the interposer provides a connection between the first FPGA and the second FPGA.

[0027] Example 20. A device comprising an interposer, a first FPGA disposed on the interposer and including a first circuit design, and a second FPGA disposed on the interposer and including the first circuit design, wherein the second FPGA is rotated relative to the first FPGA, and the interposer provides a connection between the first FPGA and the second FPGA.

[0028] A more specific description, briefly summarized above, may be made in a manner that enables a detailed understanding of the features enumerated above, by reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical exemplary implementations and should not be considered as limiting in scope.

Brief Description of the Drawings

[0029] [Figure 1] Illustrates chip - to - chip connections of a device having different ICs according to an example. [Figure 2] Illustrates chip - to - chip connections of a device having mirrored ICs according to an example. [Figure 3] Illustrates chip - to - chip connections of a device having rotated ICs according to an example. [Figure 4] Illustrates chip - to - chip connections of a device having mirrored ICs with aligned TX and RX circuits according to an example. [Figure 5] Illustrates chip - to - chip connections of a device having rotated ICs with aligned TX and RX circuits according to an example. [Figure 6] A flowchart for use in operating a multi - chip device according to an example. [Figure 7] Illustrates a 2×2 configuration of ICs on an interposer according to an example.

Modes for Carrying Out the Invention

[0030] For ease of understanding, the same reference numerals are used to indicate identical elements common to the drawings, where possible. Elements of one embodiment are intended to be usefully incorporated into other embodiments.

[0031] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and that elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of features. They are not intended as an exhaustive description of the embodiments herein or as a limitation on the scope of the claims. In addition, illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment even if not illustrated or expressly described in that way.

[0032] Embodiments of this specification describe arranging TX and RX circuits within an IC such that rotated and mirrored ICs are aligned when connected in a multichip device. In one embodiment, the TX circuit (e.g., TX physical layer or PHY) is arranged in one row, while the RX circuit (e.g., RX physical layer or PHY) is arranged in another row. Thus, when the IC is rotated or mirrored, at least one TX PHY is aligned with the RX PHY on the other IC. Thus, non-intersecting interchip connections can be formed via the interposer. In the case of a rotated IC, although the TX and RX PHYs are aligned, the bits may need to be out of sort. Software or hardware may sort the bits before the data received from the IC is processed at the receiving IC.

[0033] Figure 1 illustrates an example of an inter-chip connection 120 of a device 100 having different ICs. In this example, device 100 includes an interposer 105 on which two ICs (i.e., IC110 and IC115) are arranged. The interposer 105 provides an inter-chip connection 120 between IC110 and IC115. For example, the interposer 105 may be a silicon interposer including one or more layers containing traces for forming the connection 120. In one embodiment, ICs 110 and 115 may be mounted on the interposer 105 using, for example, copper pillars, which then electrically couple ICs 110 and 115 to the connection 120 that routes electrical signals from one IC to the other.

[0034] In this embodiment, ICs 110 and 115 are formed from different tapeouts (e.g., different mask sets). ICs 110 and 115 may be application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), systems of chips (SoCs), etc. In one embodiment, ICs 110 and 115 may have the same or very similar functions, hardware modules, or hardware blocks. However, two ICs 110 and 115 may be formed using different tapeouts so that they have RX and TX circuits that align when placed side by side on the interposer 105.

[0035] The alignment between RX PHY125 and TX PHY130 is shown in more detail in the blowout section of Figure 1. In this example, RX PHY125A and 125B and TX PHY130A and 130B are located in IC110, and RX PHY125C and 125D and TX PHY130C and 130C are located in IC115. The inter-chip connection 120, passing through the interposer 105, connects RX PHY125A and 125B in IC110 to the corresponding TX PHY130C and 130C in IC115, and connects RX PHY125C and 125D in IC115 to the corresponding TX PHY130A and 130C in IC110. As shown, the connection 120 does not cross in the interposer 105. If connection 120 were to intersect, this would mean that connection 120 would need to be routed using multiple layers (for example, one of the intersecting connections would need to be routed on a different layer within the interposer 105). However, interposers typically have very few layers (e.g., three layers), which means that there are limited options for routing intersecting interchip connections within the interposer 105. If ICs 110 and 115 are created using multiple tape-outs, the TX and RX circuits can be aligned as shown, although having multiple tape-outs adds considerable manufacturing cost.

[0036] Preferably, if ICs 110 and 115 have substantially the same hardware module, using a single tape output for both ICs 110 and 115, while still aligning the TX and RX circuits, will save costs. This will be discussed in Figures 4 and 5.

[0037] Figure 2 illustrates an example of an inter-chip connection 220 of a device 200 having mirrored ICs. Specifically, device 200 includes an interposer 105 on which ICs 210 and 215 are arranged. In this example, IC 210 is a mirror image of IC 215. In other words, the circuit layout of IC 215 is a mirror image of the circuit layout of IC 210. This is illustrated by the letter "F," where the F in IC 210 is a mirror image of the F in IC 215.

[0038] To create a mirrored circuit layout for two ICs, after designing one of the ICs, a chip designer can instruct a software design application to mirror the design to generate a mirrored circuit layout for the other IC. This can be a much simpler design process than designing two different IC designs, such as IC110 and 115 in Figure 1. However, the blown section in Figure 2 illustrates that mirroring the circuit layout can result in misalignment of the TX and RX circuits within IC210 and 215.

[0039] In this example, the RX PHY225A and 225B and TX PHY230A and 230B are located in IC210, while the RX PHY225C and 225D and TX PHY230C and 230C are located in IC215. Furthermore, Figure 2 illustrates the mirrored strings "TX" and "RX" for TX PHY230A and 230B and RX PHY225A and 225B, respectively, in relation to TX PHY230C and 230D and RX PHY225C and 225D in IC215. This further illustrates the mirrored chip layout of IC210 and IC215.

[0040] The inter-chip connection 220 passing through the interposer 105 connects the RX PHY225A and 225B in IC210 to the corresponding TX PHY230C and 230C in IC215, and the RX PHY225C and 225D in IC215 to the corresponding TX PHY230A and 230C in IC210. ​​As shown, the connection 220 crosses at the interposer 105. This means that the connection 220 needs to be routed using multiple layers within the interposer 105. However, as considered above, the interposer 105 typically has very few layers, which means that there are limited options for routing the crossing inter-chip connections within the interposer 105. Therefore, due to the limited routing space within the interposer 105, it may be impossible to connect the mirrored IC210 and 215 using the interposer 105 (or a more expensive interposer with more layers would need to be used).

[0041] Figure 3 illustrates an example of inter-chip connectivity in device 300 having rotated ICs. Specifically, device 300 includes an interposer 105 on which ICs 310A and 30B are arranged. In this example, IC 310A has the same circuit layout or circuit design as IC 310B, but is rotated 180 degrees when placed on the interposer 105. In other words, IC 310 may be formed using the same tape-out or the same set of masks. Thus, IC 310 may be exactly the same, but one chip is rotated 180 degrees relative to the other. This is illustrated by the letter "F", where the F in IC 310A is rotated 180 degrees relative to the F in IC 310B.

[0042] The callout in Figure 3 illustrates that using the same rotated IC means that the TX and RX circuits in IC310A and 310B are aligned. In this example, RX PHY325A and 325B and TX PHY330A and 330B are in IC310A, while RX PHY325C and 325D and TX PHY330C and 330C are in IC310B. Furthermore, Figure 3 illustrates the rotated strings "TX" and "RX" in TX PHY230A and 230B and RX PHY225A and 225B relative to TX PHY230C and 230D and RX PHY225C and 225D in IC310B. That is, the strings "TX" and "RX" are rotated 180 degrees in IC310A relative to the strings in IC310B.

[0043] The inter-chip connection 320, passing through the interposer 105, connects the RX PHY325A and 325B in IC310A to the corresponding TX PHY330C and 330C in IC310B, and the RX PHY325C and 325D in IC310B to the corresponding TX PHY330A and 330C in IC310A. As shown, the connection 320 does not cross in the interposer 105, which provides the advantages discussed above. This means that the connection 220 does not need to be routed using multiple layers within the interposer 105. Thus, this arrangement of RX PHY325 and TX PHY330 provides aligned circuitry when using the same but rotated ICs. However, the embodiments described in Figures 4 and 5 provide a different configuration that provides aligned TX and RX circuitry for both mirror image ICs (e.g., Figure 2) and rotated ICs (e.g., Figure 3).

[0044] Figure 4 illustrates an example of inter-chip connectivity of a device 400 having mirrored ICs with aligned TX and RX circuits. Specifically, device 400 includes an interposer 105 on which ICs 410 and 415 are arranged. In this example, IC 410 is a mirror image of IC 415. In other words, the circuit layout of IC 415 is a mirror image of the circuit layout of IC 410. This is illustrated by the letter "F," where the F in IC 410 is a mirror image of the F in IC 415. As already discussed above, mirror image circuit layouts can be a much simpler design process than designing two different IC designs, such as ICs 110 and 115 in Figure 1.

[0045] Unlike Figure 2, where arranging two mirrored ICs side-by-side results in misalignment of the TX and RX circuits, the blowout in Figure 4 illustrates that the mirrored TX and RX circuits within ICs 410 and 415 are aligned. In this example, the RX PHY425A and 425B and TX PHY430A and 430B are located in IC 410, while the RX PHY425C and 425D and TX PHY430C and 430C are located in IC 415. Furthermore, Figure 4 illustrates the mirrored strings "TX" and "RX" of TX PHY430A and 430B and RX PHY425A and 425B relative to TX PHY430C and 430D and RX PHY425C and 425D within IC 415. This further illustrates the mirrored chip layout of ICs 410 and 415.

[0046] In particular, instead of arranging the RX PHY and TX PHY in columns in Figure 2, in Figure 4, the RX PHY and TX PHY are arranged in rows in ICs 410 and 415. Therefore, when the circuit layouts are mirrored, at least one RX PHY 425 in one of the ICs aligns with the TX PHY 430 in the other IC. Thus, arranging the RX and TX PHYs in rows around the periphery of ICs 410 and 415 results in the RX and TX PHYs being aligned when the ICs are arranged side by side within device 400. In other words, the RX PHY is located in a first row parallel to the periphery of the ICs, and the TX PHY is located in a second, different row parallel to the periphery of the ICs. Figure 4 illustrates that the row containing the RX PHY 425 is closer to the periphery of ICs 410 and 415 than the row containing the TX PHY 430, but this can be reversed so that the row containing the TX PHY 430 is closer to the periphery.

[0047] Figure 5 illustrates an example of inter-chip connectivity in a device 500 having rotated ICs with aligned TX and RX circuits. Specifically, device 500 includes an interposer 105 on which ICs 510A and 510B are arranged. In this example, IC 510A has the same circuit layout or design as 510B, but is rotated 180 degrees when placed on the interposer 105. In other words, IC 510 may be formed using the same tape-out or the same set of masks. Thus, IC 510 may be exactly the same, but one chip is rotated 180 degrees relative to the other. This is illustrated by the letter "F", where the F in IC 510A is rotated 180 degrees relative to the F in IC 510B.

[0048] The callout in Figure 5 illustrates that using the same rotated IC means that the TX and RX circuits in IC510A and 510B are aligned. In this example, RX PHY525A and 525B and TX PHY530A and 530B are in IC510A, while RX PHY525C and 525D and TX PHY530C and 530C are in IC510B. Furthermore, Figure 5 illustrates the rotated strings "TX" and "RX" in TX PHY530A and 530B and RX PHY525A and 525B relative to TX PHY530C and 530D and RX PHY525C and 525D in IC510B. That is, the strings "TX" and "RX" are rotated 180 degrees in IC510A relative to the strings in IC510B.

[0049] The inter-chip connection 520, passing through the interposer 105, connects the RX PHY525A and 525B in IC510A to the corresponding TX PHY530C and 530C in IC510B, and the RX PHY525C and 525D in IC510B to the corresponding TX PHY530A and 530C in IC510A. As shown, connection 520 does not cross in the interposer 105, which provides the advantages discussed above. This means that connection 20 does not need to be routed using multiple layers within the interposer 105. Thus, as in Figure 3, the arrangement of RX PHY525 and TX PHY530 in Figure 5 provides aligned circuitry when using the same but rotated ICs. In other words, if the RX PHY525 and TX PHY530 are arranged in rows on the periphery of IC510, they will still be aligned when IC510A is rotated 180 degrees relative to IC510B, similar to the column arrangement of TX and RX PHYs illustrated in IC310 in Figure 3. Thus, Figures 4 and 5 illustrate that arranging the RX PHY and TX PHY in rows on the periphery of the IC results in aligned TX and RX circuits (e.g., non-crossing inter-chip connections in interposer 105) for both mirrored and rotated ICs.

[0050] However, when IC510 is rotated relative to each other, the TX and RX circuits are aligned, but the bits transmitted between RX PHY525 and TX PHY530 may be out of order. This is because, upon rotation, the RX PHY and TX PHY in IC510A are aligned with different RX PHY and TX PHY in IC510B. In other words, unlike the mirrored IC embodiment in Figure 4, the RX PHY and TX PHY in IC510A are aligned with different RX PHY and TX PHY in IC510B, which can result in bits transmitted by the TX PHY and received by the RX PHY being out of order.

[0051] However, incorrect bit ordering can occur at the inter-chip interface (for other reasons). There are various different bit reordering techniques that may be used to reorder bits after they have been received by the RX PHY525. That is, bits may be reordered by hardware or software elements within the receiving IC before the data is processed by other circuits within the receiving IC.

[0052] Figures 4 and 5 illustrate a 1x2 configuration (e.g., one column and two rows of ICs), but in other embodiments, the device may have a 1x3 or 1x4 configuration. In that case, some of the ICs may have a tip-to-touch connection with two ICs (e.g., using the top and bottom sides).

[0053] In one embodiment, the ICs in Figures 4 and 5 can be ASICs, FPGAs, SoCs, etc. For example, in the case of FPGAs, typically two different tape-outs are used to connect two FPGAs having different circuit designs or circuit layouts onto the same interposer. Therefore, the ability to mount two FPGAs using mirror images of their circuit layouts, or to rotate two FPGAs having the same circuit layout as described herein, can be particularly advantageous as it reduces the complexity of generating mask sets for two tape-outs or allows the use of only one tape-out.

[0054] Figure 6 is a flowchart of method 600 for using to operate a multichip device, as an example. In block 605, the first IC transmits data to the second IC using inter-chip connections in an interposer, and the first and second ICs are arranged on the interposer. Furthermore, the TX and RX PHYs on the first and second ICs may be arranged as shown in Figures 4 and 5, with the first IC including a first row of TX PHYs parallel to the periphery of the first IC and a second row of RX PHYs parallel to the periphery of the first IC, and the second IC including a third row of TX PHYs parallel to the periphery of the second IC and a fourth row of RX PHYs parallel to the periphery of the second IC. Furthermore, the inter-chip connections couple each of the RX PHYs in the first IC to the TX PHY in the second IC, and each of the RX PHYs in the second IC to the TX PHY in the first IC.

[0055] In block 610, the second IC receives data from the first IC using the inter-chip connection in the interposer. Furthermore, the second IC can transmit data to the first IC using the inter-chip connection, either in parallel or at different times.

[0056] Figure 7 illustrates an example of a 2x2 configuration of IC705 on an interposer 700. In this top view, the IC705s are positioned at each corner of the interposer 700. The interposer 700 provides connections between adjacent IC705s. For example, the interposer 700 may be a silicon interposer including one or more layers containing traces for forming connections 710. In one embodiment, the IC705s may be mounted on the interposer using solder balls, which then electrically couple the IC705s to connections 710 that route electrical signals from one IC705 to an adjacent IC705.

[0057] Unlike 1x2, 1x3, or 1x4 configurations, where at least some of the ICs use only one side to communicate with adjacent ICs, in the 2x2 configuration shown in Figure 7, each IC 705 uses two sides to communicate with two adjacent ICs. For example, IC 705C communicates with IC 705D using the horizontal connection 710B and with IC 705A using the vertical connection 710A. Thus, the 2x2 configuration effectively doubles the amount of inter-chip connectivity each IC can have compared to some of the ICs in 1x2, 1x3, or 1x4 configurations that communicate using only one side.

[0058] IC705 in Figure 7 can use the TX and RX PHY arrangement illustrated in Figures 4 and 5, where the TX and RX PHYs are arranged in peripheral rows of IC705. In this way, whether IC705 is mirrored or rotated, the TX and RX PHYs can be aligned to form a non-intersecting connection 710 in the interposer 105.

[0059] In this embodiment, the interposer 700 has a surface area exceeding the reticle limit of the manufacturing technique used to produce the interposer. The size of IC705 is limited by the reticle limit, which defines the amount of area that can be exposed and processed using the mask. Currently, for monolithic dies, the maximum size is limited to the reticle limit of 33-26 mm. Therefore, the width and height of IC705 are limited by this reticle limit.

[0060] For the interposer 700 to support multiple ICs 705 that are at or just below the reticle limit, the interposer must have a surface area exceeding the reticle limit. This means that the interposer 700 cannot be manufactured using a single exposure process. Instead, the interposer 700 includes vertical stitches 720 and horizontal stitches 730 in which multiple exposure areas slightly overlap. This allows the interposer to still have traces for forming the connection 710 and to have sufficient surface area to support a 2x2 configuration of ICs 705.

[0061] In one embodiment, the interposer 700 has a total surface area three times the size of the reticle limit (e.g., the maximum reticle field). Furthermore, unlike interposers that support 1×2, 1×3, and 1×4 configurations which may have only horizontal stitching, the interposer 700 has both horizontal stitching 730 and vertical stitching 720.

[0062] The embodiments presented in this disclosure are referenced above. However, the scope of this disclosure is not limited to the specific embodiments described. Rather, any combination of the features and elements described is intended to implement and practice the intended embodiments, whether or not they relate to different embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Accordingly, the aforementioned aspects, features, embodiments, and advantages are merely illustrative and shall not be considered elements or limitations of the appended claims unless expressly enumerated in the claims.

[0063] As will be understood by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Accordingly, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments that combine software and hardware embodiments, which may all be collectively referred to herein as “circuits,” “modules,” or “systems.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media in which computer-readable program code is embodied.

[0064] Any combination of one or more computer-readable media may be used. A computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any preferred combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include electrical connections with one or more wires, portable computer floppy disks (registered trademark), hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any preferred combination thereof. In the context of this specification, a computer-readable storage medium is any tangible medium that can contain or store programs for use by, or in connection with, an instruction execution system, apparatus, or device.

[0065] A computer-readable signal medium may include, for example, a propagating data signal in which computer-readable program code is embodied, either in the baseband or as part of a carrier wave. Such a propagating signal may take any of various forms, including but not limited to electromagnetic, optical, or any preferred combination thereof. A computer-readable signal medium may be any computer-readable medium, rather than a computer-readable storage medium, that can communicate, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device.

[0066] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, fiber optic cable, RF, or any preferred combination thereof.

[0067] Computer program code for performing the operations of the embodiments of this disclosure may be written in any combination of one or more programming languages, including, for example, object-oriented programming languages ​​such as Java®, Smalltalk, and C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages. The program code may run entirely on the user's computer, partially as a standalone software package on the user's computer, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider).

[0068] Aspects of the present disclosure are described below with reference to the flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to the embodiments presented herein. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a general-purpose computer, a dedicated computer, or a processor of another programmable data processing device such that instructions executed via the processor of the computer or other programmable data processing device result in a machine that creates means for implementing the functions / actions specified in the blocks of the flowcharts and / or block diagrams.

[0069] These computer program instructions may also be stored in computer-readable storage media, and the instructions may also instruct computers, programmable data processing devices, and / or other devices to function in a particular manner, such as to produce products containing instructions that implement functions / actions specified in blocks of flowcharts and / or block diagrams.

[0070] Computer program instructions can also be loaded into a computer, other programmable data processing device, or other device to perform a series of operational steps on the computer, other programmable device, or other device, thereby generating a computer implementation process. Thus, instructions executed on a computer or other programmable device provide a process for implementing the functions / actions specified in the blocks of a flowchart and / or block diagram.

[0071] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur in a different order than shown in the figure. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs a specified function or action or a combination of dedicated hardware and computer instructions.

[0072] The above describes specific examples, but other and further examples may be devised without deviating from the basic scope, and that scope will be determined by the "Claims" below.

Claims

1. It is a device, Interposer and, A first IC disposed on the interposer, comprising a first row of a transmit physical layer (TX PHY) parallel to the periphery of the first IC, and a second row of a receive physical layer (RX PHY) parallel to the periphery of the first IC, A second IC disposed on the interposer, the second IC including a third row of TX PHY parallel to the peripheral edge of the second IC, and a fourth row of RX PHY parallel to the peripheral edge of the second IC, A device comprising an inter-chip connection in the interposer, where each of the RX PHYs in the first IC is coupled to the TX PHY in the second IC, and each of the RX PHYs in the second IC is coupled to the TX PHY in the first IC.

2. The device according to claim 1, wherein the inter-chip connections are not crossed.

3. The device according to claim 2, wherein each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the second IC, and each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the first IC.

4. The device according to claim 1, wherein the first IC has a circuit layout that mirrors the circuit layout of the second IC.

5. The device according to claim 4, wherein bit reordering is not performed by the first IC and the second IC on bits received by the inter-chip connection.

6. The device according to claim 1, wherein the first IC has the same circuit layout as the second IC, and the circuit layout of the first IC is rotated 180 degrees with respect to the circuit layout of the second IC.

7. The device according to claim 6, wherein the first IC and the second IC are configured to perform bit sorting on bits received by the inter-chip connection.

8. The device according to claim 1, further comprising a third IC disposed on the interposer, the third IC including a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, wherein the interchip connections couple each of the RX PHYs in the third IC to the TX PHYs in the first IC, and each of the RX PHYs in the first IC to the TX PHYs in the third IC.

9. A fourth IC is disposed on the interposer, further comprising a fourth IC including a seventh row of TX PHY parallel to the periphery of the fourth IC and an eighth row of RX PHY parallel to the periphery of the fourth IC, wherein the first, second, third, and fourth ICs are arranged in a 2x2 configuration. The inter-chip connection connects each of the RX PHYs in the fourth IC to the TX PHY in the second IC, and connects each of the RX PHYs in the second IC to the TX PHY in the fourth IC, The device according to claim 8, wherein the inter-chip connections connect each of the RX PHYs in the fourth IC to the TX PHY in the third IC, and connect each of the RX PHYs in the third IC to the TX PHY in the fourth IC.

10. It is a method, The first and second ICs are arranged on an interposer, and data is transmitted from the first IC to the second IC using the inter-chip connections within the interposer. The second IC receives the data, The first IC includes a first row of a transmitting physical layer (TX PHY) parallel to the periphery of the first IC, and a second row of a receiving physical layer (RX PHY) parallel to the periphery of the first IC, The second IC includes a third row of TX PHY parallel to the periphery of the second IC, and a fourth row of RX PHY parallel to the periphery of the second IC, A method in which the inter-chip connection is configured to connect each of the RX PHYs in the first IC to the TX PHY in the second IC, and connect each of the RX PHYs in the second IC to the TX PHY in the first IC.

11. The method according to claim 10, wherein the inter-chip connections are not crossed.

12. The method according to claim 10, wherein each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the second IC, and each of the TX PHYs in the first IC is aligned in the same column as one of the RX PHYs in the first IC.

13. The method according to claim 10, wherein the first IC has a circuit layout that mirrors the circuit layout of the second IC, and bit sorting is not performed by the first IC and the second IC on bits received by the inter-chip connection.

14. The method according to claim 10, further comprising performing a bit sort on the data received by the second IC, wherein the first IC has the same circuit layout as the second IC, and the circuit layout of the first IC is rotated 180 degrees with respect to the circuit layout of the second IC.

15. The method according to claim 10, further comprising transmitting data from the first IC disposed on the interposer to a third IC, wherein the third IC includes a fifth row of TX PHYs parallel to the periphery of the third IC and a sixth row of RX PHYs parallel to the periphery of the third IC, and the interchip connection couples each of the RX PHYs in the third IC to the TX PHYs in the first IC, and each of the RX PHYs in the first IC to the TX PHYs in the third IC.

16. It is a device, Interposer and, A first FPGA disposed on the interposer, comprising a first circuit design, A device comprising a second FPGA disposed on the interposer, wherein the interposer provides a connection between the first FPGA and the second FPGA, and the second FPGA includes a second circuit design, wherein the second FPGA is (a) a mirror image of the first circuit design, or (b) rotated relative to the first FPGA.

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