Electronic components placed on the core of the circuit board

Abstract

In one embodiment, the substrate includes a core comprising a core dielectric and a first conductive pattern on a first surface of the core dielectric, and a first metallization structure on the first surface of the core dielectric. The first metallization structure comprises a first dielectric, the first dielectric having a first opening formed therein. The substrate further includes a first electronic component disposed within the first opening of the first dielectric, and a first adhesive layer bonding the first electronic component to the core.

Description

Technical Field

[0001] The present disclosure relates to a substrate, and more particularly, to an electronic component placed on a core of the substrate.

Background Art

[0002] Integrated circuit (IC) technology has achieved great progress in improving computing power through miniaturization of electrical components. An IC can be implemented in the form of an IC chip having a set of electronic circuits integrated thereon. In some implementation forms, one or more IC chips can be physically held and protected by an IC package, and various power nodes and signal nodes of one or more IC chips can be electrically coupled to respective conductive terminals of the IC package via electrical paths formed in a package substrate of the IC package. Various packaging technologies can be found in many electronic devices including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing techniques can be used to implement composite devices such as multi-electronic component devices and system on a chip (SOC) devices, and these composite devices can include, for example, specific functions such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications), etc., and can include a plurality of functional blocks designed such that each functional block executes a specific function.

[0003] In some implementations, embedded electronic components such as deep trench capacitors are incorporated into IC packaging to improve performance and reduce package size. One factor driving the use of such embedded electronic components is the demand for products in a small form factor that have electrical performance equivalent to or better than that of larger electronic components. Depending on the size and / or thickness of the package substrate, and the size and / or process node of the IC chip held thereon, a process for embedding passive devices in a package substrate for one packaging task may not be suitable for another packaging task.

[0004] Therefore, there is a need for improved methods for embedding electronic components within substrates such as package substrates, which may be suitable for a wider range of packaging tasks. [Overview of the Initiative] [Means for solving the problem]

[0005] The following provides a simplified overview of one or more embodiments disclosed herein. Therefore, this overview should not be considered a broad overview of all intended embodiments, nor should it be considered to identify the main or important elements of all intended embodiments, or to define the scope relevant to any particular embodiment. Accordingly, the sole purpose of this overview is to provide, in a simplified form, certain concepts relating to one or more embodiments of the mechanisms disclosed herein, prior to the detailed descriptions presented below.

[0006] In one embodiment, the substrate includes a core comprising a core dielectric and a first conductive pattern on a first surface of the core dielectric; a first metallization structure on the first surface of the core dielectric, comprising a first dielectric, wherein the first dielectric has a first opening formed therein; a first electronic component disposed within the first opening of the first dielectric; and a first adhesive layer bonding the first electronic component to the core.

[0007] In one embodiment, a method for manufacturing a substrate includes forming a first dielectric on a core of a substrate, which includes a core dielectric and a first conductive pattern on a first surface of the core dielectric; forming a first dielectric, which is disposed on the first surface of the core dielectric and is a first part of a first metallization structure of the substrate; forming a first opening in the first dielectric, which exposes at least a first part of the core; attaching a first electronic component, which is disposed within the first opening in the first dielectric, to the core by a first adhesive layer that bonds the first electronic component to the core; and forming a second part of a first metallization structure on the first dielectric and the first electronic component.

[0008] In one embodiment, the electronic device includes a substrate, the substrate comprising a core including a core dielectric and a first conductive pattern on a first surface of the core dielectric; a first metallization structure on the first surface of the core dielectric, comprising a first dielectric, the first dielectric having a first opening formed therein; a first electronic component disposed within the first opening of the first dielectric; and a first adhesive layer bonding the first electronic component to the core.

[0009] Other purposes and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description.

[0010] A more complete understanding of many aspects of this disclosure and their associated advantages will be easier to obtain, as they will be better understood when considered together with the accompanying drawings, which are presented merely for illustrative purposes and not to limit this disclosure, by referring to the detailed description below. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view of a first exemplary substrate having embedded electronic components according to an aspect of the present disclosure. [Figure 2] This is a cross-sectional view of a second exemplary substrate having embedded electronic components according to an aspect of the present disclosure. [Figure 3] This is a cross-sectional view of an exemplary deep trench capacitor according to an aspect of the present disclosure. [Figure 4A] This is a cross-sectional view of a third exemplary substrate having embedded electronic components and integrated circuit (IC) devices according to an aspect of the present disclosure. [Figure 4B] This is an enlarged view of a certain area in Figure 4A according to the embodiments of this disclosure. [Figure 4C] This is a cross-sectional view of a fourth exemplary substrate having embedded electronic components and IC devices according to an aspect of the present disclosure. [Figure 5A] This is a cross-sectional view of a fifth exemplary substrate having embedded electronic components and IC devices according to an aspect of the present disclosure. [Figure 5B] This is an enlarged view of a certain area in Figure 5A according to the embodiments of this disclosure. [Figure 5C] This is a cross-sectional view of a sixth exemplary substrate having embedded electronic components and IC devices according to an aspect of the present disclosure. [Figure 6A] The structures at various stages in manufacturing the exemplary substrate shown in Figure 4A according to aspects of this disclosure are shown. [Figure 6B] The structures at various stages in manufacturing the exemplary substrate shown in Figure 4A according to aspects of this disclosure are shown. [Figure 6C] The structures at various stages in manufacturing the exemplary substrate shown in Figure 4A according to aspects of this disclosure are shown. [Figure 6D] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6E] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6F] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6G] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6H] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6I] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6J] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6K] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6L] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6M] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4A according to an aspect of the present disclosure. [Figure 6N] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4C according to an aspect of the present disclosure. [Figure 6O] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 4C according to an aspect of the present disclosure. [Figure 7A] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 5A according to an aspect of the present disclosure. [Figure 7B] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 5A according to an aspect of the present disclosure. [Figure 7C] Shows the structures at various stages of manufacturing the exemplary substrate of FIG. 5A according to an aspect of the present disclosure. [Figure 7D]Figure 5C shows the structure in the manufacturing stage of an exemplary substrate according to an aspect of this disclosure. [Figure 8] This disclosure describes a method for manufacturing a substrate according to an aspect of this disclosure. [Figure 9] A side view of a package including a surface mount substrate, an integrated device, and an integrated moisture sensor device according to an aspect of this disclosure is shown. [Figure 10] This is an illustrative flowchart of a method for manufacturing a package including a substrate, integrated devices, and integrated passive devices. [Figure 11] This figure shows various electronic devices that can integrate electronic components, electronic circuits, integrated devices, integrated passive devices, passive components, packages, and / or device packages as described herein. [Modes for carrying out the invention]

[0012] By convention, features shown in the drawings may not be depicted to scale. Therefore, the dimensions of the depicted features may be enlarged or reduced as appropriate for clarity. By convention, some of the drawings have been simplified for clarity. Therefore, the drawings may not depict all components of a particular apparatus or method. Furthermore, similar reference numerals indicate similar features throughout this specification and the drawings.

[0013] The aspects of this disclosure are provided in the following description and related drawings, which cover various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. In addition, well-known elements of this disclosure are not described in detail or are omitted so as not to obscure the relevant details of this disclosure.

[0014] In this specification, the terms “exemplary” and / or “example” are used to mean “to serve as an example, case, or illustration.” Any aspect described herein as “exemplary” and / or “example” should not necessarily be construed as being preferable or more advantageous than any other aspect. Similarly, the term “aspects of the disclosure” does not require that all aspects of the disclosure include the features, advantages, or modes of operation discussed.

[0015] Those skilled in the art will understand that the information and signals described below may be represented using any of a variety of different techniques and methods. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof, depending in part on the particular application, desired design, corresponding technology, etc.

[0016] Furthermore, many embodiments are described, for example, in terms of sequences of actions to be performed by elements of a computing device. It will be recognized that the various actions described herein can be performed by specific circuits (e.g., application-specific integrated circuits, ASICs), by program instructions executed by one or more processors, or a combination of both. In addition, the sequence(s) of actions described herein, when executed, can be considered to be fully embodied in any form of non-temporary computer-readable storage medium that stores a corresponding set of computer instructions that cause or instruct the relevant processors of the device to perform the functions described herein. Thus, the various embodiments of this disclosure can be embodied in several different forms, all of which are intended to fall within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, any corresponding form of such embodiment may be described herein, for example, as “logic configured to perform” the described actions.

[0017] Figure 1 is a cross-sectional view of a first exemplary substrate 100 having an embedded electronic component according to an aspect of the present disclosure. In this example, the substrate 100 includes a core 102 having a cavity 104 extending completely through the core 102. An electronic component 106 is disposed within the cavity 104. The electronic component 106 has a top surface 108 having metal terminals 110, the metal terminals 110 providing electrical connections to a device (e.g., a capacitor) configured within the electronic component 106.

[0018] According to various aspects of this disclosure, the substrates described herein (e.g., substrate 100), including cores and embedded electronic components, refer to package substrates. A package substrate is part of an integrated circuit package that provides the package with its mechanical strength and enables the circuitry of the integrated circuit to be electrically coupled to external devices. Such package substrates should be distinguished from other substrates, such as substrates that may be contained within the embedded electronic component itself, or dies containing the substrate (e.g., silicon substrates or other similar electronic devices).

[0019] The substrate 100 further includes a plurality of dielectric layers 112 covering the upper surface 116 of the core 102 and corresponding patterned metallization layers 114. The patterned metallization layers 118 are positioned on the upper surface 116 of the core 102 to provide an electrical connection between the metal terminals 110 of the electronic component 106 and the patterned metallization layers 114. In one embodiment, the same dielectric resin material used to form the plurality of dielectric layers 112 may be used in the gap region 109 of the cavity 104, between the sidewall of the electronic component 106 and the sidewall of the cavity 104. Dispensing the dielectric resin onto the electronic component 106 and into the gap region 109 helps to fix the electronic component 106 within the cavity 104, so that once the dielectric resin has cured, the metal terminals 110 maintain electrical contact with the corresponding portions of the patterned metallization layers 118.

[0020] In one embodiment, the uppermost patterned metallization layer 114 on the top surface 120 of the substrate 100 is connected to a plurality of metal terminals 122. The patterned metallization layer 114 provides a conductive path between the metal terminals 110 and 122 of the electronic component 106. In one embodiment, the plurality of metal terminals 122 may be configured to connect to an electronic package of a surface mount device (not shown in Figure 1).

[0021] In one embodiment, a further plurality of dielectric layers 132 and corresponding patterned metallization layers 134 cover the bottom surface 136 of the core 102. Here, a patterned metallization layer 138 is positioned on the bottom surface 136 of the core 102. The bottommost patterned metallization layer 134 on the bottom surface 140 of the substrate 100 is connected to a plurality of metal terminals 142. The patterned metallization layer 134 provides a conductive path to the metal terminals 142. In one embodiment, the plurality of metal terminals 142 may be configured to connect to an electronic package of a further surface mount device (not shown in Figure 1) or to a circuit board for connection to other devices.

[0022] In Figure 1, the electronic component 106 has a height H1 that is substantially the same as the thickness H2 of the core 102. During the manufacturing of the substrate 100, the electronic component 106 is inserted into the cavity 104 before dielectric resin is injected to fill the gap region 109 between the cavity 104 and the electronic component 106. During insertion, the electronic component 106 is carefully positioned within the cavity 104 to ensure that the metal terminals 110 make proper contact with the corresponding portion of the patterned metallization layer 118 and electrically bond to it. In addition, the injection of dielectric resin into the gap region 109 should be carried out with care not to disturb the initial positioning of the electronic component 106. In one embodiment, once the dielectric resin has cured, it fixes the electronic component 106 in its proper place within the cavity 104.

[0023] In a scenario where the height H1 of the electronic component 106 and the thickness H2 of the core 102 are substantially the same, the insertion of the electronic component 106 into the cavity 104, and the subsequent injection and curing of the dielectric resin, can be achieved using processing techniques as described with reference to Figure 1. In one example, the height H1 of the electronic component and the thickness H2 of the core 102 in Figure 1 may each be 760 micrometers or less.

[0024] The structure of substrate 100 shown in Figure 1 is suitable for use in many high-performance applications (e.g., computer and automotive applications), but current trends are targeting applications that require substrates with larger body sizes. However, substrates with larger body sizes present inherent design and manufacturing problems that must be addressed (e.g., substrate warpage, the need for larger cavity sizes, the need for larger keep-out zones, etc.). These problems can be addressed, at least partially, by using a thicker core in the design and manufacture of such substrates. For example, warpage control is more easily achieved with a thicker core than with a thin core. In addition, the need for larger cavity sizes and keep-out zones can be met by using such a thicker core.

[0025] However, substrates with thick cores can be difficult to manufacture using the same packaging techniques as those used to manufacture substrates with thin cores of the type described in relation to Figure 1. In thick cores, a large gap exists between the electronic component and the cavity due to the large cavity depth relative to the height of the electronic component (for example, a thick core has a thickness greater than the height of the electronic component). In such thick core scenarios, it may be difficult or impossible to fill the gap surrounding the electronic component with dielectric resin in a manner that maintains the proper initial alignment of the electronic component within the cavity during resin injection. Furthermore, once the dielectric resin is fixed, it may be difficult or impossible to inject a sufficient amount of dielectric resin into the gap to fix the electronic component in the desired position.

[0026] Figure 2 is a cross-sectional view of a second exemplary substrate 200 having embedded electronic components according to an aspect of the present disclosure. In this example, it is assumed that the substrate 200 is manufactured using the same processing operations used to manufacture the substrate 100 shown in Figure 1. For simplicity, certain reference numerals used in Figure 1 are also used to indicate similar elements in Figure 2.

[0027] In the example shown in Figure 2, the substrate 200 differs from the substrate 100 in Figure 1 in that the substrate 200 employs a thick core 202 having a thickness H3 greater than the height H1 of the electronic component 106. According to certain aspects of this disclosure, the thickness H3 is greater than about 760 micrometers and is therefore thicker than the electronic component 106 and its corresponding thin core 102. In certain scenarios, the thick core may have a thickness substantially greater than 760 micrometers (e.g., 820 micrometers, 1240 micrometers, etc.).

[0028] The substrate 200 has a cavity 204 that is substantially deeper than the cavity 104 of the substrate 100. Therefore, during the initial placement of the electronic component 106 into the cavity 204, it becomes more difficult to align the metal terminals 110 with the corresponding portions of the patterned metallization layer 118. Initial misalignment of the electronic component 106 may result in failure to establish an electrical connection between the metal terminals 110 and the corresponding portions of the patterned metallization layer 118. In addition, it becomes difficult to accurately fill the cavity 209 (e.g., particularly the expanded gap region of the cavity 209) with enough dielectric resin to properly surround and fix the electronic component 106 in place within the cavity 204 once cured. When the substrate 200 is incorporated into a broader electronic system (e.g., an automotive sensor / computer, a mobile device, or any other type of electronic device described herein), insufficient filling of the cavity 204 with dielectric resin may subsequently cause delamination of the electronic component 106 from electrical contact with the corresponding portion of the patterned metallization layer 118. Figure 2 shows an example of delamination in region 208, where a portion of the metal terminal 110 is pulled away from the corresponding portion of the patterned metallization layer 118.

[0029] According to certain embodiments of this disclosure, the electronic component may be a deep trench capacitor (DTC). Figure 3 is a cross-sectional view of an exemplary DTC 300 according to an embodiment of this disclosure. In Figure 3, the capacitor 310 is deposited in trenches 320 of an insulator 304 on a substrate 302. The capacitor 310 may include a metal layer 312, a dielectric layer 314, and a metal layer 316. The dielectric layer 314 separates the metal layer 312 from the metal layer 316. The metal layers 312, 316 form the electrodes of the capacitor 310 and may be connected to terminals, for example, on a surface (see, for example, the upper surface 108 having metal terminals 110 of the electronic component 106 shown in Figure 1). In some scenarios, the capacitor is formed from an array of deep trenches in the substrate, with the spaces between the electrode layers filled with an electrical insulator (e.g., a dielectric). In some scenarios, the capacitor is mounted on the land side under the shadow of the integrated circuit die (land-side capacitor: LSC) or mounted adjacent to the die on the die side (die-side capacitor: DSC).

[0030] Figure 4A is a cross-sectional view of a third exemplary substrate 400A having an embedded electronic component 402 and an integrated circuit (IC) device 406 according to an aspect of the present disclosure. In some aspects, the electronic component 402 may include one or more active components (e.g., transistors), one or more passive components (e.g., diodes, resistors, inductors, capacitors, and / or deep trench capacitors), or any combination thereof.

[0031] As shown in Figure 4A, the substrate 400A includes a core 410, which comprises a core dielectric 412 having a first surface 412a and a second surface 412b, a first conductive pattern 414 on the first surface 412a of the core dielectric 412, and a second conductive pattern 416 on the second surface 412b of the core dielectric 412. One or more conductive via structures 418 are formed through the core of the core dielectric 412, and a portion of the first conductive pattern 414 may be connected to a portion of the second conductive pattern 416.

[0032] The substrate 400A also includes a first metallization structure 420 on the first surface 412a of the core dielectric 412. The first metallization structure 420 includes a first dielectric 422 on the first surface 412a of the core dielectric 412 and one or more other dielectrics 424 on the first dielectric 422. The first metallization structure 420 also includes conductive patterns and vias (shown in dark shading and unlabeled) formed within the dielectrics 422 and 424. Furthermore, an upper dielectric 432 may be formed on one or more other dielectrics 424, and a first conductive terminal 434 may be formed on the upper surface 426 of the first metallization structure 420. The first conductive terminal 434 may be electrically coupled to at least a portion of the first conductive pattern 414 via the first metallization structure 420. An IC device 406 may be mounted on the substrate 400A and electrically coupled to the first conductive terminal 434. In some embodiments, the first conductive terminal 434 and the second conductive terminal 454 may include solder balls and / or conductive pillars.

[0033] The substrate 400A further includes a second metallization structure 440 beneath the second surface 412b of the core dielectric 412. The second metallization structure 440 includes a second dielectric 442 beneath the second surface 412b of the core dielectric 412 and one or more other dielectrics 444 beneath the second dielectric 442. The second metallization structure 440 also includes conductive patterns and vias (shown in dark shading and unlabeled) formed within the dielectrics 442 and 444. Furthermore, a bottom dielectric 452 may be formed beneath one or more other dielectrics 444, and a second conductive terminal 454 may be formed on the bottom surface 446 of the second metallization structure 440. The second conductive terminal 454 may be electrically coupled to at least a portion of the second conductive pattern 416 via the second metallization structure 440. In some embodiments, the substrate 400A may be mounted on a circuit board (not shown) via a second conductive terminal 454 and electrically coupled thereto.

[0034] Figure 4A shows region 460, and Figure 4B is an enlarged view of region 460 according to an embodiment of the present disclosure. Components shown in Figure 4B that are the same as those in Figure 4A are indicated by the same shading and given the same reference numerals.

[0035] As shown in Figure 4B, the first dielectric 422 has an opening (unlabeled) formed therein for housing an electronic component 402 and an adhesive structure 470. In some embodiments, the adhesive structure 470 may include an adhesive layer 472 and an extension 474, the electronic component 402 may be placed within the opening in the first dielectric 422, and the adhesive layer 472 may bond the electronic component 402 to the core 410. In some embodiments, the adhesive layer 472 and the extension 474 may include or be made from a resin material. As shown in Figure 4B, the space between the sidewall of the opening and the sidewall of the electronic component 402 may be at least partially filled with the resin material to form the extension 474 of the adhesive structure 470. In some embodiments, the thickness of the electronic component 402 is less than or equal to the thickness of the first dielectric 422. In some embodiments, the first dielectric 422 may include one or more dielectric layers, one or more layers of conductive patterns, and one or more layers of vias.

[0036] In some embodiments, the electronic component 402 may include a first side 402a (e.g., terminal side) having conductive terminals and a second side 402b (e.g., back side) opposite to the first side and not having conductive terminals. In some embodiments, the electronic component 402 may be positioned such that the second side (e.g., back side) 402b faces the core dielectric 412, and the first side (e.g., terminal side) 402a faces away from the core dielectric 412, from which it is electrically coupled to one or more conductive features of the first metallization structure 420.

[0037] In some embodiments, the adhesive layer 472 may include a resin material that may include a polymer resin, an epoxy resin, or a combination thereof. In some embodiments, the resin material may be a thermosetting material. In some embodiments, the resin material may be of film or liquid type, whether in an uncured or partially cured form.

[0038] In some embodiments, electronic components 402 placed within a first dielectric 422 on the core 410 can improve design flexibility regarding the routing of conductive paths (including conductive patterns 414 and conductive structures of the first metallization structure 420) to save space and / or improve performance. Also, as shown in the examples of Figures 4A and 4B, the placement of components in the substrate is independent of the core thickness. In some embodiments, the resin material can be dispensed based on a volume such that the overall thickness of the resin material and electronic components 402 does not exceed the thickness of the first dielectric 422. In some embodiments, the electronic component 402 may be a deep trench capacitor, a die-side capacitor, or a land-side capacitor.

[0039] Figure 4C is a cross-sectional view of a fourth exemplary substrate 400B having an embedded electronic component 402, an electronic component 408, and an IC device 406 according to an aspect of the present disclosure. In some aspects, substrate 400B may be a variation of substrate 400A. Components shown in Figure 4C that are the same as those in Figures 4A and 4B are indicated by the same shading and given the same reference numerals.

[0040] Compared to substrate 400A, substrate 400B further includes another electronic component 408 mounted on the second surface 412b of the core dielectric 412. In some embodiments, the second dielectric 442 has an opening (unlabeled) formed therein for housing the electronic component 408 and an adhesive structure 480. In some embodiments, the adhesive structure 480 may include an adhesive layer 482 and an extension portion 484, the electronic component 408 may be placed within the opening in the second dielectric 442, and the adhesive layer 482 may bond the electronic component 408 to the core 410.

[0041] In some embodiments, the adhesive structure 480 and the electronic component 408 may be arranged in a manner similar to that of the adhesive structure 470 and the electronic component 402 shown in Figure 4B. In some embodiments, the electronic component 408 may include a first side (e.g., terminal side) having conductive terminals and a second side (e.g., back side) opposite to the first side and not having conductive terminals. In some embodiments, the electronic component 408 may be arranged such that the second side (e.g., back side) faces the core dielectric 412, and the first side (e.g., terminal side) faces away from the core dielectric 412, from which it is electrically coupled to one or more conductive features of the second metallization structure 440.

[0042] Figure 5A is a cross-sectional view of a fifth exemplary substrate 500A having an embedded electronic component 402 and an IC device 406 according to an aspect of the present disclosure. In some embodiments, the substrate 500A may be a variation of the substrate 400A. Components shown in Figure 5A that are the same as those in Figure 4A are indicated by the same shading and given the same reference numerals.

[0043] Compared to substrate 400A, the electronic component 402 is mounted on the core 410 of substrate 500A using a different method. Figure 5A shows region 510, and Figure 5B is an enlarged view of region 510 according to an aspect of the present disclosure. Components shown in Figure 5B that are the same as those in Figures 4A and 5A are indicated by the same shading and given the same reference numerals.

[0044] As shown in Figure 5B, the first dielectric 422 has an opening (unlabeled) formed therein for housing an electronic component 402 and an adhesive layer 520. In some embodiments, the electronic component 402 may be placed within the opening of the first dielectric 422, and the adhesive layer 520 may bond the electronic component 402 to the core 410. In some embodiments, the adhesive layer 520 may include a bonding film. As shown in Figure 5B, one or more other dielectrics 424 may include a dielectric 424a on top of the first dielectric 422, and a dielectric 424b on top of dielectric 424a. In some embodiments, dielectric 424a may include dielectric material, and the space between the sidewall of the opening and the sidewall of the electronic component 402 may be at least partially filled with dielectric material to form a filler portion 524. In some embodiments, the thickness of the electronic component 402 is less than or equal to the thickness of the first dielectric 422. In some embodiments, the first dielectric 422 may include one or more dielectric layers, one or more layers of conductive patterns, and one or more layers of vias.

[0045] In some embodiments, the adhesive layer 520 may include an adhesive material based on a resin material, a non-resin material, or a combination thereof. In some embodiments, the resin material may include a polymer resin, an epoxy resin, or a combination thereof. In some embodiments, the resin material may be a thermosetting material. In some embodiments, the resin material may be of film or liquid type, whether in an uncured or partially cured form.

[0046] Figure 5C is a cross-sectional view of a sixth exemplary substrate 500B according to an aspect of the present disclosure, having an embedded electronic component 402, an electronic component 408, and an IC device 406. In some aspects, substrate 500B may be a variation of substrate 500A. Components shown in Figure 5B that are the same as those in Figures 5A and 5B are indicated by the same shading and given the same reference numerals.

[0047] Compared to substrate 500A, substrate 500B further includes another electronic component 408 mounted on the second surface 412b of the core dielectric 412. In some embodiments, the second dielectric 442 has an opening (unlabeled) formed therein for housing the electronic component 408 and an adhesive layer 530. In some embodiments, the electronic component 408 may be placed within the opening of the second dielectric 442, and the adhesive layer 530 may bond the electronic component 408 to the core 410. In some embodiments, the adhesive layer 530 and the electronic component 408 may be arranged in a manner similar to the adhesive layer 520 and electronic component 402 shown in Figure 5B. For example, one or more other dielectrics 444 may include dielectric 444a and dielectric 444b, and the space between the sidewall of the opening and the sidewall of the electronic component 408 may be at least partially filled with the dielectric material of dielectric 444a to form a filler portion 534.

[0048] Figures 6A to 6M illustrate the structure at various stages of manufacturing the exemplary substrate 400A of Figure 4A according to embodiments of this disclosure. Components shown in Figures 6A to 6M that are the same as or similar to those in Figure 4A are given the same reference numerals, and their detailed descriptions may be omitted.

[0049] As shown in Figure 6A, a structure 600A including a core 610 is provided. The core 610 includes a core dielectric 412, a first conductive layer 614 on a first surface 412a of the core dielectric 412, and a second conductive layer 616 on a second surface 412b of the core dielectric 412. In some embodiments, the core 610 is a copper clad laminate (CCL) core, the first conductive layer 614 and the second conductive layer 616 contain copper, and the core dielectric 412 contains a combination of epoxy resin and glass fibers.

[0050] As shown in Figure 6B, structure 600B is formed based on structure 600A by forming one or more holes 617 that penetrate the core 610. In some embodiments, one or more holes 617 may be formed by mechanical drilling or laser drilling. In some embodiments, the thicknesses of the first conductive layer 614 and the second conductive layer 616 may be reduced to become reduced conductive layers 614' and 616'.

[0051] As shown in Figure 6C, structure 600C is formed by forming one or more conductive via structures 418 in one or more holes 617 based on structure 600B, patterning a mask to cover the reduced conductive layers 614' and 616', plating and cleaning a conductive material on the patterned mask on the conductive layers 614' and 616' to form a first conductive pattern 414 on a first surface 412a and a second conductive pattern 416 on a second surface 412b. In some embodiments, structure 600C may correspond to the core 410 in Figure 4A. In some embodiments, the first conductive pattern 414 may include a copper stopper 618.

[0052] As shown in Figure 6D, structure 600D is formed based on structure 600C by forming a first dielectric 422 on the core 410 and a second dielectric 442 below the core 410. The first dielectric 422 is located on the first surface 412a of the core dielectric 412, and the second dielectric 442 is located below the second surface 412b of the core dielectric 412. In some embodiments, the first dielectric 422 may be formed by applying a first layer of the laminate material on the first surface 412a and the first conductive pattern 414, and the second dielectric 442 may be formed by applying a second layer of the laminate material on the second surface 412b and the second conductive pattern 416. In some embodiments, the first layer and the second layer of the laminate material may include Ajinomoto build-up film (ABF) or prepreg.

[0053] As shown in Figure 6E, structure 600E is formed based on structure 600D by forming an opening 622 in the first dielectric 422 to expose a portion of the first conductive pattern 414, and by forming an opening 624 in the second dielectric 442 to expose a portion of the second conductive pattern 416. In some embodiments, the openings 622 and 624 may be formed by laser drilling or a wet etching process.

[0054] As shown in Figure 6F, structure 600F is formed by forming conductive structures 626 and 628 using openings 622 and 624 based on structure 600E. In some embodiments, conductive structures 626 and 628 may be formed based on an electroless plating process, a via filling process, a pattern plating process, and / or a seed layer removal process. In some embodiments, the first dielectric 422 and the conductive structure 626 may be part of a first metallization structure (e.g., first metallization structure 420) on the first surface 412a of the core dielectric 412. In some embodiments, the second dielectric 442 and the conductive structure 628 may be part of a second metallization structure (e.g., second metallization structure 440) below the second surface 412b of the core dielectric 412.

[0055] As shown in Figure 6G, structure 600G is formed based on structure 600F by forming an opening 632 in the first dielectric 422, the opening 632 exposing the copper stopper 618. In some embodiments, the opening 632 may be formed based on a laser drilling or wet etching process.

[0056] As shown in Figure 6H, structure 600H is formed by removing the copper stopper 618 to extend the opening 632 to form opening 632' based on structure 600G, in which case opening 632' exposes a portion of the core 410 (e.g., the first surface 412a of the core dielectric 412). In some embodiments, opening 632' may be formed based on a wet etching process.

[0057] In some embodiments, the copper stopper 618 may be omitted in the stage shown in Figure 6C, and the stages shown in Figures 6G and 6H may be combined to form the opening 632'.

[0058] As shown in Figure 6I, structure 600I is formed based on structure 600H by dispensing resin material 634 in an uncured or partially cured form into an opening 632' on at least a portion of core 410. In some embodiments, the resin material 634 may include a polymer resin, an epoxy resin, or a combination thereof.

[0059] As shown in Figure 6J, structure 600J is formed by positioning the electronic component 402 within the opening 632' based on structure 600I, and the dispensed resin material 634, in an uncured or partially cured state, at least partially fills a portion of the gap between the electronic component 402 and the core 410. In some embodiments, the dispensed resin material 634, in an uncured or partially cured state, at least partially fills the space between the sidewall of the opening 632' and the sidewall of the electronic component 402. In some embodiments, the dispensed resin material 634 may be cured so that, in a cured state, the dispensed resin material becomes an adhesive structure 470 including at least an adhesive layer 472 that bonds the electronic component 402 to the core 410.

[0060] In some embodiments, the electronic component 402 may include a first side (e.g., terminal side) having conductive terminals and a second side (e.g., back side) opposite to the first side and not having conductive terminals. In some embodiments, the electronic component 402 may be arranged such that the second side (e.g., back side) faces the core dielectric 412, and the first side (e.g., terminal side) faces away from the core dielectric 412.

[0061] As shown in Figure 6K, structure 600K is formed based on structure 600J by forming the remainder of the first metallization structure 420 on top of the first dielectric 422 and electronic component 402, and the remainder of the second metallization structure 440 beneath the second dielectric 442. In some embodiments, the first metallization structure 420 may include additional dielectric and conductive structures that can be formed in a manner similar to that which forms the first dielectric 422 and conductive structure 626 as shown with reference to Figures 6D-6F. In some embodiments, curing the dispensed resin material 634 after the electronic component 402 is placed on it may be performed during the build-up curing process for forming the remainder of the first metallization structure 420. Also in some embodiments, the second metallization structure 440 may include additional dielectric and conductive structures that can be formed in a manner similar to that which forms the second dielectric 442 and conductive structure 628 as shown with reference to Figures 6D-6F.

[0062] As shown in Figure 6L, structure 600L is formed based on structure 600K by forming an upper dielectric 432 on top of a first metallization structure 420, forming a bottom dielectric 452 below a second metallization structure 440, and forming an opening 642 in the upper dielectric 432 and an opening 644 in the bottom dielectric 452. In some embodiments, the openings 642 and 644 may expose a portion of the upper surface of the first metallization structure 420 and a portion of the lower surface of the second metallization structure 440. In some embodiments, the openings 642 and 644 may be formed based on a laser drilling or wet etching process.

[0063] As shown in Figure 6M, based on structure 600L, structure 600M is formed by forming a first conductive terminal 434 in an opening 642 above the first metallization structure 420 and a second conductive terminal 454 in an opening 644 below the second metallization structure 440. In some embodiments, structure 600M may correspond to the substrate 400A shown in Figure 4A.

[0064] In some embodiments, the first conductive terminal 434 is formed on the upper surface of the first metallization structure 420 and may be electrically coupled to at least a portion of the first conductive pattern 414 via the first metallization structure 420. In some embodiments, the second conductive terminal 454 is formed on the lower surface of the second metallization structure 440 and may be electrically coupled to at least a portion of the second conductive pattern 416 via the second metallization structure 440. In some embodiments, the first conductive terminal 434 and the second conductive terminal 454 may include solder balls and / or conductive pillars.

[0065] Figures 6N to 6O show the structure at various stages of manufacturing the exemplary substrate 400B of Figure 4C according to aspects of this disclosure. Components shown in Figures 6N to 6O that are the same as or similar to those in Figures 4A, 4C, and 6A to 6M are given the same reference numerals, and their detailed descriptions may be omitted.

[0066] As shown in Figure 6N, structure 600N is formed based on structure 600F by forming an opening 632' in the first dielectric 422 and an opening 633 in the second dielectric 442. In some embodiments, the openings 632' and 633 may be formed based on a laser drilling or wet etching process, as described with reference to Figures 6G and 6H. In some embodiments, the opening 632' exposes at least a portion of the core 410 (e.g., a portion of the first surface 412a of the core dielectric 412), and the opening 633 exposes at least another portion of the core 410 (e.g., a portion of the second surface 412b of the core dielectric 412).

[0067] As shown in Figure 6O, based on structure 600N, structure 600O is formed by attaching electronic component 402 to the core 410 by a first adhesive layer 472 of adhesive structure 470 that connects electronic component 402 to the core 410, and by attaching electronic component 408 to the core 410 by a second adhesive layer 482 of adhesive structure 480 that connects electronic component 408 to the core 410. Electronic component 402 may be placed in an opening 632' of the first dielectric 422, and electronic component 408 may be placed in an opening 633 of the second dielectric 442. Furthermore, the remainder of the first metallization structure 420 is formed on top of the electronic component 402 and the first dielectric 422, the upper dielectric 432 is formed on top of the first metallization structure 420, and the first conductive terminal 434 is formed on top of the first metallization structure 420. Furthermore, the remaining portion of the second metallization structure 440 is formed beneath the electronic component 408 and the second dielectric 442, the bottom dielectric 452 is formed beneath the second metallization structure 440, and the second conductive terminal 454 is formed beneath the second metallization structure 440.

[0068] In some embodiments, the electronic component 402 may include a first side having conductive terminals (e.g., terminal side) and a second side opposite to the first side and not having conductive terminals (e.g., back side). In some embodiments, the electronic component 402 may be arranged such that the second side of the electronic component 402 (e.g., back side) faces the core dielectric 412, and the first side of the electronic component 402 (e.g., terminal side) faces away from the core dielectric 412 (e.g., facing in the direction of the first conductive terminal 434 in Figure 6O). In some embodiments, the electronic component 408 may also include a first side having conductive terminals (e.g., terminal side) and a second side opposite to the first side and not having conductive terminals (e.g., back side). In some embodiments, the electronic component 408 may be arranged such that a second side of the electronic component 408 (e.g., the back side) faces the core dielectric 412, and a first side of the electronic component 408 (e.g., the terminal side) faces away from the core dielectric 412 (e.g., facing the direction of the second conductive terminal 454 in Figure 6O).

[0069] In some embodiments, forming structure 600O based on structure 600N can be performed based on operations as described with reference to Figures 6I to 6M. In some embodiments, structure 600O may correspond to substrate 400B shown in Figure 4C.

[0070] Figures 7A to 7C illustrate the structure at various stages of manufacturing the exemplary substrate 500A of Figure 5A according to aspects of this disclosure. Components shown in Figures 7A to 7C that are the same as or similar to those in Figures 5A and 6A to 6M are given the same reference numerals, and their detailed descriptions may be omitted.

[0071] As shown in Figure 7A, structure 700A is formed by placing an electronic component 402 having an adhesive layer 520 (e.g., including a bonding film) within an opening 632', based on structure 600H in Figure 6H. In some embodiments, the bonding film may be first attached to the electronic component 402 and then placed together with the electronic component 402 within the opening 632'. In some embodiments, the bonding film may be first placed within the opening 632', and then the electronic component 402 may be placed on the bonding film. In some embodiments, the adhesive layer 520 may include an adhesive material based on a resin material, a non-resin material, or a combination thereof. In some embodiments, the resin material may include a polymer resin, an epoxy resin, or a combination thereof. In some embodiments, the resin material may be a thermosetting material. In some embodiments, the resin material may be of film or liquid type, if it is in an uncured or partially cured form.

[0072] As shown in Figure 7B, structure 700B is formed based on structure 700A by forming dielectric 424a on top of the first dielectric 422, forming dielectric 444a below the second dielectric 442, and forming a contact structure within and on the dielectric 424a and dielectric 444a. In some embodiments, the space between the sidewall of the opening 632' and the sidewall of the electronic component 402 can be at least partially filled with the dielectric material of dielectric 424a so as to form a filler portion 524. In some embodiments, the filler portion 524 can be formed during the formation of dielectric 424a. In some embodiments, forming dielectric 424a and filling the space to form the filler portion 524 can be performed based on applying a layer of laminated material which may include Ajinomoto build-up film (ABF) or prepreg.

[0073] As shown in Figure 7C, based on structure 700B, structure 700C is formed by forming the remaining portion of the first metallization structure 420 on the electronic component 402 and the first dielectric 422, forming the upper dielectric 432 on the first metallization structure 420, and forming the first conductive terminal 434 on the first metallization structure 420. Additionally, the remaining portion of the second metallization structure 440 is formed beneath the second dielectric 442, the bottom dielectric 452 is formed beneath the second metallization structure 440, and the second conductive terminal 454 is formed beneath the second metallization structure 440.

[0074] In some embodiments, forming structure 700C based on structure 700B can be performed based on operations as described with reference to Figures 6K to 6M. In some embodiments, structure 700C may correspond to substrate 500A shown in Figure 5C.

[0075] Figure 7D shows the structure in the process of manufacturing the exemplary substrate 500B of Figure 5C according to an aspect of this disclosure. Components shown in Figure 7D that are the same as or similar to those in Figures 5A, 6A-6M, and 7A-7C are given the same reference numerals, and their detailed descriptions may be omitted.

[0076] As shown in Figure 7D, based on structure 600N in Figure 6N, structure 700D is formed by attaching electronic component 402 to the core 410 by a first adhesive layer 520 that bonds electronic component 402 to the core 410, and by attaching electronic component 408 to the core 410 by a second adhesive layer 530 that bonds electronic component 408 to the core 410. Electronic component 402 may be placed in an opening 632' of the first dielectric 422, and electronic component 408 may be placed in an opening 633 of the second dielectric 442. Furthermore, the remainder of the first metallization structure 420 is formed on top of the electronic component 402 and the first dielectric 422, the upper dielectric 432 is formed on top of the first metallization structure 420, and the first conductive terminal 434 is formed on top of the first metallization structure 420. Furthermore, the remaining portion of the second metallization structure 440 is formed beneath the electronic component 408 and the second dielectric 442, the bottom dielectric 452 is formed beneath the second metallization structure 440, and the second conductive terminal 454 is formed beneath the second metallization structure 440.

[0077] In some embodiments, forming structure 700D based on structure 600N can be performed based on operations as described with reference to Figures 7A-7C and 6K-6M. In some embodiments, structure 700D may correspond to substrate 500B shown in Figure 5C.

[0078] Figure 8 shows a method 800 for manufacturing substrates (substrates 400A, 400B, 500A, and 500B, etc.) according to an aspect of the present disclosure.

[0079] In operation 810, a first dielectric (e.g., a first dielectric 422) is formed on a substrate core (e.g., a core 410). The core may include a core dielectric (e.g., a core dielectric 412) and a first conductive pattern (e.g., a first conductive pattern 414) on a first surface (e.g., a first surface 412a) of the core dielectric. The first dielectric may be positioned on the first surface of the core dielectric, and the first dielectric may be a first portion of a first metallization structure (e.g., a first metallization structure 420) of the substrate on the first surface of the core dielectric.

[0080] In some embodiments, operation 810 may further include forming a second dielectric (e.g., a second dielectric 442) beneath a core of the substrate, the core including a second conductive pattern (e.g., a second conductive pattern 416) on a second surface (e.g., a second surface 412b) of the core dielectric, the second dielectric being located beneath the second surface of the core dielectric, and the second dielectric being a first portion of a second metallization structure (e.g., a second metallization structure 440) of the substrate beneath the second surface of the core dielectric.

[0081] In operation 820, a first opening (e.g., opening 632') is formed in the first dielectric, and the first opening exposes at least a first portion of the core. In some embodiments, the first opening may be formed based on a laser drilling or wet etching process.

[0082] In some embodiments, operation 820 may further include forming a second opening (e.g., opening 633) of the second dielectric, the second opening may expose at least a second portion of the core.

[0083] In operation 830, the first electronic component (e.g., electronic component 402) is attached to the core by a first adhesive layer (e.g., adhesive layer 472 or adhesive layer 520) that bonds the first electronic component to the core, and the first electronic component is placed in a first opening of the first dielectric.

[0084] In some embodiments, as shown with reference to Figures 6I to 6J, operation 830 may include dispensing a resin material in an uncured or partially cured form into a first opening on at least a first portion of the core, and positioning a first electronic component in the first opening such that the dispensed resin material, in an uncured or partially cured form, at least partially fills a portion of the gap between the first electronic component and the core, and curing the dispensed resin material so that, in a cured form, it forms a first adhesive layer. In some embodiments, the dispensed resin material, in an uncured or partially cured form, may at least partially fill the space between the sidewall of the first opening and the sidewall of the first electronic component.

[0085] In some embodiments, as shown with reference to Figures 7A to 7B, operation 830 may include placing the first electronic component in the first opening together with a bonding film used as the first adhesive layer.

[0086] In some embodiments, operation 830 may further include attaching a second electronic component (e.g., electronic component 408) to the core by a second adhesive layer (e.g., adhesive layer 482 or adhesive layer 530) that bonds the second electronic component to the core, and the second electronic component is located within a second opening of the second dielectric.

[0087] In operation 840, the second portion of the first metallization structure is formed on the first dielectric and the first electronic component. In some embodiments, in operation 830, curing the dispensed resin material may be performed during the build-up curing process for forming the second portion of the first metallization structure.

[0088] In some embodiments, operation 840 further includes forming a second portion of the second metallization structure beneath the second dielectric and / or second electronic component.

[0089] The technical advantage of Method 800 is that, since the manufacturing process is independent of the core thickness, it can be used to form substrates with embedded electronic components (e.g., deep trench capacitors) regardless of the core thickness.

[0090] Figure 9 shows a side view of a package 900 according to an aspect of the present disclosure, which includes a surface mount substrate 902, an integrated device 903, and an integrated passive device 905 (e.g., an embedded deep trench device and a substrate having a thick core). The package 900 may be coupled to a printed circuit board (PCB) 906 via a plurality of solder interconnects 910. The PCB 906 may include at least one board dielectric layer 960 and a plurality of board interconnects 962.

[0091] The surface mount substrate 902 includes at least one dielectric layer 920 (e.g., a substrate dielectric layer), a plurality of interconnection parts 922 (e.g., substrate interconnection parts), a solder resist layer 940, and a solder resist layer 942. The integrated device 903 may be coupled to the surface mount substrate 902 via a plurality of solder interconnection parts 930. The integrated device 903 may be coupled to the surface mount substrate 902 via a plurality of pillar interconnection parts 932 and a plurality of solder interconnection parts 930. The integrated passive device 905 may be coupled to the surface mount substrate 902 via a plurality of solder interconnection parts 950. The integrated passive device 905 may be coupled to the surface mount substrate 902 via a plurality of pillar interconnection parts 952 and a plurality of solder interconnection parts 950.

[0092] The package (e.g., 900) may be implemented within a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 900) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 900) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 900) may be configured to send and receive signals with different frequencies and / or different communication protocols.

[0093] Figure 10 shows an exemplary method 1000 for providing or manufacturing a package including an integrated device with a moisture sensor, according to an aspect of the present disclosure. In some implementations, the method 1000 of Figure 10 may be used to provide or manufacture the package 900 of Figure 9 as described in the present disclosure. However, the method 1000 may be used to provide or manufacture any of the packages described in the present disclosure.

[0094] It should be noted that the method in Figure 10 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package including an integrated device and / or an integrated passive device having a magnetic layer. In some implementations, the order of the processes may be changed or modified.

[0095] This method involves preparing a substrate (e.g., 902) (in 1005). The substrate 902 may be provided by a supplier or manufactured by the supplier. The substrate 902 includes at least one dielectric layer 920 and a plurality of interconnection sections 922. The substrate 902 may include an embedded trace substrate (ETS). In some mounting configurations, at least one dielectric layer 920 may include a prepreg layer.

[0096] The method involves bonding at least one integrated device (e.g., 903) to a first surface of a substrate (e.g., 902) (in 1010). For example, the integrated device 903 may be bonded to the substrate 902 via a plurality of pillar interconnects 932 and a plurality of solder interconnects 930. The plurality of pillar interconnects 932 may be optional. The plurality of solder interconnects 930 are bonded to a plurality of interconnects 922. A solder reflow process may be used to bond the integrated device 903 to the plurality of interconnects via the plurality of solder interconnects 930.

[0097] The method also involves bonding at least one integrated passive device (e.g., 905) to a first surface of a substrate (e.g., 902) (in 1010). For example, the integrated passive device 905 may be bonded to the substrate 902 via a plurality of pillar interconnects 952 and a plurality of solder interconnects 950. The plurality of pillar interconnects 952 may be optional. The plurality of solder interconnects 950 are bonded to a plurality of interconnects 922. A solder reflow process may be used to bond the integrated passive device 905 to the plurality of interconnects via the plurality of solder interconnects 950.

[0098] The method involves bonding a plurality of solder interconnects (e.g., 910) (in 1015) to a second surface of a substrate (e.g., 902). A solder reflow process may be used to bond the plurality of solder interconnects 910 to the substrate.

[0099] Figure 11 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, dies, interposer packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1102, a laptop computer device 1104, a fixed-location terminal device 1106, a wearable device 1108, or an automated vehicle 1110 may include a device 1100 as described herein. Device 1100 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1102, 1104, 1106, and 1108, and the vehicle 1110 shown in Figure 11 are merely examples. Device 1100 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) compatible devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0100] In the detailed explanation above, it will be seen that in the examples, different features are grouped together. This form of disclosure should not be understood as an intention that the exemplary clauses have more features than are explicitly stated within each clause. Rather, the various aspects of this disclosure may contain fewer features than all the features of the individual exemplary clauses disclosed. Accordingly, the following clauses should be considered incorporated into the explanation, and each clause may be valid on its own as a separate example. Each dependent clause may refer within itself to a specific combination with one of the other clauses, but the aspects (singular or plural) of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of aspects (singular or plural) of dependent clauses with the subject matter of any other dependent or independent clause, or any combination of features with other dependent and independent clauses. The various aspects disclosed herein explicitly include certain combinations (e.g., contradictory aspects such as defining an element as both an electrical insulator and an electrical conductor) unless it is explicitly stated or easily inferred that such combinations are not intended. Furthermore, even if a clause is not directly subordinate to an independent clause, it is intended that the nature of the clause may be included in any other independent clause.

[0101] Implementation examples are described in the following numbered sections.

[0102] Clause 1. A core comprising a core dielectric and a first conductive pattern on a first surface of the core dielectric; a first metallization structure on the first surface of the core dielectric, comprising the first dielectric, wherein the first dielectric has a first opening formed therein; a first electronic component disposed within the first opening of the first dielectric; and a first adhesive layer bonding the first electronic component to the core. A substrate, including a circuit board.

[0103] Clause 2. The substrate described in Clause 1, wherein the thickness of the first electronic component is less than or equal to the thickness of the first dielectric.

[0104] Clause 3. A substrate according to Clause 1 or 2, wherein the first adhesive layer comprises a resin material.

[0105] Clause 4. The substrate according to Clause 3, wherein the space between the side wall of the first opening and the side wall of the first electronic component is at least partially filled with a resin material.

[0106] Clause 5. The substrate according to Clause 1 or 2, wherein the first adhesive layer includes a bonding film.

[0107] Clause 6. The substrate according to Clause 5, wherein the first metallization structure further comprises one other dielectric on top of the first dielectric, the one other dielectric comprising a dielectric material, and the space between the sidewall of the first opening and the sidewall of the first electronic component is at least partially filled with the dielectric material.

[0108] Clause 7. A substrate according to any one of Clauses 1 to 6, wherein the core includes a second conductive pattern on a second surface of a core dielectric, and the substrate further comprises a second metallization structure below the second surface of the core dielectric, the second dielectric having a second opening formed therein, a second electronic component disposed within the second opening of the second dielectric, and a second adhesive layer bonding the second electronic component to the core.

[0109] Clause 8. A substrate according to any one of Clauses 1 to 7, further comprising a first conductive terminal on the upper surface of the first metallization structure, which is electrically coupled to at least a portion of the first conductive pattern via the first metallization structure.

[0110] Clause 9. The substrate according to Clause 8, wherein the core includes a second conductive pattern on a second surface of a core dielectric, and the substrate further comprises a second metallization structure below the second surface of the core dielectric, and a second conductive terminal on the lower surface of the second metallization structure, which is electrically coupled to at least a portion of the second conductive pattern via the second metallization structure.

[0111] Clause 10. A substrate according to any of Clauses 1 to 9, wherein the first adhesive layer comprises a resin material including a polymer resin, an epoxy resin, or a combination thereof, or an adhesive material based on a resin material, a non-resin material, or a combination thereof.

[0112] Clause 11. A substrate according to any of Clauses 1 to 10, wherein the core is a copper-clad laminate (CCL) core.

[0113] Clause 12. A method for manufacturing a substrate, comprising: forming a first dielectric on a core of a substrate, which includes a core dielectric and a first conductive pattern on a first surface of the core dielectric; forming a first dielectric, which is disposed on the first surface of the core dielectric and is a first portion of a first metallization structure of the substrate; forming a first opening in the first dielectric, which exposes at least a first portion of the core; attaching a first electronic component, which is disposed within the first opening in the first dielectric, to the core by a first adhesive layer that bonds the first electronic component to the core; and forming a second portion of a first metallization structure on the first dielectric and the first electronic component.

[0114] Clause 13. The method according to Clause 12, wherein mounting a first electronic component onto a core comprises dispensing a resin material in an uncured or partially cured form into a first opening on at least a first portion of the core, positioning the first electronic component within the first opening, wherein the dispensed resin material, in an uncured or partially cured form, at least partially fills a portion of the gap between the first electronic component and the core, and curing the dispensed resin material so that, in a cured form, it forms a first adhesive layer.

[0115] Clause 14. The method according to Clause 13, wherein curing of the dispensed resin material is performed during a build-up curing process to form a second portion of the first metallized structure.

[0116] Clause 15. The method according to Clause 13 or 14, wherein the dispensed resin material, in an uncured or partially cured form, at least partially fills the space between the sidewall of the first opening and the sidewall of the first electronic component.

[0117] Clause 16. The method according to Clause 12, wherein mounting the first electronic component onto the core includes placing the first electronic component together with a bonding film used as a first adhesive layer within a first opening.

[0118] Clause 17. The method according to any one of Clauses 12 to 16, wherein forming a second portion of a first metallization structure comprises forming one other dielectric on a first dielectric, the one other dielectric comprising a dielectric material, and while forming the one other dielectric on the first dielectric, the space between the sidewall of the first opening and the sidewall of the first electronic component is at least partially filled with the dielectric material.

[0119] The method according to Clause 17, wherein forming one other dielectric and at least partially filling the space is carried out on the basis of applying a layer of laminate material on the first dielectric.

[0120] Clause 19. The method according to Clause 18, wherein the layer of the laminated material comprises Ajinomoto Build-Up Film (ABF) or prepreg.

[0121] Clause 20. The method according to any one of Clauses 12 to 19, further comprising: forming a second dielectric beneath a core of a substrate, which includes a second conductive pattern on the second surface of a core dielectric; forming a second dielectric, which is a first portion of a second metallization structure of the substrate, which is located beneath the second surface of the core dielectric and below the second surface of the core dielectric; forming a second opening in the second dielectric, which exposes at least a second portion of the core; attaching a second electronic component, which is located within the second opening in the second dielectric, to the core by a second adhesive layer that bonds the second electronic component to the core; and forming a second portion of a second metallization structure beneath the second dielectric and the second electronic component.

[0122] Clause 21. The method according to any one of Clauses 12 to 19, further comprising forming a first conductive terminal on the upper surface of the first metallization structure, the first conductive terminal being electrically coupled to at least a portion of the first conductive pattern via the first metallization structure.

[0123] Clause 22. The method according to Clause 21, further comprising: forming a second metallization structure located beneath a core of a substrate, the second metallization structure having a second conductive pattern on a second surface of a core dielectric; and forming a second conductive terminal on the lower surface of the second metallization structure, the second conductive terminal being electrically coupled to at least a portion of the second conductive pattern via the second metallization structure.

[0124] Clause 23. The method according to any one of Clauses 12 to 22, wherein the first adhesive layer includes a resin material comprising a polymer resin, an epoxy resin, or a combination thereof, or an adhesive material based on a resin material, a non-resin material, or a combination thereof.

[0125] Clause 24. The method according to any of Clauses 12 to 23, wherein the first electronic component includes one or more active components, one or more passive components, or any combination thereof.

[0126] Clause 25. An electronic device comprising a substrate, wherein the substrate is A core comprising a core dielectric and a first conductive pattern on a first surface of the core dielectric; a first metallization structure on the first surface of the core dielectric, comprising the first dielectric, wherein the first dielectric has a first opening formed therein; a first electronic component disposed within the first opening of the first dielectric; and a first adhesive layer bonding the first electronic component to the core. including, Electronic devices.

[0127] Clause 26. An electronic device as described in Clause 25, wherein the first electronic component includes one or more active components, one or more passive components, or any combination thereof.

[0128] Clause 27. The electronic device according to Clause 25 or 26, wherein the substrate further comprises a first conductive terminal on the upper surface of the first metallization structure, which is electrically coupled to at least a portion of the first conductive pattern via the first metallization structure, and the electronic device further comprises an integrated circuit (IC) device mounted on the substrate and electrically coupled to the first conductive terminal.

[0129] Clause 28. An electronic device according to any one of Clauses 25 to 27, wherein the core includes a second conductive pattern on a second surface of a core dielectric, and the substrate further comprises a second metallization structure below the second surface of the core dielectric, the second dielectric having a second opening formed therein; a second electronic component disposed within the second opening of the second dielectric; and a second adhesive layer bonding the second electronic component to the core.

[0130] Clause 29. An electronic device according to any of Clauses 25 to 28, wherein the first adhesive layer includes a resin material comprising a polymer resin, an epoxy resin, or a combination thereof, or an adhesive material based on a resin material, a non-resin material, or a combination thereof.

[0131] Article 30. Electronic devices, Music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, or devices in autonomous vehicles. An electronic device as described in any of clauses 25 to 29, comprising at least one of the following:

[0132] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0133] Furthermore, those skilled in the art will understand that various exemplary logic blocks, modules, circuits, and algorithmic steps described in relation to the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate this hardware-software compatibility, various exemplary components, blocks, modules, circuits, and steps have been outlined above in relation to their functions. Whether such functions are implemented as hardware or executed as software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functions in various ways with respect to each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0134] Various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, individual gate or transistor logic, individual hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0135] The methods, sequences, and / or algorithms described in relation to the embodiments disclosed herein may be embodied in hardware directly, in software modules executed by a processor, or in a combination of the two. The software modules may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside in the user terminal as separate components.

[0136] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via computer-readable media as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any media that facilitate the transfer of computer programs from one location to another. Storage media may be any available media accessible by a computer. Such computer-readable media, but not limited to examples, may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other media accessible by a computer that can be used to carry or store desired program code in the form of instructions or data structures. Furthermore, any connection may appropriately be referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used herein, disks and discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray® discs, where a disc typically reproduces data magnetically, and a disc optically reproduces data using a laser. Combinations of the above should also be considered within the scope of computer-readable media.

[0137] While the above disclosures represent exemplary aspects of the Disclosure, it should be noted that various changes and modifications can be made to this Specified without departing from the scope of the Disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims in the aspects of the Disclosure described herein do not need to be performed in any particular order. Furthermore, elements of the Disclosure may be described or claimed in the singular, but the plural is intended unless a limitation to the singular is explicitly stated. [Explanation of symbols]

[0138] 402 Electronic Components 410 cores 412 Core Dielectrics 412a First surface 412b Second surface 414 First conductive pattern 420 First Metallization Structure 422 First Dielectric 472, 482 Adhesive layer

Claims

1. A core comprising a core dielectric and a first conductive pattern on a first surface of the core dielectric, A first metallization structure on the first surface of the core dielectric, comprising a first dielectric, wherein the first dielectric has a first opening formed therein, A first electronic component disposed within the first opening of the first dielectric, A first adhesive layer that bonds the first electronic component to the core, A substrate comprising the above.

2. The substrate according to claim 1, wherein the thickness of the first electronic component is less than or equal to the thickness of the first dielectric.

3. The substrate according to claim 1, wherein the first adhesive layer comprises a resin material.

4. The substrate according to claim 3, wherein the space between the side wall of the first opening and the side wall of the first electronic component is at least partially filled with the resin material.

5. The substrate according to claim 1, wherein the first adhesive layer includes a bonding film.

6. The first metallization structure further includes one other dielectric on top of the first dielectric, and the one other dielectric includes a dielectric material. The substrate according to claim 5, wherein the space between the side wall of the first opening and the side wall of the first electronic component is at least partially filled with the dielectric material.

7. The core includes a second conductive pattern on the second surface of the core dielectric, The aforementioned substrate, A second metallization structure located below the second surface of the core dielectric, comprising a second dielectric, wherein the second dielectric has a second opening formed therein, A second electronic component disposed within the second opening of the second dielectric, A second adhesive layer for bonding the second electronic component to the core, The substrate according to claim 1, further comprising the above.

8. The substrate according to claim 1, further comprising a first conductive terminal on the upper surface of the first metallization structure, the first conductive terminal being electrically coupled to at least a portion of the first conductive pattern via the first metallization structure.

9. The core includes a second conductive pattern on the second surface of the core dielectric, The aforementioned substrate, A second metallization structure beneath the second surface of the core dielectric, A second conductive terminal on the lower surface of the second metallization structure, which is electrically coupled to at least a portion of the second conductive pattern via the second metallization structure, It also has, The substrate according to claim 8.

10. The first adhesive layer, Resin materials including polymer resins, epoxy resins, or combinations thereof, Adhesive materials based on the aforementioned resin material, non-resin material, or a combination thereof A substrate according to claim 1, including the above.

11. The substrate according to claim 1, wherein the core is a copper-clad laminate (CCL) core.

12. A method for manufacturing a circuit board, The core of the substrate includes a core dielectric and a first conductive pattern on the first surface of the core dielectric, and on the core, a first dielectric is formed, which is disposed on the first surface of the core dielectric and is a first part of the first metallization structure of the substrate. To form a first opening in the first dielectric, which exposes at least a first portion of the core, The first electronic component, which is placed in the first opening of the first dielectric, is attached to the core by a first adhesive layer that bonds the first electronic component to the core. Forming the second portion of the first metallization structure on the first dielectric and the first electronic component, Methods that include...

13. The mounting of the first electronic component onto the core is Dispensing the resin material in an uncured or partially cured form into the first opening on at least the first portion of the core, The first electronic component is placed in the first opening, wherein the dispensed resin material, in its uncured or partially cured state, at least partially fills a portion of the gap between the first electronic component and the core. The dispensed resin material is cured so that in its cured form it becomes the first adhesive layer. The method according to claim 12, including the method described in claim 12.

14. The method according to claim 13, wherein the curing of the dispensed resin material is performed during a build-up curing process for forming the second portion of the first metallization structure.

15. The method according to claim 13, wherein the dispensed resin material, in its uncured or partially cured state, at least partially fills the space between the side wall of the first opening and the side wall of the first electronic component.

16. The mounting of the first electronic component onto the core is The method according to claim 12, comprising placing the first electronic component together with a bonding film used as the first adhesive layer in the first opening.

17. Forming the second portion of the first metallization structure includes forming one other dielectric on the first dielectric, wherein the one other dielectric comprises a dielectric material. The method according to claim 12, wherein, while the other dielectric material is being formed on the first dielectric material, the space between the sidewall of the first opening and the sidewall of the first electronic component is at least partially filled with the dielectric material.

18. The method according to claim 17, wherein forming the other dielectric and filling the space at least partially is performed based on applying a layer of multilayer material on the first dielectric.

19. The method according to claim 18, wherein the layer of the laminated material comprises Ajinomoto Build-Up Film (ABF) or prepreg.

20. The core of the substrate, which includes a second conductive pattern on the second surface of the core dielectric, and below the core, a second dielectric, which is disposed below the second surface of the core dielectric and below the second surface of the core dielectric, is formed, which is a first portion of the second metallization structure of the substrate. The second opening of the second dielectric is formed to expose at least a second portion of the core, The second electronic component, which is placed in the second opening of the second dielectric, is attached to the core by a second adhesive layer that bonds the second electronic component to the core. Forming the second portion of the second metallization structure beneath the second dielectric and the second electronic component, The method according to claim 12, further comprising:

21. The method according to claim 12, further comprising forming a first conductive terminal on the upper surface of the first metallization structure, the first conductive terminal being electrically coupled to at least a portion of the first conductive pattern via the first metallization structure.

22. The core of the substrate, which includes a second conductive pattern on the second surface of the core dielectric, is provided below the core, and a second metallization structure is provided below the second surface of the core dielectric. A second conductive terminal is formed on the lower surface of the second metallization structure, the second conductive terminal being electrically coupled to at least a portion of the second conductive pattern via the second metallization structure. The method according to claim 21, further comprising:

23. The first adhesive layer, Resin materials including polymer resins, epoxy resins, or combinations thereof, Adhesive materials based on the aforementioned resin material, non-resin material, or a combination thereof The method according to claim 12, including the method described in claim 12.

24. The method according to claim 12, wherein the first electronic component includes one or more active components, one or more passive components, or any combination thereof.

25. An electronic device comprising a substrate, wherein the substrate is A core comprising a core dielectric and a first conductive pattern on a first surface of the core dielectric, A first metallization structure on the first surface of the core dielectric, comprising a first dielectric, wherein the first dielectric has a first opening formed therein, A first electronic component disposed within the first opening of the first dielectric, A first adhesive layer that bonds the first electronic component to the core, Equipped with, Electronic devices.

26. The electronic device according to claim 25, wherein the first electronic component includes one or more active components, one or more passive components, or any combination thereof.

27. The substrate further comprises a first conductive terminal on the upper surface of the first metallization structure, which is electrically coupled to at least a portion of the first conductive pattern via the first metallization structure. The electronic device according to claim 25, further comprising an integrated circuit (IC) device mounted on the substrate and electrically coupled to the first conductive terminal.

28. The core includes a second conductive pattern on the second surface of the core dielectric, The aforementioned substrate, A second metallization structure located below the second surface of the core dielectric, comprising a second dielectric, wherein the second dielectric has a second opening formed therein, A second electronic component disposed within the second opening of the second dielectric, A second adhesive layer for bonding the second electronic component to the core, It also has, The electronic device according to claim 25.

29. The first adhesive layer, Resin materials including polymer resins, epoxy resins, or combinations thereof, The aforementioned resin material, non-resin material, or adhesive material based on a combination thereof The electronic device according to claim 25, including.

30. The aforementioned electronic device Music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, or devices in automated vehicles. The electronic device according to claim 25, comprising at least one of the following.

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