Light-emitting substrate and display panel

Abstract

This application provides a light-emitting substrate and a display panel, the light-emitting substrate having a light-emitting region and a frame region located outside the light-emitting region, the first insulating layer of the light-emitting substrate including a first via located in the light-emitting region and a second via located in the frame region, and by installing a metal barrier within the second via in the frame region, the intrusion path of water vapor is blocked, thereby improving the problem in which black spots appear on existing OLED devices after reliability testing.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to light-emitting substrates and display panels.

Background Art

[0002] In recent years, Organic Light Emitting Diode (OLED) devices have attracted more attention due to features such as active light emission, high brightness, high resolution, wide viewing angle, fast response speed, low power consumption, and flexibility. OLED devices need to undergo a reliability test for high-temperature and high-humidity operation after the module process. For example, a reliability test is performed on OLED devices in an environment where the temperature is 85°C and the humidity is 85%. However, after conducting the reliability test on OLED devices, it has been found that black spots appear on the OLED devices, which seriously affects the quality of the OLED devices.

Summary of the Invention

Problems to be Solved by the Invention

[0003] This application provides a light-emitting substrate and a display panel that can improve the problem of black spots appearing on an OLED device after the existing OLED device undergoes a reliability test.

Means for Solving the Problems

[0004] In this application, the means for solving the above problems are as follows.

[0005] In the first embodiment of the present invention, an embodiment of the present invention provides a light-emitting substrate having a light-emitting region and a frame region located outside the light-emitting region, the light-emitting substrate includes a base substrate and a plurality of light-emitting units arranged in an array on the base substrate and located in the light-emitting region, each of the plurality of light-emitting units includes at least one first transistor, the first transistor includes a first active layer placed on the base substrate and a first source electrode and a first drain electrode placed on the side of the first active layer away from the base substrate, the light-emitting substrate further includes

[0006] A first insulating layer located on the side of the first active layer closer to the first source electrode or the first drain electrode, comprising a first via located in the light-emitting region and a second via located in the frame region, wherein at least one of the first source electrode and the first drain electrode is connected to the first active layer via the corresponding first via.

[0007] The invention includes a metal shielding portion installed within the second via, which overlaps with the second via when the light-emitting substrate is viewed from the front.

[0008] In a second configuration, embodiments of the present invention further provide a display panel comprising a light-emitting substrate, the light-emitting substrate having a light-emitting region and a frame region located outside the light-emitting region, the light-emitting substrate comprising a base substrate and a plurality of light-emitting units arranged in an array on the base substrate and located in the light-emitting region, each of the plurality of light-emitting units comprising at least one first transistor, the first transistor comprising a first active layer mounted on the base substrate and a first source electrode and a first drain electrode mounted on the side of the first active layer away from the base substrate, the light-emitting substrate further comprises

[0009] A first insulating layer located on the side of the first active layer closer to the first source electrode or the first drain electrode, comprising a first via located in the light-emitting region and a second via located in the frame region, wherein at least one of the first source electrode and the first drain electrode is connected to the first active layer via the corresponding first via.

[0010] The invention includes a metal shielding portion installed within the second via, which overlaps with the second via when the light-emitting substrate is viewed from the front. [Brief explanation of the drawing]

[0011] In the following, in order to more clearly explain the embodiments or technical solutions in the prior art, we will briefly introduce the accompanying drawings that may be used in the description of the embodiments or the prior art. However, the accompanying drawings in the following description represent only some embodiments of the present invention, and it will be obvious to those skilled in the art that other accompanying drawings can be obtained based on these drawings without any creative effort.

[0012] [Figure 1] This is a schematic diagram of a partial cross-sectional structure of an OLED device related to the relevant technology.

[0013] [Figure 2] This is a schematic diagram of a first partial planar structure of a light-emitting substrate according to an embodiment of the present application.

[0014] [Figure 3] This is a schematic diagram of the first partial film layer structure of the light-emitting substrate according to the embodiment of the present application.

[0015] [Figure 4] This is a schematic diagram of the second partial film layer structure of the light-emitting substrate according to the present invention.

[0016] [Figure 5] This is a schematic diagram of the third partial film layer structure of the light-emitting substrate according to the embodiment of the present application.

[0017] [Figure 6] It is a schematic diagram of a fourth partial film layer structure of a light-emitting substrate according to an embodiment of the present application.

[0018] [Figure 7] It is a schematic diagram of a fifth partial film layer structure of a light-emitting substrate according to an embodiment of the present application.

[0019] [Figure 8] It is a schematic diagram of a second partial planar structure of a light-emitting substrate according to an embodiment of the present application.

Mode for Carrying Out the Invention

[0020] The following description of each embodiment is made with reference to the accompanying drawings in order to illustrate specific embodiments in which the present application can be implemented. Directional terms such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side surface], etc. mentioned in the specification of the present application are only in the directions referred to in the accompanying drawings. Therefore, the directional terms used are for explaining and understanding the present application and are not intended to limit the present application. In the drawings, structurally similar parts are denoted by the same reference numerals. In the accompanying drawings, the thicknesses of some layers and regions are exaggerated for the sake of clear understanding and ease of explanation. That is, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily shown, but the present application is not limited thereto.

[0021] Regarding the problem that black spots appear on the OLED device after performing a reliability test on an existing OLED device, as a result of research by the inventor of the present application, through the analysis of the defect of black spots, no problems such as peeling of the film layer in the area of the black spots were found. Through further analysis, during the process of performing a reliability test on the OLED device, water vapor in a high-temperature and high-humidity environment permeates through the base substrate, and the permeated water vapor passes through the vias in the border area and enters the light-emitting area of the OLED device. It was found that black spots appeared on the OLED device after performing a reliability test on the OLED device.

[0022] Specifically, referring to FIG. 1, which is a schematic diagram of a partial cross-sectional structure of an OLED device according to the related art, the OLED device has a light-emitting region AA' and a border region NA' located outside the light-emitting region AA'. The OLED device includes a base substrate 10' and a first transistor 21' located on one side of the base substrate 10'. The first transistor 21' includes a first active layer 211', a source electrode 212', and a drain electrode 213'. The OLED device further includes a first insulating layer 30' located between the first active layer 211' and the source electrode 212' and the drain electrode 213', and a second insulating layer 60' coated on the source electrode 212' and the drain electrode 213'. The first insulating layer 30' is an inorganic layer, and the second insulating layer 60' is an organic layer. A first via 31', a source electrode 212', and a drain electrode 213' are provided in the first insulating layer 30' located in the light-emitting region AA', and each is connected to the first active layer 211' through the corresponding first via 31'.

[0023] During the process of forming the first via 31', exposure causes the size of the first vias 31' formed in the intermediate region and the edge regions of the four sides of the light-emitting region AA' to become uneven, with the size of the first vias 31' formed in the edge regions of the four sides of the light-emitting region AA' being smaller than the size of the first vias 31' formed in the intermediate region. In order to make the size of the first vias 31' formed throughout the entire light-emitting region AA' uniform, a second via 32', which is a dummy via not used for connecting each structure, may be formed in the first insulating layer 30' located in the frame region NA', and the second via 32' is filled with the second insulating layer 60'.

[0024] However, during reliability testing of OLED devices, water vapor in a high-temperature, high-humidity environment permeates the base substrate 10', and the permeated water vapor passes through the second via 32' in the bezel region NA' and enters the light-emitting region AA' of the OLED device. This is because the base layer 11' of the base substrate 10' is made of organic material. Although a barrier layer 12' made of inorganic material is installed on the base substrate 10', there are limits to the water vapor barrier performance of the barrier layer 12', and it is not possible to completely block water vapor permeation. In addition, during the process of forming the second via 32', there is a high possibility that microcracks will occur in the barrier layer 12' below the second via 32', weakening the water vapor barrier performance of the barrier layer 12', so that water vapor enters from the base layer 11', permeates the barrier layer 12' and reaches the second via 32'. On the other hand, because the second insulating layer 60' filled in the second via 32' is made of an organic material, water vapor penetrates the light-emitting region AA' along the second insulating layer 60' inside the second via 32', causing some of the light-emitting pixels in the light-emitting region AA' to fail and resulting in black spots. Through the inventor's tireless efforts, the cause of the black spots has now been discovered.

[0025] Therefore, this application provides a light-emitting substrate and a display panel for solving the above problems.

[0026] Embodiments of the present application provide a light-emitting substrate having a light-emitting region and a frame region located outside the light-emitting region, the light-emitting substrate includes a base substrate and a plurality of light-emitting units arranged in an array on the base substrate and located in the light-emitting region, each of the plurality of light-emitting units includes at least one first transistor, the first transistor includes a first active layer placed on the base substrate and a first source electrode and a first drain electrode placed on the side of the first active layer away from the base substrate, the light-emitting substrate further includes

[0027] A first insulating layer located on the side of the first active layer closer to the first source electrode or the first drain electrode, comprising a first via located in the light-emitting region and a second via located in the frame region, wherein at least one of the first source electrode and the first drain electrode is connected to the first active layer via the corresponding first via.

[0028] The invention includes a metal shielding portion installed within the second via, which overlaps with the second via when the light-emitting substrate is viewed from the front.

[0029] In one embodiment, the light-emitting substrate further includes an auxiliary shielding portion, the auxiliary shielding portion being located between the first insulating layer and the base substrate, the second via exposing a portion of the auxiliary shielding portion, and the metal shielding portion being connected to the auxiliary shielding portion.

[0030] In one embodiment, the auxiliary blocking section is installed on the same layer as the first active layer.

[0031] In one embodiment, the first transistor further includes a first gate electrode positioned in alignment with the first active layer, and the auxiliary blocker is located on the same layer as the first gate electrode.

[0032] In one embodiment, each of the plurality of light-emitting units further includes a second transistor connected to the first transistor, the second transistor including a second active layer, a second source electrode and a second drain electrode, the first insulating layer being located on the side of the second active layer closer to the second source electrode or the second drain electrode, and the auxiliary interruption portion being installed on the same layer as the second active layer.

[0033] In one embodiment, the first transistor is a polysilicon transistor, the second transistor is an oxide transistor, the first insulating layer further includes a third via located in the light-emitting region, at least one of the second source electrode and the second drain electrode is connected to the second active layer via the corresponding third via, the depth of the third via being less than or equal to the depth of the first via.

[0034] In one embodiment, the frame region includes a first frame region and a second frame region located on opposite sides of the light-emitting region, a binding region is provided within the first frame region, and the second via is located within the second frame region.

[0035] In one embodiment, the hole diameter of the first via is larger than the hole diameter of the second via.

[0036] In one embodiment, the base substrate includes at least one base layer and at least one blocking layer, the blocking layer being located between the base layer and the first transistor.

[0037] In one embodiment, the metal shielding portion is installed on the same layer as the first source electrode or the first drain electrode.

[0038] In one embodiment, each of the plurality of light-emitting units further includes a first electrode connected to the first transistor, the first electrode being located on the side of the first transistor away from the base substrate, and the metal shielding portion being installed on the same layer as one of the first electrode, the first source electrode, and the first drain electrode.

[0039] In one embodiment, the embodiment of the present application further provides a display panel, the display panel including one of the light-emitting substrates in the above embodiment.

[0040] In the light-emitting substrate and display panel according to the present application, the light-emitting substrate has a light-emitting region and a frame region located outside the light-emitting region, the first insulating layer of the light-emitting substrate includes a first via located in the light-emitting region and a second via located in the frame region, at least one of the first source electrode and the first drain electrode of the first transistor is connected to the first active layer via the corresponding first via, and the metal shielding portion is installed in the second via and overlaps with the second via when the light-emitting substrate is viewed from the front. In the present application, by installing the metal shielding portion in the second via of the frame region, the metal shielding portion blocks water vapor that has permeated the base substrate during reliability testing from passing through the second via, thereby blocking the water vapor intrusion path and improving the problem in existing OLED devices in which black spots appeared on the OLED device after reliability testing.

[0041] The following describes in detail the light-emitting substrate and display panel of the present application with reference to the attached drawings and specific embodiments.

[0042] Referring to Figures 2 and 3, Figure 2 is a schematic diagram of a first partial planar structure of a light-emitting substrate according to an embodiment of the present application, and Figure 3 is a schematic diagram of a first partial film layer structure of a light-emitting substrate according to an embodiment of the present application. As shown in Figure 2, the light-emitting substrate 100 has a light-emitting region AA and a frame region NA located outside the light-emitting region AA. The light-emitting substrate 100 includes a base substrate 10 and a plurality of light-emitting units 20 arranged in an array on the base substrate 10 and located in the light-emitting region AA.

[0043] Referring to Figures 2 and 3, each of the plurality of light-emitting units 20 includes at least one first transistor 21, the first transistor 21 including a first active layer 211 installed on the base substrate 10 and a first source electrode 212 and a first drain electrode 213 installed on the side of the first active layer 211 away from the base substrate 10. The light-emitting substrate 100 further includes a first insulating layer 30 and a metal barrier 40. The first insulating layer 30 is installed on the side of the first active layer 211 closer to the first source electrode 212 or the first drain electrode 213, and the first insulating layer 30 includes a first via 31 located in the light-emitting region AA and a second via 32 located in the frame region NA, and at least one of the first source electrode 212 and the first drain electrode 213 is connected to the first active layer 211 via the corresponding first via 31. The metal shielding portion 40 is installed within the second via 32, and when the light-emitting substrate 100 is viewed from the front, the metal shielding portion 40 overlaps with the second via 32.

[0044] In this embodiment, by installing a metal shielding portion 40 within the second via 32 of the frame region NA, the metal shielding portion 40 blocks water vapor that has permeated the base substrate 10 during reliability testing from passing through the second via 32, thereby blocking the water vapor intrusion path and improving the problem in existing OLED devices in which black spots appear on the OLED device after reliability testing.

[0045] Specifically, as shown in Figure 3, the base substrate 10 includes at least one base layer and at least one blocking layer, the blocking layer being located between the base layer and the first transistor 21. For example, the base substrate 1 includes a first base layer 11 and a first blocking layer 12 that are stacked, the first blocking layer 12 being located between the first base layer 11 and the first transistor 21. Optionally, the base substrate 10 may further include a second base layer 13 and a second blocking layer 14, the second blocking layer 14 being located between the first base layer 11 and the second base layer 13, the second base layer 13 being located on the side of the first base layer 11 away from the first blocking layer 12. Here, the material of the first base layer 11 and the material of the second base layer 13 are the same, and for example, both may be organic materials such as polyimide (PI), and the material of the second barrier layer 14 and the material of the first barrier layer 12 are the same, and for example, both may be inorganic materials such as silicon oxide and silicon nitride.

[0046] The first transistor 21 is mounted on the base substrate 10, more specifically, on the side of the first barrier layer 12 away from the first base layer 11. The first transistor 21 includes a first active layer 211, a first source electrode 212, a first drain electrode 213, and a first gate electrode 214. The first active layer 211 includes a channel region 2111 and source regions 2112 and drain regions 2113 located on opposite sides of the channel region 2111. The first source electrode 212 is connected to the source region 2112 of the first active layer 211, and the first drain electrode 213 is connected to the drain electrode of the first active layer 211. The first gate electrode 214 is mounted in alignment with the first active layer 211, more specifically, in alignment with the channel region 2111 of the first active layer 211.

[0047] Selectively, the first source electrode 212 and the first drain electrode 213 are installed in the same layer. In this application, "installed in the same layer" means that when at least two different structures are obtained by patterning a film layer formed from the same material during the manufacturing process, these at least two different structures are installed in the same layer. For example, in this embodiment, the first source electrode 212 and the first drain electrode 213 are patterned from the same metal film layer, so the first source electrode 212 and the first drain electrode 213 are installed in the same layer. Of course, in some other embodiments, the first source electrode 212 and the first drain electrode 213 do not have to be installed in the same layer.

[0048] Optionally, the first source electrode 212 and the first drain electrode 213 may be formed as multiple layers or a single layer containing a low-resistance material or a highly corrosion-resistant material, such as Al, Ti, Mo, Cu, Ni, or alloys thereof. For example, the first source electrode 212 and the first drain electrode 213 may be a stack of three layers of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo.

[0049] The first gate electrode 214 may be located on the side of the first active layer 211 closer to the base substrate 10, or it may be located on the side of the first active layer 211 further away from the base substrate 10. This embodiment describes the case where the first gate electrode 214 is located on the side of the first active layer 211 further away from the base substrate 10 as an example. The first gate electrode 214 is also located between the first active layer 211 and the first source electrode 212. The first gate electrode 214 may be formed as a plurality of layers or a single layer containing a low-resistance material such as Al, Ti, Mo, Cu, Ni or an alloy thereof, or a highly corrosion-resistant material such as a metallic material such as Ti or Mo. The material of the first active layer 211 includes a semiconductor material such as amorphous silicon (a-Si) or polycrystalline silicon (p-Si), for example, low-temperature polycrystalline silicon (LTPS).

[0050] The first insulating layer 30 is located between the first source electrode 212, the first drain electrode 213 and the first gate electrode 214, and the material of the first insulating layer 30 includes an inorganic material such as silicon oxide or silicon nitride. The light-emitting substrate 100 further includes a first gate electrode insulating layer 50 located between the first gate electrode 214 and the first active layer 211, and a second insulating layer 60 located on the side of the first transistor 21 away from the base substrate 10. The first gate electrode insulating layer 50 is coated on the surface of the first active layer 211 and the base substrate 10, and the material of the first gate electrode insulating layer 50 includes an inorganic material such as silicon oxide or silicon nitride. The second insulating layer 60 is coated on the surface of the first source electrode 212, the first drain electrode 213, and the first insulating layer 30. The second insulating layer 60 is an organic layer, and the material of the second insulating layer 60 includes polyacrylate, polyimide, silica-based organic materials, and the like.

[0051] The first insulating layer 30 is provided with a first via 31 and a second via 32. Specifically, the first via 31 is provided in the first insulating layer 30 located in the light-emitting region AA, and the second via 32 is provided in the first insulating layer 30 located in the frame region NA. The first via 31 penetrates the first insulating layer 30 and the first gate electrode insulating layer 50, exposing a portion of the first active layer 211. The first source electrode 212 is connected to the source region 2112 of the first active layer 211 via the corresponding first via 31, and the first drain electrode 213 is connected to the drain region 2113 of the first active layer 211 via the corresponding first via 31.

[0052] The metal barrier portion 40 is located within the second via 32, the depth of the second via 32 is greater than the depth of the first via 31, and the second via 32 penetrates the first insulating layer 30 and the first gate electrode insulating layer 50. Of course, in some other embodiments, of course, in other embodiments, under the influence of the etching process, when forming the second via 32, there may be a phenomenon of over-etching such that the second via 32 penetrates a portion of the first barrier layer 12, i.e., the second via 32 also penetrates a portion of the base substrate 10, in which case the metal barrier portion 40 is also located within the base substrate 10.

[0053] When the light-emitting substrate 100 is viewed from the front, the metal shielding portion 40 overlaps with the second via 32, that is, the orthographic projection of the metal shielding portion 40 onto the base substrate 10 is within the range of the orthographic projection of the second via 32 onto the base substrate 10. Here, the orthographic projection of the second via 32 onto the base substrate 10 is within the range of the orthographic projection of the metal shielding portion 40 onto the base substrate 10. In other words, the orthographic projection of the metal shielding portion 40 onto the base substrate 10 is such that the metal shielding portion 40 completely covers the inner wall of the second via 32, and the orthographic projection of the metal shielding portion 40 onto the base substrate 10 is such that the orthographic projection of the second via 32 onto the base substrate 10 completely covers the orthographic projection of the second via 32 onto the base substrate 10. For example, the metal shielding portion 40 fills the entire second via 32 so that the inside of the second via 32 is filled with the metal shielding portion 40.

[0054] The material of the metal shielding portion 40 is a metal or a metal oxide. Because metal materials or metal oxides are dense, they have better water vapor shielding performance compared to inorganic and organic materials. Therefore, by installing the metal shielding portion 40 inside the second via 32, it is possible to block the water vapor intrusion path, preventing water vapor from passing through the second via 32 and entering the light-emitting region AA. This avoids the problem of black spots appearing in existing OLED devices after reliability testing due to water vapor permeating the base substrate 10 and passing through the second via 32 to enter the light-emitting region AA, thereby improving the problem of black spots appearing in existing OLED devices after reliability testing.

[0055] Selectively, the metal shielding portion 40 is installed on the same layer as the first source electrode 212 or the first drain electrode 213. That is, since the metal shielding portion 40 is formed in the frame region NA during the process of forming the first source electrode 212 and the first drain electrode 213 in the light-emitting region AA, the metal shielding portion 40 is formed using the same process as the first source electrode 212 and the first drain electrode 213, thereby achieving improvement over the black spot problem without adding any extra processes.

[0056] In one embodiment, referring to Figures 2 and 3 in succession, the frame region NA includes a first frame region BSA and a second frame region TSA located on opposite sides of the light-emitting region AA, a binding region BDA is installed within the first frame region BSA, the binding region BDA is used for binding a driver IC or the like, and the second via 32 is located within the second frame region TSA.

[0057] In one embodiment, the arrangement pattern of the second via 32 is the same as the arrangement pattern of the first via 31, and the hole diameter of the first via 31 is larger than the hole diameter of the second via 32 in order to improve the uniformity of the first via 31 within the light-emitting region AA.

[0058] In one embodiment, with reference to Figures 2 to 4, Figure 4 is a schematic diagram of the second partial film layer structure of the light-emitting substrate 100 according to the embodiment of the present application. As shown in Figure 4, the light-emitting substrate 100 further includes an auxiliary barrier portion 70 located between the first insulating layer 30 and the base substrate 10, and differs from the above embodiment in that the second via 32 exposes a part of the auxiliary barrier portion 70 and the metal barrier portion 40 is connected to the auxiliary barrier portion 70.

[0059] When the light-emitting substrate 100 is viewed from the front, the auxiliary blocking portion 70 overlaps with the second via 32. That is, the orthographic projection of the auxiliary blocking portion 70 onto the base substrate 10 overlaps with the orthographic projection of the second via 32 onto the base substrate 10. Here, the orthographic projection of the second via 32 onto the base substrate 10 is within the range of the orthographic projection of the auxiliary blocking portion 70 onto the base substrate 10. In other words, the orthographic projection of the auxiliary blocking portion 70 onto the base substrate 10 is such that the orthographic projection of the second via 32 completely covers the orthographic projection of the base substrate 10.

[0060] The water vapor permeability of the auxiliary shielding portion 70 is lower than that of the inorganic material, and / or the etching rate of the auxiliary shielding portion 70 is lower than that of the inorganic material. For example, by making the water vapor permeability of the auxiliary shielding portion 70 lower than that of the base substrate 10, the water vapor shielding performance of the metal shielding portion 40 is improved, further improving the problem of black spots. By making the etching rate of the auxiliary shielding portion 70 lower than that of the first insulating layer 30, over-etching of the inorganic layer is avoided, and a thick inorganic layer can remain below the second via 32, improving the water vapor shielding effect and further improving the problem of black spots.

[0061] Selectively, the auxiliary blocking portion 70 is installed on the same layer as the first active layer 211. That is, since the auxiliary blocking portion 70 is formed in the frame region NA during the process of forming the first active layer 211 in the light-emitting region AA, the auxiliary blocking portion 70 is formed using the same process as the first active layer 211, thereby achieving improvement over the black spot problem without adding any extra steps. Since the etching rate of the first active layer 211 is lower than that of the inorganic material, the etching rate of the auxiliary blocking portion 70, which is installed on the same layer as the first active layer 211, is also lower than that of the inorganic material. In this way, when forming the second via 32, the auxiliary blocking portion 70 protects the inorganic layer below it (i.e., the first blocking layer 12) from over-etching and prevents microcracks in the inorganic layer. Further explanations can be found in the embodiments described above and are therefore omitted here.

[0062] In one embodiment, with reference to Figures 2 to 5, Figure 5 is a schematic diagram of a third partial film layer structure of the light-emitting substrate 100 according to an embodiment of the present application. As shown in Figure 5, the first transistor 21 further includes a first gate electrode 214 positioned in alignment with the first active layer 211, and the auxiliary blocker 70 is installed on the same layer as the first gate electrode 214, which is different from the above embodiment. The first gate electrode 214 is located on the side of the first active layer 211 away from the base substrate 10, for example, the first gate electrode 214 is located between the first active layer 211 and the first source electrode 212.

[0063] Since the material of the first gate electrode 214 is metal, the material of the auxiliary shielding portion 70, which is installed on the same layer as the first gate electrode 214, is also metal. Because the material of the metal is dense, it has better water vapor shielding performance compared to the cases of inorganic and organic materials. That is, by making the water vapor permeability of the auxiliary shielding portion 70 smaller than that of the inorganic material, the water vapor shielding performance of the metal shielding portion 40 can be further improved. Also, when forming the second via 32 by dry etching, the etching rate of the metal material is smaller than that of the inorganic material, that is, the etching rate of the auxiliary shielding portion 70 is smaller than that of the inorganic material. As a result, when etching the first insulating layer 30 to form the second via 32, the inorganic layer below the auxiliary shielding portion 70 is not etched due to the shielding of the auxiliary shielding portion 70, thereby maintaining a larger thickness of the inorganic layer and preventing microcracks in the inorganic layer below the auxiliary shielding portion 70. Here, the depth of the second via 32 is smaller than the depth of the first via 31. Further explanations can be found by referring to the embodiments described above, and are therefore omitted here.

[0064] In one embodiment, with reference to Figures 2 to 6, Figure 6 is a schematic diagram of a fourth partial film layer structure of the light-emitting substrate 100 according to an embodiment of the present application. As shown in Figure 6, each of the plurality of light-emitting units 20 further includes a first electrode 22 connected to the first transistor 21, the first electrode 22 is located on the side of the first transistor 21 away from the base substrate 10, and the metal shielding portion 40 is installed on the same layer as one of the first electrode 22, the first source electrode 212, and the first drain electrode 213, which is different from the above embodiment.

[0065] Specifically, the metal shielding portion 40 is installed on the same layer as the first electrode 22. That is, since the metal shielding portion 40 is formed in the frame region NA during the process of forming the first electrode 22 in the light-emitting region AA, the metal shielding portion 40 is formed using the same process as the first electrode 22, thereby achieving improvement in the black spot problem without adding any extra processes. Optionally, the first electrode 22 is a transparent conductive film such as ITO (Indium Tin Oxide, ITO). Of course, in order to improve the light emission efficiency of the light-emitting substrate 100, the first electrode 22 may also be a reflective electrode, for example, the first electrode 22 may be a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a combination thereof, or a single or multilayer formed of ITO, IZO, ZnO or In2O3.

[0066] Since the first electrode 22 is made of metal or metal oxide, the metal shielding portion 40, which is installed on the same layer as the first electrode 22, is also made of metal or metal oxide. Because metal or metal oxide materials are dense, they have better water vapor shielding performance compared to inorganic and organic materials. Therefore, by installing the metal shielding portion 40 inside the second via 32, it is possible to block the water vapor intrusion path, preventing water vapor from passing through the second via 32 and entering the light-emitting region AA. This avoids the problem of black spots appearing when water vapor permeates the base substrate 10 and enters the light-emitting region AA during high-temperature, high-humidity reliability testing, and improves the problem of black spots appearing on existing OLED devices after reliability testing.

[0067] Of course, the light-emitting substrate 100 further includes a second electrode and a light-emitting device, the light-emitting device emitting light under the combined action of the first electrode 22 and the second electrode, where optionally the first electrode 22 is the anode and the second electrode is the cathode. The light-emitting device may be a light-emitting layer formed of an organic light-emitting material, the light-emitting layer located between the first electrode 22 and the second electrode. Alternatively, the light-emitting device may be a light-emitting diode (LED) chip, a micro light-emitting diode (Micro-LED) chip, or a sub-millimeter light-emitting diode (Mini-LED) chip. Further explanations can be found in the embodiments described above and are therefore omitted here.

[0068] In one embodiment, with reference to Figures 2 to 7, Figure 7 is a schematic diagram of a fifth partial film layer structure of the light-emitting substrate 100 according to an embodiment of the present application. As shown in Figure 7, each of the plurality of light-emitting units 20 further includes a second transistor 23 connected to the first transistor 21, the second transistor 23 includes a second active layer 231, a second source electrode 232 and a second drain electrode 233, the first insulating layer 30 is located on the side of the second active layer 231 closer to the second source electrode 232 or the second drain electrode 233, and the auxiliary interruption unit 70 is installed on the same layer as the second active layer 231, which is different from the above embodiment.

[0069] Selectively, the first transistor 21 is a polysilicon transistor, the second transistor 23 is an oxide transistor, the first insulating layer 30 further includes a third via 33 located in the light-emitting region AA, and at least one of the second source electrode 232 and the second drain electrode 233 is connected to the second active layer 231 via the corresponding third via 33, where the depth of the third via 33 is less than or equal to the depth of the first via 31.

[0070] Specifically, the first transistor 21 further includes a third electrode 215 located on the side of the first gate electrode 214 away from the first active layer 211, and the third electrode 215 is positioned in alignment with the first gate electrode 214. The second transistor 23 further includes a second gate electrode 234 and a third gate electrode 235, and the third gate electrode 235 is located on the same layer as the third electrode 215. The second active layer 231 is located on the side of the third gate electrode 235 away from the base substrate 10, and the second gate electrode 234 is located on the side of the second active layer 231 away from the third gate electrode 235. The second source electrode 232 is located on the same layer as the second drain electrode 233, and the second source electrode 232 is located on the same layer as the first source electrode 212, and the first source electrode 212 and the first drain electrode 213 are located on the same layer. The second drain electrode 233 is connected to the second active layer 231 via the third via 33, and the second drain electrode 233 is also connected to the first active layer 211 via the corresponding first via 31. This enables the connection between the second drain electrode 233 and the first source electrode 212, and consequently, the connection between the second transistor 23 and the first transistor 21.

[0071] The light-emitting substrate 100 further includes a third insulating layer 80 located between the third electrode 215 and the first gate electrode 214, a second gate electrode insulating layer 90 located between the third gate electrode 235 and the second active layer 231, and a third gate electrode insulating layer 91 located between the second active layer 231 and the second gate electrode 234. The third insulating layer 80, the second gate electrode insulating layer 90, and the third gate electrode insulating layer 91 are all inorganic layers, and are inorganic layers formed from inorganic materials such as silicon oxide and silicon nitride. Here, the materials of the third electrode 215, the second gate electrode 234, and the third gate electrode 235 may be the same as those of the first gate electrode 214.

[0072] The material of the second active layer 231 includes a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO). Since the water vapor permeability of metal oxides is lower than that of inorganic materials, and the etching rate of metal oxides is lower than that of inorganic materials, the water vapor permeability of the auxiliary barrier 70, which is installed on the same layer as the second active layer 231, is lower than that of inorganic materials, and the etching rate of the auxiliary barrier 70 is lower than that of inorganic materials. As a result, the auxiliary barrier 70 can protect the inorganic layer below it.

[0073] Of course, in several other embodiments, the auxiliary blocking portion 70 may be further installed on the same layer as the metal layer such as the second gate electrode 234 or the third gate electrode 235, but such examples are omitted here. Further explanations can be found by referring to the embodiments described above and are therefore omitted here.

[0074] In one embodiment, with reference to Figures 2 to 8, Figure 8 is a schematic diagram of a second partial planar structure of the light-emitting substrate 100 according to the embodiment of the present application. As shown in Figure 8, the second via 32 is also installed within the first frame region BSA, and differs from the above embodiment in that the number of the second via 32 in the first frame region BSA is smaller than the number of the second via 32 in the second frame region TSA, so as to avoid the area occupied by the second via 32 in the first frame region BSA being too large and affecting the setting of the binding region BDA.

[0075] Selectively, the bezel area NA further includes a third bezel area LSA and a fourth bezel area RSA connected between the first bezel area BSA and the second bezel area TSA, and the second vias 32 are also located in the third bezel area LSA and the fourth bezel area RSA, and the number of the second vias 32 in the third bezel area LSA is smaller than the number of the second vias 32 in the second bezel area TSA in order to reduce the area of ​​the third bezel area LSA and the fourth bezel area RSA and realize a narrow bezel. Further explanation can be found in the embodiments described above and is therefore omitted here.

[0076] Based on the same inventive concept, embodiments of the present application further provide a display panel, the display panel including one of the light-emitting substrates 100 of the above embodiments. The display panel includes an organic light-emitting diode (OLED) display panel, a light-emitting diode (LED) display panel, a micro light-emitting diode (Micro-LED) display panel, or a sub-millimeter light-emitting diode (Mini-LED) display panel, etc.

[0077] From the above embodiments, the following should be understood.

[0078] In the light-emitting substrate and display panel according to the present application, the light-emitting substrate has a light-emitting region and a frame region located outside the light-emitting region, the first insulating layer of the light-emitting substrate includes a first via located in the light-emitting region and a second via located in the frame region, at least one of the first source electrode and the first drain electrode of the first transistor is connected to the first active layer via the corresponding first via, and the metal shielding portion is installed in the second via and overlaps with the second via when the light-emitting substrate is viewed from the front. In the present application, by installing the metal shielding portion in the second via of the frame region, the metal shielding portion blocks water vapor that has permeated the base substrate during reliability testing from passing through the second via, thereby blocking the water vapor intrusion path and improving the problem in existing OLED devices in which black spots appear on the OLED device after reliability testing.

[0079] In the above embodiments, emphasis is placed on the description of each embodiment, and some embodiments lack detailed descriptions, but the descriptions of other embodiments can be referenced.

[0080] While embodiments of the present application have been described in detail above, and specific examples have been used to illustrate the principles and embodiments of the present application, the above descriptions of embodiments are merely intended to aid in understanding the technical solutions and core ideas of the present application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the above embodiments, or that some technical features can be replaced with equivalent ones. Such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of each embodiment of the present application. [Explanation of Symbols]

[0081] 1: Base board 10: Base board 11: First base layer 12: First barrier layer 13: Second base layer 14: Second barrier layer 20: Light-emitting unit 21: The first transistor 22: First electrode 23: The second transistor 30: First insulating layer 31: The first beer 32: The second beer 33: The third beer 40: Metal shielding section 50: First gate electrode insulating layer 60: Second insulating layer 70: Auxiliary shutoff section 80: Third insulating layer 90: Second gate electrode insulating layer 91: Third gate electrode insulating layer 100: Light-emitting substrate 211: First active layer 212: First source electrode 213: First drain electrode 214: First gate electrode 215: Third electrode 231: Second active layer 232: Second source electrode 233: Second drain electrode 234: Second gate electrode 235: Third gate electrode 2111: Channel area 2112: Source area 2113: Drain area

Claims

1. A light-emitting substrate having a light-emitting region and a frame region located outside the light-emitting region, The light-emitting substrate includes a base substrate and a plurality of light-emitting units arranged in an array in the light-emitting region, each of the plurality of light-emitting units includes at least one first transistor, the first transistor includes a first active layer placed on the base substrate and a first source electrode and a first drain electrode placed on the side of the first active layer away from the base substrate, The light-emitting substrate further, A first insulating layer located on the side of the first active layer closer to the first source electrode or the first drain electrode, comprising a first via located in the light-emitting region and a second via located in the frame region, wherein at least one of the first source electrode and the first drain electrode is connected to the first active layer via the corresponding first via. A metal shielding portion installed within the second via, wherein, when the light-emitting substrate is viewed from the front, the metal shielding portion overlaps with the second via, A light-emitting substrate including a light-emitting substrate.

2. The light-emitting substrate further includes an auxiliary shielding portion, the auxiliary shielding portion being located between the first insulating layer and the base substrate, the second via exposing a portion of the auxiliary shielding portion, and the metal shielding portion being connected to the auxiliary shielding portion. The light-emitting substrate according to claim 1.

3. The auxiliary blocking section is installed on the same layer as the first active layer. The light-emitting substrate according to claim 2.

4. The first transistor further includes a first gate electrode positioned in alignment with the first active layer, and the auxiliary blocker is located on the same layer as the first gate electrode. The light-emitting substrate according to claim 2.

5. Each of the plurality of light-emitting units further includes a second transistor connected to the first transistor, the second transistor including a second active layer, a second source electrode and a second drain electrode, the first insulating layer is located on the side of the second active layer closer to the second source electrode or the second drain electrode, and the auxiliary interruption portion is installed on the same layer as the second active layer. The light-emitting substrate according to claim 2.

6. The first transistor is a polysilicon transistor, and the second transistor is an oxide transistor. The first insulating layer further includes a third via located in the light-emitting region, and at least one of the second source electrode and the second drain electrode is connected to the second active layer via the corresponding third via. The depth of the third via is less than or equal to the depth of the first via. The light-emitting substrate according to claim 5.

7. The frame region includes a first frame region and a second frame region located on opposite sides of the light-emitting region, a binding region is provided within the first frame region, and the second via is located within the second frame region. The light-emitting substrate according to claim 1.

8. The diameter of the hole in the first via is larger than the diameter of the hole in the second via. The light-emitting substrate according to claim 7.

9. The base substrate includes at least one base layer and at least one blocking layer, the blocking layer being located between the base layer and the first transistor. The light-emitting substrate according to claim 1.

10. The metal shielding portion is installed on the same layer as the first source electrode or the first drain electrode. The light-emitting substrate according to claim 1.

11. Each of the plurality of light-emitting units further includes a first electrode connected to the first transistor, the first electrode being located on the side of the first transistor away from the base substrate, and the metal shielding portion being installed on the same layer as one of the first electrode, the first source electrode, and the first drain electrode. The light-emitting substrate according to claim 1.

12. A display panel including a light-emitting substrate, The light-emitting substrate has a light-emitting region and a frame region located outside the light-emitting region. The light-emitting substrate includes a base substrate and a plurality of light-emitting units arranged in an array in the light-emitting region, each of the plurality of light-emitting units includes at least one first transistor, the first transistor includes a first active layer placed on the base substrate and a first source electrode and a first drain electrode placed on the side of the first active layer away from the base substrate, The light-emitting substrate further, A first insulating layer located on the side of the first active layer closer to the first source electrode or the first drain electrode, comprising a first via located in the light-emitting region and a second via located in the frame region, wherein at least one of the first source electrode and the first drain electrode is connected to the first active layer via the corresponding first via. A metal shielding portion installed within the second via, wherein, when the light-emitting substrate is viewed from the front, the metal shielding portion overlaps with the second via, A display panel including this.

13. The light-emitting substrate further includes an auxiliary shielding portion, the auxiliary shielding portion being located between the first insulating layer and the base substrate, the second via exposing a portion of the auxiliary shielding portion, and the metal shielding portion being connected to the auxiliary shielding portion. The display panel according to claim 12.

14. The auxiliary blocking section is installed on the same layer as the first active layer. The display panel according to claim 13.

15. The first transistor further includes a first gate electrode positioned in alignment with the first active layer, and the auxiliary blocker is located on the same layer as the first gate electrode. The display panel according to claim 13.

16. Each of the plurality of light-emitting units further includes a second transistor connected to the first transistor, the second transistor including a second active layer, a second source electrode and a second drain electrode, the first insulating layer being located on the side of the second active layer closer to the second source electrode or the second drain electrode, and the auxiliary interruption portion being installed on the same layer as the second active layer. The display panel according to claim 13.

17. The first transistor is a polysilicon transistor, and the second transistor is an oxide transistor. The first insulating layer further includes a third via located in the light-emitting region, and at least one of the second source electrode and the second drain electrode is connected to the second active layer via the corresponding third via. The depth of the third via is less than or equal to the depth of the first via. The display panel according to claim 16.

18. The frame region includes a first frame region and a second frame region located on opposite sides of the light-emitting region, a binding region is provided within the first frame region, and the second via is located within the second frame region. The display panel according to claim 12.

19. The diameter of the hole in the first via is larger than the diameter of the hole in the second via. The display panel according to claim 18.

20. Each of the plurality of light-emitting units further includes a first electrode connected to the first transistor, the first electrode being located on the side of the first transistor away from the base substrate, and the metal shielding portion being installed on the same layer as one of the first electrode, the first source electrode, and the first drain electrode. The display panel according to claim 12.

Images