METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE

Abstract

To provide a manufacturing method of a nitride semiconductor device capable of highly accurately controlling an acceptor concentration on a surface of a gallium nitride layer, and the nitride semiconductor device.SOLUTION: A manufacturing method of a nitride semiconductor device includes: a first implantation step of performing ion implantation of a p-type impurity at one face side of a gallium nitride layer, thereby forming a p-type implantation layer in the gallium nitride layer; a diffusion step of diffusing the p-type impurity contained in the p-type implantation layer by applying heat treatment to the gallium nitride layer, thereby forming a p-type diffusion layer in the gallium nitride layer; and a surface concentration control step of removing a part of the p-type diffusion layer from the one face side, thereby matching a surface concentration of the p-type diffusion layer to a preset value.SELECTED DRAWING: Figure 2C

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device. [Background technology]

[0002] It is known that when a gallium nitride (GaN)-based material is doped with impurities and the impurity-doped GaN-based material is subjected to a heat treatment, roughness having irregularities occurs on the surface of the GaN-based material (see, for example, Patent Document 1). Patent Document 1 discloses that the surface of the GaN-based material is polished after the heat treatment in order to remove the surface roughness and the like that occurs during the heat treatment. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-5190 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to improve the characteristics of devices formed on the gallium nitride layer, it is desirable to control the acceptor concentration on the surface of the gallium nitride layer with high precision.

[0005] The present invention has been made in light of the above-mentioned problems, and has an object to provide a manufacturing method for a nitride semiconductor device and a nitride semiconductor device that are capable of controlling the acceptor concentration on the surface of a gallium nitride layer with high precision. [Means for solving the problem]

[0006] In order to solve the above problems, a manufacturing method for a nitride semiconductor device according to one aspect of the present invention includes a first implantation step of ion-implanting a p-type impurity into one surface side of a gallium nitride layer to form a p-type implantation layer in the gallium nitride layer, a diffusion step of forming a p-type diffusion layer in the gallium nitride layer by subjecting the gallium nitride layer to a heat treatment to diffuse the p-type impurity contained in the p-type implantation layer, and a surface concentration adjustment step of removing a part of the p-type diffusion layer from the one surface side to adjust a surface concentration of the p-type diffusion layer to a preset value.

[0007] A nitride semiconductor device according to one aspect of the present invention includes a gallium nitride layer and a p-type diffusion layer provided on one surface side of the gallium nitride layer, the p-type diffusion layer having a concentration peak position where the concentration of p-type impurity is maximum, the concentration peak position being present on a surface of the p-type diffusion layer. Effect of the Invention

[0008] According to the present invention, it is possible to provide a manufacturing method for a nitride semiconductor device and a nitride semiconductor device that are capable of controlling the acceptor concentration in the surface of a gallium nitride layer with high precision. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1A is a cross-sectional view illustrating a method for manufacturing a GaN semiconductor device according to a first embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view showing a method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention. [Figure 1C] FIG. 1C is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. [Figure 2A] FIG. 2A is a graph showing an example of the concentration distribution of Mg and N in the manufacturing process of the GaN semiconductor device according to the first embodiment of the present invention. [Figure 2B] FIG. 2B is a graph showing an example of the concentration distribution of Mg and N in the manufacturing process of the GaN semiconductor device according to the first embodiment of the present invention. [Figure 2C]FIG. 2C is a graph showing an example of the concentration distribution of Mg and N in the manufacturing process of the GaN semiconductor device according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a graph showing the results of a simulation of the relationship between the heat treatment temperature and the Mg concentration after the heat treatment. [Figure 3B] FIG. 3B is a graph showing the results of a simulation of the relationship between the heat treatment temperature and the Mg concentration after the heat treatment. [Figure 4A] FIG. 4A is a graph showing the results of a simulation of the relationship between the implantation concentration of N and the Mg concentration after heat treatment (when the Mg implantation peak concentration is 4E+19 cm −3 ). [Figure 4B] FIG. 4B is a graph showing the results of a simulation of the relationship between the N implantation concentration and the Mg concentration after heat treatment (when the Mg implantation peak concentration is 4E+19 cm −3 ). [Figure 5A] FIG. 5A is a graph showing the results of a simulation of the relationship between the implantation concentration of N and the Mg concentration after heat treatment (when the Mg implantation peak concentration is 2E+19 cm −3 ). [Figure 5B] FIG. 5B is a graph showing the results of a simulation of the relationship between the N implantation concentration and the Mg concentration after heat treatment (when the Mg implantation peak concentration is 2E+19 cm −3 ). [Figure 6A] FIG. 6A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 6B] FIG. 6B is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 6C] FIG. 6C is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 6D] FIG. 6D is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 6E] FIG. 6E is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 6F] FIG. 6F is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 7A] FIG. 7A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to embodiment 3 of the present invention. [Figure 7B] FIG. 7B is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the third embodiment of the present invention. [Figure 7C] FIG. 7C is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the third embodiment of the present invention. [Figure 7D] FIG. 7D is a cross-sectional view showing a manufacturing method of a GaN semiconductor device according to the third embodiment of the present invention. [Figure 7E] FIG. 7E is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the third embodiment of the present invention. [Figure 7F] FIG. 7F is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the third embodiment of the present invention. [Figure 8A] FIG. 8A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to embodiment 4 of the present invention. [Figure 8B] FIG. 8B is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the fourth embodiment of the present invention. [Figure 8C] FIG. 8C is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to embodiment 4 of the present invention. [Figure 8D] FIG. 8D is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the fourth embodiment of the present invention. [Figure 8E] FIG. 8E is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the fourth embodiment of the present invention. [Figure 8F] FIG. 8F is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to embodiment 4 of the present invention. [Figure 8G] FIG. 8G is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the fourth embodiment of the present invention. [Figure 8H] FIG. 8H is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to embodiment 4 of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description. In addition, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from each other.

[0011] In the following description, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up." In the following description, + and - attached to p and n respectively mean that the semiconductor region has a relatively high or low impurity concentration compared to a semiconductor region without + or -. However, even if the same p and p are attached to semiconductor regions, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0012] <Embodiment 1> A method for manufacturing a gallium nitride semiconductor device (hereinafter, GaN semiconductor device) 1 according to embodiment 1 of the present invention will be described. FIGS. 1A to 1C are cross-sectional views showing a method for manufacturing the GaN semiconductor device 1 according to embodiment 1 of the present invention. FIGS. 2A to 2C are graphs showing an example of the concentration distribution of Mg and N in the process of manufacturing the GaN semiconductor device 1 according to embodiment 1 of the present invention. Specifically, FIG. 2A shows the concentration distribution of Mg and N in the cross section shown in FIG. 1A. FIG. 2B shows the concentration distribution of Mg and N in the cross section shown in FIG. 1B. FIG. 2C shows the concentration distribution of Mg and N in the cross section shown in FIG. 1C. In each of the graphs in FIGS. 2A to 2C, the horizontal axis shows the depth (nm) from the surface 10a of the GaN substrate 10, and the vertical axis shows the concentration (cm -3) The horizontal axis shows the depth of 0 nm, which indicates the surface position of the GaN substrate before the implanted layer is removed. The GaN semiconductor device 1 is manufactured by various types of equipment such as a film forming apparatus, an exposure apparatus, an etching apparatus, an ion implantation apparatus, a heat treatment apparatus, a CMP (Chemical Mechanical Polishing) apparatus, etc. Hereinafter, these apparatuses are collectively referred to as manufacturing equipment.

[0013] 1A, the manufacturing equipment ions-implants magnesium (Mg; an example of a "p-type impurity" of the present invention) into a surface 10a (an example of a "one surface" of the present invention) of a GaN substrate 10 (an example of a "gallium nitride layer" of the present invention) to form a p-type implanted layer 23' in the GaN substrate 10 (an example of a "first implantation step" of the present invention). The GaN substrate 10 may be a bulk substrate of single crystal, or may be a substrate in which a single crystal GaN layer is formed on a single crystal GaN substrate by epitaxial growth.

[0014] Next, the manufacturing equipment ions-implants an element other than Mg into the surface 10a side of the GaN substrate 10 (an example of the "second implantation step" of the present invention). For example, an element other than Mg is nitrogen element (N). By ion-implanting N into the surface 10a side of the GaN substrate 10, crystal defects are generated in the p-type implantation layer 23' and a layer located below the p-type implantation layer 23'.

[0015] In the N ion implantation step, the N implantation conditions may be set so that the depth from the surface 10a of the GaN substrate 10 to the N implantation peak position (hereinafter, N implantation peak depth) is deeper than the depth from the surface 10a to the Mg implantation peak position (hereinafter, Mg implantation peak depth) (see FIG. 2A). In this step, the N implantation conditions may be set so that the concentration at the N implantation peak position is equal to or less than one time the concentration at the Mg implantation peak position (see FIG. 2A). The N implantation conditions include, for example, the N implantation energy and the N dose. The implantation energy may be called the acceleration energy. The larger the N implantation energy, the deeper the N implantation depth from the surface 10a of the GaN substrate 10. The larger the N dose, the higher the N concentration. The above-mentioned Mg ion implantation step and N ion implantation step may be performed in any order without any restriction. The manufacturing apparatus may ion implant Mg and then ion implant N as described above, or may ion implant Mg and then ion implant N.

[0016] Next, the manufacturing equipment applies a heat treatment to the GaN substrate 10. By this heat treatment, as shown in FIG. 1B and FIG. 2B, Mg contained in the p-type implantation layer 23' is diffused to the periphery (for example, in the depth direction) of the p-type implantation layer 23' and activated (one example of the "diffusion step" of the present invention). As a result, the p-type diffusion layer 23 is formed in the GaN substrate 10. The surface portion of the p-type diffusion layer 23 includes the p-type implantation layer 23' after Mg is diffused. Furthermore, by the above heat treatment, at least a part of the crystal defects caused by the ion implantation of Mg and N is restored. The depth direction is, for example, the thickness direction of the GaN substrate 10, which is a direction perpendicular to the surface 10a of the GaN substrate 10.

[0017] As shown in the simulation results described later (see FIGS. 3A and 3B), the maximum temperature of the heat treatment is preferably equal to or higher than 1300° C. For example, by subjecting GaN substrate 10 to a heat treatment having a maximum temperature of equal to or higher than 1300° C. and equal to or lower than 1500° C., Mg ions implanted into GaN substrate 10 can be easily diffused to the periphery of GaN substrate 10 (for example, in the depth direction).

[0018] Next, as shown in FIG. 1C, the manufacturing equipment removes a part of p-type diffusion layer 23 from surface 10a side of GaN substrate 10 that has been subjected to heat treatment, so that the Mg concentration at surface 10a of GaN substrate 10 (hereinafter, surface Mg concentration) is adjusted to a preset value (one example of the "surface concentration adjustment step" of the present invention). The thickness of GaN substrate 10 removed from surface 10a side is, for example, 150 nm or more and 300 nm or less. The preset value is, for example, 1.0E+17 cm -3 More than 1.0E+19cm -3 The following is the case. Note that E+ is an exponential notation. For example, 1.0E+17 is 1.0×10 17 means...

[0019] For example, the relationship between the depth from the surface 10a of the GaN substrate 10 and the Mg concentration is determined in advance by simulation or experiment, as shown in FIG. 2C. Then, the surface 10a side of the GaN substrate 10 is removed by a thickness (depth) based on the above relationship so as to obtain a desired surface Mg concentration. For example, at least one of CMP processing and dry etching may be used as the removal method. Alternatively, at least one of CMP processing and dry etching may be used in addition to wet etching, or only wet etching may be used if the etching rate is high. This allows the surface Mg concentration after removal to be adjusted to a desired value.

[0020] 1C, at least the range from surface 10a of GaN substrate 10 to the Mg implantation peak position may be removed. That is, the thickness of the surface layer portion removed from GaN substrate 10 may be equal to or greater than the Mg implantation peak depth. This allows the Mg concentration distribution to be adjusted so that the concentration peak position where the Mg concentration is maximum in p-type diffusion layer 23 is located on surface 10a after removal (see FIG. 2C). Through the above steps, the GaN semiconductor device 1 according to embodiment 1 is completed.

[0021] As described above, the manufacturing method of the GaN semiconductor device 1 according to the first embodiment of the present invention includes a first implantation step of ion-implanting Mg into the front surface 10a side of the GaN substrate 10 to form a p-type implantation layer 23′ in the GaN substrate 10, a diffusion step of performing a heat treatment on the GaN substrate 10 to diffuse the Mg contained in the p-type implantation layer 23′ to form a p-type diffusion layer 23 in the GaN substrate 10, and a surface concentration adjustment step of removing a portion of the p-type diffusion layer 23 from the front surface 10a side of the GaN substrate 10 to adjust the surface concentration of the p-type diffusion layer 23 to a preset value.

[0022] According to this method, after Mg is diffused from p-type implantation layer 23' to form p-type diffusion layer 23, the surface portion of p-type diffusion layer 23 is removed. The surface portion of p-type diffusion layer 23 is a portion that includes p-type implantation layer 23' and contains many crystal defects due to ion implantation. By removing this surface portion, it is possible to reduce the crystal defects on the surface of p-type diffusion layer 23. In addition, by removing the surface portion in which the activation rate of Mg is low and the variation in Mg concentration is large due to the influence of crystal defects, it is possible to control the acceptor concentration (e.g., activated surface Mg concentration) on the surface of p-type diffusion layer 23 with high precision.

[0023] Furthermore, the method for manufacturing the GaN semiconductor device 1 according to the first embodiment of the present invention may further include a second implantation step of ion-implanting N into the front surface 10a side of the GaN substrate 10 before the diffusion step. This can promote the diffusion of Mg in the diffusion step, as shown in the simulation results described later (see FIGS. 3A to 5B), and facilitates increasing the surface Mg concentration of the p-type diffusion layer 23.

[0024] A GaN semiconductor device 1 according to a first embodiment of the present invention includes a GaN substrate 10 and a p-type diffusion layer 23 provided on the surface 10a side of the GaN substrate 10. The p-type diffusion layer 23 has a concentration peak position where the Mg concentration is maximum. The concentration peak position is present at the surface of the p-type diffusion layer 23. The surface Mg concentration of the p-type diffusion layer 23 is the maximum value of the Mg concentration in the p-type diffusion layer 23, and its value is, for example, 1.0E+17 cm -3 More than 1.0E+19cm -3 The GaN semiconductor device 1 having such a configuration can be manufactured by the above-mentioned manufacturing method, so that the acceptor concentration in the surface 10a of the GaN substrate 10 can be controlled with high precision.

[0025] <Simulation results> (Relationship between heat treatment temperature and Mg concentration after heat treatment) 3A and 3B are graphs showing the results of a simulation of the relationship between the heat treatment temperature and the Mg concentration after heat treatment. Specifically, FIG. 3A shows the results of a simulation of the Mg concentration distribution in the depth direction when Mg ions are implanted into a GaN substrate and the GaN substrate is heat treated under conditions of a maximum temperature of 1300°C and a treatment time at the maximum temperature of 5 minutes. FIG. 3B shows the results of a simulation of the Mg concentration distribution in the depth direction when Mg ions are implanted into a GaN substrate and the GaN substrate is heat treated under conditions of a maximum temperature of 1200°C and a treatment time at the maximum temperature of 5 minutes. In FIGS. 3A and 3B, the horizontal axis shows the depth (μm) from the surface of the GaN substrate, and the vertical axis shows the Mg concentration (cm -3 )

[0026] In Figures 3A and 3B, "Mg only" indicates data when only Mg is implanted into the GaN substrate. "Mg+N" indicates data when both Mg and N are implanted into the GaN substrate. "Mg+N, as-impla" indicates data immediately after Mg and N are implanted (i.e., before heat treatment). In Figures 3A and 3B, "Mg+N, as-impla" is the same data.

[0027] In the simulation shown in FIG. 3A and FIG. 3B, Mg was implanted with an energy of 10 keV, and the Mg concentration at the Mg implantation peak position (hereinafter, Mg implantation peak concentration) was 4E+19 cm -3 The Mg dose was adjusted so that N was implanted into the GaN substrate at a depth of 300 nm from the surface to the surface of the GaN substrate at a concentration of 6E+18 cm -3 Multi-stage ion implantation was performed so as to obtain a constant concentration of 1.0.

[0028] As can be seen by comparing FIG. 3A and FIG. 3B, it was confirmed that Mg is more likely to diffuse in the depth direction in the heat treatment after ion implantation of Mg at 1300°C than at 1200°C. In addition, as can be seen by comparing "Mg only" and "Mg+N" in the simulation result at 1300°C in FIG. 3B, the surface concentration of Mg (for example, the concentration in the depth range of 0.15 μm to 0.3 μm) can be increased when N is ion implanted. This is considered to be because crystal defects are generated by ion implantation of N, and Mg is thermally diffused into the layer where the crystal defects are generated. It is considered that Mg is more likely to thermally diffuse in a layer where crystal defects are generated than in a layer without crystal defects.

[0029] (Relationship between N implantation concentration and Mg concentration after heat treatment) (1) Mg implantation peak concentration is 4E+19cm -3 in the case of 4A and 4B show the relationship between the N implantation concentration and the Mg concentration after heat treatment (the Mg implantation peak concentration is 4E+19 cm -3 4A and 4B are graphs showing the results of a simulation of the case where Mg and N (or only Mg) are ion-implanted into a GaN substrate, and then the GaN substrate is heat-treated under the conditions of a maximum temperature of 1300° C. and a treatment time at the maximum temperature of 5 minutes.

[0030] In this simulation, Mg is implanted at 10 keV energy with a peak Mg implant concentration of 4E+19 cm -3 In this simulation, a total of six conditions were prepared as N ion implantation conditions: the three conditions shown in FIG. 4A and the three conditions shown in FIG. 4B. FIG. 4A shows a simulation in which the N implantation concentration was constant (0 cm -3 , 1.0E+17cm -3 , 1.0E+18cm -34B shows the results when N was implanted in multiple stages so that the implantation concentration of N was constant (3.0E+18 cm 3 ) in the range from the surface of the GaN substrate to a depth of 300 nm. -3 , 6.0E+18cm -3 , 1.0E+19cm -3 4A shows the results when N is implanted in multiple steps so that the implantation concentration is 0 cm -3 4A and 4B show the case where only Mg was ion-implanted without ion-implanting N. As shown in Fig. 4A and 4B, it was confirmed that the higher the implantation concentration of N, the easier Mg diffuses in the depth direction.

[0031] (2) Mg implantation peak concentration is 2E+19cm -3 in the case of 5A and 5B show the relationship between the N implantation concentration and the Mg concentration after heat treatment (the Mg implantation peak concentration is 2E+19 cm -3 5A and 5B are graphs showing the results of a simulation of the case where Mg and N (or only Mg) are ion-implanted into a GaN substrate, and then the GaN substrate is heat-treated under the conditions of a maximum temperature of 1300° C. and a treatment time at the maximum temperature of 5 minutes.

[0032] The only difference between the simulations shown in Figures 5A and 5B and those shown in Figures 4A and 4B is the Mg implantation peak concentration. In this simulation, Mg is implanted with an implantation energy of 10 keV, and the Mg implantation peak concentration is 2E+19 cm -3 FIG. 5A shows a single-stage ion implantation in which the N implantation concentration was constant (0 cm -3 , 1.0E+17cm -3 , 1.0E+18cm -3 5B shows the results when N was implanted in multiple stages so that the implantation concentration of N was constant (3.0E+18 cm 3 ) in the range from the surface of the GaN substrate to a depth of 300 nm. -3 , 6.0E+18cm -3, 1.0E+19cm -3 ) is obtained by multi-stage ion implantation of N.

[0033] As shown in Figures 5A and 5B, this simulation also confirmed that the higher the N implantation concentration, the easier Mg diffuses in the depth direction. Also, as can be seen by comparing Figures 4A and 4B with Figures 5A and 5B, it was confirmed that the Mg concentration in the Mg diffusion layer increases when the Mg implantation peak concentration is increased. The Mg diffusion layer is a layer in which Mg is diffused by heat treatment.

[0034] In addition, from the results of Figures 4A to 5B, it was found that the Mg concentration in the Mg diffusion layer can be controlled by the implantation concentration of N and Mg. By obtaining the analysis results (profiles) as shown in Figures 4A to 5B and removing a predetermined thickness of the surface part of the Mg diffusion layer based on the obtained profile, the surface Mg concentration after removal can be controlled to a desired value (for example, 1.0E+19 cm -3 It was found that the following values ​​could be adjusted:

[0035] <Embodiment 2> Next, a method for manufacturing the GaN semiconductor device 1A according to the second embodiment of the present invention will be described. FIGS. 6A to 6F are cross-sectional views showing a method for manufacturing the GaN semiconductor device 1A according to the second embodiment of the present invention. As shown in FIG. 6A, a manufacturing apparatus forms a GaN layer 12 on the surface of an n+ type GaN substrate 11. For example, the GaN substrate 11 is an N+ type GaN single crystal substrate. The n-type impurity contained in the GaN substrate 11 is one or more elements selected from the group consisting of Si (silicon), O (oxygen), and Ge (germanium). As an example, the n-type impurity contained in the GaN substrate 11 is Si or O, and the impurity concentration of Si in the GaN substrate 11 is 5×10 17 cm -3The manufacturing equipment epitaxially grows an n-type GaN layer 12 on a GaN substrate 11 by metal organic chemical vapor deposition (MOCVD). In the process of epitaxially growing the GaN layer 12, the manufacturing equipment dopes the GaN layer 12 with Si as an n-type impurity. The concentration (carrier concentration) of the n-type impurity in the GaN layer 12 is, for example, 1.0E+16 cm -3 The thickness of the GaN layer 12 after deposition is, for example, 10 μm.

[0036] Next, as shown in FIG. 6B, the manufacturing equipment forms a p+ type implantation layer 21' on the surface 10a side of the GaN substrate 10. For example, the manufacturing equipment forms a first mask (not shown) on the surface 10a of the GaN substrate 10. The first mask is made of a silicon oxide (SiO2) film, an aluminum oxide (Al2O3) film, or a photoresist. The first mask has a shape that opens above the region where the p+ type implantation layer 21' is to be formed and covers above the other regions. The manufacturing equipment ions-implants Mg as a p-type impurity into the surface 10a side of the GaN substrate 10 on which the first mask is formed (first Mg implantation step; an example of the "first implantation step" of the present invention).

[0037] In the first Mg implantation step, the depth from the surface 10a of the GaN substrate 10 to the Mg implantation peak position (i.e., the Mg implantation peak depth) is 20 nm, and the Mg concentration at the Mg implantation peak position (i.e., the Mg implantation peak concentration) is 1.0E+20 cm -3 The Mg implantation conditions are set so that: By implanting Mg ions under the conditions set in this way, a p+ type implanted layer 21' is formed on the front surface 10a side of the GaN substrate 10. After the p+ type implanted layer 21' is formed, the manufacturing equipment removes the first mask.

[0038] Next, the manufacturing equipment ions-implants N into the front surface 10a of the GaN substrate 10 (first N implantation step; an example of the "second implantation step" of the present invention). In the first N implantation step, the depth from the front surface 10a of the GaN substrate 10 to the N implantation peak position (i.e., N implantation peak depth) is 100 nm, and the N concentration at the N implantation peak position (i.e., N implantation peak concentration) is 1.0E+20 cm -3The N implantation conditions are set so that N ions are implanted under the conditions set in this way, whereby crystal defects can be generated in the p+ type implantation layer 21′ and the layer located below the p+ type implantation layer 21′.

[0039] Next, the manufacturing equipment forms a p-type implantation layer 23' on the surface 10a side of the GaN substrate 10 (second Mg implantation step; an example of the "first implantation step" of the present invention). For example, the manufacturing equipment forms a second mask (not shown) on the surface 10a of the GaN substrate 10. The second mask is made of a SiO2 film, an Al2O3 film, or a photoresist. The second mask has an opening above the region where the p-type implantation layer 23' is to be formed, and has a shape that covers the other regions above. The manufacturing equipment ions implants Mg as a p-type impurity into the surface 10a side of the GaN substrate 10 on which the second mask has been formed. In the second Mg implantation step, the Mg implantation peak depth is 20 nm and the Mg implantation peak concentration is 4.0E+19 cm -3 The Mg implantation conditions are set so that: Mg ions are implanted under the conditions set in this way, thereby forming a p-type implanted layer 23'. After the p-type implanted layer 23' is formed, the manufacturing equipment removes the second mask.

[0040] Next, the manufacturing equipment ion-implants N into the front surface 10a of the GaN substrate 10 (a second N implantation step; an example of the "second implantation step" of the present invention). In the second N implantation step, the N implantation peak depth is 500 nm, and the N implantation peak concentration is 1.0E+19 cm -3 The N implantation conditions are set so that N ions are implanted under the conditions set in this way, thereby generating crystal defects in the p-type implanted layer 23' and the layer located below the p-type implanted layer 23'. The order of execution of the first Mg injection process and the second Mg injection process is not limited to the above. The order of execution of the first Mg injection process and the second Mg injection process may be interchanged. The second Mg injection process may be executed first, and then the first Mg injection process.

[0041] The order of execution of the first N injection process and the second N injection process is not limited to the above. The order of execution of the first N injection process and the second N injection process may be interchanged. The second N injection process may be executed first, and then the first N injection process may be executed. The first N implantation step and the second N implantation step may be performed at any timing before the heat treatment of FIG. 6C described next. For example, the first N implantation step and the second N implantation step may be performed after the first Mg implantation step and the second Mg implantation step. Alternatively, the first Mg implantation step and the second Mg implantation step may be performed after the first N implantation step and the second N implantation step. At least one of the first N implantation step and the second N implantation step may be performed between the first Mg implantation step and the second Mg implantation step.

[0042] Next, the manufacturing equipment applies a heat treatment to the GaN substrate 10. This heat treatment causes the Mg implanted in the p+ type implantation layer 21' and the p type implantation layer 23' to diffuse around (for example, in the depth direction) and to be activated, forming the p+ type diffusion layer 21 and the p type diffusion layer 23 as shown in FIG. 6C. The surface portion of the p+ type diffusion layer 21 includes the p+ type implantation layer 21' after the Mg has diffused. The surface portion of the p type diffusion layer 23 includes the p type implantation layer 23' after the Mg has diffused. In addition, at least a part of the crystal defects generated in the p+ type implantation layer 21' and the p type implantation layer 23 by the ion implantation of Mg and N is restored by this heat treatment. The heat treatment conditions are, for example, a maximum temperature in a chamber in which the heat treatment is performed of 1300°C or higher and 1500°C or lower, a pressure in the chamber of 10 Torr or higher and 760 Torr or lower, an atmosphere in the chamber of an inert gas such as N2 or Ar, and a treatment time at the maximum temperature of 5 minutes or higher and 30 minutes or lower.

[0043] In the embodiment of the present invention, a protective film (not shown) may be formed on the surface 10a of the GaN substrate 10 before the heat treatment shown in FIG. 6C is performed. The protective film has a function of preventing nitrogen (N) atoms from being released from the GaN layer during the heat treatment. When nitrogen atoms are released from the GaN substrate, nitrogen vacancies are formed at the positions where the nitrogen atoms are released. Since the nitrogen vacancies can function as donor-type defects, there is a possibility that the development of p-type characteristics is inhibited. To prevent this, the manufacturing equipment may cover the surface 10a of the GaN substrate 10 with a protective film and perform the heat treatment in this state.

[0044] It is preferable that this protective film has high heat resistance, impurities do not diffuse from the protective film to the GaN substrate 10, and can be selectively removed from the GaN substrate 10. High heat resistance means that the protective film does not substantially decompose to such an extent that pits (through openings) are not formed in the protective film even when heat-treated at a temperature of 800°C or higher and 2000°C or lower. The protective film is, for example, an aluminum nitride (AlN) film, a SiO2 film, or a silicon nitride (SiN) film. The protective film may be a laminated film in which another film is laminated on an AlN film. The other film may be, for example, one or more of a SiO2 film, a SiN film, and a GaN film.

[0045] Next, as shown in FIG. 6D, the manufacturing equipment removes a part of p+ type diffusion layer 21 and a part of p-type diffusion layer 23 from the surface 10a side of GaN substrate 10 that has been subjected to heat treatment, so as to adjust the Mg concentration at the surface of p+ type diffusion layer 21 (i.e., the surface Mg concentration) and the surface Mg concentration of p-type diffusion layer 23 to predetermined values, respectively. For example, the manufacturing equipment performs CMP processing on the surface 10a side of the GaN substrate 10 to remove a predetermined thickness of each of the surface portions of the p+ type diffusion layer 21 and the p-type diffusion layer 23. The thickness to be removed is, for example, 150 nm or more and 300 nm or less. This increases the surface Mg concentration of the p+ type diffusion layer 21 to, for example, 6.0E+18 cm -3 The surface Mg concentration of the p-type diffusion layer 23 can be set to, for example, 1.0E+17 cm -3 It can be.

[0046] In this step, the area from surface 10a of GaN substrate 10 to the Mg implantation peak position may be removed. That is, the thickness of the surface layer portion removed from GaN substrate 10 may be equal to or greater than the Mg implantation peak depth. The distance from surface 10a of GaN substrate 10 to the Mg implantation peak position may be 150 nm or more and 300 nm or less.

[0047] Next, as shown in FIG. 6E, the manufacturing equipment forms an n+ type source layer 31 and an n-type JFET region 33 in the GaN substrate 10. The JFET region 33 is a part of the drift region. The drift region functions as a current path between the n+ type GaN substrate 11 and the p-type diffusion layer 23. The JFET region 33 has a higher concentration of n-type impurities and a lower electrical resistance than the other drift regions. By providing the JFET region, it is possible to reduce the on-resistance of the MOS transistor.

[0048] For example, the manufacturing equipment forms a third mask (not shown) on the surface 10a side of the GaN substrate 10 in order to form the source layer 31. The third mask has a shape that opens above the region where the source is to be formed and covers the other regions above. The manufacturing equipment ions-implants silicon (Si) as an n-type impurity onto the surface 10a side of the GaN substrate 10 on which the second mask has been formed. In this Si ion implantation step, the implantation concentration of Si is 4.0E+19 cm from the surface 10a (after CMP processing) of the GaN substrate 10 to a depth of 50 nm. -3 After the multi-stage Si ion implantation, the manufacturing equipment removes the third mask.

[0049] Also, before or after the above-mentioned Si ion implantation process, the manufacturing equipment forms a fourth mask (not shown) on the surface 10a side of the GaN substrate 10 in order to form an n-type JFET region 33. The fourth mask has a shape that opens above the region where the JFET is to be formed and covers the above of other regions. The manufacturing equipment ions implants oxygen (O) as an n-type impurity on the surface 10a side of the GaN substrate 10 on which the fourth mask has been formed. In this oxygen (O) ion implantation process, the implantation concentration of oxygen (O) is set to 1.0E+17 cm from the surface 10a (after CMP processing) of the GaN substrate 10 to a depth of 500 nm. -3 After the multi-stage ion implantation of oxygen (O) is performed, the manufacturing equipment removes the fourth mask.

[0050] After the above-mentioned Si ion implantation process and oxygen (O) ion implantation process are performed, the manufacturing equipment performs a heat treatment on the GaN substrate 10. This heat treatment causes the Si and oxygen (O) ion implanted in the GaN substrate 10 to diffuse and be activated. As a result, an n+ type source layer 31 and an n-type JFET region 33 are formed in the GaN substrate 10. Furthermore, at least a part of the crystal defects caused by the ion implantation of Si and oxygen (O) are repaired by this heat treatment. The conditions of the heat treatment are, for example, a maximum temperature of 1100°C in a chamber in which the heat treatment is performed, an atmosphere in the chamber of N2, and a treatment time at the maximum temperature of 10 minutes.

[0051] Next, as shown in FIG. 6F, the manufacturing equipment forms a gate insulating film 35 on the surface 10a of the GaN substrate 10. The gate insulating film 35 is, for example, silicon oxide (SiO2) or Al2O3. Next, the manufacturing equipment forms a gate electrode 37 on the gate insulating film 35. The gate electrode 37 is made of, for example, aluminum (Al), nickel (Ni), titanium nitride (TiN), tungsten (W), polysilicon (poly-Si), or the like.

[0052] Next, the manufacturing equipment forms a source electrode 41 on the n+ source layer 31 and the p+ diffusion layer 21. Also, before or after the process of forming the source electrode 41, the manufacturing equipment forms a drain electrode 43 on the back surface 10b side of the GaN substrate 10. The source electrode 41 and the drain electrode 43 are made of, for example, a laminated film in which Al is laminated on titanium (Ti). Ti is the lower layer and Al is the upper layer. Through the above processes, a GaN semiconductor device 1A having a MOS transistor with a vertical planar structure is completed as shown in FIG. 6F.

[0053] According to the second embodiment of the present invention, after Mg is diffused from the p-type implantation layer 23' to form the p-type diffusion layer 23, the surface portion of the p-type diffusion layer 23 is removed. The surface portion of the p-type diffusion layer 23 is a portion that includes the p-type implantation layer 23' and contains many crystal defects due to ion implantation. By removing this surface portion, it is possible to reduce the crystal defects on the surface of the p-type diffusion layer 23. In addition, by removing the surface portion in which the activation rate of Mg is low and the variation in Mg concentration is large due to the influence of crystal defects, it is possible to control the acceptor concentration on the surface of the p-type diffusion layer 23 with high precision.

[0054] In the GaN semiconductor device 1A, a channel of a MOS transistor with a vertical planar structure can be formed on or near the surface of the p-type diffusion layer 23, which has few crystal defects and has a highly precisely controlled acceptor concentration. This makes it possible to improve the characteristics of the MOS transistor with a vertical planar structure (for example, reducing leakage current caused by crystal defects and reducing variations in threshold voltage caused by acceptor concentration).

[0055] Moreover, according to the second embodiment of the present invention, after Mg is diffused from p+ type injection layer 21' to form p+ type diffusion layer 21, the surface portion of p+ type diffusion layer 21 is removed. The surface portion of p+ type diffusion layer 21 is a portion that includes p+ type injection layer 21' and contains many crystal defects due to ion injection. By removing this surface portion, it is possible to reduce the crystal defects on the surface of p+ type diffusion layer 21. Furthermore, by removing the surface portion in which the activation rate of Mg is low and the variation in Mg concentration is large due to the influence of crystal defects, it is possible to control the acceptor concentration on the surface of p+ type diffusion layer 21 with high precision.

[0056] In the GaN semiconductor device 1A, a source electrode 41 is formed on the surface of the p+ type diffusion layer 21, which has few crystal defects and whose acceptor concentration is controlled with high precision, and serves also as a p+ contact electrode. The surface of the p+ type diffusion layer 21, which is joined to the source electrode 41, has few crystal defects and whose acceptor concentration is controlled with high precision. This makes it possible to reduce the contact resistance between the p+ type diffusion layer 21 and the source electrode 41.

[0057] <Embodiment 3> In the above embodiment 2, the semiconductor device 1A having a MOS transistor with a planar structure has been described. However, in the embodiments of the present invention, the MOS transistor of the GaN semiconductor device is not limited to a planar structure and may have, for example, a trench structure.

[0058] 7A to 7F are cross-sectional views showing a manufacturing method of a GaN semiconductor device 1B according to embodiment 3 of the present invention. In FIG. 7A, the manufacturing apparatus forms a p+ type implantation layer 21' and a p-type implantation layer 23' on the surface 10a side of the GaN substrate 10 under ion implantation conditions similar to those in embodiment 2. In the step of forming the p-type implantation layer 23', unlike FIG. 6B described in embodiment 2, the p-type implantation layer 23' may be formed continuously between one p+ type implantation layer 21' and the other p+ type implantation layer 21' adjacent to each other in the horizontal direction (direction parallel to the surface 10a). In addition, before or after the step of forming the p+ type implantation layer 21' (first Mg implantation step) and the step of forming the p type implantation layer 23' (second Mg implantation step), the manufacturing equipment may perform the first N implantation step and the second N implantation step described in the embodiment 2. The ion implantation conditions of the first N implantation step and the second N implantation step are the same as those of the embodiment 2, for example.

[0059] Next, the manufacturing equipment applies a heat treatment to the GaN substrate 10. This heat treatment causes the Mg implanted in the p+ type injection layer 21' and the p type injection layer 23' to diffuse around (for example, in the depth direction) and to be activated, forming the p+ type diffusion layer 21 and the p type diffusion layer 23 as shown in FIG. 7B. Also, at least a part of the crystal defects generated in the p+ type injection layer 21' and the p type injection layer 23 by the ion implantation of Mg and N is restored by this heat treatment. The conditions of this heat treatment are the same as those of the heat treatment for diffusing and activating the Mg implanted in the p+ type injection layer 21' and the p type injection layer 23' in the second embodiment, for example. Note that in the third embodiment, as in the second embodiment, a protective film (not shown) may be formed on the surface 10a of the GaN substrate 10 before this heat treatment.

[0060] Next, as shown in FIG. 7C, the manufacturing equipment removes a part of p+ type diffusion layer 21 and a part of p type diffusion layer 23 from the surface 10a side of GaN substrate 10 that has been subjected to heat treatment, thereby adjusting the surface Mg concentration of p+ type diffusion layer 21 and the surface Mg concentration of p type diffusion layer 23 to preset values, respectively. For example, the manufacturing equipment performs CMP processing on the surface 10a side of GaN substrate 10 to remove the surface layer portion of GaN substrate 10. In the third embodiment, as in the second embodiment, the thickness to be removed is, for example, 150 nm or more and 300 nm or less. Thereby, the surface Mg concentration of p+ type diffusion layer 21 is adjusted to, for example, 6.0E+18 cm -3 The surface Mg concentration of the p-type diffusion layer 23 can be set to, for example, 1.0E+17 cm -3 It can be.

[0061] Next, as shown in Fig. 7D, the manufacturing equipment forms an n+ type source layer 31 in the GaN substrate 10. The method of forming the source layer 31 is, for example, the same as that of embodiment 2. Note that the step of forming the source layer 31 shown in Fig. 7D may be performed after the step of forming the trench H1 (see Fig. 7E) described next. Next, the manufacturing equipment performs dry etching in the depth direction on a region between one p+ type diffusion layer 21 and the other p+ type diffusion layer 21 adjacent in the horizontal direction on the surface 10a side of the GaN substrate 10. As a result, as shown in FIG. 7E, the manufacturing equipment forms a trench H1 on the surface 10a side of the GaN substrate 10. The depth of the trench H1 from the surface 10a is, for example, 500 nm or more and 1 μm or less. The trench H1 is formed with a dimension such that it penetrates the p type diffusion layer 23 and the n- type GaN layer 12 becomes the bottom.

[0062] 7F, the manufacturing equipment forms a gate insulating film 35 on the inner side and bottom surface of the trench H1. Next, the manufacturing equipment forms a gate electrode 37. The gate electrode 37 is formed so as to fill the trench H1 with the gate insulating film 35 interposed therebetween. The subsequent steps are the same as, for example, those of embodiment 2. The manufacturing equipment forms a source electrode 41 on the n+ source layer 31 and the p+ diffusion layer 21. Also, before or after the step of forming the source electrode 41, the manufacturing equipment forms a drain electrode 43 on the back surface 10b side of the GaN substrate 10. Through the above steps, a GaN semiconductor device 1B having a MOS transistor with a vertical trench structure is completed.

[0063] According to the third embodiment of the present invention, as in the second embodiment, the acceptor concentration in the surface of the p-type diffusion layer 23 can be controlled to a high concentration. As a result, in the GaN semiconductor device 1B, a channel of a MOS transistor with a vertical trench structure can be formed in the surface of the p-type diffusion layer 23, which has few crystal defects and has a highly precisely controlled acceptor concentration, and in its vicinity. This makes it possible to improve the characteristics of the MOS transistor with a vertical trench structure (for example, reducing leakage current caused by crystal defects and reducing variations in threshold voltage caused by acceptor concentration). Moreover, according to the third embodiment of the present invention, the acceptor concentration in the surface of the p-type diffusion layer 23 can be controlled to a high concentration, as in the second embodiment. This makes it possible to reduce the contact resistance between the p+ type diffusion layer 21 and the source electrode 41 in the GaN semiconductor device 1B as well.

[0064] <Embodiment 4> In an embodiment of the present invention, Mg implanted into a p-type injection layer (or a P+ injection layer) may be diffused in a direction intersecting the thickness direction of the substrate rather than in the thickness direction of the substrate to form a p-type diffusion layer (or a P+ type diffusion layer). 8A to 8H are cross-sectional views showing a method for manufacturing a GaN semiconductor device 1C according to embodiment 4 of the present invention. In FIG. 8A, the manufacturing equipment ion-implants Mg into the front surface 10a side of the GaN substrate 10 under ion implantation conditions similar to those in embodiment 2, for example, to form a p+ type implantation layer 21' (first Mg implantation step). Before and after the first Mg implantation step, the manufacturing equipment also performs the first N implantation step described in embodiment 2. The ion implantation conditions in the first N implantation step are the same as those in embodiment 2, for example. This allows crystal defects to be generated in the p+ type implantation layer 21' and the layer located below the p+ type implantation layer 21'.

[0065] Next, the manufacturing equipment applies a heat treatment to the GaN substrate 10. This heat treatment causes the Mg implanted in the p+ type implantation layer 21' to diffuse to the periphery (for example, in the depth direction) and is activated, forming the p+ type diffusion layer 21 as shown in FIG. 8B. This heat treatment also repairs at least a part of the crystal defects caused in the p+ type implantation layer 21' by the ion implantation of Mg and N. The conditions of this heat treatment are the same as those of the heat treatment in the second embodiment, for example, when diffusing and activating the Mg implanted in the p+ type implantation layer 21' and the p type implantation layer 23'. In the fourth embodiment, as in the second embodiment, a protective film (not shown) may be formed on the surface 10a of the GaN substrate 10 before this heat treatment.

[0066] Next, as shown in FIG. 8C, the manufacturing equipment performs CMP processing on the surface 10a side of the GaN substrate 10 to remove the surface layer of the p+ type diffusion 21. As a result, the manufacturing equipment adjusts the surface concentration of the p+ type diffusion 21 to a preset value. In the fourth embodiment, as in the third embodiment, the thickness to be removed is, for example, 150 nm or more and 300 nm or less. As a result, the surface Mg concentration of the p+ type diffusion layer 21 is adjusted to, for example, 6.0E+18 cm -3 It can be. Next, as shown in Fig. 8D, the manufacturing equipment forms an n+ type source layer 31 in the GaN substrate 10. The method of forming the source layer 31 is, for example, the same as that of embodiment 2. Note that the step of forming the source layer 31 shown in Fig. 7D may be performed after the step of forming the trench H1 (see Fig. 8E) described next.

[0067] Next, the manufacturing equipment performs dry etching in the depth direction on a region between one p+ type diffusion layer 21 and the other p+ type diffusion layer 21 adjacent in the horizontal direction on the surface 10a side of the GaN substrate 10. As a result, as shown in FIG. 8E, the manufacturing equipment forms a trench H1 on the surface 10a side of the GaN substrate 10. The depth of the trench H1 from the surface 10a is, for example, 500 nm or more and 1 μm or less. The trench H1 is formed with a dimension such that it penetrates the source layer 31 and the n- type GaN layer 12 becomes the bottom.

[0068] Next, as shown in FIG. 8F, the manufacturing equipment ion-implants Mg into the inner surface of the trench H1 to form a p-type implantation layer 23' (second Mg implantation step). For example, the manufacturing equipment forms a fifth mask (not shown) on the surface 10a of the GaN substrate 10. The fifth mask is made of a SiO2 film, an Al2O3 film, or a photoresist. The fifth mask has an opening above the trench H1 and has a shape that covers the upper parts of other regions. The manufacturing equipment obliquely ions-implants Mg as a p-type impurity into the surface 10a side of the GaN substrate 10 on which the fifth mask is formed.

[0069] In the Mg oblique ion implantation process, the Mg implantation peak depth is 20 nm and the Mg implantation peak concentration is 1.0E+19 cm -3 The Mg implantation conditions are set so that: In the oblique ion implantation process, the implantation depth is indicated not by the distance in the thickness direction of the GaN substrate 10 (the vertical direction in FIG. 8E) but by the distance in the horizontal direction (the horizontal direction in FIG. 8E) perpendicular to the thickness direction. In the oblique Mg ion implantation process, the Mg peak depth means the horizontal distance from the inner side surface of the trench H1 to the Mg implantation peak position. In the oblique ion implantation process of Mg, it is preferable to adjust the tilt angle so that Mg is implanted into the inner side surface of trench H1 and the amount of Mg implanted into the bottom surface of trench H1 is less than that into the inner side surface of trench H1 (ideally, the amount of Mg implanted into the bottom surface of trench H1 is zero). The tilt angle is the inclination angle with respect to the normal direction of surface 10a of GaN substrate 10.

[0070] Also, before or after the step of forming the p-type implantation layer 23' (second Mg implantation step), the manufacturing equipment ion-implants N into the inner surface of the trench H1. For example, the manufacturing equipment obliquely implants N into the front surface 10a side of the GaN substrate 10 on which the fifth mask is formed. In the oblique N ion implantation step, the N peak depth is 20 nm, and the N peak concentration is 1.0E+19 cm -3 The N implantation conditions are set so that: In the oblique ion implantation process of N, the N peak depth means the horizontal distance from the inner side surface of the trench H1 to the implantation peak position of N. This makes it possible to generate crystal defects in the p-type implanted layer 23' and in a layer horizontally adjacent to the p-type implanted layer 23'.

[0071] Next, the manufacturing equipment applies a heat treatment to the GaN substrate 10. This heat treatment causes the Mg implanted in the p-type implantation layer 23' to diffuse around (for example, horizontally) and is activated, forming the p-type diffusion layer 23 as shown in FIG. 8G. The surface portion of the p-type diffusion layer 23 faces the inner side surface of the trench H1 and includes the p-type implantation layer 23' after Mg diffusion. Furthermore, at least a part of the crystal defects generated in the p-type implantation layer 23' by the oblique ion implantation of Mg and N is restored by this heat treatment. The conditions of this heat treatment are the same as those of the heat treatment when diffusing and activating the Mg implanted in the p+ type implantation layer 21'. Furthermore, a protective film (not shown) may be formed on the surface 10a of the GaN substrate 10 before this heat treatment.

[0072] Next, the manufacturing equipment removes the surface layer of the inner surface of trench H1 to adjust the surface Mg concentration of p-type diffusion layer 23 to a preset value. For example, the manufacturing equipment performs a wet process using TMAH on GaN substrate 10 to remove the surface layer of the inner surface of trench H1. This adjusts the surface Mg concentration of p-type diffusion layer 23 to, for example, 6.0E+18 cm -3 It can be. The subsequent steps are the same as those of, for example, embodiment 3. As shown in Fig. 8H, the manufacturing equipment forms a gate insulating film 35 on the inner side and bottom surface of the trench H1. Next, the manufacturing equipment forms a gate electrode 37. The gate electrode 37 is formed so as to fill the trench H1 with the gate insulating film 35 interposed therebetween.

[0073] Next, the manufacturing equipment forms a source electrode 41 on the n+ source layer 31 and the p+ diffusion layer 21. Also, before or after the process of forming the source electrode 41, the manufacturing equipment forms a drain electrode 43 on the back surface 10b side of the GaN substrate 10. Through the above processes, a GaN semiconductor device 1C having a MOS transistor with a vertical trench structure is completed.

[0074] According to the fourth embodiment of the present invention, as in the third embodiment, the acceptor concentration in the surface of the p-type diffusion layer 23 can be controlled to a high concentration. As a result, in the GaN semiconductor device 1C, a channel of a MOS transistor with a vertical trench structure can be formed in and near the surface of the p-type diffusion layer 23, which has few crystal defects and has a highly precisely controlled acceptor concentration. This makes it possible to improve the characteristics of the MOS transistor with a vertical trench structure (for example, reducing leakage current caused by crystal defects and reducing variations in threshold voltage caused by acceptor concentration). Moreover, according to the fourth embodiment of the present invention, the acceptor concentration in the surface of the p-type diffusion layer 23 can be controlled to a high concentration, as in the third embodiment. This makes it possible to reduce the contact resistance between the p+ type diffusion layer 21 and the source electrode 41 in the GaN semiconductor device 1C as well.

[0075] <Other embodiments> As described above, the present invention has been described by the first to fourth embodiments and the modified examples, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modified examples will become apparent to those skilled in the art from this disclosure. For example, in the above-described embodiments 2 to 4, n+ source layer 31 is formed after p-type diffusion layer 23 is formed. However, in the embodiments of the present invention, p-type diffusion layer 23 may be formed after n+ source layer 31 is formed. In this case, at least a part of the surface layer of n+ source layer 31 may be removed in the surface concentration adjustment step of p-type diffusion layer 23. For this reason, in the ion implantation step for forming n+ source layer 31, it is preferable to set the implantation conditions of n-type impurities so that the implantation peak depth of the n-type impurities is deeper by the thickness of the surface layer to be removed.

[0076] In the embodiment of the present invention, the gate insulating film 35 may be a silicon oxynitride (SiON) film, a hafnium silicon oxide (HfSiO) film, or a silicon nitride (Si3N4) film in addition to the SiO2 film or Al2O3 film. The gate insulating film 35 may also be a composite film formed by stacking several single-layer insulating films. A vertical MOS transistor using an insulating film other than a SiO2 film as the gate insulating film 35 may be called a vertical MIS transistor. The MIS transistor refers to a more comprehensive insulated gate transistor including a MOS transistor.

[0077] Thus, the present invention naturally includes various embodiments not described here. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiments 1 to 4 and modified examples. Furthermore, the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present. The technical scope of the present invention is defined only by the invention-specifying matters related to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0078] 1, 1A, 1B, 1C GaN semiconductor device 10 GaN substrate 10a surface 10b back side 11 GaN substrate 12 GaN layers 21 Diffusion Layer 21 p+ type diffusion layer 21´ p+ type injection layer 23 p-type diffusion layer 23´ p-type injection layer 31 Source Layer 33 JFET area 35 Gate insulating film 37 Gate electrode 41 Source electrode 43 Drain electrode H1 Trench

Claims

1. a first implantation step of ion-implanting a p-type impurity into one surface side of a gallium nitride layer to form a p-type implanted layer in the gallium nitride layer; a diffusion step of forming a p-type diffusion layer in the gallium nitride layer by diffusing the p-type impurity contained in the p-type injection layer by subjecting the gallium nitride layer to a heat treatment; a surface concentration adjustment step of removing a part of the p-type diffusion layer from the one surface side to adjust the surface concentration of the p-type diffusion layer to a preset value; In the surface concentration adjusting step, removing the p-type diffusion layer from the one surface to an area beyond a peak position of implantation of the p-type impurity.

2. In the first implantation step, the concentration of the p-type impurity at the implantation peak position is 1.0E+19 cm －３ 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the conditions for injecting said p-type impurity are set so that the value of n-type impurity is higher than

3. In the diffusion step, 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein a maximum temperature of the heat treatment is set to 1300° C. or more and 1500° C. or less, and a treatment time at the maximum temperature is set to 5 minutes or more and 30 minutes or less.

4. 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein a distance from said one surface to a peak position of implantation of said p-type impurity is not less than 150 nm and not more than 300 nm.

5. The preset value is 1.0E+17 cm －３ Above 1.0E+19cm －３ The method for manufacturing a nitride semiconductor device according to claim 1 , wherein:

6. In the surface concentration adjusting step, The method for manufacturing a nitride semiconductor device according to claim 1 , further comprising the step of: grinding a portion of said p-type diffusion layer by subjecting said one surface side of said gallium nitride layer to a CMP process.

7. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the p-type impurity is magnesium (Mg).

8. 8. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising, before the diffusion step, a second implantation step of ion-implanting an element different from the p-type impurity into the one surface side of the gallium nitride layer.

9. 9. The method for manufacturing a nitride semiconductor device according to claim 8, wherein in the second implantation step, implantation conditions for the element are set such that a depth from the one surface to an implantation peak position of the element is deeper than a depth from the one surface to an implantation peak position of the p-type impurity.

10. 10. The method for manufacturing a nitride semiconductor device according to claim 8, wherein in the second implantation step, implantation conditions of the element are set so that a concentration of the element at an implantation peak position is equal to or less than 1 time a concentration of the p-type impurity at an implantation peak position.

11. The method for manufacturing a nitride semiconductor device as described in claim 9, wherein in the surface concentration adjustment step, the p-type diffusion layer is ground from the one surface to a position deeper than the injection peak position of the element.

12. The method for manufacturing a nitride semiconductor device according to claim 8 , wherein the element is nitrogen.

13. a gallium nitride layer; a p-type diffusion layer provided on one surface side of the gallium nitride layer, the p-type diffusion layer has a first concentration peak position where the concentration of the p-type impurity is maximum; the first concentration peak position is present at the outermost surface of the p-type diffusion layer, a concentration of the p-type impurity in the p-type diffusion layer continuously decreases from the outermost surface in a depth direction of the p-type diffusion layer.

14. The p-type diffusion layer further comprises an element different from the p-type impurity, The nitride semiconductor device according to claim 13 , wherein in said p-type diffusion layer, a second concentration peak position where the concentration of said element is maximum is present on said outermost surface.

15. The surface concentration of the p-type impurity is 1.0E+17 cm －３ Above 1.0E+19cm －３ 15. The nitride semiconductor device according to claim 13, wherein:

16. 16. The nitride semiconductor device according to claim 13, wherein the p-type impurity is magnesium (Mg).

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