Semiconductor device manufacturing method

Abstract

To provide a method for manufacturing a semiconductor device capable of improving productivity.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: sticking a first tape (rear surface tape) to a rear surface of a semiconductor wafer to cover a rear surface electrode of the semiconductor wafer (step S1); sticking a second tape (outer peripheral tape) to an outer peripheral part of the semiconductor wafer to cover an end part of the semiconductor wafer (step S2); increasing adhesion power between the semiconductor wafer and the first and second tapes by heating the semiconductor wafer stuck with the first and second tapes at a temperature of 40°C or higher (step S3); forming a plating layer on a front surface electrode of the semiconductor wafer by subjecting the semiconductor wafer to plating treatment with the first and second tapes stuck to the semiconductor wafer (step S4); and peeling the second tape and the first tape in this order (steps S5 and S6). The first and second tapes are a UV tape. An adhesive layer does not remain on a surface of the semiconductor wafer because the first and second tapes are peeled after the adhesive layer is cured by UV irradiation.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventionally, in a vertical semiconductor device having surface electrodes (electrode pads) on both main surfaces, a wiring structure is known in which different external connection terminals (e.g., terminal pins or copper foil plates) are soldered to the front and back electrodes, respectively. By soldering the front electrode and the external connection terminal, it is possible to realize higher density mounting of the module package, improved current density, reduced wiring capacitance for faster switching speeds, and improved cooling efficiency of the semiconductor element, compared to when the front electrode and the external connection terminal are connected by wire bonding.

[0003] The front electrode is usually formed using a metal containing aluminum (Al) that has high electrical conductivity. Since aluminum has poor solder wettability, a metal layer with good solder wettability (e.g., a nickel (Ni) layer) is formed on the surface of the front electrode to improve the solder wettability of the surface of the front electrode, thereby improving the bonding reliability at the interface between the front electrode and the solder layer. As a method for forming a metal layer with good solder wettability on the surface of the front electrode, plating treatments using electrolytic plating and electroless plating are known.

[0004] As a method for plating predetermined locations on a semiconductor wafer, a method has been proposed in which a plating process is performed with tape affixed to locations on the semiconductor wafer where no plating layer is to be formed (see, for example, Patent Documents 1 to 4 below). In Patent Documents 1 to 4 below, the locations on the semiconductor wafer where no plating layer is to be formed (backside electrode and wafer periphery) are covered and protected with tape to prevent deposition of a plating layer on locations where no plating layer is to be formed (hereinafter, referred to as abnormal deposition), contamination of the plating bath due to abnormally deposited and peeled-off plating layer, and changes in bath composition over time.

[0005] In addition, the following Patent Documents 1 and 2 disclose that, when using a rib-shaped semiconductor wafer in which the thickness is thin at the center and the outer periphery is left thick by a certain width, a first tape is attached to the entire back surface of the semiconductor wafer so as to be in close contact with the inclined surface of the step generated on the back surface of the semiconductor wafer due to the thickness difference between the center and outer periphery of the semiconductor wafer and with the flat portion of the back surface of the semiconductor wafer that is outside the step, and a second tape is attached to the outer periphery of the semiconductor wafer so as to overlap the first tape on the flat portion on the back surface side of the outer periphery of the semiconductor wafer.

[0006] In addition, the following Patent Documents 1, 2, and 4 disclose the use of a UV tape having an adhesive layer that hardens and reduces adhesive strength when irradiated with ultraviolet (UV) light as a tape to be attached to a semiconductor wafer. In addition, the following Patent Document 4 discloses that when attaching tape to the back surface of a semiconductor wafer, the semiconductor wafer that has been subjected to a thinning process is heated to 40°C to 60°C to maintain a convex warped state on the front surface side, and a plating process is performed on the semiconductor wafer in this convex warped state on the front surface side, thereby reducing warping of the semiconductor wafer after the tape is peeled off. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2014-086667 A [Patent Document 2] JP 2016-152317 A [Patent Document 3] JP 2016-058677 A [Patent Document 4] JP 2011-222898 A Summary of the Invention [Problem to be solved by the invention]

[0008] However, the inventors' intensive research has revealed that in the above-mentioned conventional plating method, even if plating is performed while the portions of the semiconductor wafer where no plating layer is to be formed (the back surface and outer periphery of the semiconductor wafer) are covered with tape, the following three problems occur. The first problem is that plating solution seeps into the gap between the back surface of the semiconductor wafer and the tape, causing a "stain" of the plating solution on the back surface electrode at the outer periphery of the semiconductor wafer, resulting in a defective appearance. The inventors verified the cause of this first problem by using a semiconductor wafer with a rib shape.

[0009] 16 and 17 are plan views showing a schematic view of a semiconductor wafer after a conventional plating process, as viewed from the backside. FIG. 16(a) shows the state of the backside of a semiconductor wafer 110 after the second tape attached to the outer periphery of the semiconductor wafer is peeled off and before the first tape 101 is peeled off. FIG. 17(a) shows the state of the backside electrode 114 of the semiconductor wafer 110 after the first tape attached to the entire backside of the semiconductor wafer is peeled off. FIG. 16(b) and 17(b) show enlarged views of the areas surrounded by frames A1 and A2 in FIG. 16(a) and 17(a), respectively. FIG. 18 and FIG. 19 are cross-sectional views showing the cross-sectional structures of the areas surrounded by frames A1 and A2 in FIG. 16 and FIG. 17, respectively.

[0010] The rib-shaped semiconductor wafer 110 is a semiconductor wafer in which the thickness of the central portion 111 is reduced from the back surface 110b side, and the outer periphery 112 is left thicker than the central portion 111 at a predetermined width along the periphery. According to the plating method described in the above Patent Documents 1 and 2, the first tape 101 is attached to the entire back surface 110b of the semiconductor wafer 110 so as to be in close contact with the inclined surface 113b of the step 113 generated on the back surface 110b due to the thickness difference between the central portion 111 and the outer periphery 112 of the semiconductor wafer 110, and with the flat portion 112b of the back surface 110b of the semiconductor wafer 110 that is outside the step 113 (hereinafter referred to as the back surface flat portion of the outer periphery 112 of the semiconductor wafer 110).

[0011] After first tape 101 was attached, a second tape (not shown) was attached to outer periphery 112 of semiconductor wafer 110 so as to overlap first tape 101 at back surface flat portion 112b of outer periphery 112 of semiconductor wafer 110. Then, after plating of the front surface electrodes of semiconductor wafer 110, the second tape was peeled off and then first tape 101 was peeled off. First tape 101 was a UV tape, and UV irradiation was applied to first tape 101 to harden the adhesive layer of first tape 101 and reduce the adhesive force of the adhesive layer, and then first tape 101 was peeled off from back surface 110b of semiconductor wafer 110.

[0012] As a result, it was confirmed that after the first tape 101 was peeled off, the rear surface electrode 114 of the semiconductor wafer 110 had a wide area around the entire circumference along the edge of the semiconductor wafer 110, resulting in a defective appearance 122 (hatched area) caused by a "stain" of the plating solution (FIG. 17(a)). In this semiconductor wafer 110, it was confirmed that after the second tape was peeled off, the plating solution 121 (hatched area) had partially penetrated and accumulated between the rear surface of the semiconductor wafer 110 and the first tape 101 at the outer periphery 112 of the semiconductor wafer 110 (FIG. 16(b)). The defective appearance caused by the plating solution 121 also occurred in the area (hatched area) 121' where the plating solution 121 had accumulated (FIG. 17(b)).

[0013] If plating solution 121 (hatched portion) accumulates between back surface 110b of semiconductor wafer 110 and first tape 101 (Figure 18), when first tape 101 is lifted off semiconductor wafer 110 due to gas generated from the adhesive layer of first tape 101 during UV irradiation, this plating solution 121 will move between back surface 110b of semiconductor wafer 110 and first tape 101, from back surface flat portion 112b of outer periphery 112 of semiconductor wafer 110, along inclined surface (mesa edge) 113b of step 113 toward central portion 111, and then permeate (be absorbed) over a wide area into the back surface electrode (Figure 19), presumably resulting in appearance defect 122.

[0014] The second problem is that plating solution gets in between the outer periphery of the semiconductor wafer and the second tape, seeping into the outer periphery of the semiconductor wafer, making it impossible to automatically read the wafer ID (Identification: a mark used to identify the semiconductor wafer) formed on the outer periphery of the semiconductor wafer in the process after plating.The third problem is that plating solution gets in between the outer periphery of the semiconductor wafer and the second tape, causing an unnecessary plating layer to deposit (abnormal deposition) on the outer periphery of the semiconductor wafer.

[0015] The plating layer that is abnormally deposited on the outer periphery of the semiconductor wafer peels off from the semiconductor wafer and floats in the plating bath, causing contamination of the plating bath and changes in the bath composition over time, or reattaching to the semiconductor wafer and causing defects in the appearance of the front electrode. Defective appearance caused by "stains" of the plating solution on the front electrode or back electrode may cause fatal defects in the semiconductor device, such as defective solder joints, and reduce the yield (production number). Errors in automatic reading of the wafer ID reduce the throughput of the manufacturing process. Contamination of the plating bath and changes in the bath composition over time require more frequent cleaning of the plating tank and shorten the life of the plating solution.

[0016] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve productivity. [Means for solving the problem]

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a plating layer is formed on a first main surface side of a semiconductor wafer by plating, and has the following features: A first step is performed to form a first electrode on the first main surface of the semiconductor wafer. A second step is performed to attach a first tape to the second main surface of the semiconductor wafer and cover the second main surface of the semiconductor wafer with the first tape. A third step is performed to attach a second tape to the outer periphery of the semiconductor wafer and cover an edge of the semiconductor wafer with the second tape. The semiconductor wafer with the first tape and the second tape attached is heated to a temperature of 40° C. or higher. Below 80℃for more than 20 minutes in an atmosphere of 40 minutes or less A fourth step is performed in which the first tape and the second tape are heated by a heat treatment to increase adhesive strength between the semiconductor wafer and the first tape and the second tape. After the fourth step, a fifth step is performed in which the plating layer is formed on the surface of the first electrode by the plating treatment.

[0020] Furthermore, the manufacturing method of a semiconductor device according to the present invention further includes a sixth step of peeling the second tape from the semiconductor wafer after the fifth step. The second tape has an adhesive layer that is hardened by ultraviolet light irradiation to reduce adhesive strength. In the third step, the second tape is attached by adhering the adhesive layer to the surface of the semiconductor wafer across the first and second main surfaces of the semiconductor wafer, and the edge of the semiconductor wafer is covered with the second tape. In the sixth step, the adhesive layer of the second tape is hardened by ultraviolet light irradiation, and then the second tape is peeled off.

[0021] In the method for manufacturing a semiconductor device according to the present invention, in the third step, the second tape is attached across from the first main surface to the second main surface of the semiconductor wafer so as to overlap the first tape at the outer periphery of the semiconductor wafer on the second main surface of the semiconductor wafer, and the sixth step includes curing the adhesive layer of the second tape attached to the first main surface of the semiconductor wafer by irradiating the ultraviolet light from the first main surface of the semiconductor wafer, and then peeling off the second tape.

[0022] In addition, in the method for manufacturing a semiconductor device according to the present invention, in the third step, the second tape is attached so as to go around an outer periphery of the semiconductor wafer at least once.

[0023] In addition, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, in the fourth step, the semiconductor wafer is placed in a heating furnace and the first tape and the second tape are directly heated.

[0024] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that, in the fourth step, the semiconductor wafer is placed on a stage heated by a heating means and the first tape and the second tape are heated.

[0025] In addition, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, in the fourth step, the atmosphere in which the semiconductor wafer is heated is a nitrogen atmosphere.

[0026] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that in the first step, the first electrode is formed on a first main surface of the semiconductor wafer and a second electrode is formed on a second main surface of the semiconductor wafer, and in the second step, the first tape is attached to the second main surface of the semiconductor wafer to cover the second electrode with the first tape.

[0027] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a rib-shaped semiconductor wafer is used as the semiconductor wafer, which is thin in thickness at the center and leaves a predetermined width thick at the outer periphery. In the fifth step, the semiconductor wafer with the first and second tapes attached thereto is immersed in a plating solution to form the plating layer on the surface of the first electrode. In the fifth step, the semiconductor wafer with the first and second tapes attached thereto is exposed at a periphery of the semiconductor wafer, and in the third step, the second tape is directly attached to the first main surface of the semiconductor wafer at the periphery of the semiconductor wafer.

[0028] According to the above-mentioned invention, the adhesive strength between the semiconductor wafer and the first and second tapes can be increased, thereby preventing the plating solution from the plating process from seeping into the gap between the back surface of the semiconductor wafer and the first tape, which would cause poor appearance of the back surface electrode of the semiconductor wafer due to the plating solution. Effect of the Invention

[0029] The method for manufacturing a semiconductor device according to the present invention has the effect of improving productivity. [Brief description of the drawings]

[0030] [Figure 1] 1 is a flowchart showing an outline of a manufacturing method of a semiconductor device according to an embodiment; [Diagram 2] 1 is a cross-sectional view showing a state during the manufacturing process of a semiconductor device according to an embodiment; [Diagram 3] 1 is a cross-sectional view showing a state during the manufacturing process of a semiconductor device according to an embodiment; [Figure 4] 1 is a perspective view showing a state during the manufacture of a semiconductor device according to an embodiment; [Diagram 5] 1 is a plan view showing a state during the manufacture of a semiconductor device according to an embodiment; [Figure 6] 1 is a cross-sectional view showing a state during the manufacturing process of a semiconductor device according to an embodiment; [Figure 7] 1 is a cross-sectional view showing an example of a front surface element structure of a semiconductor wafer to which a manufacturing method for a semiconductor device according to an embodiment is applied; [Figure 8] 1 is a cross-sectional view showing an example of a front surface element structure of a semiconductor wafer to which a manufacturing method for a semiconductor device according to an embodiment is applied; [Figure 9] 10 is a characteristic diagram showing the relationship between the heating temperature and the peel strength of the second tape (outer peripheral tape) in Experimental Example 1. FIG. [Figure 10] 10 is a characteristic diagram showing the relationship between the heating temperature and the peel strength of the second tape (outer peripheral tape) in Experimental Example 1. FIG. [Figure 11] 13 is a characteristic diagram showing the relationship between the heating time and the peel strength of the second tape (outer peripheral tape) in Experimental Example 2. FIG. [Figure 12] 13 is a characteristic diagram showing the relationship between the heating time and the peel strength of the second tape (outer peripheral tape) in Experimental Example 2. FIG. [Figure 13] 13 is a graph showing the composition analysis results of the rear electrode of Experimental Example 3. [Figure 14] 13 is a graph showing the composition analysis results of the rear electrode of Experimental Example 3. [Figure 15] FIG. 10 is an explanatory diagram showing a schematic diagram of a method for measuring the peel strength of a second tape in Experimental Example 4. [Figure 16] FIG. 1 is a plan view showing a schematic view of a semiconductor wafer after a conventional plating process, as observed from the back surface side. [Figure 17] FIG. 1 is a plan view showing a schematic view of a semiconductor wafer after a conventional plating process, as observed from the back surface side. [Figure 18] 17 is a cross-sectional view showing the cross-sectional structure of a portion surrounded by a frame A1 in FIG. 16. [Figure 19] 18 is a cross-sectional view showing the cross-sectional structure of a portion surrounded by a frame A2 in FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, preferred embodiments of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the embodiments and the accompanying drawings, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0032] (Embodiment) A method for manufacturing a semiconductor device according to an embodiment will be described by taking as an example a case where plating is performed on a rib-shaped semiconductor wafer. Fig. 1 is a flowchart showing an outline of the method for manufacturing a semiconductor device according to an embodiment. Figs. 2, 3 and 6 are cross-sectional views showing a state during the manufacturing of a semiconductor device according to an embodiment. Fig. 4 is an overhead view showing a state during the manufacturing of a semiconductor device according to an embodiment. Fig. 5 is a plan view showing a state during the manufacturing of a semiconductor device according to an embodiment.

[0033] 2, 3, and 6 show semiconductor wafer 10 during processing in steps S1, S2, and S6 of FIG. 1, respectively. FIGS. 4 and 5 show semiconductor wafer 10 during processing in step S5 of FIG. 1. As will be described later, rib-shaped semiconductor wafer 10 is produced by thinning the central portion of semiconductor wafer 10, which has a substantially uniform thickness, by grinding it from the back surface (second main surface) 10b side at any timing during the manufacture of the semiconductor device, and leaving peripheral portion 12 thicker than central portion 11 along the periphery by a predetermined width. "Substantially uniform thickness" means that the thickness is the same within a range that includes tolerances due to process variations.

[0034] First, a predetermined front surface element structure (not shown) is formed in each chip region (not shown) in the central portion 11 of the semiconductor wafer 10 on the front surface (first main surface) 10a of the semiconductor wafer 10 having a substantially uniform thickness by a general method. The chip region is a portion that is separated into individual semiconductor chips after dicing (cutting) of the semiconductor wafer 10. The predetermined front surface element structure is a functional portion for obtaining various functions of the semiconductor device and an insulating layer for electrically insulating the functional portions from each other, and is composed of each portion of the surface region of the front surface 10a of the semiconductor wafer 10, and surface electrodes, insulating layers, etc. on the front surface 10a of the semiconductor wafer 10.

[0035] The various portions of the surface region of the front surface 10a of the semiconductor wafer 10 include, for example, various portions of the MOS gates of bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field effect transistors having an insulated gate (MOS gate) made of a three-layer structure of metal-oxide film-semiconductor), and the anode regions of diodes.

[0036] On the top surface of the front surface 10a of the semiconductor wafer 10, a front surface electrode (front surface electrode: not shown) containing aluminum (Al) is formed in each chip region. The front surface electrode is an emitter electrode of a bipolar transistor or an IGBT, a source electrode of a MOSFET, or an anode electrode of a diode, and functions as an electrode pad to which an external connection terminal (e.g., a terminal pin or a copper foil plate) is soldered. Except for the front surface electrode, the front surface 10a of the semiconductor wafer 10 is covered with an insulating layer such as an interlayer insulating film 23 and a passivation film 24 (see FIGS. 7 and 8).

[0037] In the outer periphery 12 of the semiconductor wafer 10, a wafer ID (an inscription for identifying the semiconductor wafer 10) is formed, for example, by a laser marker on the front surface 10a of the semiconductor wafer 10 or on an insulating layer on the front surface 10a of the semiconductor wafer 10 (not shown). Next, the central portion 11 of the semiconductor wafer 10 is ground (back-grinded) from the back surface 10b side, and is ground and thinned to a position corresponding to the product thickness used as a semiconductor device. As a result, the semiconductor wafer 10 has a rib shape in which only the thickness of the central portion 11 is thinned, and the outer periphery 12 remains thick along the periphery by a predetermined width (see FIG. 2).

[0038] In the following description, the rib-shaped semiconductor wafer 10 will simply be referred to as the semiconductor wafer 10. A step 13 is generated on the back surface 10b of the semiconductor wafer 10 due to a difference in thickness between a central portion 11 and an outer periphery 12. The portion of the semiconductor wafer 10 from the step 13 to the end portion is the outer periphery 12 of the semiconductor wafer 10. The outer periphery 12 of the semiconductor wafer 10 acts as a reinforcing member for maintaining the strength of the semiconductor wafer 10 during the manufacture of the semiconductor device. No chip region is formed on the outer periphery 12 of the semiconductor wafer 10. The width of the outer periphery 12 may be adjusted as appropriate, but is, for example, about 2 mm to 6 mm.

[0039] A portion 12b of the back surface 10b of the semiconductor wafer 10 outside the step 13 (toward the wafer edge) (hereinafter referred to as the back surface flat portion of the outer peripheral portion 12 of the semiconductor wafer 10) remains flat. A portion of the back surface 10b of the semiconductor wafer 10 between the central portion 11 and the back surface flat portion 12b of the outer peripheral portion 12 (mesa edge of the step 13) may be an inclined surface 13b inclined with respect to the back surface 10b of the semiconductor wafer 10 such that the thickness of the outer peripheral portion 12 of the semiconductor wafer 10 increases from the inside (the central portion 11 side) toward the outside. The width of the outer peripheral portion 12 of the semiconductor wafer 10 is preferably about 2.5 mm or more and 5.0 mm or less.

[0040] Next, the entire back surface of the semiconductor wafer 10 is uniformly removed by etching to remove damage that has occurred on the back surface of the semiconductor wafer 10 after grinding. For example, the entire back surface of the semiconductor wafer 10 may be removed by about 10 μm to 30 μm using a mixed acid etching solution. Next, the semiconductor wafer 10 is cleaned by a general method, and then a predetermined back surface element structure is formed in each chip region of the central portion 11 of the semiconductor wafer 10 on the back surface 10b of the semiconductor wafer 10. The predetermined back surface element structure is a functional portion for obtaining various functions of the semiconductor device and an insulating layer for electrically insulating the functional portions from each other, and is composed of each portion of the surface region of the back surface 10b of the semiconductor wafer 10 and a surface electrode on the back surface 10b of the semiconductor wafer 10.

[0041] The various portions of the surface region of the back surface 10b of the semiconductor wafer 10 are the buffer region, the collector region of the bipolar transistor or IGBT, the drain region of the MOSFET, and the cathode region of the diode. On the outermost surface of the back surface 10b of the semiconductor wafer 10, a back surface electrode (front surface electrode: not shown) is formed over the entire back surface 10b from the central portion 11 to the inclined surface 13b of the step 13 and the back surface flat portion 12b of the outer peripheral portion 12. The back surface electrode is the collector electrode of the bipolar transistor or IGBT, the drain electrode of the MOSFET, or the cathode electrode of the diode.

[0042] The back electrode is formed by sequentially laminating, for example, an aluminum layer, a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer by a sputtering method. The state up to this point is not shown, but refer to FIG. 2 for the parts marked with reference numerals. Next, a first tape 1 (back tape) is attached to the entire outermost surface (surface of the back electrode) of the back surface 10b of the semiconductor wafer 10, and the entire back electrode of the semiconductor wafer 10 is covered and protected with the first tape 1 (step S1, FIG. 2: second process). The processes from step S1 shown in FIG. 1 to step S6 described later may be performed after the formation of the front surface electrode and before the formation of the back electrode. In this case, the first tape 1 is attached directly to the back surface 10b of the semiconductor wafer 10.

[0043] The first tape 1 is attached to the central portion 11, the inclined surface 13b of the step 13, and the back flat portion 12b of the outer periphery 12 of the semiconductor wafer 10 so as to cover the entire back surface 10b of the semiconductor wafer 10. The first tape 1 has, for example, a circular planar shape with a diameter substantially equal to that of the semiconductor wafer 10. The diameter substantially equal to that of the semiconductor wafer 10 means, for example, a diameter such that the first tape 1 does not protrude outward from the edge of the semiconductor wafer 10 and does not lie 1.5 mm or more inward (toward the central portion 11 of the semiconductor wafer) from the edge of the semiconductor wafer 10 in a state where the first tape 1 is attached to the back surface 10b of the semiconductor wafer 10, and this range is preferable. In addition, it is preferable that the edge of the first tape 1 overlaps with the boundary with the outer edge (chamfered portion (not shown)) of the back flat portion 12b, but it may protrude. By overlapping the edge of first tape 1 with the boundary with the outer edge of back surface flat portion 12b, it is possible to increase the adhesive strength between first tape 1 and semiconductor wafer 10. In addition, it is possible to increase the adhesive strength between first tape 1 and second tape 2.

[0044] The first tape 1 is a UV-transmitting UV tape having an adhesive layer that hardens when irradiated with ultraviolet (UV) rays, reducing its adhesive strength. The first tape 1 has an adhesive layer (not shown) on the entire surface of one side of a circular, planar substrate having a diameter substantially the same as that of the semiconductor wafer 10, and is attached with the adhesive layer side facing the semiconductor wafer 10. The first tape 1 is made of a material that is resistant to chemicals and heat to a plating solution used in a plating process described later. The first tape 1 may be made of the same material as the second tape 2 described later.

[0045] Next, second tape 2 is attached to outer periphery 12 of semiconductor wafer 10 to cover and protect the entire edge of semiconductor wafer 10 with second tape 2 (outer periphery tape) (step S2, FIG. 3: third process). Second tape 2 is attached across from front surface 10a to back surface 10b of semiconductor wafer 10 so as to sandwich and cover the edge of semiconductor wafer 10. Second tape 2 is attached to front surface 10a (or the insulating layer on front surface 10a) of semiconductor wafer 10 at outer periphery 12 of semiconductor wafer 10, and is also attached to first tape 1 on back surface flat portion 12b.

[0046] The second tape 2 has a generally rectangular band-like planar shape that is longer than the outer periphery (circumference) of the semiconductor wafer 10. One end in the short side direction of the second tape 2 is located on the front surface 10a of the semiconductor wafer 10, and the other end in the short side direction is located on the first tape 1 at the back surface flat portion 12b of the outer periphery 12 of the semiconductor wafer 10, covering the edge and chamfered portion (reference numerals not shown) of the semiconductor wafer 10. The chamfered portion of the semiconductor wafer 10 is a generally arc-shaped portion between the front surface 10a and back surface 10b of the semiconductor wafer 10 and the edge.

[0047] The end of the second tape 2 in the short side direction is located on the flat portion of the front surface 10a inside the chamfered portion, so as not to reach the central portion 11 of the semiconductor wafer 10. The other end of the second tape 2 in the short side direction overlaps the first tape 1 so as to completely cover the back surface flat portion 12b of the outer periphery 12 of the semiconductor wafer 10. For example, it is preferable that the other end of the second tape 2 in the short side direction protrudes from the inner end of the back surface flat portion 12b of the outer periphery 12 of the semiconductor wafer 10 toward the central portion 11 by 1.5 mm or less. In addition, it is preferable that the other end of the second tape 2 in the short side direction overlaps with the end (boundary between the back surface flat portion 12b and the inclined surface 13b) on the inner side (the central portion 11 side) of the back surface flat portion 12b of the outer periphery 12 of the semiconductor wafer 10, but it may protrude. The protruding portion of the second tape 2 from the inner end of the back flat portion 12b toward the center portion 11 may be attached to the first tape 1 on the inclined surface 13b. The width of the second tape 2 in the short side direction is, for example, about 6 mm, and it is preferable that the second tape 2 be attached to the front surface 10a and the back surface 10b of the semiconductor wafer 10 by approximately half the width in the short side direction. This makes it possible to increase the adhesive strength of the second tape 2.

[0048] The second tape 2 is attached so as to go around the circumference of the semiconductor wafer 10 at least once in the longitudinal direction. The longitudinal ends of the second tape 2 are preferably overlapped by a predetermined width. The width by which the longitudinal ends of the second tape 2 overlap is preferably, for example, about 1 cm or more and 5 cm or less. This allows the longitudinal ends of the second tape 2 to be reliably adhered to each other, making it difficult for the second tape 2 to peel off from the semiconductor wafer 10 during plating. Also, the other end (hereinafter referred to as a protruding portion: see FIG. 5) 2a of the second tape 2 overlapping one longitudinal end may be left protruding. By leaving the protruding portion 2a of the second tape 2 protruding, the second tape 2 is easily peeled off.

[0049] The second tape 2 is a UV-transmitting UV tape having an adhesive layer that hardens when irradiated with UV light and has a reduced adhesive strength. The second tape 2 has an adhesive layer (not shown) on the entire surface of one of the substrates having a substantially rectangular band-like planar shape that is longer than the outer periphery of the semiconductor wafer 10, and is attached with the adhesive layer side facing the semiconductor wafer 10. The substrate of the second tape 2 has elasticity that allows it to be folded to such an extent that no gap is formed between the substrate and the semiconductor wafer 10. The second tape 2 is made of a material that is resistant to chemicals and heat to the plating solution used in the plating process described below.

[0050] Next, the semiconductor wafer 10 with the first and second tapes 1, 2 attached is heated (hereinafter referred to as tape annealing) (step S3: fourth process). This tape annealing heats the adhesive layers of the first and second tapes 1, 2, thereby increasing the adhesive strength between the semiconductor wafer 10 and the first and second tapes 1, 2. The higher the tape annealing temperature, the greater the adhesive strength between the semiconductor wafer 10 and the first and second tapes 1, 2. The tape annealing temperature is, for example, about 40°C or higher and 80°C or lower, and is preferably lower than the temperatures of the plating pre-treatment and plating treatment described below.

[0051] By setting the tape annealing temperature to equal to or higher than the above lower limit, the adhesive strength between the semiconductor wafer 10 and the first and second tapes 1, 2 is increased to an extent that the plating solution for the plating process described below does not penetrate between the semiconductor wafer 10 and the first and second tapes 1, 2. If the tape annealing temperature exceeds the above upper limit, it becomes difficult to peel the first and second tapes 1, 2 (the peel strength increases), and part of the adhesive layer of the first and second tapes 1, 2 is likely to remain on the surface of the semiconductor wafer 10. Furthermore, if the tape annealing temperature becomes too high, there is a risk that the electrical characteristics of the semiconductor device will fluctuate.

[0052] In this embodiment, the adhesive strength of the first and second tapes 1, 2 is increased by tape annealing the semiconductor wafer 10 to which the first and second tapes 1, 2 are attached. As an alternative to tape annealing, a method of increasing the adhesive strength by attaching the first and second tapes 1, 2 to the semiconductor wafer 10 heated to a predetermined temperature is also conceivable. However, in order to attach the first and second tapes 1, 2 to the heated semiconductor wafer 10, there is a risk that the manufacturing equipment will become complicated and the manufacturing cost will increase, which is not preferable. In addition, the first and second tapes 1, 2 have a larger thermal expansion coefficient than the semiconductor wafer 10. Therefore, by attaching the first and second tapes 1, 2 to the heated semiconductor wafer 10, there is a risk that the stress caused by attaching the first and second tapes 1, 2 will be larger than in the case of tape annealing. Therefore, in order to increase the adhesive strength of the first and second tapes 1, 2 attached to the semiconductor wafer 10, it is preferable to tape anneal the semiconductor wafer 10 to which the first and second tapes 1, 2 are attached.

[0053] It is presumed that by performing tape annealing for a predetermined time, the adhesive layer of the first and second tapes 1 and 2 is heated and softened, and the minute gap between the first and second tapes 1 and 2 is filled and adhered to the substrate, thereby improving the adhesive strength with the substrate. The tape annealing time for increasing the adhesive strength of the first and second tapes 1 and 2 attached to the semiconductor wafer 10 is preferably about 30 minutes, for example. The adhesive strength between the semiconductor wafer 10 and the first and second tapes 1 and 2 (hereinafter referred to as the initial adhesive strength) increases to a level where the plating solution of the plating process described below does not penetrate between the semiconductor wafer 10 and the second tape 2 by tape annealing for about 30 minutes. The adhesive strength between the semiconductor wafer 10 and the first and second tapes 1 and 2 does not change from the initial adhesive strength by tape annealing for about 3 hours or less, and increases by only about 10% even by tape annealing for more than 3 hours.

[0054] The tape annealing may be performed in, for example, a nitrogen (N2) atmosphere in which the surface of the front electrode is not oxidized. The tape annealing may be a batch type in which a plurality of semiconductor wafers 10 housed in a wafer cassette are collectively processed, or a sheet type in which the semiconductor wafers 10 are processed one by one. The tape annealing may be lamp heating in which the target is directly heated by a heating means such as an infrared lamp or a lamp heater, or may be atmospheric heat treatment in which the target is indirectly heated by exposing it to a heated atmosphere.

[0055] When the tape annealing is lamp heating, for example, the semiconductor wafer 10 may be placed in a heating furnace (oven furnace: not shown) to directly heat the semiconductor wafer 10 and the first and second tapes 1 and 2. The semiconductor wafer 10 and the first and second tapes 1 and 2 may be heated by placing the semiconductor wafer 10 on a stage (hot plate: not shown) heated by a heating means. In this case, too, it is preferable to cover the hot plate and flow a predetermined flow rate of nitrogen gas into it to create a nitrogen (N2) atmosphere. Only the semiconductor wafer 10 may be heated on the hot plate, and the first and second tapes 1 and 2 may be indirectly heated via the semiconductor wafer 10.

[0056] Next, the semiconductor wafer 10 with the first and second tapes 1, 2 attached thereto is subjected to electroless plating at a temperature of, for example, about 80°C to form a plating layer (not shown) on the surface of the front electrode (front electrode: not shown) on the front surface of the semiconductor wafer 10 (step S4: fifth process). The plating layer contains a metal such as nickel that has high adhesion to the solder layer, and is formed between the front electrode that has low adhesion to the solder layer and the external connection terminal that will be solder-joined to the front electrode in a later process. The thickness of the plating layer may be, for example, about 5 μm.

[0057] Next, the second tape 2 (periphery tape) is peeled off from the outer periphery 12 of the semiconductor wafer 10 (step S5, FIGS. 4 and 5: sixth step). Specifically, the semiconductor wafer 10 is placed and fixed on a stage (not shown) capable of adsorbing the semiconductor wafer 10, with the back surface 10b facing the stage. Then, by rotating the stage while UV light 3 is irradiated from the front surface 10a side of the semiconductor wafer 10 to several points (three points in FIG. 4) on the second tape 2 on the outer periphery 12 of the semiconductor wafer 10, the UV light 3 is irradiated to the entire circumference of the second tape 2 on the outer periphery 12 of the semiconductor wafer 10.

[0058] In this way, the entire circumference of the second tape 2 is irradiated with UV light 3, and the portion of the adhesive layer of the second tape 2 that is attached to the front surface 10a of the semiconductor wafer 10 is cured, thereby reducing the adhesive strength (peel strength of the second tape 2) to the front surface 10a of the semiconductor wafer 10. In FIG. 4, the arrow indicates the rotation direction of the stage that rotates around the circumference with the columnar holding part 4 that holds the circular, planar stage as the central axis. The second tape 2 is peeled off from the semiconductor wafer 10 by pulling the protruding part 2a of the second tape 2. The arrow 2b in FIG. 5 indicates the direction in which the protruding part 2a is pulled.

[0059] By using a UV tape for the second tape 2, it is possible to prevent a part of the adhesive layer from remaining on the front surface 10a of the semiconductor wafer 10. In addition, since the adhesive layer of the second tape 2 is irradiated with UV light 3 and cured, even if a part of the adhesive layer of the second tape 2 remains on the front surface 10a of the semiconductor wafer 10, it is possible to prevent the semiconductor wafer 10 from sticking to a conveying means in a subsequent process. In addition, the second tape 2 is attached to the first tape 1 on the back surface 10b side of the semiconductor wafer 10, and after the second tape 2 is peeled off, a part of the adhesive layer of the second tape 2 may remain on the surface of the first tape 1. For this reason, it is not necessary to irradiate the second tape 2 with UV light from the back surface 10b side of the semiconductor wafer 10.

[0060] Next, the first tape 1 (back surface tape) is peeled off from the back surface 10b of the semiconductor wafer 10 (step S6, FIG. 6). Specifically, UV light (not shown) is irradiated onto the first tape 1 from the back surface 10b side of the semiconductor wafer 10 to harden the adhesive layer of the first tape 1 and reduce the adhesive strength (peel strength of the first tape 1) to the outermost surface of the back surface 10b of the semiconductor wafer 10. Then, for example, another tape 5 is attached near the end of the first tape 1, and the first tape 1 is peeled off by lifting and pulling this tape 5. The arrow 5a in FIG. 6 indicates the direction in which the tape 5 is pulled.

[0061] Since the adhesive layer of the first tape 1 is cured by irradiating it with UV light 3, it is possible to prevent a portion of the adhesive layer from remaining on the surface of the back surface 10b of the semiconductor wafer 10. Even if a portion of the adhesive layer of the first tape 1 remains on the outermost surface of the back surface 10b of the semiconductor wafer 10, it is possible to prevent the semiconductor wafer 10 from sticking to a conveying means or a stage in a subsequent process. Then, each chip area of ​​the semiconductor wafer 10 is cut (diced) into individual chip shapes to form semiconductor chips, thereby completing a semiconductor device having a predetermined element structure.

[0062] In the above-mentioned step S4, the plating process is performed using an electroless plating method, but the plating process is not limited to this, and for example, an electrolytic plating method may be used. In addition, the plating layer formed on the surface of the front surface electrode is not limited to a nickel plating layer or a gold plating layer, and can be variously changed. In addition, when multiple front surface electrodes (electrode pads) are arranged in one chip area, a plating layer may be formed on all of these multiple front surface electrodes.

[0063] 7 and 8 are cross-sectional views showing an example of a front surface element structure of a semiconductor wafer to which the manufacturing method of a semiconductor device according to the embodiment is applied. Figures 7 and 8 show a front surface element structure of an outer peripheral portion 12 of a semiconductor wafer 10. The manufacturing method of a semiconductor device according to the embodiment described above is applicable to the case of producing (manufacturing) a semiconductor device having a front surface element structure (not shown) in which a front surface electrode is exposed on the outermost surface of the front surface 10a of the semiconductor wafer 10 in the central portion 11 (see FIG. 2) of the semiconductor wafer 10.

[0064] At the edge of the semiconductor wafer 10, the front surface 10a of the semiconductor wafer 10 may be covered with an insulating layer such as an initial oxide film 21, an interlayer insulating film 23, or a passivation film 24 (FIG. 7), or may be exposed (FIG. 8). Reference numeral 22 denotes a polysilicon layer constituting, for example, a gate runner of an IGBT or MOSFET, or a diode. By exposing the front surface 10a of the semiconductor wafer 10 at the outer periphery 12 of the semiconductor wafer 10, the adhesive strength of the second tape 2 (see FIG. 3) on the front surface 10a of the semiconductor wafer 10 can be increased. However, in either case, plating solution during plating processing may seep between the back surface 10b of the semiconductor wafer 10 and the first tape 1, causing a defective appearance, and therefore the manufacturing method of the semiconductor device according to this embodiment is useful.

[0065] As described above, according to the embodiment, after the second tape is attached to the outer periphery of the semiconductor wafer, the first and second tapes attached to the back surface and outer periphery of the semiconductor wafer, respectively, are heated (tape annealed) at a temperature of 40° C. or higher before plating. This increases the adhesive strength between the semiconductor wafer and the first and second tapes, thereby preventing the plating solution from seeping into the gap between the back surface of the semiconductor wafer and the first tape and causing poor appearance of the back surface electrode of the semiconductor wafer due to the plating solution, thereby improving productivity.

[0066] Furthermore, according to the embodiment, the increased adhesive strength between the semiconductor wafer and the first and second tapes enables automatic reading of the wafer ID formed on the outer periphery of the semiconductor wafer, thereby improving productivity. Furthermore, according to the embodiment, the increased adhesive strength between the semiconductor wafer and the first and second tapes makes it possible to suppress abnormal deposition of the plating layer on the edge of the semiconductor wafer. This makes it possible to suppress contamination of the plating bath and changes in bath composition over time, and to suppress defects in the appearance of the semiconductor wafer, thereby improving productivity.

[0067] Also, according to the embodiment, the first and second tapes are UV tapes, and when the first and second tapes are peeled off, the adhesive layers of the first and second tapes are cured by UV irradiation to reduce the adhesive strength. This makes it difficult for a portion of the adhesive layers of the first and second tapes to remain on the surface of the semiconductor wafer. Even if a portion of the adhesive layers of the first and second tapes remains on the surface of the semiconductor wafer, the adhesive layers have been cured by UV irradiation, so that the semiconductor wafer can be prevented from sticking to a conveying means or the like in a subsequent process. This makes it possible to suppress cracking of the semiconductor wafer, thereby improving productivity.

[0068] Even in conventional methods that do not involve tape annealing, the adhesive strength between the semiconductor wafer and the second tape increases if the semiconductor wafer with the second tape attached is left at room temperature for at least two hours from immediately after the attachment of the second tape (=0 hours). Specifically, the adhesive strength between the semiconductor wafer and the second tape increases the longer the leaving time at room temperature, and the inventors have confirmed that even in cases where tape annealing is not performed, the adhesive strength increases to a level that prevents the plating solution of the plating process from penetrating between the semiconductor wafer and the second tape when the wafer is left at room temperature for, for example, about 17 hours from immediately after the attachment of the second tape.

[0069] In this way, even in the conventional method, by leaving the semiconductor wafer with the first and second tapes attached for a long time before plating, the adhesive strength between the semiconductor wafer and the first and second tapes can be increased, but the longer the leaving time, the more likely it is that dust and other deposits that can cause defects will adhere to the semiconductor wafer. Also, during mass production, the semiconductor wafer is temporarily removed from the production line and left (stored), which may make it difficult to secure a storage space for the semiconductor wafer removed from the production line and to manage the time of the production line.

[0070] On the other hand, according to the embodiment, as described above, after the second tape is attached and before the plating process, the adhesive strength between the semiconductor wafer and the first and second tapes can be increased by tape annealing. Therefore, there is no need to remove the semiconductor wafer from the production line and leave it there, and the semiconductor wafer can be sequentially introduced into the post-process from the pre-process. This makes it possible to prevent adhesion of dust and other deposits that may cause defects to the semiconductor wafer. In addition, the above-mentioned problems caused by removing the semiconductor wafer from the production line and leaving it there during mass production do not occur.

[0071] (Experimental Example 1) The temperature (heating temperature) of the tape annealing (the process of step S3 in FIG. 1) was examined. Figures 9 and 10 are characteristic diagrams showing the relationship between the heating temperature and the peel strength of the second tape (peripheral tape) of Experimental Example 1. The peel strength of the second tape attached to the peripheral portion of the semiconductor wafer was measured immediately after tape annealing and after leaving it at room temperature (23°C) for a predetermined time after tape annealing (hereinafter referred to as Experimental Example 1).

[0072] For Experimental Example 1, three samples (with heating) were produced with tape annealing temperatures of 40°C, 60°C, and 80°C. The tape annealing time for the samples with tape annealing (with heating) in Experimental Example 1 was 30 minutes (shown as "30 minutes heating" in Figure 9). The "23°C room temperature" sample in Experimental Example 1 is a sample without tape annealing (without heating), which was left at room temperature (23°C) for 30 minutes between application of the second tape and plating treatment.

[0073] Here, the first tape in Experimental Example 1 was a UV tape, and the second tape was a tape having a normal adhesive layer. A normal adhesive layer is an adhesive layer that is not cured and loses adhesive strength when exposed to ultraviolet (UV) rays. It has been confirmed that the same results as in Experimental Example 1 were obtained when a UV-transmitting UV tape having an adhesive layer that is cured and loses adhesive strength when exposed to ultraviolet (UV) rays was used as the second tape.

[0074] In addition, for each sample in Experimental Example 1, a plating process was performed after tape annealing (for samples without tape annealing, the second tape was attached and then left for 30 minutes), and the presence or absence of defective appearance of the back electrode, the presence or absence of abnormal deposition of the plating layer on the edge of the semiconductor wafer, and whether or not the wafer ID could be automatically read were confirmed. For each sample in Experimental Example 1, the methods of attaching the second tape, tape annealing, and plating were performed in accordance with the manufacturing method of the semiconductor device according to the embodiment described above (see FIGS. 1 to 6). For samples for which peel strength was actually evaluated, no plating process was performed.

[0075] FIG. 9 shows the relationship between the heating temperature of the second tape and the peel strength for each sample in Experimental Example 1. FIG. 10 shows the relationship between the time (elapsed time) that the second tape was left at room temperature after heating and the peel strength. For comparison, FIG. 9 also shows the peel strength of the second tape of each sample in Experimental Example 1 before tape annealing (shown as "initial value" in FIG. 9). The samples in Experimental Example 1 without tape annealing showed the same results for both the initial peel strength of the second tape and the peel strength after 30 minutes of heating (i.e., leaving it for 30 minutes).

[0076] From the results shown in FIG. 9, it was confirmed that the peel strength of the second tape was increased by tape annealing. The method for measuring the peel strength of the second tape will be described later. Furthermore, as a result of performing plating processing on the sample without tape annealing in Experimental Example 1, it was confirmed that seepage of plating solution occurred between the rear surface of the semiconductor wafer and the first and second tapes, resulting in a defective appearance (see FIGS. 16 and 17). In addition, an abnormal deposition of a plating layer occurred on the edge of the semiconductor wafer (not shown). It was confirmed that the wafer ID could not be automatically read.

[0077] On the other hand, for each sample with tape annealing in Experimental Example 1, a plating process was performed after tape annealing, and it was confirmed that no infiltration of plating solution occurred between the back surface of the semiconductor wafer and the first tape in any of the samples with tape annealing. In addition, it was confirmed that no abnormal deposition of the plating layer occurred on the edge of the semiconductor wafer, and that the wafer ID could be automatically read (not shown). The peel strength at this time was 3.0 N or more.

[0078] In addition, in each sample with tape annealing in Experimental Example 1, it was confirmed that part of the adhesive layer of the second tape remained on the surface of the semiconductor wafer. This is because a normal adhesive layer was used for the second tape. As described later, by using a UV-transmitting UV tape for the second tape, which has an adhesive layer that hardens when exposed to ultraviolet (UV) rays and has a low adhesive strength, it is possible to prevent part of the adhesive layer from remaining on the surface of the semiconductor wafer.

[0079] Moreover, in the elapsed time (horizontal axis) in FIG. 10, tape annealing was performed at a specified temperature for the first 30 minutes, and then the samples were left at room temperature. The result at room temperature of 23°C is the result of leaving the samples without tape annealing. From the results shown in FIG. 10, it was confirmed that the second tape of each sample with tape annealing in Experimental Example 1 had a high peel strength after tape annealing, but when the samples were left at room temperature after that, the peel strength remained almost unchanged even if the leaving time was longer. It was confirmed that when the tape annealing temperature was 80°C, the peel strength of the second tape tended to decrease slightly as the leaving time was longer.

[0080] In addition, it was confirmed that when tape annealing is not performed, the peel strength of the second tape increases as the time left at room temperature after application of the second tape increases. Note that, although the results for the second tape are shown in Experimental Example 1, it was confirmed that similar results regarding heating temperature and peel strength were obtained for the first tape as well.

[0081] From the above results, it was confirmed that the peel strength of the second tape can be increased by tape annealing, and that it depends on the temperature of the tape annealing, but is almost independent of the time left at room temperature after tape annealing. Therefore, by adjusting the temperature of the tape annealing, it is possible to adjust the peel strength of the second tape to a predetermined value. By performing tape annealing after attaching the second tape, plating can be performed at any timing after tape annealing, which increases the degree of freedom in managing the time from after tape annealing to plating.

[0082] (Experimental Example 2) The time (heating time) for tape annealing the second tape was examined. Figures 11 and 12 are characteristic diagrams showing the relationship between the heating time and the peel strength of the second tape (outer peripheral tape) in Experimental Example 2. The adhesive strength (peel strength of the first and second tapes) between the semiconductor wafer and the first and second tapes (back surface tape and outer peripheral tape) was initially increased by tape annealing for 30 minutes (hereinafter referred to as initial tape annealing), and then further tape annealing (hereinafter referred to as additional tape annealing) was performed for a predetermined time, after which the peel strength of the second tape was measured (hereinafter referred to as Experimental Example 2).

[0083] As samples with tape annealing (heating) in Experimental Example 2, a sample with only initial tape annealing (elapsed time = 0 minutes) and three samples with additional tape annealing for 30 minutes (min), 60 minutes, and 180 minutes after the initial tape annealing were prepared in the first measurement. In the second measurement, a sample with only initial tape annealing and two samples with additional tape annealing for 3 hours and 6 hours after the initial tape annealing were prepared. The tape annealing temperature for each sample in Experimental Example 2 was 60°C.

[0084] The second tape of the sample in Experimental Example 2 was a tape having a normal adhesive layer. Two samples each (hereinafter referred to as samples 1 and 2) were prepared under the same conditions for the first and second measurements. In each sample of Experimental Example 2, the methods of attaching the first and second tapes, tape annealing, and plating were in accordance with the manufacturing method of the semiconductor device according to the embodiment described above (see Figs. 1 to 6). The samples for which the peel strength was actually evaluated were not plated.

[0085] From the results shown in Figures 11 and 12, it was confirmed that the peel strength of the second tape of the sample with tape annealing in Experimental Example 2 did not change from the initial peel strength when tape annealed for up to about 3 hours, and even when tape annealed for more than 3 hours but less than 6 hours, the increase was only about 10%. The initial peel strength is the peel strength after initial tape annealing only. For tape annealing, changing the annealing time to 30 minutes or more did not result in a significant improvement in peel strength. From these experimental results, it is preferable to set the annealing time to 20 to 40 minutes, taking throughput into consideration.

[0086] (Experimental Example 3) The state of the surface electrode (rear electrode) protected with UV tape (first tape: rear tape) after tape annealing and UV tape peeling was examined. Figures 13 and 14 are graphs showing the composition analysis results of the rear electrode of Experimental Example 3. Figure 13 shows a photoelectron spectrum (wide spectrum) measured by ESCA (Electron Spectroscopy for Chemical Analysis). Figure 14 shows the composition ratio of the rear electrode obtained from Figure 13.

[0087] The composition analysis of the back electrode after the first tape peeling of a sample (hereinafter referred to as Experimental Example 3) produced according to the semiconductor device manufacturing method of the above-mentioned embodiment (see Figs. 1 to 6) was performed by ESCA, and the results are shown in Figs. 13 and 14 as "with heating". In addition, Figs. 13 and 14 show a sample without tape annealing as "without heating". The first tape (back tape) of the sample of Experimental Example 3 was UV tape, and the annealing temperature and time of the sample with tape annealing were 80°C and 30 minutes, respectively. Here, UV irradiation was performed when the first tape was peeled off.

[0088] The conditions for the sample without tape annealing (without heating) in Experimental Example 3 were the same as those for the sample with tape annealing in Experimental Example 3, except that tape annealing was not performed. In Experimental Example 3, three samples each with and without tape annealing (hereinafter referred to as samples 1 to 3) were produced under the same conditions. The back electrode in Experimental Example 3 had a layered structure in which an aluminum layer, a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer were layered in this order. The ESCA analysis diameter (diameter) in Experimental Example 3 was 100 μm.

[0089] From the results shown in Figures 13 and 14, it was confirmed that the composition ratio of the rear electrode was almost the same for both the samples with and without tape annealing in Experimental Example 3, and that tape annealing did not adversely affect the rear electrode. The composition ratio of the rear electrode in Figure 13 is the ratio of the impurity amount (semi-quantitative value) of the rear electrode. In addition, the carbon (C) amount of the rear electrode of the sample with tape annealing in Experimental Example 3 was almost the same as the carbon amount of the rear electrode of the sample without tape annealing in Experimental Example 3, and it was confirmed that the adhesive layer of the first tape did not remain on the surface of the rear electrode even after tape annealing.

[0090] The results of Experimental Examples 2 and 3 above were obtained when the temperature of tape annealing (the treatment of step S3 in FIG. 1) in the manufacturing method of a semiconductor device according to the embodiment described above was set to about 40° C. or higher and 80° C. or lower. The peel strength of the second tape in Experimental Examples 1 and 2 is the peel strength against silicon (Si), and corresponds to the case where the front surface of the semiconductor wafer is exposed at the edge of the semiconductor wafer (see FIG. 8). However, similar results to Experimental Examples 1 to 3 were obtained even when the front surface of the semiconductor wafer at the edge of the semiconductor wafer was covered with an insulating layer (see FIG. 7).

[0091] (Experimental Example 4) As Experimental Example 4, a method for measuring the peel strength of the second tape (outer peripheral tape) in Experimental Examples 1 and 2 will be described. Fig. 15 is an explanatory diagram that typically shows a method for measuring the peel strength of the second tape in Experimental Example 4. Fig. 15 shows the state at the time of measuring the peel strength of the second tape 2 for a sample (hereinafter referred to as Experimental Example 4) in which a first tape 1 (back surface tape) and a second tape 2 (outer peripheral tape) are attached according to the manufacturing method for a semiconductor device according to the embodiment described above (steps S1 and S2 in Fig. 1, Figs. 2 and 3).

[0092] As shown in FIG. 15, first, the semiconductor wafer 10 of Experimental Example 4 (semiconductor wafer 10 with first and second tapes 1, 2 attached thereto) is placed and fixed on a stage (not shown) capable of adsorbing the semiconductor wafer 10 with the back surface 10b facing the stage. Next, the hook 32 of a general digital force gauge 31 is wrapped around the protruding portion 2a of the second tape 2. Next, the digital force gauge 31 is pulled in the direction in which the second tape 2 is peeled off (arrow 2b in FIG. 5). The force 33 (indicated by the hollow arrow) at which the second tape 2 begins to peel off is determined as the peel strength of the second tape 2.

[0093] Although not shown in the figures, the peel strength of the first tape 1 may be measured in the same manner as the above-mentioned method for measuring the peel strength of the second tape 2. Specifically, for example, one end of another tape 5 (see FIG. 6) is attached near the end of the first tape 1, and a hook 32 (see FIG. 15) of a digital force gauge 31 is wrapped around the other end of this tape 5. After that, the digital force gauge 31 is pulled in the direction in which the first tape 1 is peeled off (arrow 5a in FIG. 6), and the force 33 (see FIG. 15) at which the first tape 1 begins to peel off may be determined as the peel strength of the first tape 1.

[0094] The present invention can be modified in various ways without departing from the spirit of the present invention, and the element structure, the material of the electrode and plating layer, the location where the plating layer is formed (the main surface of the semiconductor wafer), the constituent material and dimensions of the first and second tapes, etc. are variously set according to the required specifications, etc. For example, the plating layer may be formed on the back surface of the semiconductor wafer while the front surface and the outer periphery of the semiconductor wafer are protected with tape. The same effect as that of the present invention can be obtained even when the first tape is attached to the back surface (or front surface) of the semiconductor wafer after the second tape is attached to the outer periphery of the semiconductor wafer. The same effect as that of the present invention can be obtained even when the first and second tapes are attached to a semiconductor wafer of approximately uniform thickness instead of a ribbed semiconductor wafer. [Industrial Applicability]

[0095] INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a semiconductor device in which a surface electrode is exposed on the outermost surface of at least one of the main surfaces of a semiconductor substrate (semiconductor chip). [Explanation of symbols]

[0096] 1 First tape (back tape) 2. Second tape (outer tape) 2a Protruding part of the second tape 2b Arrow indicating the direction to peel off the second tape 3 UV light 4 Table holder 5 Tape for peeling off the first tape 5a Arrow indicating the direction to peel off the tape for the first tape peeling 10. Semiconductor Wafers 10a Front surface of semiconductor wafer 10b Backside of semiconductor wafer 11 Center of semiconductor wafer 12 Outer periphery of semiconductor wafer 12b: Flat back surface of the outer periphery of the semiconductor wafer 13. Steps on the periphery of semiconductor wafers 13b Sloping surface of step on outer periphery of semiconductor wafer 21 Initial oxide film 22 Polysilicon layer 23 Interlayer insulating film 24 Passivation film 31 Digital Force Gauge 32 Digital force gauge hook 33 Force measured by digital force gauge

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: forming a plating layer on a first main surface side of a semiconductor wafer by plating; a first step of forming a first electrode on a first main surface of the semiconductor wafer; a second step of attaching a first tape to a second main surface of the semiconductor wafer to cover the second main surface of the semiconductor wafer with the first tape; a third step of attaching a second tape to an outer periphery of the semiconductor wafer to cover an edge of the semiconductor wafer with the second tape; a fourth step of heating the semiconductor wafer with the first tape and the second tape attached thereto by a heat treatment in an atmosphere having a temperature of 40° C. or more and 80° C. or less for 20 minutes or more and 40 minutes or less to increase adhesive strength between the first tape and the second tape and the semiconductor wafer; a fifth step of forming the plating layer on the surface of the first electrode by plating after the fourth step; 2. A method for manufacturing a semiconductor device comprising the steps of:

2. After the fifth step, the method further includes a sixth step of peeling the second tape from the semiconductor wafer; the second tape has an adhesive layer that is cured by exposure to ultraviolet light and has a reduced adhesive strength; In the third step, the second tape is attached by adhering the adhesive layer to the surface of the semiconductor wafer across the first main surface and the second main surface of the semiconductor wafer, thereby covering an edge of the semiconductor wafer with the second tape; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the sixth step, the adhesive layer of the second tape is cured by the ultraviolet light irradiation, and then the second tape is peeled off.

3. In the third step, the second tape is attached across the first main surface to the second main surface of the semiconductor wafer so as to overlap the first tape at the outer periphery of the semiconductor wafer on the second main surface of the semiconductor wafer; 3. The method for manufacturing a semiconductor device according to claim 2, characterized in that in the sixth step, the adhesive layer of the second tape attached to the first main surface of the semiconductor wafer is hardened by irradiating the ultraviolet light from the first main surface of the semiconductor wafer, and then the second tape is peeled off.

4. A method for manufacturing a semiconductor device described in any one of claims 1 to 3, characterized in that in the third step, the second tape is attached so as to go around the outer periphery of the semiconductor wafer at least once.

5. A method for manufacturing a semiconductor device described in any one of claims 1 to 4, characterized in that in the fourth step, the semiconductor wafer is placed in a heating furnace and the first tape and the second tape are directly heated.

6. A method for manufacturing a semiconductor device described in any one of claims 1 to 4, characterized in that in the fourth step, the semiconductor wafer is placed on a stage heated by a heating means and the first tape and the second tape are heated.

7. A method for manufacturing a semiconductor device as described in claim 5 or 6, characterized in that in the fourth step, the atmosphere in which the semiconductor wafer is heated is a nitrogen atmosphere.

8. In the first step, the first electrode is formed on a first main surface of the semiconductor wafer, and a second electrode is formed on a second main surface of the semiconductor wafer; 8. The method for manufacturing a semiconductor device according to claim 1, wherein in the second step, the first tape is attached to the second main surface of the semiconductor wafer to cover the second electrode with the first tape.

9. A method for manufacturing a semiconductor device described in any one of claims 1 to 8, characterized in that the semiconductor wafer is a rib-shaped semiconductor wafer having a thin central portion and a thick outer periphery of a predetermined width.

10. A method for manufacturing a semiconductor device described in any one of claims 1 to 9, characterized in that in the fifth step, the semiconductor wafer with the first tape and the second tape attached is immersed in a plating solution to form the plating layer on the surface of the first electrode.

11. A first main surface of the semiconductor wafer is exposed at an outer periphery of the semiconductor wafer, 11. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, the second tape is directly attached to the first main surface of the semiconductor wafer in the outer periphery of the semiconductor wafer.

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