Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of having a high withstand voltage while permitting manufacturing variation.SOLUTION: A semiconductor device includes a semiconductor layer 10 having an element region 101 in which an element structure is formed and a terminal end region 102 positioned at a periphery of the element region. The terminal end region includes: a plurality of guard rings 16 arranged in a first depth range of the semiconductor layer; and a resurf layer 17 which is arranged in a second depth range, different from the first depth range, of the semiconductor layer, and is arranged so as to face the plurality of guard rings in the depth direction of the semiconductor layer. An electric field intensity distribution of the plurality of guard rings and an electric field intensity distribution of the resurf layer in an intensity relation opposite to each other in a direction from an inner periphery side to an outer periphery side of the terminal end region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 discloses a semiconductor device in which a plurality of p-type guard rings and a plurality of p-type diffusion regions are provided in a termination region of a semiconductor layer. Each of the guard rings is provided at a position exposed on the surface of the semiconductor layer. Each of the diffusion regions is provided at a position deeper than the depth at which the guard rings are provided. In this way, the guard rings and the diffusion regions are provided at different depths in the termination region of the semiconductor layer.

[0003] When the semiconductor device is turned off, a depletion layer spreads from the element region toward the termination region. The depletion layer spreads toward the outer periphery and deep part of the termination region while passing through the multiple guard rings and multiple diffusion regions. By providing the multiple guard rings and multiple diffusion regions, the depletion layer spreading from the element region spreads widely toward the outer periphery and deep part of the termination region, thereby improving the breakdown voltage of the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-65238 A Summary of the Invention [Problem to be solved by the invention]

[0005] In this type of semiconductor device, it is desirable to appropriately position the multiple guard rings and the multiple diffusion regions relative to each other in order to obtain a high breakdown voltage. However, it is difficult to appropriately position the multiple guard rings and the multiple diffusion regions relative to each other due to misalignment between a mask for forming the multiple guard rings and a mask for forming the multiple diffusion regions. This specification provides a semiconductor device that can tolerate manufacturing variations and has high breakdown voltage characteristics. Furthermore, this specification also provides a manufacturing method of a semiconductor device that can be used when manufacturing such a semiconductor device. [Means for solving the problem]

[0006] The semiconductor device (1) disclosed in this specification may include a semiconductor layer (10) having an element region (101) in which an element structure is formed, and a termination region (102) located around the element region. The termination region may have a first breakdown voltage holding structure (16, 17, 18) provided in a first depth range of the semiconductor layer, and a second breakdown voltage holding structure (16, 17, 18) provided in a second depth range different from the first depth range of the semiconductor layer and arranged to face the first breakdown voltage holding structure in the depth direction of the semiconductor layer. At least one of the first breakdown voltage holding structure and the second breakdown voltage holding structure is a resurf layer (17, 18). The electric field strength distribution of the first breakdown voltage holding structure and the electric field strength distribution of the second breakdown voltage holding structure have opposite height relationships from the inner periphery side to the outer periphery side of the termination region.

[0007] In the semiconductor device, at least one of the first and second breakdown voltage structures is formed of the RESURF layer, so that the influence of the deviation in the relative positional relationship between the first and second breakdown voltage structures is suppressed. Furthermore, in the semiconductor device, the relationship of the height of the electric field strength distribution of the first and second breakdown voltage structures is reversed, so that the electric field strength distribution obtained by combining the distributions of the electric field strengths is uniformed from the inner periphery side to the outer periphery side of the termination region. Therefore, the semiconductor device can hold a high voltage in the termination region of the semiconductor layer. In this way, the semiconductor device can tolerate manufacturing variations and have high breakdown voltage characteristics.

[0008] A manufacturing method of a semiconductor device (1) disclosed in this specification can include a deposition step of depositing a mask (44) on a semiconductor layer (100) such that the aperture ratio of the mask varies along at least one direction parallel to an upper surface of the semiconductor layer, a reflow step of reflowing the mask such that the thickness of the mask varies along the one direction, and an ion implantation step of ion-implanting impurities into the semiconductor layer through the mask to form RESURF layers (17, 18).

[0009] According to the above-mentioned manufacturing method, the RESURF layer having a varying impurity concentration can be formed by ion-implanting dopants through the mask having a varying thickness. This manufacturing method is particularly useful when the material of the semiconductor layer has a small impurity diffusion property. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic cross-sectional view (cross-sectional view taken along line II-II in FIG. 1) of a main part of a semiconductor device according to the present embodiment. [Diagram 3] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Figure 4] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Diagram 5] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Figure 6] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Figure 7] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Figure 8] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Figure 9] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Figure 10] 2 is a schematic cross-sectional view of a main part in a process for manufacturing the semiconductor device of the present embodiment shown in FIG. [Figure 11] 1 is a schematic cross-sectional view (cross-sectional view taken along line II-II in FIG. 1) of a main part of a semiconductor device according to a modified example of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] 1 and 2, the semiconductor device 1 includes a semiconductor layer 10, a source electrode 22 covering a part of the upper surface 10A of the semiconductor layer 10, an interlayer insulating film 24 covering a part of the upper surface 10A of the semiconductor layer 10, a drain electrode 26 covering the entire lower surface 10B of the semiconductor layer 10, and a plurality of trench-type insulating gates 30. The semiconductor device 1 of this embodiment is a vertical MOSFET and is used as a power semiconductor device. As shown in FIG. 2, the source electrode 22 and the interlayer insulating film 24 are provided on the upper surface 10A of the semiconductor layer 10, but these components are omitted in FIG. 1.

[0012] The semiconductor layer 10 is not particularly limited, but is, for example, a semiconductor layer made of silicon carbide (SiC). The semiconductor layer 10 has an element region 101 and a termination region 102. As shown in FIG. 1, the element region 101 is disposed in the center of the semiconductor layer 10 when viewed from a direction (Z direction) perpendicular to the upper surface 10A of the semiconductor layer 10 (hereinafter, referred to as "when the semiconductor layer 10 is viewed in plan"), and is defined within the semiconductor layer 10 as a range in which a switching element structure (in this example, a MOSFET structure) is formed. The termination region 102 is disposed around the element region 101, which is a peripheral portion of the semiconductor layer 10, when the semiconductor layer 10 is viewed in plan, and is defined within the semiconductor layer 10 as a range in which a breakdown voltage holding structure (in this example, a plurality of guard rings 16 and a resurf layer 17, which will be described later) is formed.

[0013] As shown in FIG. 2, the semiconductor layer 10 is + 11, n-type drain region - a p-type drift region 12, a p-type body region 13, + A plurality of source regions 14 of type p + A plurality of body contact regions 15 of the type p + The semiconductor device has a plurality of p-type guard rings 16 and a p-type resurf layer 17. In this embodiment, the guard ring 16 is composed of five guard rings 16a, 16b, 16c, 16d, and 16e, but may be composed of a different number of guard rings. The guard ring 16 is also called a field limiting ring (FLR). The body region 13, the plurality of source regions 14, and the plurality of body contact regions 15 are selectively formed in the surface layer portion of the element region 101. The plurality of guard rings 16 and the resurf layer 17 are selectively formed in the termination region 102. In this embodiment, the boundary between the element region 101 and the termination region 102 is defined by the periphery of the body region 13.

[0014] The drain region 11 is disposed in the back layer portion of the semiconductor layer 10 in both the element region 101 and the termination region 102, and is provided at a position exposed to the lower surface 10B of the semiconductor layer 10. The drain region 11 contains a high concentration of n-type impurities (e.g., nitrogen or phosphorus, etc.) and is in ohmic contact with a drain electrode 26 that covers the lower surface 10B of the semiconductor layer 10.

[0015] The drift region 12 is provided on the drain region 11 in both the element region 101 and the termination region 102. The n-type impurity concentration of the drift region 12 is lower than the n-type impurity concentration of the drain region 11.

[0016] The body region 13 is disposed on the drift region 12 located in the element region 101, and is provided in a surface layer portion of the semiconductor layer 10. The body region 13 is formed by introducing p-type impurities (e.g., aluminum or boron) into the surface layer portion of the semiconductor layer 10 using an ion implantation technique.

[0017] The source region 14 is disposed on the body region 13 located in the element region 101, and is provided at a position exposed on the upper surface 10A of the semiconductor layer 10. The source region 14 is separated from the drift region 12 by the body region 13. The source region 14 is formed by introducing n-type impurities into a surface layer portion of the semiconductor layer 10 using ion implantation technology. The source region 14 contains a high concentration of n-type impurities, and is in ohmic contact with a source electrode 22 that covers the upper surface 10A of the semiconductor layer 10.

[0018] The body contact region 15 is disposed on the body region 13 located in the element region 101, and is provided at a position exposed on the upper surface 10A of the semiconductor layer 10. The body contact region 15 is formed by introducing p-type impurities into a surface layer portion of the semiconductor layer 10 using ion implantation technology. The body contact region 15 contains a high concentration of p-type impurities, and is in ohmic contact with the source electrode 22 that covers the upper surface 10A of the semiconductor layer 10.

[0019] As shown in FIG. 1, a plurality of trench-type insulating gates 30 are formed on the upper surface 10A of the semiconductor layer 10 in a range corresponding to the element region 101, and are arranged in a stripe pattern when the semiconductor layer 10 is viewed in plan. Each of the trench-type insulating gates 30 extends in one direction (Y direction). As shown in FIG. 2, the trench-type insulating gate 30 has a gate insulating film 32 made of silicon oxide and a gate electrode 34 made of polysilicon. The gate electrode 34 faces a portion of the body region 13 that separates the drift region 12 and the source region 14 via the gate insulating film 32. This allows the portion of the body region 13 that separates the drift region 12 and the source region 14 to function as a channel region.

[0020] In this manner, a MOSFET structure is formed in element region 101 of semiconductor layer 10, which is composed of drain region 11, drift region 12, body region 13, source region 14, body contact region, and trench-type insulated gate 30. Meanwhile, two voltage-withstanding structures are formed in termination region 102 of semiconductor layer 10, namely, a voltage-withstanding structure composed of multiple guard rings 16 and a voltage-withstanding structure composed of RESURF layer 17.

[0021] The guard rings 16 are disposed on the drift region 12 located in the termination region 102, and are provided at positions exposed to the upper surface 10A of the semiconductor layer 10. The guard rings 16 are provided in a range from the upper surface 10A of the semiconductor layer 10 to a predetermined depth. The potential of each of the guard rings 16 is floating. As shown in FIG. 1, each of the guard rings 16 is provided so as to go around the element region 101 when the semiconductor layer 10 is viewed in plan, and is concentric with and similar to the other guard rings. In this way, the guard rings 16 are laid out so that each guard ring appears repeatedly from the inner periphery side to the outer periphery side of the termination region 102.

[0022] 2, the multiple guard rings 16 are adjusted so that the spacing between adjacent guard rings increases from the inner periphery side toward the outer periphery side of termination region 102. That is, when semiconductor layer 10 is viewed in plan, the area ratio (area per unit area) of guard rings 16 decreases from the inner periphery side toward the outer periphery side of termination region 102.

[0023] The resurf layer 17 is disposed in the drift region 12 located in the termination region 102, and is provided in a predetermined depth range of the semiconductor layer 10. The resurf layer 17 is a p-type diffusion region that continuously spreads in the surface direction of the semiconductor layer 10 from the inner periphery side to the outer periphery side of the termination region 102. The potential of the resurf layer 17 is floating. The resurf layer 17 is separated from the multiple guard rings 16, and is disposed so as to face the multiple guard rings 16 in the depth direction of the semiconductor layer 10. When the semiconductor layer 10 is viewed in plan, the resurf layer 17 is provided so as to go around the periphery of the element region 101, similar to the multiple guard rings 16. As will be described in the manufacturing method described later, the resurf layer 17 has a profile in which the p-type impurity concentration decreases from the inner periphery side to the outer periphery side of the termination region 102.

[0024] Next, the operation of the semiconductor device 1 will be described. When the semiconductor device 1 is in operation, a voltage is applied between the drain and source such that the potential of the drain electrode 26 is higher than the potential of the source electrode 22. When the potential of the gate electrode 34 becomes higher than a threshold, a channel is formed in the body region 13 in an area in contact with the gate insulating film 32. Then, electrons flow from the source electrode 22 to the drain electrode 26 via the source region 14, the channel, the drift region 12, and the drain region 11. On the other hand, when the potential of the gate electrode 34 becomes equal to or lower than the threshold, the channel disappears and the flow of electrons stops. In this way, the semiconductor device 1 can control the current flowing between the source electrode 22 and the drain electrode 26 based on the potential of the gate electrode 34.

[0025] When the semiconductor device 1 is turned off, a depletion layer spreads from the pn junction surface between the drift region 12 and the body region 13 into the drift region 12. In the drift region 12 of the element region 101, the depletion layer spreads from the upper surface 10A side toward the lower surface 10B side. In the drift region 12 of the termination region 102, the depletion layer spreads from the inner periphery side toward the outer periphery side. In the semiconductor device 1, two breakdown voltage structures consisting of a plurality of guard rings 16 and a resurf layer 17 are provided in the termination region 102, so that the breakdown voltage structures are provided even in a deep position of the termination region 102. Therefore, the depletion layer spreading from the element region 101 can spread widely toward the outer periphery and deep side of the termination region 102.

[0026] In the semiconductor device 1, at least one of the two breakdown voltage holding structures is the resurf layer 17. Therefore, the breakdown voltage does not decrease significantly even if there is a misalignment between the multiple guard rings 16 and the resurf layer 17. The semiconductor device 1 can tolerate manufacturing variations when forming the multiple guard rings 16 and the resurf layer 17.

[0027] Furthermore, in the semiconductor device 1, the area ratio (area per unit area) of the multiple guard rings 16 when the semiconductor layer 10 is viewed in plan is smaller from the inner periphery side of the termination region 102 to the outer periphery side. Therefore, the electric field strength distribution of the multiple guard rings 16 when the semiconductor device 1 is turned off is relatively low on the inner periphery side of the termination region 102 and relatively high on the outer periphery side of the termination region. That is, the electric field strength distribution of the multiple guard rings 16 tends to increase from the inner periphery side of the termination region 102 to the outer periphery side. On the other hand, in the semiconductor device 1, the p-type impurity concentration of the RESURF layer 17 decreases from the inner periphery side of the termination region 102 to the outer periphery side. Therefore, the electric field strength distribution of the RESURF layer 17 when the semiconductor device 1 is turned off is relatively high on the inner periphery side of the termination region 102 and relatively low on the outer periphery side of the termination region. That is, the electric field strength distribution of the RESURF layer 17 tends to decrease from the inner periphery side of the termination region 102 to the outer periphery side. In this way, in semiconductor device 1, the relationship of the high and low electric field strength distributions of the multiple guard rings 16 and RESURF layer 17 is reversed, so that the electric field strength distribution obtained by combining the respective electric field strength distributions is uniformed from the inner periphery side toward the outer periphery side of termination region 102. Therefore, semiconductor device 1 can hold a high voltage in termination region 102, and can have a high breakdown voltage characteristic.

[0028] Next, a description will be given of a manufacturing method of the semiconductor device 1. Note that the manufacturing method of the semiconductor device 1 is characterized by a step of forming the RESURF layer 17, so the following will describe the step of forming the RESURF layer 17, and descriptions of the other steps will be omitted.

[0029] First, a semiconductor layer 100 is prepared in which a silicon carbide epilayer is stacked on a silicon carbide substrate, as shown in Fig. 3. The silicon carbide substrate is the drain region 11, and the epilayer is a part of the drift region 12. As will be described later, a silicon carbide epilayer is formed on the semiconductor layer 100 by epitaxial growth technology, thereby forming the semiconductor layer 10 shown in Figs.

[0030] 4, an NSG (Non-doped Silicate Glass) film 42 and a BPSG (Boro-Phospho Silicate Glass) film 44 are formed on the semiconductor layer 100. The NSG film 42 is used to suppress the diffusion of boron and phosphorus impurities contained in the BPSG film 44 into the semiconductor layer 100. The BPSG film 44 is used as a mask during ion implantation, as described later.

[0031] 5, resist 46 is formed on BPSG film 44. A plurality of openings 46a are formed in resist 46 in an area corresponding to termination region 102. Resist 46 is formed such that the opening ratio decreases from the inner periphery side to the outer periphery side of termination region 102.

[0032] 6, a dry etching technique is used to etch a portion of the BPSG film 44 exposed from each of the multiple openings 46a in the resist 46. As a result, multiple openings 44a corresponding to the multiple openings 46a in the resist 46 are formed in the BPSG film 44.

[0033] Next, as shown in FIG. 7, the resist 46 is removed using a resist remover.

[0034] 8, the surface of BPSG film 44 is fluidized using a reflow technique. This causes the surface of BPSG film 44 to be flattened in a tapered shape according to the aperture ratio. Since the aperture ratio of BPSG film 44 is formed so that it decreases from the inner periphery side toward the outer periphery side of termination region 102, BPSG film 44 is formed so that the surface of BPSG film 44 increases from the inner periphery side toward the outer periphery side of termination region 102, that is, BPSG film 44 is formed so that its thickness increases from the inner periphery side toward the outer periphery side of termination region 102.

[0035] 9, p-type impurities are implanted into the semiconductor layer 10 through the NSG film 42 and the BPSG film 44 by using an ion implantation technique. The p-type impurities are implanted into the semiconductor layer 10 while changing the implantation energy of the p-type impurities (i.e., the implantation depth of the impurities). Since the thickness of the BPSG film 44 increases from the inner periphery side toward the outer periphery side of the termination region 102, the concentration of the p-type impurities introduced into the semiconductor layer 100 decreases from the inner periphery side toward the outer periphery side of the termination region 102.

[0036] 10, the implanted p-type impurities are activated by annealing to form RESURF layer 17. This results in the formation of RESURF layer 17 in which the p-type impurity concentration decreases from the inner periphery side toward the outer periphery side of termination region 102. This annealing step may be used in combination with another annealing step.

[0037] After this, epitaxial growth technology is used to form n-type - A re-epi layer is then deposited corresponding to the remaining portion of the drift region 12. Furthermore, the surface structure of the element region 101 and the multiple guard rings 16 of the termination region 102 are formed, and the semiconductor device 1 is completed.

[0038] As is well known, in a semiconductor layer made of silicon carbide, dopants hardly diffuse. Therefore, even if ions are implanted through a mask for ion implantation with a varying aperture ratio as in the conventional technology, diffusion in the surface direction is insufficient, and a RESURF layer is formed intermittently in the surface direction, or a RESURF layer in which the impurity concentration repeatedly increases and decreases in the surface direction is formed. On the other hand, according to the above manufacturing method, a BPSG film 44 whose thickness varies from the inner periphery side to the outer periphery side of the termination region 102 is formed prior to the ion implantation step, and ions are implanted through the BPSG film 44, thereby forming a RESURF layer 17 in which the impurity concentration in the surface direction changes continuously. In this way, the above method for forming the RESURF layer 17 is particularly useful when the material of the semiconductor layer is silicon carbide.

[0039] In the above embodiment, the area ratio (area per unit area) of the multiple guard rings 16 when the semiconductor layer 10 is viewed in plan is smaller from the inner periphery side to the outer periphery side of the termination region 102, and the p-type impurity concentration of the RESURF layer 17 decreases from the inner periphery side to the outer periphery side of the termination region 102. Instead of this example, the area ratio (area per unit area) of the multiple guard rings 16 when the semiconductor layer 10 is viewed in plan may be larger from the inner periphery side to the outer periphery side of the termination region 102, and the p-type impurity concentration of the RESURF layer 17 may increase from the inner periphery side to the outer periphery side of the termination region 102. In this case, as in the above embodiment, the relationship between the height of the electric field intensity distribution of the multiple guard rings 16 and the RESURF layer 17 is reversed, and the semiconductor device 1 can have a high breakdown voltage characteristic. The area ratio of the multiple guard rings 16 may be adjusted by the interval between the adjacent guard rings 16, may be adjusted by the area of ​​each guard ring 16, or may be adjusted by a combination of these. In the above embodiment, the multiple guard rings 16 are arranged in a shallow range of the semiconductor layer 10, and the RESURF layer 17 is arranged in a deep range of the semiconductor layer 10. Instead of this example, the multiple guard rings 16 may be arranged in a deep range of the semiconductor layer 10, and the RESURF layer 17 may be arranged in a shallow range of the semiconductor layer 10. In this case as well, the area ratio of the multiple guard rings 16 arranged in the deep range may increase from the inner periphery side toward the outer periphery side of the termination region 102, and the p-type impurity concentration of the RESURF layer 17 arranged in the shallow range may increase from the inner periphery side toward the outer periphery side of the termination region 102.

[0040] 11, two resurf layers 17, 18 may be provided in the termination region 102. In this example, when the p-type impurity concentration of the resurf layer 17 arranged in a deep range decreases from the inner periphery side to the outer periphery side of the termination region 102, the p-type impurity concentration of the resurf layer 18 arranged in a shallow range increases from the inner periphery side to the outer periphery side of the termination region 102, and conversely, when the p-type impurity concentration of the resurf layer 17 arranged in a deep range increases from the inner periphery side to the outer periphery side of the termination region 102, the p-type impurity concentration of the resurf layer 18 arranged in a shallow range decreases from the inner periphery side to the outer periphery side of the termination region 102. In these cases, the relationship between the heights of the electric field strength distributions of the two resurf layers 17, 18 is reversed, as in the above embodiment, and the semiconductor device 1 can have high breakdown voltage characteristics. These resurf layers 17, 18 can be formed using the above-mentioned manufacturing method.

[0041] The technical elements disclosed in this specification are listed below. Note that each of the technical elements below is useful independently.

[0042] The semiconductor device disclosed in this specification may include a semiconductor layer having an element region in which an element structure is formed, and a termination region located around the element region. The material of the semiconductor layer is not particularly limited, and may be, for example, silicon carbide. Here, various types of element structures may be adopted as the element structure formed in the element region. Examples of the element structure include a MOSFET structure and an IGBT structure. The termination region may have a first breakdown voltage structure provided in a first depth range of the semiconductor layer, and a second breakdown voltage structure provided in a second depth range different from the first depth range of the semiconductor layer and arranged to face the first breakdown voltage structure in the depth direction of the semiconductor layer. The first depth range may be shallower than the second depth range, or the first depth range may be deeper than the second depth range. At least one of the first breakdown voltage structure and the second breakdown voltage structure is a resurf layer. The electric field strength distribution of the first withstand voltage holding structure and the electric field strength distribution of the second withstand voltage holding structure have opposite height relationships from the inner periphery side to the outer periphery side of the termination region.

[0043] In the semiconductor device, the first breakdown voltage holding structure may include the RESURF layer, and the second breakdown voltage holding structure may include a plurality of guard rings. In this case, (1) when the impurity concentration of the RESURF layer of the first breakdown voltage holding structure decreases from the inner circumference side to the outer circumference side, the area ratio (area per unit area) of the guard ring of the second breakdown voltage holding structure decreases from the inner circumference side to the outer circumference side, and (2) when the impurity concentration of the RESURF layer of the first breakdown voltage holding structure increases from the inner circumference side to the outer circumference side, the area ratio (area per unit area) of the guard ring of the second breakdown voltage holding structure increases from the inner circumference side to the outer circumference side. In either case of (1) or (2), the relationship between the height of the electric field strength distribution of the first breakdown voltage holding structure and that of the second breakdown voltage holding structure is reversed, and the semiconductor device can have high breakdown voltage characteristics.

[0044] In the above semiconductor device, the first breakdown voltage holding structure may be the RESURF layer, and the second breakdown voltage holding structure may also be the RESURF layer. In this case, when the impurity concentration of the RESURF layer of the first breakdown voltage holding structure decreases from the inner periphery side toward the outer periphery side, the impurity concentration of the RESURF layer of the second breakdown voltage holding structure may increase from the inner periphery side toward the outer periphery side. The relationship of the height of the electric field strength distribution of the first breakdown voltage holding structure and the second breakdown voltage holding structure is reversed, and the above semiconductor device can have high breakdown voltage characteristics.

[0045] The method for manufacturing a semiconductor device disclosed in this specification may include a deposition step of forming a mask on a semiconductor layer such that the aperture ratio of the mask varies along at least one direction parallel to the upper surface of the semiconductor layer, a reflow step of reflowing the mask such that the thickness of the mask varies along the one direction, and an ion implantation step of ion-implanting impurities into the semiconductor layer through the mask to form a resurf layer. The material of the semiconductor layer is not particularly limited, but may be, for example, silicon carbide. This manufacturing method can form any resurf layer required in various regions.

[0046] In the above manufacturing method, the semiconductor layer may have an element region in which an element structure is formed, and a termination region located around the element region. In the film forming step, the mask may be formed such that an aperture ratio of the mask varies from an inner periphery side to an outer periphery side in the termination region. According to this manufacturing method, the RESURF layer can be formed in the termination region.

[0047] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0048] : semiconductor device, 10: semiconductor layer, 11: drain region, 12: drift region, 13: body region, 14: source region, 15: body contact region, 16: guard ring, 17: resurf layer, 22: source electrode, 24: interlayer insulating film, 26: drain electrode, 30: trench type insulating gate, 101: element region, 102: termination region

Claims

1. A semiconductor device (1), The semiconductor layer (10) has an element region (101) in which an element structure is formed, and a termination region (102) located around the element region, The termination region is a first breakdown voltage holding structure (16, 17, 18) provided in a first depth range of the semiconductor layer; a second voltage-breaking holding structure (16, 17, 18) that is provided in a second depth range different from the first depth range of the semiconductor layer and that is disposed so as to face the first voltage-breaking holding structure in a depth direction of the semiconductor layer, At least one of the first and second breakdown voltage holding structures is a RESURF layer (17, 18), a height relationship between the electric field strength distribution of the first withstand voltage holding structure and the electric field strength distribution of the second withstand voltage holding structure from the inner periphery side to the outer periphery side of the termination region is reversed.

2. The semiconductor device according to claim 1 , wherein the material of the semiconductor layer is silicon carbide.

3. the first breakdown voltage holding structure includes the RESURF layer, the second voltage-resistant structure includes a plurality of guard rings (16); (1) when an impurity concentration of the RESURF layer of the first breakdown voltage holding structure decreases from the inner periphery side toward the outer periphery side, an area ratio (area per unit area) of the guard ring of the second breakdown voltage holding structure decreases from the inner periphery side toward the outer periphery side, (2) A semiconductor device as described in claim 1 or 2, wherein when the impurity concentration of the RESURF layer of the first breakdown voltage holding structure increases from the inner circumference side toward the outer circumference side, an area ratio (area per unit area) of the guard ring of the second breakdown voltage holding structure increases from the inner circumference side toward the outer circumference side.

4. the first breakdown voltage holding structure is the RESURF layer, the second breakdown voltage holding structure is also the RESURF layer, 3. The semiconductor device according to claim 1, wherein when an impurity concentration of the RESURF layer of the first breakdown voltage holding structure decreases from the inner periphery side toward the outer periphery side, an impurity concentration of the RESURF layer of the second breakdown voltage holding structure increases from the inner periphery side toward the outer periphery side.

5. A method for manufacturing a semiconductor device (1), comprising the steps of: a deposition step of depositing a mask (44) on a semiconductor layer (100) having an element region (101) in which an element structure is formed and a termination region (102) located around the element region, the mask being deposited such that an aperture ratio of the mask varies from an inner periphery side to an outer periphery side in the termination region; a reflow process of reflowing the mask, the reflow process varying a thickness of the mask along a direction from the inner periphery side to the outer periphery side; an ion implantation step of ion-implanting impurities into the semiconductor layer through the mask to form a RESURF layer (17, 18); It is equipped with The termination region is a first breakdown voltage holding structure (16, 17, 18) provided in a first depth range of the semiconductor layer; a second voltage-breaking holding structure (16, 17, 18) that is provided in a second depth range different from the first depth range of the semiconductor layer and that is disposed so as to face the first voltage-breaking holding structure in a depth direction of the semiconductor layer, At least one of the first and second breakdown voltage holding structures is the RESURF layer (17, 18).

6. The method for manufacturing a semiconductor device according to claim 5 , wherein the material of the semiconductor layer is silicon carbide.

Images