Light emitting device and measuring device

Abstract

To provide a light-emitting device and the like that suppresses the effect of capacitance on the waveform of light-emitting pulses.SOLUTION: The light-emitting device includes a light-emitting unit having a light-emitting element, a capacitance unit that is connected to the light-emitting unit, and a control unit that controls the potential of the capacitance unit when the light-emitting element of the light-emitting unit emits light.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a light emitting device and a measurement device. [Background technology]

[0002] Patent Document 1 describes a light-emitting component comprising a substrate, a plurality of light-emitting elements provided on the substrate and emitting light in a direction intersecting the surface of the substrate, and a plurality of thyristors stacked on the plurality of light-emitting elements and driving the light-emitting elements to emit light or increase the amount of light emitted when turned on, the thyristors having an opening in the path of light from the light-emitting elements toward the thyristors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-57652 A Summary of the Invention [Problem to be solved by the invention]

[0004] Measurement equipment that uses the ToF (Time of Flight) method to measure the three-dimensional shape of an object requires a light emitting device that generates a light emitting pulse with a rise and fall time of the order of several hundred ps with a light emitting current of the order of A. However, there is a risk that the waveform of the light emitting pulse will deteriorate due to the capacitance (electrical capacitance) associated with the light emitting device. The present invention provides a light emitting device and the like in which the effect of capacitance on the waveform of a light emitting pulse is suppressed. [Means for solving the problem]

[0005] The present invention relates to a light emitting device, comprising: a light emitting unit having a light emitting element; a capacitance unit connected to the light emitting unit; and a control unit that controls a potential of the capacitance unit when the light emitting element in the light emitting unit emits light. 、 Equipped with The light emitting section and the capacitance section are provided on one semiconductor substrate, the capacitance section is formed of a pn junction that is a structure equivalent to the light emitting element provided on the semiconductor substrate, the light emitting section and the capacitance section are connected by the semiconductor substrate, and the potential applied to the capacitance section by the control section is a potential that does not forward bias the pn junction. It is a light-emitting device. The invention described in claim 2 is the light-emitting device described in claim 1, characterized in that the control unit sets the potential of the capacitance unit to a first potential when the light-emitting current flowing through the light-emitting unit is on, and when the light-emitting current flowing through the light-emitting unit is changed from on to off, sets the potential of the capacitance unit from the first potential to a second potential that is greater in absolute value than the first potential. The invention described in claim 3 is the light-emitting device described in claim 2, characterized in that it includes a drive unit connected to the light-emitting unit and the capacitance unit and turns on or off the light-emitting current flowing through the light-emitting unit, and the control unit sets the potential from the first potential to the second potential depending on the timing when the drive unit turns the light-emitting current from on to off. The invention described in claim 4 is the light-emitting device described in claim 2, characterized in that the light-emitting section has a first capacitance in parallel with the light-emitting element, the capacitance section has a second capacitance, and the first potential and / or the second potential are potentials at which the first capacitance and the second capacitance are connected in series and a displacement current flows. The invention described in claim 5 is the light emitting device described in claim 4, characterized in that the second capacitance is equal to or greater than one time the first capacitance. A sixth aspect of the present invention is the light emitting device according to the fifth aspect, wherein the second capacitance is four times or less than the first capacitance. Claim 7 In the invention described in the above, the light emitting section includes a plurality of the light emitting elements. , issue 2. The light emitting device according to claim 1, further comprising a selection section for selecting the light emitting element to be caused to emit light, the selection section being stacked on the capacitance section. Claim 8 In the present invention, the control unit sets the selected light emitting element to a different potential when the light emitting element is caused to emit light, from a potential when the selection unit selects the light emitting element to emit light. 7 The light emitting device according to the present invention is Claim 9The invention described in the above is characterized in that the control unit sets the capacitance unit to a first potential when the selection unit makes the selection, and sets the capacitance unit to a second potential having an absolute value greater than that of the first potential when the selection unit completes the selection. 8 The light emitting device according to the present invention is Claim 10 The invention described in the above is the light emitting device according to the first aspect, characterized in that the control unit sets the potential of the capacitance unit to a floating state during the light emission. Claim 11 The invention described in claims 1 to 10 and a light receiving unit that receives light emitted from the light emitting unit of the light emitting device and reflected by a measured object, and measures the three-dimensional shape of the measured object. Effect of the Invention

[0006] According to the invention as recited in claim 1, the effect of capacitance on the waveform of the light emission pulse can be suppressed. According to the invention as recited in claim 2, the rise and fall times of the light emission pulse can be shortened. According to the invention as recited in claim 3, the potential can be set more easily than in a case where the driving section does not correspond to the timing at which the light-emitting current is turned on or off. According to the invention as recited in claim 4, the rise and / or fall time of the light emission pulse can be shortened compared to a case where a displacement current is not used. According to the invention as recited in claim 5, it is easy to obtain a voltage that turns off the light emitting element. According to the invention described in claim 6, the charging and discharging time is shortened compared to the case where the second capacity is more than four times larger. Claim 7 According to the invention described in the above, irradiation can be divided from the light emitting section, compared to a case where a selection section is not provided. Claim 8 According to the invention described in the above, the effect of capacitance on the waveform of the light emission pulse is suppressed, compared to the case where the same potential is used. Claim 9According to the invention described in the above, the effect of capacitance on the light emission pulse waveform is suppressed, compared to the case where the second potential is less than the absolute value of the first potential. Claim 10 According to the invention described in the above, the effect of the capacitance section on the waveform of the light emission pulse is suppressed. Claim 11 According to the invention described in the above, a measuring device capable of measuring a three-dimensional shape is provided. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram illustrating a configuration of a measurement device. [Diagram 2] FIG. 2 is a perspective view illustrating an illumination area onto which light is illuminated from the light emitting device. [Diagram 3] 3 is an equivalent circuit of a light emitting device to which the first embodiment is applied. [Figure 4] 1A and 1B are diagrams illustrating the operation of a light source including a shift thyristor, a coupling transistor, a light-emission control thyristor, and a VCSEL, where (a) is an equivalent circuit, and (b) is a cross-sectional view of a portion of the shift thyristor T and the coupling transistor. [Diagram 5] 1A and 1B are diagrams illustrating the layout and cross section of a light source, where (a) is the layout, and (b) is a cross section taken along line VB-VB in (a). [Figure 6] 1 shows the emission pulse waveforms of a VCSEL in a light emitting device, where (a) and (b) are the emission pulse waveforms of the VCSEL in a light emitting device having a shift section, and (c) is the emission pulse waveform of the VCSEL in a light emitting device not having a shift section. [Figure 7] 1A is an enlarged cross-sectional view of a light source, and FIG. 1B is an equivalent circuit of the portion shown in the enlarged cross-sectional view. [Figure 8] 1 is a diagram illustrating the effect of a capacitance unit on a light-emitting pulse waveform in a light-emitting device, where (a) is when the driver is on, (b) is when the driver is switched from on to off, (c) is when the driver is off, and (d) is when the driver is switched from off to on. [Figure 9] 1A and 1B are diagrams illustrating the operation of a light emitting device to which the first embodiment is applied, where (a) is when the driver is on, (b) is when the driver is shifted from on to off, (c) is when the driver is off, and (d) is when the driver is shifted from off to on. [Figure 10] 13 is a diagram for explaining a generalized control of changing the potential of the control potential, in which (a) shows a case where the driver is on, and (b) shows a case where the driver is shifted from on to off. [Figure 11] 1 illustrates the relationship between the capacitance to capacitance ratio and the substrate potential when the driver is off, where (a) is the case where the substrate potential when the driver is on is 2 V, and (b) is the case where the substrate potential when the driver is on is 1 V. [Figure 12] 3 is an equivalent circuit of a light emitting device shown for comparison. [Figure 13] FIG. 13 is a diagram illustrating a case where a driver is switched from on to off in a light emitting device for comparison. [Figure 14] 1 is a measurement flowchart to which the first embodiment is applied, in which (a) is a flowchart and (b) is a diagram for explaining control of a control potential. [Figure 15] 13 is an equivalent circuit of a light emitting device to which the second embodiment is applied. [Figure 16] 11A and 11B are diagrams illustrating the operation of a light emitting device to which a second embodiment is applied, where (a) is when the driver is on, (b) is when the driver is shifted from on to off, (c) is when the driver is off, and (d) is when the driver is shifted from off to on. [Figure 17] The light emission pulse waveform of a VCSEL in a light emitting device (a) is when the control potential is kept at the ground potential when the driver is turned off, and (b) is when the control potential is set to the floating potential when the driver is turned off. [Figure 18] 11 is a measurement flowchart to which the second embodiment is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. A measuring device that measures the three-dimensional shape of an object based on the ToF (Time of Flight) method measures the three-dimensional shape of the object based on the flight time of light. In other words, the ToF method measures the distance from the light emitting device to the object based on the flight time of light from the time when light is emitted from the light emitting device to the time when it is reflected by the object and received by the 3D sensor. To accurately measure the three-dimensional shape of the object, an optical pulse with rise and fall times of several hundred ps is required with an emission current of several A.

[0009] [First embodiment] (Measuring device 100) Fig. 1 is a block diagram for explaining the configuration of a measurement device 100. The measurement device 100 includes a light emitting device 1 and a three-dimensional sensor 5 (hereinafter referred to as a 3D sensor 5). The light emitting device 1 includes a light source 10, a control unit 50, and a driving unit 60. Note that Fig. 1 shows a measurement control unit 110 in addition to the measurement device 100.

[0010] The light source 10 in the light emitting device 1 emits light toward the object to be measured. The 3D sensor 5 acquires the light (reflected light) reflected by the object to be measured. The 3D sensor 5 then outputs information (distance information) about the distance to the object to be measured based on the time from when the emitted light is received until the reflected light is received. The 3D sensor 5 is an example of a light receiving unit.

[0011] The measurement control unit 110 is configured as a computer including a CPU, ROM, RAM, etc., and identifies the three-dimensional shape (hereinafter referred to as 3D shape) of the object to be measured based on distance information acquired from the 3D sensor 5. Identifying the 3D shape of the object to be measured may be referred to as three-dimensional measurement, 3D measurement, or 3D sensing. The measurement device 100 may include the measurement control unit 110.

[0012] Such a measuring device is applied to recognize a measurement target from a specified 3D shape. For example, it is mounted on a portable information processing device and used to recognize the face of a user who is trying to access the device. In other words, the 3D shape of the face of the user who has accessed the device is specified, and it is determined whether or not the user is permitted to access the device. Only when the user is recognized as being permitted to access the device, the device (portable information processing device) is permitted to be used. This measuring device is also applicable to cases where the 3D shape of an object is continuously measured, such as in augmented reality (AR).

[0013] Such a measuring device can be applied to information processing devices other than portable information processing devices, such as personal computers (PCs).

[0014] (divided irradiation) 2 is a perspective view illustrating an irradiation area 200 where light is irradiated from the light emitting device 1. Here, the irradiation area 200 is a range where light emitted from the light emitting device 1 is irradiated in order to measure the 3D shape of the object to be measured. When the object to be measured exists in the irradiation area 200, the 3D shape of the object to be measured is measured.

[0015] The irradiation area 200 is divided into a plurality of irradiation sections 210. The light emitting unit 11 of the light emitting device 1 described later includes a plurality of light emitting elements, and light is irradiated from the light emitting elements corresponding to each irradiation section 210. The light emitting device 1 irradiating light for each irradiation section 210 is referred to as divided irradiation. Although FIG. 2 shows 4×3 irradiation sections 210 arranged two-dimensionally, the number of irradiation sections 210 may be other than 4×3. In the case of divided irradiation, a light emitting element corresponding to each irradiation section 210 may be selected, and the selected light emitting element may be made to emit light, and the unselected light emitting element may be made not to emit light. In the following, it is described that the light emitting device 1 performs divided irradiation, and the selected light emitting element emits light. However, the irradiation area 200 may be irradiated collectively. Incidentally, the irradiation area 200 is irradiated collectively is referred to as collective irradiation.

[0016] (Light emitting device 1) 3 is an equivalent circuit of the light emitting device 1 to which the first embodiment is applied. In FIG. 3, the right direction of the paper is the +x direction. Thyristors and transistors are indicated by symbols, and resistors are indicated by rectangles. The same is true for other cases. As described above, the light emitting device 1 includes a light source 10, a control unit 50, and a driving unit 60.

[0017] (light source 10) The light source 10 has a φ1 terminal, a φ2 terminal, a VGK terminal, and a V C Terminal and V LD Terminal and V K A terminal VGK is a potential (power supply potential VGK) for driving the shift unit 12 in the light source 10, and V C is a potential (control potential V C ), V LD is the potential (light-emitting potential V LD , ), V K is the potential (substrate potential V K ).

[0018] The light source 10 includes a light emitting section 11, a shift section 12, and a capacitance section 13. The capacitance section 13 will be described with reference to Figures 7(a) and (b). The light emitting unit 11 includes a plurality of vertical cavity surface emitting lasers (VCSELs) and light emission control thyristors S. In the following description, the vertical cavity surface emitting lasers (VCSELs) are abbreviated as VCSELs. 3shows six VCSELs (VCSEL(1) to VCSEL(6)) and six light-emission control thyristors S (light-emission control thyristors S(1) to S(6)). The anode of the VCSEL is connected to the cathode of the light-emission control thyristor S. In other words, the VCSEL and the light-emission control thyristor S with the same number are connected in series. The six VCSELs and the six light-emission control thyristors S are arranged from one side (the -x direction side) to the other side (the +x direction side). The VCSEL is an example of a light-emitting element. The light-emitting element may be a thyristor such as the light-emission control thyristor S, and the pn junction in the thyristor may be an element that emits light.

[0019] The shift section 12 includes a plurality of shift thyristors T, coupling transistors Q, power supply line resistances Rg, current limiting resistances RL, and coupling resistances Rc. FIG. 3 shows six shift thyristors T (shift thyristors T(1) to T(6)) and six coupling transistors Q (coupling transistors Q(1) to Q(6)). Note that, although FIG. 3 shows six power supply line resistances Rg, six current limiting resistances RL, and six coupling resistances Rc, they are not numbered. Each of the shift thyristors T, coupling transistors Q, power supply line resistances Rg, current limiting resistances RL, and coupling resistances Rc constitutes a shift unit 12a. The six shift units 12a are arranged from one side (-x direction side) to the other side (+x direction side). The shift section 12 includes a power supply line resistance Rg and a start resistance Rs at an end on one side (-x direction side). Furthermore, the light source 10 includes current limiting resistors R1 and R2.

[0020] In the shift unit 12a, the shift thyristor T and the coupling transistor Q are connected. The coupling transistor Q in the shift unit 12a is connected to the light-emitting control thyristor S of the light-emitting section 11. In other words, the shift thyristors T(1) to T(6) are connected to the coupling transistors Q(1) to Q(6), and the coupling transistors Q(1) to Q(6) are connected to the same numbers as the light-emitting control thyristors S(1) to S(6). Here, six light-emitting control thyristors S, coupling transistors Q, light-emitting control thyristors S, and VCSELs are shown, but other numbers may be used.

[0021] In the light source 10, the VGK terminal is a power supply line 71, the φ1 terminal is a shift signal line 72-1, the φ2 terminal is a shift signal line 72-2, and the V C The terminal is the control potential layer 73, V LD Terminal is light emitting potential line 74, V K The terminal is connected to the substrate electrode 75. In FIG. 3, the control potential layer 73 is drawn as a line, but as shown in FIG. 7(a) described later, it is a p-type semiconductor layer 83. Therefore, it is referred to as the control potential layer 73. Similarly, in FIG. 3, the substrate electrode 75 is drawn as a line, but as shown in FIG. 5(b) described later, it is an electrode (rear electrode) provided on the rear surface of the n-type semiconductor substrate 80 constituting the light source 10. Therefore, it is referred to as the substrate electrode 75. When the shift signal lines 72-1 and 72-2 are not to be distinguished from each other, they are referred to as the shift signal line 72.

[0022] The capacitance section 13 is V C Terminal and V K It is the electrical capacitance (hereinafter referred to as capacitance) formed between the terminals.

[0023] (Control unit 50) The control unit 50 generates shift signals p1, p2 and a control signal pc to control the light source 10. The control unit 50 includes buffers Buf1 and Buf2, power supplies VS1, VS2, and VS3, and a driver Drv1. The buffer Buf1 supplies a shift signal p1 to a φ1 terminal of the light source 10. The buffer Buf2 supplies a shift signal p2 to a φ2 terminal of the light source 10. The driver Drv1 supplies a control potential VC A light source of 10 V C Supply to the terminal.

[0024] The power supply VS1 generates a power supply potential VGK and supplies it to the VGK terminal of the light source 10. The power supply VS1 also serves as the power supply for the buffers Buf1 and Buf2. That is, when the shift signals p1 and p2 are at H level (sometimes referred to as "H"), the buffers Buf1 and Buf2 output approximately the voltage of the power supply VS1, and when the shift signals p1 and p2 are at L level (sometimes referred to as "L"), they output approximately the ground potential (ground potential GND (0V)). Note that the power supply for the buffers Buf1 and Buf2 may be a power supply independent of the power supply potential VGK. In the following, supplying the ground potential GND is referred to as grounding, and ground is referred to as GND.

[0025] The power supply VS2 is the light-emitting potential V LD The light source generates 10 V LD Supply to the terminal.

[0026] The driver Drv1 includes, for example, a complementary type (CMOS configuration) driver element in which an NMOS transistor and a PMOS transistor are combined. The source of the NMOS transistor is grounded, and the source of the PMOS transistor is connected to a power supply VS3. The drain of the NMOS transistor and the drain of the PMOS transistor are connected to each other, and V C The gate of the NMOS transistor and the gate of the PMOS transistor are connected to each other, and a control signal pc is supplied to the NMOS transistor. When the control signal pc is at the H level, V C The control potential V supplied to the terminal C potential V L When the control signal pc is at the L level, V C The control potential V supplied to the terminal C potential V H In addition, the potential V H is the potential supplied by the power supply VS3. Here, as an example, V L is the ground potential GND (0V), and V H As will be described later, the potential VL is an example of a first potential, and the potential V H is an example of the second potential. Note that the driver Drv1 has a driver element configured with a CMOS, but may be another type of driver element or a switch.

[0027] Although the control unit 50 generates the shift signals p1, p2 and the control signal pc, it may receive these signals from the measurement control unit 110. Moreover, the control unit 50 and the measurement control unit 110 may be combined to form a control unit.

[0028] (Drive unit 60) The driver 60 generates a light emission signal pI to cause the VCSEL of the light source 10 to emit light. The driving unit 60 includes a driver Drv2 and a light emission current limiting resistor RI. The driver Drv2 includes, for example, an NMOS transistor as a driver element. The NMOS transistor has a source that is grounded and a drain that is connected to V K The NMOS transistor is turned on or off by a light emission signal pI applied to the gate. When the light emission signal pI is at an H level, the driver Drv2 is turned on, the drain of the NMOS transistor is at the ground potential GND (0 V), and the V K The terminal changes toward the ground potential GND (0V). When the light emission signal pI is at the L level, the driver Drv2 is turned off. Note that other elements such as an insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor) may be used instead of the NMOS transistor. Note that although the driving unit 60 generates the light emission signal pI, the light emission signal pI may be received from the measurement control unit 110. Also, the driving unit 60 and the measurement control unit 110 may be combined to form a driving unit.

[0029] The connection relationship in the light source 10 will be explained using an enlarged view. The light-emission control thyristor S may be referred to as the light-emission control thyristor, the shift thyristor T as the shift thyristor, and the coupling transistor Q as the coupling transistor. The light-emission control thyristor S and the shift thyristor T may be referred to as the thyristor without distinction.

[0030] (Operation of shift thyristor, coupling transistor, VCSEL and light emission control thyristor) Here, the basic operation of the light source 10 will be described. The shift thyristor and the light-emission control thyristor are thyristors with an npnp structure. The thyristors are equipped with an n-type cathode K (hereinafter, written as cathode K, and the same applies below), a p-type gate Gp (p-gate Gp), an n-type gate Gn (n-gate Gn), and a p-type anode A (anode A). Note that the light-emission control thyristor S does not use the p-gate Gp for control, so it is not shown.

[0031] The coupling transistor is a multi-collector npn bipolar transistor. The coupling transistor has an n-type emitter E (emitter E), a p-type base B (base B), and n-type collectors Cf, Cs (collector Cf, Cs).

[0032] The above symbols are used without distinction between thyristors and coupling transistors. The same applies to the bipolar transistors that make up the thyristors described below. However, the thyristor is composed of a combination of a single-collector npn bipolar transistor and a pnp bipolar transistor. Therefore, they are written as emitter E, base B, and collector C. In the following, even if symbols are not attached to the figures, the symbols Anode A, cathode K, n-gate Gn, p-gate Gp, emitter E, base B, and collector C will be used.

[0033] The shift thyristor T, the coupling transistor Q, the light-emission control thyristor S, and the VCSEL are composed of a III-V compound semiconductor, such as GaAs. Here, the forward voltage (diffusion potential) Vd of the junction of this compound semiconductor is set to 1.5 V, and the saturation voltage Vsat of the bipolar transistor composed of the compound semiconductor is set to 0.3 V. In addition, the ground potential GND is set to 0 V, the power supply potential VGK is set to 5 V, and the light-emission potential V LD is set to 7 V. The shift signals p1 and p2, the control signal pc, and the light emission signal pI are signals whose L level is 0 V ("L" (0 V)) and whose H level is 5 V ("H" (5 V)).

[0034] Fig. 4 is a diagram explaining the operation of the light source 10 using the shift thyristor T(1), the coupling transistor Q(1), the light-emission control thyristor S(1), and the VCSEL(1). Fig. 4(a) is an equivalent circuit, and Fig. 4(b) is a cross-sectional view of the shift thyristor T(1) and the coupling transistor Q(1). Fig. 4(a) also shows the shift thyristor T(2).

[0035] As shown in FIG. 4(a), the shift thyristor T(1) is composed of a combination of an npn bipolar transistor Tr1 (hereinafter, referred to as npn transistor Tr1) and a pnp bipolar transistor Tr2 (hereinafter, referred to as pnp transistor Tr2). The base B of the npn transistor Tr1 is connected to the collector C of the pnp transistor Tr2, and the collector C of the npn transistor Tr1 is connected to the base B of the pnp transistor Tr2. The emitter E of the npn transistor Tr1 is the cathode K of the shift thyristor T(1), and the emitter E of the pnp transistor Tr2 is the anode A of the shift thyristor T(1). The collector C of the npn transistor Tr1 (base B of the pnp transistor Tr2) is the n gate Gn of the shift thyristor T(1), and the collector C of the pnp transistor Tr2 (base B of the npn transistor Tr1) is the p gate Gp of the shift thyristor T(1).

[0036] The cathode K of the shift thyristor T(1) (the emitter E of the npn transistor Tr1) is connected to the control potential layer 73. The control potential layer 73 is connected to a control potential V C V C The n-gate Gn of the shift thyristor T(1) is connected to a terminal. An anode A of the shift thyristor T(1) (emitter E of the pnp transistor Tr2) is connected to a shift signal line 72-1. The shift signal line 72-1 is connected to a φ1 terminal to which a shift signal p1 is supplied. An n-gate Gn of the shift thyristor T(1) is connected to a connection point between a start resistor Rs and a power supply line resistor Rg connected in series. The other side (the side other than the connection point) of the start resistor Rs is connected to a shift signal line 72-2. The shift signal line 72-2 is connected to a φ2 terminal to which a shift signal p2 is supplied. The other side (the side other than the connection point) of the power supply line resistor Rg is connected to a power supply line 71. The power supply line 71 is connected to a VGK terminal to which a power supply potential VGK is supplied.

[0037] The coupling transistor Q(1) is an npn transistor. The base B of the coupling transistor Q(1) is connected to the p-gate Gp (the base B of the npn transistor Tr1 and the collector C of the pnp transistor Tr2) of the shift thyristor T(1). The emitter E of the coupling transistor Q(1) is connected to the control potential layer 73. The collector Cf of the coupling transistor Q(1) is connected to the power supply line 71 via a coupling resistor Rc and a power supply line resistor Rg connected in series. The connection point between the coupling resistor Rc and the power supply line resistor Rg is connected to the n-gate Gn of the shift thyristor T(2).

[0038] The npn transistor Tr1 in the shift thyristor T(1) and the coupling transistor Q(1) form a current mirror circuit. That is, a current proportional to the current flowing through the npn transistor Tr1 flows through the coupling transistor Q(1).

[0039] The collector Cs of the coupling transistor Q(1) is connected to the n-gate Gn of the light-emission control thyristor S(1) and is also connected to a light-emission potential line 74 via a current-limiting resistor RL. The light-emission potential line 74 is connected to a light-emission potential VLD V LD is connected to the terminal.

[0040] As described above, the VCSEL(1) and the light-emission control thyristor S(1) are connected in series. In other words, the anode A of the VCSEL(1) and the cathode K of the light-emission control thyristor S(1) are connected. The anode A of the light-emission control thyristor S(1) is connected to the light-emission potential line 74. The cathode K of the VCSEL(1) is connected to the substrate electrode 75. The substrate electrode 75 is connected to a V K It is connected to the terminal (see Figure 3).

[0041] The anode A of the shift thyristor T(2) is connected to a shift signal line 72-2. The shift signal line 72-2 is connected to a φ2 terminal to which a shift signal p2 is supplied. As shown in FIG. 3, the anode A of the odd-numbered shift thyristor T is connected to a shift signal line 72-1, and the anode A of the even-numbered shift thyristor T is connected to a shift signal line 72-2. Except for the connection relationship between the shift thyristor T and the shift signal lines 72-1 and 72-2, the connection relationship between the shift thyristors T numbered 2 or more, the coupling transistor, the light-emission control thyristor S, and the VCSEL is the same as that between the shift thyristor T(1), the coupling transistor Q(1), the light-emission control thyristor S(1), and the VCSEL(1). Hereinafter, they may be referred to as a shift signal p1(φ1) and a shift signal p2(φ2).

[0042] First, the operation of the shift thyristor T(1) in the shift section 12 will be described. It is assumed that the power supply line 71 is at the power supply potential VGK (5V), the control signal pc is "L" (0V) and the control potential layer 73 is at the ground potential GND (0V), the shift signals p1 (φ1) and p2 (φ2) are "L" (0V) and the shift signal lines 72-1 and 72-2 are at the ground potential GND (0V), the light emission signal pI is "L" (0V), the driver Drv2 is off, and no voltage is supplied to the substrate electrode 75. This state is referred to as the initial state.

[0043] At this time, the npn transistor Tr1 and the pnp transistor Tr2 constituting the shift thyristor T(1) are in an off state. The n gate Gn of the shift thyristor T(1) is connected to the connection point between the start resistor Rs and the power line resistor Rg connected in series. The other side (the side not the connection point) of the start resistor Rs is connected to the "L" (0V) shift signal line 72-2, and the other side (the side not the connection point) of the power line resistor Rg is connected to the 5V power line 71. Therefore, the n gate Gn becomes a voltage obtained by dividing the voltage difference (5V) between the start resistor Rs and the power line resistor Rg. If the resistance ratio between the start resistor Rs and the power line resistor Rg is 1:5 as an example, the n gate Gn becomes 0.83V.

[0044] Here, when the shift signal p1 (φ1) transitions from "L" (0V) to "H" (5V), the voltage difference between the emitter E (anode A) ("H" (5V)) and base B (p-gate Gp) (0.83V) of the pnp transistor Tr2 of the shift thyristor T(1) becomes 4.17V, which is greater than the forward voltage Vd (1.5V). This causes a forward bias between the emitter E and base B, and the pnp transistor Tr2 transitions from the off state to the on state. Then, the collector C (base B of the npn transistor Tr1) of the pnp transistor Tr2 becomes 4.7V, which is the emitter E ("H" (5V)) minus the saturation voltage Vsat (0.3V), which is greater than the forward voltage Vd (1.5V). This causes a forward bias between the emitter E and base B, and the npn transistor Tr1 transitions from the off state to the on state. Since the npn transistor Tr1 and the pnp transistor Tr2 in the shift thyristor T(1) are turned on, the shift thyristor T(1) transitions from the off state to the on state. The transition of the shift thyristor T from the off state to the on state is referred to as "turn on." The transition of the shift thyristor T from the on state to the off state is referred to as "turn off."

[0045] That is, in the initial state, when the shift signal p1 (φ1) transitions from "L" (0V) to "H" (5V), the shift thyristor T(1) turns on and transitions from the off state to the on state. Here, the state in which the shift thyristor T(1) can turn on when the anode A becomes "H" (5V) is expressed as a state in which it can transition to the on state. The same applies to other cases.

[0046] When the shift thyristor T(1) turns on, the n gate Gn of the shift thyristor T(1) becomes 0.3V, which is the saturation voltage Vsat. The anode A becomes a voltage determined by the sum of the forward voltage Vd and the saturation voltage Vsat (Vd+Vsat) and the voltage drop due to the internal resistance of the shift thyristor T. Here, it is assumed that the anode A becomes 1.9V. In other words, when the shift thyristor T(1) turns on, the shift signal line 72-1 transitions from 5V to 1.9V. Then, the p gate Gp of the shift thyristor T(1) becomes 1.6V.

[0047] As described above, the shift thyristor T(1) turns on when the potential of the n gate Gn becomes lower than the potential of the anode A by the forward voltage Vd (1.5 V) or more. The shift thyristor T(1) turns off when the potential of the shift signal line 72-1 (potential between the anode A and the cathode K) becomes less than the above 1.9 V. For example, when the anode A becomes "L" (0 V), the potential difference between the anode A and the cathode K becomes 0 V, so the shift thyristor T(1) turns off. On the other hand, if the voltage of the shift signal line 72-1 (potential difference between the anode A and the cathode K) is 1.9 V or more, the shift thyristor T(1) is maintained in the on state. Therefore, 1.9 V is represented as the holding voltage. Even if the holding voltage is applied, if there is no current flowing to maintain the shift thyristor T(1) in the on state, the shift thyristor T(1) is not maintained in the on state. The current that maintains the on-state is referred to as the "holding current."

[0048] Next, the operation of the coupling transistor Q(1) will be described. If the shift thyristor T(1) is in the off state, the npn transistor Tr1 is in the off state. Therefore, the coupling transistor Q(1) is also in the off state. At this time, in the coupling transistor Q(1), the emitter E is connected to the control potential layer 73 which is at the ground potential GND (0V). The collector Cf is at the power supply potential VGK (5V) via the power supply line resistance Rg and the coupling resistance Rc which are connected in series. Also, the collector Cs is at the light-emitting potential V LD (7V).

[0049] As described above, when the shift thyristor T(1) turns on, the shift signal line 72-1 becomes 1.9V. Then, the p-gate Gp of the shift thyristor T(1) becomes 1.6V. Since the base B of the coupling transistor Q(1) is connected to the p-gate Gp of the shift thyristor T(1), the forward voltage Vd (1.5V) or more is applied between the emitter E and base B of the coupling transistor Q(1), that is, the coupling transistor Q(1) becomes forward biased. This causes the coupling transistor Q(1) to transition from the off state to the on state. Then, the collector Cf becomes the saturation voltage Vsat (0.3V) (the collector Cs will be described later). The connection point between the power supply line resistance Rg and the coupling resistance Rc (the n-gate Gn of the shift thyristor T(2)) becomes a voltage obtained by dividing the voltage difference (4.7V) between the voltage of the power supply line 71 (5V) and the voltage of the collector Cf (0.3V) by the power supply line resistance Rg and the coupling resistance Rc. If the resistance ratio of the power supply line resistance Rg and the coupling resistance Rc is 5:1 as an example, the connection point between the power supply line resistance Rg and the coupling resistance Rc (the n gate Gn of the shift thyristor T(2)) becomes 1.08V.

[0050] The anode A of the shift thyristor T(2) is connected to the shift signal line 72-2. The shift signal line 72-2 is connected to the φ2 terminal to which the shift signal p2 (φ2) is supplied. Since the shift signal p2 (φ2) is "L" (0V), the shift thyristor T(2) does not turn on. However, when the shift signal p2 (φ2) transitions from "L" (0V) to "H" (5V), the anode A of the shift thyristor T(2) connected to the shift signal line 72-2 becomes "H" (5V). Then, the potential difference (3.92V) between the anode A and the n-gate Gn (1.08V) of the shift thyristor T(2) becomes equal to or greater than the forward voltage Vd (1.5V). Then, the n-gate Gn-anode A of the shift thyristor T(2) is forward biased, and the shift thyristor T(2) turns on. At this time, the shift thyristor T(1) and the shift thyristor T(2) are in the on state. Next, when the shift signal p1 (φ1) transitions from "H" (5V) to "L" (0V), the anode A of the shift thyristor T(1) becomes "L" (0V), and the shift thyristor T(1) is turned off.

[0051] That is, the on state of the shift thyristor T is shifted by alternately switching the shift signals p1 (φ1) and p2 (φ2) between "L" (0V) and "H" (5V) with a period during which both are "H" (5V). In this way, there are multiple elements, and the operation in which the elements that are turned on among the multiple elements transition one after another is the shift operation. In the embodiments in this specification, the elements that are turned on or off by this shift operation are the shift elements.

[0052] Finally, the operation of the light-emission control thyristor S(1) and the VCSEL(1) will be described. The collector Cs of the coupling transistor Q(1) is connected to the n-gate Gn of the light-emission control thyristor S(1). Therefore, when the coupling transistor Q(1) transitions from the OFF state to the ON state, the potential of the n-gate Gn of the light-emission control thyristor S(1) connected to the collector Cs becomes 0.3 V, similar to the potential of the collector Cs of the coupling transistor Q(1). The anode A of the light-emission control thyristor S(1) is connected to the light-emission potential line 74. The light-emission potential line 74 is connected to the light-emission potential V LD (7V) is supplied to V LD The anode An and gate Gn of the light-emitting control thyristor S(1) are connected to the terminals. Therefore, the voltage between the anode An and gate Gn of the light-emitting control thyristor S(1) is 6.7 V, and the pn junction between the anode An and gate Gn of the light-emitting control thyristor S(1) is in the forward direction. Then, the collector Cs of the coupling transistor Q(1) is connected to the light-emitting potential V LD A current is drawn from the anode An of the light-emitting control thyristor S(1) through the pn junction between the gate Gn and the anode An of the light-emitting control thyristor S(1). This causes the collector Cs of the coupling transistor Q(1) to reach approximately the light-emitting potential V LD (7V) minus the forward voltage Vd (1.5V) is 5.5V. At this point, the driver Drv2 turns on and V K The terminal changes toward the ground potential GND (0 V). As a result, the substrate electrode 75 and the cathode K of the VCSEL(1) change toward 0 V. This turns on the light-emission control thyristor S(1), causing a current to flow through the light-emission control thyristor S(1) and VCSEL(1), which are connected in series, and causes the VCSEL(1) to emit light.

[0053] In other words, when the coupling transistor Q(1) is turned on and the n gate Gn of the light-emission control thyristor S(1) is at 5.5V, the VCSEL(1) emits light when the driver Drv2 is turned on. Therefore, when the coupling transistor Q(1) is turned on and a forward bias (5.5V) is applied between the anode An and gate Gn of the light-emission control thyristor S(1), this is referred to as a state in which the VCSEL(1) is capable of emitting light. The light-emission control thyristor S controls the light emission of the VCSEL by the potential of the n gate Gn, so it is referred to as the light-emission control thyristor.

[0054] When the driver Drv2 is turned from on to off, the light-emitting current that had been flowing through the light-emission control thyristor S(1) and VCSEL(1) stops flowing, and the light emission of the VCSEL(1) stops (becomes quenched).

[0055] At this time, assume that the shift thyristor T(1) goes from on to off, causing the coupling transistor Q(1) to transition from on to off. In other words, the collector Cs of the coupling transistor Q(1) cannot maintain 5.5 V. The n-gate Gn of the light-emitting control thyristor S(1) is driven by the light-emitting potential V LD (7V). Therefore, the n-gate Gn of the light-emission control thyristor S(1) is connected to the light-emission potential line 74 of the light-emission potential V LD (7V). At this time, the parasitic capacitance Cag (capacitance is Cag) between the anode and n-gate Gn of the light-emitting control thyristor S(1) is discharged via the current-limiting resistor RL (resistance value is RL) with a time constant of RL x Cag. Meanwhile, the charges stored in the parasitic capacitance Cgg between the n-gate Gn and p-gate Gp of the light-emitting control thyristor S(1), the parasitic capacitance Cgk between the p-gate Gp and cathode K, and the parasitic capacitance Cv of the VCSEL(1) cannot move, so the potentials of the p-gate Gp and cathode K of the light-emitting control thyristor S(1) rise by the amount that the potential of the n-gate Gn has risen.

[0056] Here, when the light emission signal pI changes from "L" (0 V) to "H" (5 V) and the driver Drv2 is turned on again, the substrate potential V Ksuddenly changes toward the ground potential GND (0V). That is, the substrate electrode 75 to which the cathode K of the VCSEL(1) is connected suddenly changes toward the ground potential GND (0V). As a result, a displacement current flows through the parasitic capacitances Cag, Cgg, and Cgk, and the light-emission control thyristor S(1) turns on with this as a threshold current, and the VCSEL(1) emits light. That is, once the VCSEL(1) emits light, the VCSEL(1) emits light again when the driver Drv2 turns on again, even if the shift thyristor T(1) is not in the on state. Even after this, the VCSEL(1) can repeatedly emit light and turn off. That is, the VCSEL(1) can generate multiple light-emission pulses continuously. Note that if the rise in the potential of the cathode K of the light-emission control thyristor S(1) is small and close to the ground potential GND, the light-emission control thyristor S(1) does not turn on even if the driver Drv2 turns on again. The light emission pulse may be referred to as a light pulse or a pulsed light.

[0057] The shift thyristor T(1) not being on includes a case where the shift thyristor T(1) has transitioned to an off state, as well as a case where the shift unit 12 has stopped operating, that is, is off. The shift unit 12 being off means, for example, a state where both shift signals p1 and p2 are set to "L" (0V). As described above, once a VCSEL has emitted light, it can continuously generate multiple light emission pulses even if the shift unit 12 is turned off. Putting the VCSEL in a state where it can emit light again is referred to as manifesting a memory effect. Note that when the shift unit 12 is turned off, no current flows through the shift thyristor T and the coupling transistor Q, and therefore the power consumption of the light source 10 is suppressed.

[0058] Control potential V C is supplied to the cathode K of the shift thyristor T and the emitter E of the coupling transistor Q. Therefore, when the shift unit 12 is operated, the control potential V C However, when the shift unit 12 is not operated or when the shift unit 12 is turned off, the control potential V Cmay be set to a potential different from the ground potential GND (0V).

[0059] In other words, the initial state is a state in which the power supply line 71 is at the power supply potential VGK (5V), the control potential layer 73 is at the ground potential GND (0V), the shift signals p1 (φ1) and p2 (φ2) are "L" (0V), the shift signal lines 72-1 and 72-2 are at the ground potential GND (0V), the light emission signal pI is "L" (0V), the driver Drv2 is off, and no voltage is supplied to the substrate electrode 75. In the initial state, the shift thyristor T(1) is in a state in which it can be switched to the on state. Here, when the shift signal p1 (φ1) (shift signal line 72-1) is switched from "L" (0V) to "H" (5V), the shift thyristor T(1) is turned on and switches from the off state to the on state. When the shift thyristor T(1) is turned on, the coupling transistor Q(1) switches from the off state to the on state. Then, the anode A and the n-gate Gn of the light-emission control thyristor S(1) are forward biased, and the VCSEL(1) is put into a state in which it can emit light. Then, the substrate potential V K When the potential of the VCSEL changes toward the ground potential GND (0 V), the light-emission control thyristor S(1) turns on and the VCSEL(1) emits light.

[0060] Also, when the coupling transistor Q(1) is turned on, the shift thyristor T(2) is in a state in which it can transition to an on state. Then, when the shift signal p2(φ2) (shift signal line 72-2) transitions from "L" (0V) to "H" (5V), the shift thyristor T(2) turns on. Note that, when the shift signal p1(φ1) (shift signal line 72-1) transitions from "H" (5V) to "L" (0V), the cathode K and anode A of the shift thyristor T(1) become "L" (0V), and the shift thyristor T(1) turns off. The other shift thyristors T, coupling transistors Q, light-emission control thyristors S, and VCSELs operate in the same manner. That is, the shift thyristor T in the on state is shifted by the shift signal p1(φ1) and the shift signal p2(φ2).

[0061] Once VCSEL(1) emits light, a memory effect appears, and multiple light emission pulses can be generated continuously even if shift unit 12 is turned off.

[0062] Here, the shift thyristor T(1), the coupling transistor Q(1), the light-emission control thyristor S(1), and the VCSEL(1) have been described, but the on state of the shift thyristor T is shifted by the operation of the shift unit 12, and the VCSEL connected to the on-state shift thyristor T and the coupling transistor Q is selected as the VCSEL to emit light. Then, the VCSEL to be emitted is caused to emit light as described above. In this way, by causing the VCSEL selected by the shift unit 12 to emit light, irradiation is performed for each irradiation section 210 in the divided irradiation. The shift unit 12 is an example of a selection unit.

[0063] As shown in FIG. 4(b), the light source 10 is a semiconductor component configured by stacking a plurality of semiconductor layers (see FIG. 5 described later). FIG. 4(b) shows a portion where an n-type semiconductor layer 85, a p-type semiconductor layer 86, an n-type semiconductor layer 87, and a p-type semiconductor layer 88 constituting the shift thyristor T(1) and the coupling transistor Q(1) are stacked. The shift thyristor T(1) is configured with the n-type semiconductor layer 85 as the cathode K, the p-type semiconductor layer 86 as the p-gate Gp, the n-type semiconductor layer 87 as the n-gate Gn, and the p-type semiconductor layer 88 as the anode A. On the other hand, the coupling transistor Q(1) is configured with the n-type semiconductor layer 85 as the emitter E, the p-type semiconductor layer 86 as the base B, and the n-type semiconductor layer 87 as the collectors Cf and Cs. Here, the cathode K of the shift thyristor T(1) and the emitter E of the coupling transistor Q(1) are electrically connected via the n-type semiconductor layer 85. Similarly, the p-gate Gp of the shift thyristor T(1) and the base B of the coupling transistor Q(1) are electrically connected via a p-type semiconductor layer 86. The n-gate Gn of the shift thyristor T(1) and the collectors Cf, Cs of the coupling transistor Q(1) are both composed of an n-type semiconductor layer 87, but are separated. The same is true for the other shift thyristors T and coupling transistors Q.

[0064] Fig. 5 is a diagram illustrating the layout and cross section of the light source 10. Fig. 5(a) is the layout, and Fig. 5(b) is a cross section along line VB-VB in Fig. 5(a). Fig. 5(a) mainly illustrates the shift thyristors T(1) to T(4), the coupling transistors Q(1) to Q(4), the light-emission control thyristors S(1) to S(4), and VCSEL(1) to VCSEL(4). Fig. 5(b) illustrates a cross section of the light-emission control thyristor S(1), VCSEL(1), shift thyristor T(1), coupling transistor Q(1), the coupling resistor Rc connected to the coupling transistor Q(1), and the power line resistor Rg.

[0065] As shown in FIG. 5(b), the light source 10 is configured by stacking an n-type semiconductor layer 81, an active layer 82, a p-type semiconductor layer 83, a tunnel junction layer 84, an n-type semiconductor layer 85, a p-type semiconductor layer 86, an n-type semiconductor layer 87, and a p-type semiconductor layer 88 on an n-type semiconductor substrate 80. The elements such as the shift thyristor T, the coupling transistor Q, the light-emission control thyristor S, and the VCSEL are configured from a plurality of islands separated by removing a part of the semiconductor layer by etching. The island may be referred to as a mesa, and the etching for forming the island (mesa) may be referred to as mesa etching. In the following, the islands (islands 300, 301 to 307) will be described, focusing on the island 301 where the light-emission control thyristor S(1) and the VCSEL(1) are provided, and the island 302 where the shift thyristor T(1) and the coupling transistor Q(1) are provided.

[0066] The island 300 is a portion in which the shift section 12 (see FIG. 3) such as the shift thyristor T(1) and the coupling transistor Q(1) is provided, and an n-type semiconductor layer 81, an active layer 82, a p-type semiconductor layer 83, a tunnel junction layer 84, and an n-type semiconductor layer 85 are left on an n-type semiconductor substrate 80 without being removed.

[0067] A VCSEL(1) and a light-emission control thyristor S(1) are stacked on an island 301. A shift thyristor T(1) and a coupling transistor Q(1) shown in FIG. 2(b) are provided on an island 302. A current-limiting resistor RL is provided on an island 303, and a power supply line resistor Rg and a coupling resistor Rc are provided on an island 304. A power supply line resistor Rg and a start resistor Rs are provided on an island 305. A current-limiting resistor R1 is provided on an island 306, and a current-limiting resistor R2 is provided on an island 307.

[0068] The layout and cross section will be described below with reference to FIGS. 5(a) and 5(b). Around the island 301, the n-type semiconductor layer 81, the active layer 82, the p-type semiconductor layer 83, the tunnel junction layer 84, the n-type semiconductor layers 85 and 87, and the p-type semiconductor layers 86 and 88 are removed by etching. A p-ohmic electrode 321 that easily makes ohmic contact with the p-type semiconductor layer is provided on the p-type semiconductor layer 88. An n-ohmic electrode 331 that easily makes ohmic contact with the n-type semiconductor layer is provided on the n-type semiconductor layer 87 that is exposed by removing the p-type semiconductor layer 88. In the VCSEL (1), the n-type semiconductor layer 81 is the cathode K (see FIG. 4(a)), the active layer 82 is the active layer, and the p-type semiconductor layer 83 is the anode A (see FIG. 4(a)). In the light-emitting control thyristor S (1), the n-type semiconductor layer 85 is the cathode K, the p-type semiconductor layer 86 is the p-gate Gp (p-gate layer), the n-type semiconductor layer 87 is the n-gate Gn (n-gate layer), and the p-type semiconductor layer 88 is the anode A. The n-ohmic electrode 331 is the n-gate Gn of the light-emission control thyristor S(1).

[0069] As shown in FIG. 5(b), a VCSEL(1) is provided on an n-type semiconductor substrate 80, and an emission control thyristor S(1) is layered on the VCSEL(1) via a tunnel junction layer 84. The tunnel junction layer 84 prevents a p-type semiconductor layer 83 of the VCSEL(1) and an n-type semiconductor layer 85 of the emission control thyristor S(1) from being reverse biased, making it difficult for a current to flow. The tunnel junction layer 84 is an n-type junction layer doped with a high concentration of n-type impurities. ++ layer and p++ Even in the case of reverse bias, a current flows due to the tunnel effect.

[0070] The island 301 is cylindrical except for the portion where the n-ohmic electrode 331 is provided. The p-ohmic electrode 321 is provided in an annular shape on the p-type semiconductor layer 88 of the cylindrical island 301. A part of the semiconductor layer constituting the p-type semiconductor layer 83 exposed by etching is oxidized from the cylindrical outer periphery, forming a current blocking portion β through which current does not easily flow in an annular shape. On the other hand, the central portion that is not oxidized becomes a current passing portion α through which current easily flows. Light is emitted from the central portion of the annular p-ohmic electrode 321. The current blocking portion β is formed by providing an AlAs layer or an AlGaAs layer with a high Al concentration in the p-type semiconductor layer 83, and oxidizing the exposed outer periphery to oxidize Al. The peripheral portion of the VCSEL (1) has many defects due to etching, and non-radiative recombination is likely to occur. Therefore, by providing the current blocking portion β, the power consumed by non-radiative recombination is suppressed. By providing the current blocking portion β, it is possible to reduce power consumption and improve light extraction efficiency. The light extraction efficiency is the amount of light that can be extracted per unit of electric power.

[0071] 5(a) and 5(b), the VCSEL(1) emits light through the light-emission control thyristor S(1). Note that the light-emission control thyristor S(1) (tunnel junction layer 84, n-type semiconductor layers 85 and 87, and p-type semiconductor layers 86 and 88) in the portion of the island 301 from which the light is emitted may be removed. In this case, the light-emission control thyristor S(1) becomes cylindrical. This prevents the light emitted by the VCSEL(1) from being absorbed by the light-emission control thyristor S(1) and causing a decrease in the amount of light.

[0072] Around the island 302, the p-type semiconductor layer 86, the n-type semiconductor layer 87, and the p-type semiconductor layer 88 are removed by etching (see FIG. 4(b)). A p-ohmic electrode 322 is provided on the p-type semiconductor layer 88. The p-ohmic electrode 322 is an electrode (anode A electrode) connected to the anode A of the shift thyristor T(1), and is connected to a shift signal line 72-1 to which a shift signal p1 (φ1) is supplied. N-ohmic electrodes 332, 333, and 334 are provided on the n-type semiconductor layer 87 exposed by removing the p-type semiconductor layer 88. The n-ohmic electrodes 332 and 334 are electrodes (collector Cf and Cs electrodes) connected to the collectors Cs and Cf of the coupling transistor Q(1). The n-type semiconductor layer 87 between the p-ohmic electrode 322 and the n-ohmic electrodes 332 and 334 is removed (see FIG. 4(b)). The n-ohmic electrode 333 is an electrode (n-gate Gn electrode) connected to the n-gate Gn of the shift thyristor T(1).

[0073] Around the island 303, the p-type semiconductor layer 86, the n-type semiconductor layer 87, and the p-type semiconductor layer 88 are removed by etching. Furthermore, in the island 303, the p-type semiconductor layer 88 is removed by etching (see island 304 shown in FIG. 5(b)). Two n-ohmic electrodes 335, 336 are provided on the exposed n-type semiconductor layer 87. The n-type semiconductor layer 87 between the two n-ohmic electrodes 335, 336 is a current limiting resistor RL.

[0074] Around the island 304, the p-type semiconductor layer 86, the n-type semiconductor layer 87, and the p-type semiconductor layer 88 are removed by etching. Furthermore, in the island 304, the p-type semiconductor layer 88 is removed by etching. Three n-ohmic electrodes 337, 338, and 339 are provided on the exposed n-type semiconductor layer 87. The n-type semiconductor layer 87 between the n-ohmic electrodes 337 and 338 is a coupling resistance Rc, and the n-type semiconductor layer 87 between the n-ohmic electrodes 338 and 339 is a power line resistance Rg.

[0075] The island 305 is configured similarly to the island 304, and is provided with a start resistor Rs and a power line resistor Rg. The islands 306 and 307 are configured similarly to the island 303, and are provided with current limiting resistors R1 and R2.

[0076] An n-ohmic electrode 338 is provided on the exposed n-type semiconductor layer 85 of the island 300. On the back surface of the n-type semiconductor substrate 80, a substrate electrode 75 is provided.

[0077] Next, the connections will be described. In Fig. 5(a), the wiring used for the connections (power supply line 71, shift signal lines 72-1 and 72-2, and light emission potential line 74) are shown as straight lines. The p-ohmic electrode 321, which is the anode A electrode of the light-emitting control thyristor S(1) of the island 301, has a light-emitting potential V LD An n-ohmic electrode 331 which is the n-gate Gn electrode of the light-emission control thyristor S(1) of the island 301 is connected to an n-ohmic electrode 332 which is the collector Cs electrode of the coupling transistor Q(1) of the island 302. The n-ohmic electrode 332 is connected to an n-ohmic electrode 336 of a current limiting resistor RL provided in the island 303. An n-ohmic electrode 335 of the island 303 is connected to the light-emission potential line 74.

[0078] A p-ohmic electrode 322 which is an anode A electrode of the shift thyristor T(1) of the island 302 is connected to a shift signal line 72-1. The shift signal line 72-1 is connected to a φ1 terminal to which a shift signal p1 is supplied via a current limiting resistor R1 provided in the island 306. An n-ohmic electrode 333 which is an n-gate Gn electrode of the shift thyristor T(1) of the island 302 is connected to an n-ohmic electrode (without symbol) which is a connection point between the power supply line resistor Rg and the start resistor Rs provided in the island 305. An n-ohmic electrode 334 which is a collector Cf electrode of the coupling transistor Q(1) of the island 302 is connected to one n-ohmic electrode 337 of the coupling resistor Rc of the island 304.

[0079] The other n-ohmic electrode 338 of the coupling resistance Rc of the island 304 is connected to an n-ohmic electrode (no symbol) which is the n-gate Gn electrode of the shift thyristor T(2). The other n-ohmic electrode 339 of the power supply line resistance Rg of the island 304 is connected to the power supply line 71 to which the power supply potential VGK is supplied.

[0080] One n-ohmic electrode (no symbol) of the start resistance Rs of the island 305 is connected to the shift signal line 72-2. The other n-ohmic electrode (no symbol) of the power supply line resistance Rg of the island 305 is connected to the power supply line 71. The shift signal line 72-2 is connected to a φ2 terminal to which a shift signal p2 (φ2) is supplied via a current limiting resistance R2 provided in the island 307.

[0081] The shift signal line 72-1 is connected to the p-ohmic electrode which is the anode A electrode of the odd-numbered shift thyristors T, and the shift signal line 72-2 is connected to the p-ohmic electrode which is the anode A electrode of the even-numbered shift thyristors T.

[0082] The other shift thyristors T, coupling transistors Q, light-emission control thyristors S, and VCSELs are configured similarly to the shift thyristor T(1), coupling transistor Q(1), light-emission control thyristor S(1), and VCSEL(1).

[0083] The n-ohmic contact 338 of the exposed n-type semiconductor layer 85 of the island 300 is connected to a control potential V C V C The control potential V C is supplied to the n-type semiconductor layer 85, the tunnel junction layer 84, and the p-type semiconductor layer 83 via the n-ohmic electrode 338. Therefore, the p-type semiconductor layer 83 is referred to as the control potential layer 73. The control potential layer 73 may include the n-type semiconductor layer 85 and the tunnel junction layer 84, which have the same potential as the p-type semiconductor layer 83. A back electrode provided on the back surface of the n-type semiconductor substrate 80 is referred to as the substrate electrode 75. The substrate electrode 75 is connected to a substrate potential VK V K It is a terminal.

[0084] As shown in FIG. 5(b), the shift section 12, which is composed of the shift thyristor T, the coupling transistor Q, the power line resistance Rg, the coupling resistance Rc, the start resistance Rs, and the current limiting resistances RL, R1, and R2, is provided on the laminated semiconductor layer (n-type semiconductor layer 81, active layer 82, and p-type semiconductor layer 83) that constitutes the VCSEL. The laminated semiconductor layer (n-type semiconductor layer 81, active layer 82, and p-type semiconductor layer 83) below the shift section 12 does not function as a VCSEL. In other words, the laminated semiconductor layer (n-type semiconductor layer 81, active layer 82, and p-type semiconductor layer 83) that constitutes the VCSEL is not removed, and an n-type semiconductor layer 85, a p-type semiconductor layer 86, an n-type semiconductor layer 87, and a p-type semiconductor layer 88 are laminated thereon to constitute the shift section 12. This prevents the manufacturing process from becoming complicated. Here, the laminated semiconductor layer on which the shift section 12 is provided is referred to as a structure equivalent to a VCSEL (light-emitting element).

[0085] As described above, the light source 10 is a semiconductor component provided on one semiconductor substrate (n-type semiconductor substrate 80).

[0086] (Light emitting pulse waveform of light emitting device 1) The waveform of the light emission pulse (hereinafter referred to as the light emission pulse waveform) in the case of the light emitting device 1 having the shift section 12 and in the case of a light emitting device (not shown) not having the shift section 12 will be described. In the light emitting device 1 having the shift section 12, as described above, the control potential V C is set to the ground potential GND (0 V). A light emitting device not including the shift unit 12 includes only the light emission control thyristor S and the VCSEL connected in series in Fig. 3, Fig. 4(a) and Fig. 4(b), and the light emission control thyristor S connected to the VCSEL to be caused to emit light is controlled by an external signal.

[0087] Fig. 6 shows the emission pulse waveform of the VCSEL in the light emitting device 1. Figs. 6(a) and (b) show the emission pulse waveform of the VCSEL in the light emitting device 1 equipped with a shift section 12, and Fig. 6(c) shows the emission pulse waveform of the VCSEL in a light emitting device (not shown) that does not have a shift section. In Figs. 6(a), (b), and (c), the emission pulse waveform is shown on the left, and a schematic diagram of the emission pulse waveform is shown on the right. In the emission pulse waveform shown on the left, the horizontal axis is time with one division being 5 ns, and the vertical axis is light intensity (au).

[0088] The VCSEL light emission pulse waveform in the light emitting device not including the shift section shown in FIG. 6(c) has a constant rising and falling slope as shown in the schematic diagram on the right.

[0089] In contrast, the light emission pulse waveform shown in Fig. 6(a) has a changing slope in the falling portion, as shown in the schematic diagram on the right. In other words, the falling portion has two parts with different slopes. The part indicated by arrow δ has a gentler slope than the part indicated by arrow γ. Here, the part indicated by arrow δ is called a shoulder. If the falling portion of the light emission pulse waveform has a shoulder, the fall time will be longer than if there is no shoulder (as in Fig. 6(c)).

[0090] Moreover, as shown in the schematic diagram on the right side, the light emission pulse waveform shown in Fig. 6(b) has, in addition to a first peak indicated by an arrow ε, a second peak indicated by an arrow ζ at the falling portion of the first peak. In other words, when the light emission pulse waveform has a second peak at the falling portion, the falling time becomes longer compared to when there is no second peak (as in Fig. 6(c)).

[0091] Next, in the light-emitting device 1 having the shift section 12, the control potential V C This section explains why a shoulder or a second peak appears in the falling part of the light emission pulse waveform when the potential is set to the ground potential GND (0V). 7 shows an enlarged cross-sectional view of the light source 10 and an equivalent circuit of the portion shown in the enlarged cross-sectional view. FIG. 7(a) shows the enlarged cross-sectional view, and FIG. 7(b) shows the equivalent circuit of the portion shown in the enlarged cross-sectional view. In FIG. 7(a), in order to show the pn junction, an n-type semiconductor substrate 80 is shown as n, an n-type semiconductor layer 81 in the VCSEL in the light-emitting section 11 is shown as VCSEL n, a p-type semiconductor layer 83 in the VCSEL is shown as VCSEL p, and a light-emission control thyristor S is shown on the VCSEL. Note that the active layer 82 and the tunnel junction layer 84 are omitted.

[0092] In the shift section 12, the n-type semiconductor layer 81 is indicated as n, and the p-type semiconductor layer 83 is indicated as p. A shift thyristor T and a coupling transistor Q are indicated as the shift section 12 on the p-type semiconductor layer 83. Note that the active layer 82 and the tunnel junction layer 84 are omitted.

[0093] As shown in FIG. 5(a), the control potential V C V C The terminal is connected to an n-type semiconductor layer 85 that constitutes the shift thyristor T and the coupling transistor Q. However, as described above, the n-type semiconductor layer 85 is provided on the p-type semiconductor layer 83 via the tunnel junction layer 84. The tunnel junction layer 84 is provided so that the n-type semiconductor layer 85 and the p-type semiconductor layer 83 are not reverse biased. Therefore, the n-type semiconductor layer 85 and the p-type semiconductor layer 83 are at the same potential. Therefore, in FIG. 7(a), V C The terminal is described as being connected to the p-type semiconductor layer 83. As described above, the p-type semiconductor layer 83 is the control potential layer 73.

[0094] The drain of the NMOS transistor in the driver Drv2 is connected to a substrate electrode 75 provided on the back surface of the n-type semiconductor substrate 80. The source of the NMOS transistor is set to the ground potential GND (0 V). K is supplied.

[0095] When the driver Drv2 is on, the light emission potential V LD A current flows from the VCSEL to the driver Drv2 via the light emission control thyristor S. At this time, the substrate potential V K becomes, for example, about 2 V (expressed as up to 2 V) due to an internal resistance (resistance Rv shown in FIG. 7(b)) in the light-emitting unit 11.

[0096] In the shift unit 12, V C The terminal is set to the ground potential GND (0V). Therefore, the pn junction between the n-type semiconductor layer 81 (up to 2V) and the p-type semiconductor layer 83 (0V) in the shift section 12 is reverse biased. In other words, the pn junction between the n-type semiconductor layer 81 and the p-type semiconductor layer 83 constitutes a capacitance, which accumulates electric charge. The capacitance constituted by the pn junction between the n-type semiconductor layer 81 and the p-type semiconductor layer 83 in the shift section 12 is the capacitance section 13. V C Terminal control potential V C is the potential of the p-type semiconductor layer 83 constituting the capacitance. The n-type semiconductor layer 81 is provided on the n-type semiconductor substrate 80 and has the same potential as the n-type semiconductor substrate 80. The substrate electrode 75, which is the back electrode of the n-type semiconductor substrate 80, is connected to the substrate potential V K The n-type semiconductor substrate 80 and the n-type semiconductor layer 81 are connected to a substrate potential V K Therefore, the capacitance formed by the pn junction between the n-type semiconductor layer 81 and the p-type semiconductor layer 83 is connected to the control potential V C and the substrate potential V K A differential voltage between these is applied.

[0097] In the equivalent circuit shown in FIG. 7(b), the light-emitting unit 11 is represented by a parallel connection of the VCSEL, the light-emission control thyristor S, the internal resistance Rv, and the capacitance C1, which are connected in series. As shown in FIG. 3, the light-emitting unit 11 is configured by connecting a plurality of VCSELs and light-emission control thyristors S in parallel, which are connected in series. Therefore, the VCSELs and the light-emission control thyristors S connected in series other than the VCSEL (connected in series with the light-emission control thyristor S) to be emitted become the capacitance C1 connected in parallel to the VCSEL (connected in series with the light-emission control thyristor S) to be emitted. The internal resistance Rv is a resistance to the current flowing through the VCSEL and the light-emission control thyristor S connected in series. In other words, the internal resistance Rv is a resistance included inside the VCSEL and the light-emission control thyristor S, and is not a resistance provided externally. For example, the internal resistance Rv increases when the current passage portion α of the VCSEL becomes smaller (narrower). In addition, in divided irradiation, the internal resistance Rv increases when the number of irradiation sections 210 increases and the number of VCSELs to be simultaneously emitted decreases. In FIG. 7(b), the potential at the connection point between the VCSEL and the internal resistance Rv is the internal potential V R The capacitance C1 is an example of a first capacitance.

[0098] On the other hand, as described above, the capacitive section 13 is represented by a parallel connection of the capacitance C2 and the pn junction (indicated by a diode symbol in FIG. 7(b)) formed by the n-type semiconductor layer 81 and the p-type semiconductor layer 83. The capacitance C2 is an example of the second capacitance.

[0099] For the sake of simplicity, only the shift thyristor T is shown as the shift unit 12. The shift unit 12 is not related to the light emission pulse waveform. In the following, the description of the shift unit 12 will be omitted.

[0100] As shown in Fig. 7(a), the capacitance C2 of the capacitance section 13 is provided below the shift section 12. Therefore, when the area occupied by the shift section 12 in the light source 10 increases, the capacitance C2 increases. As can be seen from the layout diagram of Fig. 5(a), which is shown as an example, the area occupied by the shift section 12 is not small compared to that of the light-emitting section 11. In other words, the capacitance C2 of the shift section 12 is not small compared to the capacitance C1 of the light-emitting section 11, and affects the light emission pulse waveform.

[0101] The light source 10 is provided on one semiconductor substrate (n-type semiconductor substrate 80). That is, the light emitting unit 11 and the capacitance unit 13 are connected by the n-type semiconductor substrate 80 and the substrate electrode 75. The resistance between the light emitting unit 11 and the capacitance unit 13 is determined by the area of ​​the n-type semiconductor substrate 80 and the substrate electrode 75. The capacitance unit 13 may be provided separately from the light emitting unit 11. In this case, the light emitting unit 11 and the capacitance unit 13 are connected by wiring. That is, when the light emitting unit 11 and the capacitance unit 13 are provided on one semiconductor substrate (n-type semiconductor substrate 80), the resistance between the light emitting unit 11 and the capacitance unit 13 is reduced compared to the case where they are connected by wiring.

[0102] Next, the effect of the capacitance section 13 on the light emission pulse waveform will be described. 8 is a diagram for explaining the influence of the capacitance section 13 on the light emission pulse waveform in the light emitting device 1. FIG. 8(a) shows the case where the driver Drv2 is on, FIG. 8(b) shows the case where the driver Drv2 is shifted from on to off, FIG. 8(c) shows the case where the driver Drv2 is off, and FIG. 8(d) shows the case where the driver Drv2 is shifted from off to on. Here, the light emission potential V LD is set to 7V. And the control potential V C is fixed to the ground potential GND (0V). In Fig. 8 (a), (b), (c), and (d), the on state of the driver Drv2 is represented as ON, and the off state as OFF. The same applies below. The path of the light emission current is indicated by a dashed line.

[0103] When the driver Drv2 is on, the light-emission control thyristor S is on and the VCSEL emits light.LD (7V) is supplied to V LD A light-emitting current flows from the terminal to GND via the light-emitting control thyristor S, the VCSEL, the internal resistor Rv, and the driver Drv2. Here, the forward voltage Vd is set to 1.5 V. Therefore, the voltage applied to the light-emitting control thyristor S in the on state is 1.5 V, and the voltage applied to the VCSEL that is emitting light is also 1.5 V. Therefore, the internal potential V R In other words, 3V is applied to the series connection of the light emission control thyristor S and the VCSEL. At this time, the substrate potential V K is 2 V. 2 V is applied to the internal resistor Rv.

[0104] As shown in FIG. 8B, when the driver Drv2 is switched from on to off, the light emission current flowing through the series-connected light emission control thyristor S, VCSEL, and internal resistance Rv drops with a time constant (C1+C2)×Rv determined by the parallel capacitance of the capacitance C1 and capacitance C2, and the internal resistance Rv. Then, the substrate potential V K increases from 2V to 4V. The substrate potential V K During the period in which the voltage rises from 2 V to 4 V, 3 V is applied to the series connection of the light-emission control thyristor S and the VCSEL, so that the light-emission control thyristor S is in the ON state and the VCSEL continues to emit light.

[0105] As shown in FIG. 8(c), when the driver Drv2 is off, the substrate potential V K When the substrate potential V K At this time, the internal potential V R is the substrate potential V K It will be the same 4V.

[0106] As shown in FIG. 8(d), when the driver Drv2 is switched from off to on, the light-emitting current rises with a time constant determined by the parallel capacitance of the capacitors C1 and C2 and the on-resistance of the driver Drv2. The on-resistance of the driver Drv2 is smaller than the internal resistance Rv. Therefore, the light-emitting current rises in a shorter time than the fall (rises faster). Then, the state transitions to FIG. 8(a).

[0107] As described above, in the light emitting device 1, the control potential V C is set to the ground potential GND (0V), when the driver Drv2 is switched from on to off, the light-emitting current falls with a time constant (C1+C2)×Rv determined by the parallel capacitance of the capacitances C1 and C2 and the internal resistance Rv. As described above, the capacitance C2 is not smaller than the capacitance C1. In other words, the light-emitting current flows with the capacitances C1 and C2 connected in parallel (referred to as the parallel connection state), so a shoulder or a second peak occurs at the fall, and the fall characteristics are deteriorated.

[0108] Fig. 9 is a diagram for explaining the operation of the light emitting device 1 to which the first embodiment is applied. Fig. 9(a) shows the case where the driver Drv2 is on, Fig. 9(b) shows the case where the driver Drv2 is shifted from on to off, Fig. 9(c) shows the case where the driver Drv2 is off, and Fig. 9(d) shows the case where the driver Drv2 is shifted from off to on. Here, the description will be given assuming that the capacitance C1 is 100 pF and the capacitance C2 is 200 pF. In Figs. 9(a), (b), and (d), the light emitting current is indicated by a dashed line, and the displacement current is indicated by a solid line.

[0109] In the first embodiment, the control potential V C are controlled to different potentials in response to the on and off states of the driver Drv2. As shown in FIG. 9(a), when the driver Drv2 is on, the control potential V C is set to the ground potential GND (0V). This state is the same as the state shown in FIG. 8(a). In other words, the light emission control thyristor S is in the ON state, and the VCSEL emits light. The light emission potential V LD (7V) is supplied to VLD A light-emitting current flows from the terminal through the light-emitting control thyristor S, the VCSEL, the internal resistor Rv, and the driver Drv2 to GND. The internal potential V R is 4V, and the substrate potential V K is 2V. Therefore, 5V (=7V-2V) is applied to the 100pF capacitance C1, and a charge of 500pC is stored. 2V (=2V-0V) is applied to the 200pF capacitance C2, and a charge of 400pC is stored.

[0110] As shown in FIG. 9(b), when the driver Drv2 is switched from ON to OFF, the control potential V C V goes from 0V to 3.3V. C The terminal suddenly transitions from ground potential GND (0V) to 3.3V, and V C Terminal to V LD A displacement current corresponding to a potential difference of 3.3 V flows toward the terminal. As a result, the charge of the 100 pF capacitance C1 changes from 500 pC to 280 pC, and the charge of the 200 pF capacitance C2 changes from 400 pC to 180 pC, and the substrate potential V K is pulled up towards 4.2V. Similarly, the internal potential V R The internal voltage V R When the internal potential V exceeds 4V, the VCSEL turns off. R exceeds 4V, the voltage applied to the series connection of the light-emission control thyristor S and the VCSEL becomes less than 3V. As a result, the light-emission control thyristor S cannot maintain the on state and turns off, forcibly cutting off the light-emission current flowing through the VCSEL. As a result, the fall time of the light-emission pulse is delayed by the control potential V C The control potential V is shortened (the fall becomes faster) compared to when the control potential V is not changed from 0V to 3.3V. In other words, the effect of the capacitance C2 on the light emission pulse waveform is suppressed. Note that the displacement current flows when the capacitances C1 and C2 are connected in series (series connection state). C The timing when the control potential V CThe transition from 0V to 3.3V may be after the driver Drv2 is turned off, as long as the fall time can be shortened.

[0111] In the state shown in FIG. 9(c) in which the driver Drv2 is off and no light emission current flows, the control potential V C is maintained at 3.3 V. Then, the capacitance C1 maintains a state in which a charge of 280 pC is stored, and the capacitance C2 maintains a state in which a charge of 180 pC is stored. Then, the internal potential V R maintains 4.2V.

[0112] As shown in FIG. 9(d), when the driver Drv2 transitions from off to on, the control potential V C Set V from 3.3V to 0V. C The terminal suddenly transitions from 3.3V to 0V. This causes the V LD Terminal to V C A displacement current corresponding to a potential difference of 3.3 V flows toward the terminals, charging the capacitances C1 and C2. Then, the substrate potential V K is suddenly lowered from 4.2V. At this time, the driver Drv2 that has been turned on also charges the capacitors C1 and C2. That is, the capacitor C1 is charged from 280pC to 500pC, and the capacitor C2 is charged from 180pC to 400pC. Then, the substrate potential V K When the control voltage V is reduced to 4V or less, the light-emission control thyristor S turns on, current starts to flow through the light-emission control thyristor S and the VCSEL connected in series, and the VCSEL starts emitting light. C The displacement current caused by shifting the control potential V from 3.3 V to 0 V assists in charging the capacitances C1 and C2, shortening the delay time until the VCSEL starts emitting light. In other words, the rise time of the light emission pulse is C In this case, the time required for the control voltage V to be applied is shortened (the rise time is faster) compared to when the control voltage V is not changed from 0V to 3.3V. In other words, the effect of the capacitance C2 on the light emission pulse waveform is suppressed. In this case, too, the displacement current flows in a state in which the capacitances C1 and C2 are connected in series (referred to as a series connection state). CThe timing when the control potential V C The transition from 3.3V to 0V may be after the driver Drv2 is turned on, as long as the rise time can be shortened.

[0113] Returning to FIG. 9(a), the capacitors C1 and C2 are charged by the driver Drv2, and the substrate potential V K When the voltage reaches 2V, the light emission current reaches a steady value.

[0114] Figure 10 shows the control potential V C 10A and 10B are diagrams for explaining a generalized control for making the potentials of the driver Drv2 different. Fig. 10A shows the case where the driver Drv2 is on, and Fig. 10B shows the case where the driver Drv2 is shifted from on to off. Note that the light emission current is indicated by a dashed line, and the displacement current is indicated by a solid line. Also, the "+" added to the capacitances C1 and C2 means that the charge is positive when a positive charge is accumulated.

[0115] A case where the driver Drv2 in FIG. 10(a) is on will be described. In this case, the light emission control thyristor S is turned on and the VCSEL emits light. Therefore, V LD The light-emitting current flows from the terminal to GND. Here, the substrate potential V K is the V on At this time, the control potential V C is the potential V L Then, the amount of charge Q1 stored in the capacitance C1 and the amount of charge Q2 stored in the capacitance C2 are as shown in Equation 1. In the following, the capacitance value of the capacitance C1 is denoted as C1, and the capacitance value of the capacitance C2 is denoted as C2.

[0116]

number

[0117] Next, a case where the driver Drv2 in FIG. 10B is switched from on to off will be described. When the driver Drv2 is switched from on to off, the control potential V C potential V L to potential V H The potential V H is the potential V L This is the case when an n-type semiconductor substrate 80 is used, and when a p-type semiconductor substrate is used, the polarity is reversed. That is, the potential V H is the potential V L It is a potential that is greater in absolute value.

[0118] The driver Drv2 is switched from on to off, and the control potential V C potential V L to potential V H When the control potential V C potential difference (V H -V L ) flows through the capacitances C1 and C2 in series. Then, as shown in Equation 2, the substrate potential V K is the substrate potential V K ', the charge Q1 of the capacitance C1 becomes charge Q1', and the charge Q2 of the capacitance C2 becomes charge Q2'. Then, from equations 1 and 2, the substrate potential V K ' is expressed as in Equation 3. Note that the charge Q D is the amount of charge transferred by the displacement current.

[0119]

number

[0120]

number

[0121] The voltage applied to the series connection of the light emission control thyristor S and the VCSEL (light emission potential V LD -Substrate potential V KWhen the forward voltage Vd of each thyristor becomes less than the sum (3 V) of their respective forward voltages Vd (for example, 1.5 V), the light-emission control thyristor S turns off, the light-emission current is cut off, and the light emission stops (goes out).

[0122] Substrate potential V K If the substrate potential V′ is increased, the light-emission control thyristor S is quickly turned off and the light emission is easily stopped. K To increase the capacitance, C2 must be increased or the control voltage V C The potential V H Although the capacitance C2 is described as being formed of a pn junction formed in the lower part of the shift section 12, in order to increase the capacitance C2, an external capacitance may be added in parallel with the capacitance C2.

[0123] Figure 11 shows the relationship between the ratio of capacitance C2 to capacitance C1 and the substrate potential V K FIG. 11(a) is a diagram illustrating the relationship between the substrate potential V K (V on ) is 2V, Fig. 11(b) shows the substrate potential V K (V on 11(a) and (b), the horizontal axis represents the capacitance ratio C2 / C1, and the vertical axis represents the substrate potential V K '(V). Note that the control potential V C potential V L The ground potential GND (0V) and the potential V H is set to 3.3V.

[0124] The substrate potential V K (V on ) is 2V, the substrate potential V K ' is the V when the capacitance C2 is 0 on From (2V), as the capacitance ratio C2 / C1 increases, V on +V H -V L(5.3V). And when the capacitance ratio C2 / C1 is 2, the substrate potential V K At this time, the voltage V ′ applied to the light emission control thyristor S and the VCSEL connected in series is LD -V K The substrate potential V′ becomes 2.8 V, and the VCSEL stops emitting light (goes quenched). K If the voltage is set to 4V or higher, the VCSEL will stop emitting light (be quenched).

[0125] The substrate potential V K (V on ) is 1V, the substrate potential V K ' is the V when the capacitance C2 is 0 on (From 1V, as the capacitance ratio C2 / C1 increases, V on +V H -V L (4.3V). However, even if the capacitance ratio C2 / C1 is 10, the substrate potential V K ' does not reach 4V. If the capacitance ratio C2 / C1 is 10, the control voltage V C The potential V to be set as H It is required that the supply voltage be higher than 3.3V.

[0126] As described above, when the driver Drv2 is off, the substrate potential V K The larger the control potential V', the quicker the light-emitting control thyristor S turns off and the easier it is to stop the light emission. C The potential V H However, if the capacitance C2 is made too large, it takes time to charge and discharge. Therefore, as shown in FIG. 11(a), when the driver Drv2 is on, the substrate potential V K (V on ) and the substrate potential V when the driver Drv2 is off. KIt is preferable to select a capacitance C2 having a large difference from the substrate potential V K It is preferable that the capacitance ratio C2 / C1 is 1 or more (1 time or more), at which a large change in capacitance C2' is observed. Compared to when the capacitance ratio C2 / C1 is less than 1, it is easier to set the voltage to turn the VCSEL off. Furthermore, it is even more preferable that the capacitance ratio C2 / C1 is 4 or less (4 times or less), so that the capacitance C2 does not become too large. Compared to when the capacitance ratio C2 / C1 exceeds 4, the charging and discharging times are shortened.

[0127] Here, the control potential V C potential V L and potential V H The internal resistance Rd (resistance value Rd) (not shown) of the driver Drv1 (see FIG. 1) that controls the V C The time constant Rd×C1C2 / (C1+C2) of the current flowing in series from the terminal through the capacitances C1 and C2 is set to be smaller than the time constant Rv×(C1+C2) when the light-emitting current flows in parallel through the capacitances C1 and C2 (see FIG. 8(b)). C The displacement current caused by controlling the substrate potential V flows more quickly than when the light emission current flows in parallel through the capacitances C1 and C2 and falls (as in FIG. 8(b)). K However, the substrate potential V K This shortens the fall time of the light emission pulse (makes the fall faster).

[0128]

number

[0129] Here, when the driver Drv2 is turned on, the control potential V C potential V L (For example, 0V) and turn off the driver Drv2 with the control potential V C potential V H (For example, 3.3 V) was set. L, V H It is preferable that the potential V is a potential that does not forward bias the pn junction of the capacitance section 13. If the pn junction of the capacitance section 13 is forward biased, a current will flow and power consumption will increase. H is the potential V L The potential V is greater in absolute value than the potential V H is the potential V L If the absolute value of the potential is smaller than that of the substrate potential V K decreases, and the fall time of the light emission pulse becomes longer instead.

[0130] (Light emitting device 2 as a comparative example) In the light emitting device 1 to which the first embodiment is applied, the driver element of the driver Drv2 is an NMOS. C If the capacitance C1 is fixed to the ground potential GND (0V), when the driver Drv2 is turned off, the light-emitting current flows in parallel through the capacitances C1 and C2. This causes the time constant of the fall of the light-emitting current to become large. Therefore, it is possible to use a driver Drv2' in which the driver element of the driver Drv2 is replaced with a complementary type (CMOS configuration) driver element that combines an NMOS transistor and a PMOS transistor. In other words, even when the NMOS transistor is off, the substrate potential V K Make it possible to raise the

[0131] 12 is an equivalent circuit diagram of the light emitting device 2 shown for comparison. The light emitting device 2 does not include the driver Drv1 in the control unit 50 of the light emitting device 1 shown in FIG. C The driver Drv2′ includes a driver Drv2′ in which the NMOS transistor, which is the driver element of the driver Drv2 in the driving section 60 of the light emitting device 1 shown in FIG. 3, is replaced with a CMOS transistor. The source of the NMOS transistor of the driver Drv2′ is grounded, and the drain of the PMOS transistor is connected to the light emitting potential V LDThe drain of the NMOS transistor and the drain of the PMOS transistor are connected to each other, and the substrate potential V K Supplying V K The gate of the NMOS transistor and the gate of the PMOS transistor are connected together to supply the light emission signal pI. When the light emission signal pI is “L” (0V), the NMOS transistor is OFF and the PMOS transistor is ON, and the connection point between the drain of the NMOS transistor and the drain of the PMOS transistor is at the light emission potential V LD On the other hand, when the light emitting signal pI is "H" (5V), the NMOS transistor is ON, the PMOS transistor is OFF, and the connection point between the drain of the NMOS transistor and the drain of the PMOS transistor is at the ground potential GND (0V). The other configurations are the same as those of the light emitting device 1.

[0132] Fig. 13 is a diagram for explaining a case where the driver Drv2' is shifted from on to off in the light emitting device 2 for comparison. Fig. 13 corresponds to Fig. 10(b). In Fig. 13, the light emission current is indicated by a dashed line.

[0133] As mentioned above, the source of the PMOS transistor of the driver Drv2′ is V LD When the light emission signal pI changes from "H" (5V) to "L" (0V), the NMOS transistor of the driver Drv2' turns off and the PMOS transistor turns on. Then, a current flows in parallel to the capacitors C1 and C2 via the PMOS transistor. This causes the substrate potential V K is the light emission potential V LD Therefore, the light emission pulse falls quickly. In other words, by configuring the driver Drv2' with a CMOS, the fall time of the light emission pulse is shortened (the fall becomes faster).

[0134] At this time, the amount of charge Q C Then, the charge Q CAs shown in equation 5, charges move in parallel to the capacitances C1 and C2. The power E consumed by this charge transfer is shown in equation 6. Note that C is (C1+C2) and V is (V LD -V on ).

[0135]

number

[0136]

number

[0137] Here, V LD 7V, V on If the voltage is 2V, C1 is 200pF, C2 is 120pF, the pulse width of the light pulse is 5ns, and the duty is 5%, power is consumed twice in 100ns. Therefore, the consumed power E is (200pF+100pF)×(7V-2V) 2 / 2×2 / 100ns, which is 0.08W. On the other hand, if the light emission current is 1A, the power consumed for light emission is calculated as 7V×1A×5%, which is 0.35W. In other words, the power E consumed for charging and discharging the capacitances C1 and C2 is large, at more than 20% of the power consumed for light emission. This is because current flows in parallel through the capacitances C1 and C2. In other words, the parallel capacitance of the capacitances C1 and C2 is C1+C2, which in the above case is 320pF.

[0138] On the other hand, the control potential V C In the first embodiment, in which the capacitances C1 and C2 are controlled to different potentials, as shown in FIG. 9B, the capacitance C1 and the capacitance C2 appear to be in series. Therefore, the series capacitance is C1C2 / (C1+C2), which is 75 pF in the above case. Therefore, the power P consumed by charging and discharging the capacitances C1 and C2 in the first embodiment is 75 pF×(3.3 V). 2 / 2×2 / 100ns, which is 0.00817W. That is, the control potential V CThe power P consumed by charging and discharging in the first embodiment in which the driver Drv2' is controlled to different values ​​is about 1 / 10 of the power E consumed by charging and discharging when the driver Drv2' is configured with a CMOS.

[0139] If the driver Drv2' is configured as a CMOS, the control voltage V C In addition, the driver Drv1 (see FIG. 3) that controls the substrate potential V K is the light emission potential V LD However, the substrate potential V K is the light emission potential V LD When the voltage is raised to 1 V, the light-emitting section 11 becomes reverse-biased, and the charge accumulated in the light-emission control thyristor S and the VCSEL becomes difficult to escape. This may cause the memory effect to continue. Therefore, if the driver Drv2' is configured as a CMOS, an erasing means for erasing the memory effect is required.

[0140] On the other hand, the control potential V C In the first embodiment, in which the capacitances C1 and C2 are controlled to different potentials, the power consumed for charging and discharging the capacitances C1 and C2 is suppressed, and the control potential V C This makes it possible to eliminate the memory effect.

[0141] (Measurement Flowchart to which the First Embodiment is Applied) Next, a measurement flowchart to which the first embodiment is applied will be described. FIG. 14 is a measurement flowchart to which the first embodiment is applied. FIG. 14(a) is a flowchart, and FIG. 14(b) is a measurement flowchart to which the control potential V C 14A is a diagram for explaining the control of the shift unit 12. In Fig. 14A, ON of the shift unit 12 is represented as ON, and OFF of the shift unit 12 is represented as OFF. The same applies below.

[0142] First, the control potential V C The control of the control potential V Cis controlled in response to the change in the light emission signal pI, that is, the light emission pulse. In other words, when the light emission signal pI transitions from "L" (0V) to "H" (5V), the control potential V C potential V H (e.g., 3.3V) to potential V L (for example, 0 V). As a result, as shown in FIG. 9(d), a displacement current flows in series through the capacitances C1 and C2, and the substrate potential V K The control potential V C potential V L (e.g., 0V) to potential V H (e.g., 3.3 V). As a result, as shown in FIG. 9(b), a displacement current flows in series through the capacitances C2 and C1, and the substrate potential V K In this way, the rise and fall of the light emission pulse and the control potential V C By making the timing of control to be different correspond to the timing of the control, the potential can be easily set.

[0143] As mentioned above, the control potential V C potential V H (e.g., 3.3V) to potential V L The timing of the transition to the control potential V (for example, 0 V) ​​does not have to be when the light emission signal pI transitions from "L" (0 V) to "H" (5 V), but may be after the light emission signal pI transitions from "L" (0 V) to "H" (5 V). C potential V L (e.g., 0V) to potential V H The timing of the transition to the control potential V (for example, 3.3 V) does not have to be when the light emission signal pI transitions from "H" (5 V) to "L" (0 V), but may be after the light emission signal pI transitions from "H" (5 V) to "L" (0 V). In other words, as shown by the dashed line in FIG. 14(b), C The change in may occur later than the change in the luminescence signal pI.

[0144] 14(a), an operation of the light emitting device 1 to which the first embodiment is applied will be described. There are a number of flows for operating the light emitting device 1. First, the flow on the left side will be described. In step 10 (denoted as S10 in FIG. 14(a), and the same applies to other steps), the control unit 50 turns on the shift unit 12. That is, the light emitting device 1 is set to the above-mentioned initial state. At this time, the control potential V C Set to ground potential GND (0V) (V L =0V). In step 11, the control unit 50 operates the shift unit 12 to select the VCSEL to emit light.

[0145] In step 12, the driving unit 60 causes the selected VCSEL to emit light. At this time, the control unit 50 controls the control potential V C is set to 0 V. This light emission causes the memory effect. Note that this light emission is not used for measurement, so it is referred to as a pre-light emission.

[0146] In step 13, the control unit 50 turns off the shift unit 12. As described above, for example, the shift signals p1 and p2 are set to “L” (0 V). This prevents current from flowing through the shift thyristor T and the coupling transistor Q, thereby reducing the power consumption of the shift unit 12.

[0147] In step 14, the driving unit 60 turns the driver Drv2 on and off to continuously generate a plurality of light emission pulses from the VCSEL (continuous light emission pulses). The light reflected from the object to be measured in response to each light emission pulse is received by the 3D sensor 5 (see FIG. 1), and an electric charge corresponding to each light emission pulse is accumulated in a capacitance (capacitor) within the 3D sensor 5. The distance to the object to be measured is measured from the electric charge accumulated by the continuous light emission pulses. At this time, as shown in FIG. 14(b), the control unit 50 controls the control potential V C The period during which a plurality of light emitting pulses are generated in succession is defined as the light emitting period. In other words, the control unit 50 controls the control potential V Cis set to the ground potential GND (0V), and at a certain point during light emission, the control potential V C V is the same as the shift period (when selected). L (ground potential GND (0V)), and during other times when light is emitted, a potential V different from the shift period (selection time) is set. H Set it to (3.3V).

[0148] It is not necessary to perform step 13. In other words, the control unit 50 does not need to turn off the shift unit 12. Even if the shift signal p1 or the shift signal p2 is maintained at “H” (5 V), the VCSEL generates continuous light emission pulses due to the memory effect.

[0149] In step 15, the control unit 50 determines whether or not to cause the next VCSEL to emit light. If it is determined that the next VCSEL is to emit light (Yes), the process returns to step 10, the light emitting device 1 is initialized, and the shift unit 12 is turned ON. Thereafter, measurements are performed according to the flow described above. Once the shift unit 12 is turned OFF, the information on the VCSEL selected before it was turned OFF is lost. Therefore, when the next VCSEL is to emit light, the light emitting device 1 is initialized, and the shift operation is restarted from the shift thyristor T(1), and the next VCSEL to be emitted is selected.

[0150] If it is determined in step 15 that the next VCSEL is not to emit light (No), the measurement in step 16 ends.

[0151] Next, the flow on the right side will be described. Although steps 17 and 19 are described separately, they are consecutive steps. As in step 14, the driving unit 60 turns the driver Drv2 on and off to generate continuous light emission pulses from the VCSEL and measure the distance to the object to be measured. At this time, as shown in FIG. 14(b), the control unit 50 controls the control potential V C Even in this case, once the VCSEL emits light, a memory effect occurs. Therefore, the VCSEL generates continuous light emission pulses.

[0152] Then, in step 18, the control unit 50 executes steps 17 After the VCSEL emits light in step 17, the shift unit 12 is promptly turned off. If the VCSEL emits light in step 17, a memory effect occurs, so it is preferable to turn off the shift unit 12 promptly after the VCSEL emits light in step 17. Then, the above-mentioned steps 15 and onwards are executed.

[0153] When multiple light emission pulses are generated in succession, the first light pulse may have a different light emission pulse waveform from the other light emission pulses, such as a lower peak, compared to the subsequent light pulses. In such a case, it is preferable to use the first light emission pulse as a preliminary light emission and not use it for measurement, as in step 12. If the first light emission pulse waveform is the same or has only a small difference from the other light emission pulse waveforms, the first light emission pulse may be used for measurement, as in step 17.

[0154] [Second embodiment] In the first embodiment, the control unit 50 controls the control potential V C at different potentials (potential V L and potential V H ) In the second embodiment, the control unit 50 does not set one of the potentials to a specific potential, but sets it to a floating state. The floating state may be called a float or floating. Here, the potential in the floating state is expressed as "Hi-Z".

[0155] 15 is an equivalent circuit diagram of the light emitting device 3 to which the second embodiment is applied. The light emitting device 3 includes a driver Drv1' instead of the driver Drv1 in the control unit 50 of the light emitting device 1 shown in FIG. The driver Drv1' uses, for example, an NMOS transistor as a driver element. The other configurations are the same as those of the light emitting device 1.

[0156] The source of the NMOS transistor of the driver Drv1′ is grounded, and the drain is connected to the control potential V C The terminal VC The gate of the driver Drv1′ is supplied with a control signal pc that goes between “H” (5V) and “L” (0V). When the control signal pc is “H” (5V), the driver Drv1′ is turned ON and the control potential V C becomes the ground potential GND (0V) and when the control signal pc is "L" (0V), the driver Drv1' turns OFF and the control potential V C becomes floating (Hi-Z).

[0157] 16 is a diagram for explaining the operation of the light emitting device 3 to which the second embodiment is applied. FIG. 16(a) shows the case where the driver Drv2 is on, FIG. 16(b) shows the case where the driver Drv2 is shifted from on to off, FIG. 16(c) shows the case where the driver Drv2 is off, and FIG. 16(d) shows the case where the driver Drv2 is shifted from off to on. Here, the light emitting potential V LD is 7 V. The light emission current path is shown by a dashed line.

[0158] The case where the driver Drv2 is on, as shown in FIG. 16(a), is immediately after the shift unit 12 is operated to select the VCSEL that has emitted light. For this reason, the control potential V C is at ground potential GND (0V), which is the same as in Figure 8(a).

[0159] As shown in FIG. 16(b), when the driver Drv2 is switched from ON to OFF, the control potential V C is set from 0V to a floating potential (Hi-Z). Then, the light emission current flowing through the series-connected light emission control thyristor S, VCSEL, and internal resistance Rv is prevented from flowing to the capacitance C2, and flows toward the capacitance C1. In other words, the light emission current falls with a time constant C1×Rv determined by the capacitance C1 and the internal resistance Rv. This time constant is the control potential V C is smaller than the time constant (C1+C2)×Rv when the control potential V is set to the ground potential GND (0V). C When set to floating potential (Hi-Z), the control potential V CIn comparison with the case where the potential of the light emitting pulse is set to the ground potential GND (0 V), the fall time of the light emitting pulse is shortened (fall becomes faster).

[0160] As shown in FIG. 16(c), when the driver Drv2 is off, the substrate potential V K When the control potential V reaches 4V, the light emission control thyristor S transitions from the on state to the off state, and the VCSEL stops emitting light (becomes quenched). This state is the same as in FIG. 8(c), but when the control potential V C is maintained at a floating potential (Hi-Z).

[0161] As shown in FIG. 16(d), the driver Drv2 is switched from off to on. At this time, the control potential V C is maintained at a floating potential (Hi-Z). Then, the light-emitting current rises with a time constant determined by the capacitance C1 and the on-resistance of the driver Drv2. The on-resistance of the driver Drv2 is smaller than the internal resistance Rv. Therefore, the light-emitting current rises faster than it falls. After this, we return to FIG. 16(b). In other words, while the VCSEL is generating multiple consecutive light emission pulses, the control potential V C is set to floating potential (Hi-Z).

[0162] As described above, when the driver Drv2 is switched from on to off, the control potential V C By shifting from the ground potential GND (0V) to the floating potential (Hi-Z), the fall time of the light-emitting current is shortened (the fall becomes faster). In other words, the effect of the capacitance C2 on the light-emitting pulse waveform is suppressed.

[0163] 17 shows the waveform of a light emission pulse of the VCSEL in the light emitting device 3. FIG. 17(a) shows the waveform of a light emission pulse of the VCSEL when the driver Drv2 is turned off by changing the control potential V C When the control potential V C is set to a floating potential (Hi-Z). As in Fig. 6(a), (b), and (c), the horizontal axis represents time with one division being 5 ns, and the vertical axis represents light intensity (au).

[0164] As shown in FIG. 17(a), the control potential V C When the control potential V is set to the ground potential GND (0V), a shoulder is observed at the falling edge of the light emission pulse (indicated by the arrow δ) as in FIG. 6(a). On the other hand, when the control potential V C When the control potential V is set to a floating potential (Hi-Z), no shoulder is observed at the falling edge of the light emission pulse. C By setting to a floating potential (Hi-Z), the fall time of the light emission pulse is shortened (the fall becomes faster).

[0165] (Measurement Flowchart to which the Second Embodiment is Applied) Next, a measurement flowchart to which the second embodiment is applied will be described. FIG. 18 is a measurement flowchart to which the second embodiment is applied.

[0166] There are multiple flows for operating the light emitting device 3. The flow on the left side will be explained. In step 20, the control unit 50 turns on the shift unit 12. That is, the light emitting device 1 is set to the initial state described above. At this time, the control potential V C Set the voltage to ground potential GND (0V) (V L =0V). In step 21, the control unit 50 operates the shift unit 12 to select the VCSEL to emit light. Steps 20 and 21 are the same as steps 10 and 11 in FIG. 14(a).

[0167] In step 22, the driver 60 causes the selected VCSEL to emit light. At this time, the control potential V C is 0 V. This light emission causes the memory effect. This light emission is not used for measurement, so it is referred to as a pre-light emission. Step 22 is the same as step 12 in FIG. 14(a).

[0168] In step 23, the control unit 50 turns off the shift unit 12. As described above, for example, the shift signals p1 and p2 are set to “L” (0 V). This prevents current from flowing through the shift thyristor T and the coupling transistor Q, thereby reducing the power consumption of the shift unit 12.

[0169] In step 24, the driving unit 60 turns the driver Drv2 on and off to continuously generate a plurality of light emission pulses from the VCSEL (continuous light emission pulses). The light reflected from the object to be measured during each light emission pulse is received by the 3D sensor 5 (see FIG. 1), and an electric charge corresponding to each light emission pulse is accumulated in a capacitance (capacitor) within the 3D sensor 5. The distance to the object to be measured is measured from the electric charge accumulated by the continuous light emission pulses. At this time, the control unit 50 controls the control potential V C to a floating potential (Hi-Z). The timing for setting the potential to the floating potential (Hi-Z) may be any timing as long as it is before the end of the first VCSEL emission in step 24. The period during which a plurality of emission pulses are generated in succession is defined as the emission time. In other words, the control unit 50 sets the control potential V C is set to the ground potential GND (0V), and when emitting light, the control potential V C is set to a potential (here, floating potential (Hi-Z)) different from that during the period (selection).

[0170] In step 25, the control unit 50 determines whether or not to cause the next VCSEL to emit light. Step 25 and subsequent steps are similar to those in step 15 and subsequent steps in FIG.

[0171] Next, the flow on the right side will be described. Although steps 27 and 29 are described separately, they are consecutive steps. As in step 24, the driving unit 60 turns the driver Drv2 on and off to generate continuous light emission pulses from the VCSEL and measure the distance to the object. At this time, the control unit 50 controls the control potential V Cis set to a floating potential (Hi-Z). Once the VCSEL emits light, a memory effect occurs. Therefore, the VCSEL generates continuous light emission pulses. The timing for setting the potential to the floating potential (Hi-Z) may be any time before the first VCSEL emission in step 27 ends.

[0172] Then, in step 28, the control unit 50 turns off the shift unit 12 promptly after the VCSEL emits light in step 27. Once the VCSEL emits light in step 27, a memory effect occurs. Therefore, it is preferable to turn off the shift unit 12 promptly after the VCSEL emits light in step 27.

[0173] Thereafter, the above-mentioned step 25 and subsequent steps are executed.

[0174] Here, the control potential V C However, the control potential V C The control potential V does not necessarily have to be a floating potential (Hi-Z). C is a potential that suppresses the light emission current from flowing when the capacitance C1 and the capacitance C2 are connected in parallel (parallel connection state) at the time of the falling edge of the light emission pulse. For example, the control potential V C may be a potential that forward-biases the pn junction (the pn junction formed by the n-type semiconductor layer 81 and the p-type semiconductor layer 83) that constitutes the capacitance C2 of the capacitance section 13.

[0175] In the first and second embodiments, the light-emitting element is a VCSEL, and one light-emission control thyristor S and a VCSEL are connected in series to one shift unit 12a. However, a plurality of light-emission control thyristors S and VCSELs connected in series may be connected to one shift unit 12a. Also, a plurality of VCSELs may be provided to one light-emission control thyristor S. A plurality of VCSELs are simultaneously selected by one shift unit 12a and emit light in parallel. In this way, the amount of light irradiated to the irradiation section 210 in divided irradiation is increased.

[0176] 3 and 5(a), the light emitting elements (VCSELs) in the light source 10 are illustrated as being arranged one-dimensionally, but the light emitting elements may be arranged two-dimensionally. For example, by arranging the light emitting elements two-dimensionally in the light source 10, the light emitting elements can be made to emit light corresponding to the two-dimensionally arranged irradiation sections 210.

[0177] In addition, in the first and second embodiments, a selection unit is used to select the light-emitting element (VCSEL) that causes the shift unit 12 to emit light. However, the selection unit may be configured to send a signal directly from the driver to the thyristor of the light-emitting element, rather than being a shift unit that performs a shift operation.

[0178] Although the light source 10 described above is a common cathode, it may be a common anode. In this case, an n-ohmic electrode is provided on the n-gate layer (n-type semiconductor layer 87), but a p-ohmic electrode may be provided on the p-gate layer (p-type semiconductor layer 86). Furthermore, in the shift section 12 of the light source 10, the shift thyristors T are connected by the coupling transistor Q, but may be connected by a diode or a resistor.

[0179] In addition, in the first and second embodiments, the light emitting unit and the capacitance unit are provided on a single semiconductor substrate, but the capacitance unit provided on a different substrate may be connected to the light emitting unit by wiring, or the light emitting unit may be configured so as not to have a shared layer even on the same substrate.

[0180] In the first embodiment, the control potential V Cis controlled to different potentials in response to the on and off of the driver Drv2, but the potential may be switched during the course of the light emission even if it is not necessarily switched at the first light emission, for example, when light emission is performed multiple times. Specifically, both 0V and 3.3V may be present at the time of light emission. However, even in this case, the potential is set to 0V at the time of selection. In other words, the capacitance section is composed of a selection section that selects the light-emitting element to be emitted, and when the selection section sets the potential to a different potential from that at the time of selection when the light-emitting element to be emitted is selected in the light-emitting section at the time of light emission to cause the selected light-emitting element to emit, the potential may be set to the same potential as that at the time of selection for a certain period of time during light emission to cause the selected light-emitting element to emit.

[0181] In addition, when light is emitted, the control potential V C In the case where the potentials are controlled to be different from each other, the potentials may be switched frequently only when charges are likely to be accumulated in accordance with light emission, but since this complicates the driving, the potentials may be switched in a certain period of time. In other words, the capacitance section is composed of a selection section that selects the light-emitting element to be emitted, and during a certain period of time, such as multiple consecutive emissions during light emission to cause the selected light-emitting element to emit light, the selection section sets the potential to a different potential from that when the light-emitting element to be emitted is selected in the light-emitting section. 、 It is also possible to use the following.

[0182] Although the embodiment of the present invention has been described above, various modifications may be made without departing from the spirit of the present invention. [Explanation of symbols]

[0183] 1, 2, 3...light emitting device, 5...three-dimensional sensor (3D sensor), 10...light source, 11...light emitting section, 12...shift section, 12a...shift unit, 13...capacitor section, 50...control section, 60...drive section, 71...power supply line, 72, 72-1, 72-2...shift signal line, 73...control potential layer, 74...light emitting potential line, 75...substrate electrode, 80...n-type semiconductor substrate, 81, 85, 87...n-type semiconductor layer, 82...active layer, 83, 86, 88...p-type semiconductor layer, 84...tunnel junction layer, 100...measurement device, 110...measurement control unit, 200...irradiation area, 210...irradiation section, Buf1, Buf2...buffer, Drv1, Drv1', Drv2, Drv2'...driver, GND...ground potential, p1, p2...shift signal, pI...emission signal, pc...control signal, Q...coupling transistor, Rv...internal resistance, S...emission control thyristor, T...shift thyristor, VCSEL...vertical cavity surface emitting laser, V C …Control voltage, Vd…Forward voltage (diffusion voltage), VGK…Power supply voltage, V K …substrate potential, V LD …Light emitting potential, Vsat…Saturation voltage, VS1, VS2, VS3…Power supply

Claims

1. a light emitting section having a light emitting element; a capacitance section connected to the light emitting section; a control unit that controls a potential of the capacitance unit when the light emitting element in the light emitting unit emits light, the light emitting section and the capacitance section are provided on a single semiconductor substrate, the capacitance portion is formed of a pn junction that is a structure equivalent to the light emitting element provided on the semiconductor substrate, the light emitting section and the capacitance section are connected by the semiconductor substrate, The potential applied to the capacitance section by the control section is a potential that does not forward bias the pn junction. Light emitting device.

2. The control unit is When a light-emitting current flowing through the light-emitting unit is on, a potential of the capacitance unit is set to a first potential; When a light-emitting current flowing through the light-emitting unit is switched from on to off, the potential of the capacitance unit is set from the first potential to a second potential that is greater in absolute value than the first potential.

2. The light emitting device according to claim 1 .

3. a drive unit connected to the light emitting unit and the capacitance unit, for turning on or off a light emitting current flowing in the light emitting unit; 3 . The light emitting device according to claim 2 , wherein the control unit sets the potential from the first potential to the second potential in accordance with a timing when the drive unit switches the light emitting current from on to off.

4. the light emitting section has a first capacitance in parallel with the light emitting element, The capacitance section has a second capacitance, 3. The light emitting device according to claim 2, wherein the first potential and / or the second potential is a potential at which the first capacitance and the second capacitance are connected in series to cause a displacement current to flow.

5. 5. The light emitting device according to claim 4, wherein the second capacitance is equal to or greater than the first capacitance.

6. 6. The light emitting device according to claim 5, wherein the second capacitance is four times or less than the first capacitance.

7. The light emitting unit includes a plurality of the light emitting elements, A selection unit for selecting the light emitting element to be emitted, The selection section is stacked on the capacitance section.

2. The light emitting device according to claim 1 .

8. The control unit is When the selected light emitting element is made to emit light, the potential is set to a different potential from that when the selection unit selects the light emitting element to be made to emit light.

8. The light emitting device according to claim 7.

9. The control unit is 9. The light-emitting device according to claim 8, wherein the capacitance section is set to a first potential when the selection section is being selected, and when the selection section is completed, the capacitance section is set to a second potential having an absolute value greater than the first potential.

10. The light emitting device according to claim 1 , wherein the control unit sets the potential of the capacitance unit to a floating state during the light emission.

11. A light emitting device according to any one of claims 1 to 10, a light receiving unit that receives light emitted from the light emitting unit of the light emitting device and reflected by the object to be measured, A measuring device that measures the three-dimensional shape of the object to be measured.

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