Method for manufacturing a trench type semiconductor device

Abstract

To provide a manufacturing method of a trench type semiconductor device capable of improving yield by preventing etching of a silicon substrate when forming a metal plug in a contact hole.SOLUTION: A manufacturing method of a trench type semiconductor device, in which a trench 18 is formed on one surface side of the semiconductor substrate, and a gate electrode 9 is embedded in the trench 18 with a gate insulating film 8 interposed therebetween, includes the steps of forming a thermal oxide film 13 on one surface side of the semiconductor substrate, forming an interlayer insulating film 10 on the thermal oxide film 13, forming a barrier metal 14 such that at least a portion of the side wall portion is in contact with the thermal oxide film 13, and embedding a metal plug 15 in the barrier metal 14.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a trench type semiconductor device. [Background technology]

[0002] There are high expectations for reducing the power consumption of power semiconductor devices, which play a central role in power conversion equipment for various applications such as industrial and electric vehicles. Among power semiconductor devices, IGBTs (Insulated Gate Bipolar Transistors) can achieve a low on-voltage due to the conductivity modulation effect, and are easy to control by voltage-driven gate control, so their use is steadily becoming established. In particular, trench-gate IGBTs, in which the gate electrode is formed in a trench provided on the surface of a silicon (Si) wafer, can increase the density (total channel length) of the electron inversion layer (channel), thereby lowering the on-voltage.

[0003] FIG. 15 is a cross-sectional view showing the structure of a conventional trench gate IGBT. As shown in FIG. - A p-type base layer 105 is provided on one surface layer of a silicon substrate having a p-type drift layer 101, and an n-type base layer 105 is provided on the other surface layer. + A field stop layer (hereinafter abbreviated as FS layer) 103 is provided, + The surface layer of the FS layer 103 is p + (Hereinafter, the side on which the p-type base layer 105 is provided is referred to as the front surface of the silicon substrate, and the p + The side on which the p-type collector layer 102 is provided is defined as the back surface of the silicon substrate. - A plurality of trenches 118 are provided down to the type drift layer 101 .

[0004] Inside the p-type base layer 105, ++ The p-type base layer 105 is provided with an n-type emitter region 106.++ Selectively adjacent to the p-type emitter region 106 ++ A p-type contact region 107 is provided. An n-type inversion layer is formed in a portion of the p-type base layer 105 along the side wall of the trench 118, and serves as a current path for a main current in the on-state.

[0005] The emitter electrode 111 is connected to the p ++ type contact region 107 and n ++ The collector electrode 112 is conductively connected to the p-type emitter region 106 on the back side of the silicon substrate. + The gate electrode 109 is conductively connected to the type collector layer 102. The gate electrode 109 is provided within the trench 118 with the gate insulating film 108 interposed therebetween.

[0006] A method for forming the emitter electrode 111 will be specifically described below. An interlayer insulating film 110 is formed on one surface layer of a silicon substrate, a part of the interlayer insulating film 110 is etched to form a contact hole, and a metal member such as a metal plug 115 is embedded in the contact hole to form a connection. The metal plug 115 is, for example, a tungsten plug. Previously, the aluminum (Al) electrode, which is the emitter electrode 111, and the silicon substrate were directly connected to each other, but as the contact hole became narrower due to miniaturization, it became impossible to ensure good contact with the silicon substrate using Al, which is mainly formed by sputtering. For this reason, a structure has been adopted in which a metal member such as a tungsten plug is embedded in the contact hole, the silicon substrate and tungsten (W) are connected at the bottom of the contact hole, and W is connected to the Al electrode at the top of the contact hole.

[0007] Here, a method for depositing W and forming a tungsten plug is the CVD (Chemical Vapor Deposition) method. In this case, a W film is often formed by using a reduction reaction between WF6 (tungsten hexafluoride) gas and H2 (hydrogen) gas. In this case, since WF6 gas etches the silicon substrate and the silicon oxide (SiO2) film of the interlayer insulating film 110, a barrier metal 114 is provided to prevent the silicon substrate and the SiO2 film from being etched when W is deposited using WF6 gas. The barrier metal 114 is often formed by a titanium (Ti)-based film using a sputtering method, and the contact resistance is often controlled within a desired range by performing silicidation by controlling the film thickness and heating after sputtering.

[0008] Also, in a trench-gate IGBT, a structure is known in which a gate insulating film of SiO2 formed by a thermal oxidation film formed by oxidizing a part of a silicon substrate on the surface of the silicon substrate, and an interlayer insulating film made of silicate glass containing boron and phosphorus is deposited thereon (see, for example, Patent Document 1 below). Also, it is known that, for example, tungsten is used for the contact plug, the interlayer insulating film is made of a lower interlayer insulating film and an upper interlayer insulating film, the lower interlayer insulating film is made of, for example, HTO (High Temperature Oxide), and the upper interlayer insulating film is made of, for example, BPSG (Boron Phosphorous Silicon Glass) (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent No. 3384198 [Patent Document 2] JP 2017-163107 A Summary of the Invention [Problem to be solved by the invention]

[0010] Here, by the heat treatment after sputtering, the barrier metal 114 at the bottom of the contact hole reacts with silicon (Si) and becomes a silicide, so that the film thickness becomes two to three times that before the heat treatment, and the barrier properties are ensured. However, on the sidewall of the contact hole (for example, region S in FIG. 15), there is almost no reaction with the interlayer insulating film 110, so the film thickness remains thin as before the heat treatment. For this reason, when the barrier metal 114 is formed by the sputtering method, the film thickness of the barrier metal 114 is often thin, especially on the sidewall. Moreover, the film quality of the barrier metal 114 on this sidewall is often a relatively sparse film, and in terms of film thickness and film quality, this is an area with relatively weak barrier properties.

[0011] If a tungsten plug is formed in this state, the interlayer insulating film 110 may be etched by WF6 gas or the like in the region where the barrier metal 114 on the sidewall of the contact hole has a weak barrier property. In particular, when a BPSG film is used for the interlayer insulating film 110, the amount of etching may be large due to the presence of moisture adsorbed in the BPSG film. If this etching progresses and the WF6 gas reaches the silicon substrate as shown by the arrow A in FIG. 15, the WF6 gas may react with Si, and the silicon substrate may also be etched. This may significantly impair the electrical characteristics of the semiconductor device, and the yield of the semiconductor device may decrease.

[0012] In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a method for manufacturing a trench-type semiconductor device that can prevent a silicon substrate from being etched when a metal plug is formed in a contact hole and thereby improve yield. [Means for solving the problem]

[0013] In order to solve the above-mentioned problems and achieve the object of the present invention, the present invention provides a method for manufacturing a trench-type semiconductor device having a unit cell including a gate electrode embedded in the trench via a gate insulating film, the method comprising the steps of: forming a thermal oxide film separate from the gate insulating film on one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film on the thermal oxide film; forming a barrier metal such that at least a part of a sidewall of the thermal oxide film is in contact with the thermal oxide film; and forming a unit cell including a gate insulating film on the surface of the semiconductor substrate. and and burying a metal plug in the barrier metal in the unit cell covered with the barrier metal. In the step of forming the thermal oxide film, the thermal oxide film is formed by performing a heat treatment in an oxygen atmosphere.

[0014] In order to solve the above-mentioned problems and achieve the object of the present invention, another configuration of the present invention is a method for manufacturing a trench-type semiconductor device having a unit cell in which a trench is formed on one surface side of a semiconductor substrate containing silicon, and the unit cell includes a gate electrode embedded in the trench via a gate insulating film, the method comprising the steps of: forming a first film separate from the gate insulating film on one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a part of a sidewall portion of the first film is in contact with the first film; and and burying a metal plug in the barrier metal in the unit cell covered with the barrier metal. The first film is denser than the interlayer insulating film. In the step of forming the first film, the first film is formed by performing a heat treatment in an oxygen atmosphere.

[0015] In order to solve the above-mentioned problems and achieve the object of the present invention, another configuration of the present invention is a method for manufacturing a trench-type semiconductor device having a unit cell in which a trench is formed on one surface side of a semiconductor substrate containing silicon, and the unit cell includes a gate electrode embedded in the trench via a gate insulating film, the method comprising the steps of: forming a first film separate from the gate insulating film on one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a part of a sidewall portion of the first film is in contact with the first film; and and burying a metal plug in the barrier metal in the unit cell covered with the barrier metal. The first film has an etching rate with respect to halogen smaller than that of the interlayer insulating film. In the step of forming the first film, the first film is formed by performing a heat treatment in an oxygen atmosphere. In order to solve the above-mentioned problems and achieve the object of the present invention, another configuration of the present invention is a method for manufacturing a trench-type semiconductor device having a unit cell including a gate electrode embedded in the trench via a gate insulating film, the method including the steps of: forming a thermal oxide film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film on the thermal oxide film; forming a barrier metal such that at least a part of a sidewall portion having a thickness thinner than a bottom portion is in contact with the thermal oxide film; and embedding a metal plug in the barrier metal having the sidewall portion in the unit cell in which the surface of the semiconductor substrate is covered with the thermal oxide film and the barrier metal. In order to solve the above-mentioned problems and achieve the object of the present invention, another configuration of the present invention is a method for manufacturing a trench-type semiconductor device having a unit cell including a gate electrode embedded in the trench via a gate insulating film, the method including the steps of: forming a first film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a portion of a sidewall portion having a thickness thinner than a bottom portion is in contact with the first film; and embedding a metal plug in the barrier metal having the sidewall portion in the unit cell in which the surface of the semiconductor substrate is covered with the first film and the barrier metal, the first film being a film denser than the interlayer insulating film.In order to solve the above-mentioned problems and achieve the object of the present invention, another configuration of the present invention is a method for manufacturing a trench-type semiconductor device having a unit cell including a gate electrode embedded in the trench via a gate insulating film, the method including the steps of: forming a first film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a part of a sidewall portion having a thickness thinner than a bottom portion is in contact with the first film; and embedding a metal plug in the barrier metal having the sidewall portion in the unit cell in which the surface of the semiconductor substrate is covered with the first film and the barrier metal, the first film having an etching rate with respect to halogen smaller than that of the interlayer insulating film. Effect of the Invention

[0016] The method for manufacturing a trench-type semiconductor device according to the present invention has the effect of preventing a decrease in the yield of semiconductor devices caused by etching of the silicon substrate when forming a metal plug in a contact hole. [Brief description of the drawings]

[0017] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment; [Diagram 2] 1A to 1C are cross-sectional views showing a state during the manufacture of a semiconductor device according to an embodiment (part 1). [Diagram 3] 4 is a cross-sectional view (part 2) showing a state during the manufacture of the semiconductor device according to the embodiment. FIG. [Figure 4] 4A to 4C are cross-sectional views (part 3) illustrating a state during the manufacture of the semiconductor device according to the embodiment. [Diagram 5] 4 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the embodiment (part 4). FIG. [Figure 6] 5 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment (part 5). FIG. [Figure 7]6 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; FIG. [Figure 8] FIG. 7 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; [Figure 9] 8 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; FIG. [Figure 10] 9 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; FIG. [Figure 11] FIG. 10 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; [Figure 12] FIG. 11 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; [Figure 13] FIG. 12 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; [Figure 14] FIG. 13 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to an embodiment; [Figure 15] FIG. 1 is a cross-sectional view showing the structure of a conventional trench gate IGBT. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] A preferred embodiment of the semiconductor device manufacturing method and the semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, but the concentrations are not necessarily the same. In the following description of the embodiment and the attached drawings, the same symbols are attached to similar configurations, and duplicate explanations are omitted.

[0019] (Embodiment) The semiconductor device according to the present invention will be described by taking a trench-gate IGBT as an example. FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. In FIG. 1, only two unit cells (functional units of an element) are shown, and other unit cells adjacent to these are not shown. The IGBT shown in FIG. - The IGBT has a MOS (Metal Oxide Semiconductor) gate on the front surface (surface on the p-type base layer 5 side) of a semiconductor substrate (silicon substrate: semiconductor chip) made of silicon that serves as the p-type drift layer 1.

[0020] As shown in FIG. 1, the semiconductor device according to the embodiment has n - A p-type base layer (a second semiconductor layer of a second conductivity type) 5 is selectively provided in a surface layer of a main surface (front surface) of an n-type drift layer (a first semiconductor layer of a first conductivity type) 1. - The back side of the drift layer 1 is + A type FS layer 3 is provided, and n + On the surface of the FS layer 3, + A collector layer (fourth semiconductor layer of the second conductivity type) 2 is provided.

[0021] The p-type base layer 5 includes p ++ Type contact region 7 and n ++ A first conductive type emitter region (third semiconductor layer) 6 is selectively provided. ++ The emitter region 6 is p ++ The p-type contact region 7 is disposed next to the p ++ The contact region 7 is ++ It may be deeper than the emitter region 6. ++ In the region adjacent to the p-type emitter region 6, an n-type - A trench 18 is provided so as to reach the type drift layer 1. A gate electrode 9 made of polysilicon is buried in the trench 18 via a gate insulating film 8 which is, for example, a thermal oxide film.

[0022] A thermal oxide film 13 and an interlayer insulating film 10 are laminated on the gate electrode 9 to insulate it from the emitter electrode 11. The thermal oxide film 13 and the interlayer insulating film 10 are n ++ The n-type emitter region 6 may be provided on a portion of the n-type emitter region 6. In a contact hole selectively opened in the thermal oxide film 13 and the interlayer insulating film 10, the emitter electrode 11 is connected to the n-type emitter region 6 via the barrier metal 14 and the metal plug 15. ++ 6, p-type emitter region ++ The emitter electrode 11 may be grounded or may have a negative voltage applied to it. + A collector electrode 12 is provided in electrical contact with the collector layer 12. A positive voltage is applied to the collector electrode 12.

[0023] The barrier metal 14 covers the contact hole, and in the embodiment, the barrier metal 14 is made of, for example, Ti, TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), or the like, or is a laminate of these. The metal plug 15 is made of a metal different from the emitter electrode 11, and is, for example, a tungsten plug in which tungsten is embedded in the barrier metal 14. The metal plug 15 may also be a molybdenum plug in which molybdenum (Mo) is embedded in the barrier metal 14.

[0024] In the IGBT of the embodiment, a thermal oxide film 13 formed by thermal oxidation, which is formed by oxidizing a part of a silicon substrate, is provided between the silicon substrate and the interlayer insulating film 10. In FIG. 1, the thermal oxide film 13 is also provided between the interlayer insulating film 10 and the gate electrode 9, but it is sufficient that the thermal oxide film 13 is provided between the silicon substrate and the interlayer insulating film 10, and the thermal oxide film 13 between the interlayer insulating film 10 and the gate electrode 9 is not necessary. In general, the thermal oxide film 13 is denser than an oxide film formed by a CVD method such as a BPSG film, and its etching rate with respect to halogen is significantly reduced. For this reason, it is preferable to form the thermal oxide film 13 on the silicon substrate (n ++By providing the thermal oxide film 13 between the first emitter region 6 and the interlayer insulating film 10, when forming a tungsten plug as a metal plug 15 in a region where the barrier metal 14 is thin and has a relatively weak barrier property on the side wall of the contact hole (for example, region S in FIG. 1), even if the interlayer insulating film 10 is etched by WF6 gas or the like, the presence of the thermal oxide film 13, which has a significantly slow etching rate, significantly reduces the amount of etching by the thermal oxide film 13 as shown by arrow A in FIG. 1, and significantly reduces the possibility that the WF6 gas will reach the silicon substrate. As a result, in the IGBT of the embodiment, when forming the metal plug 15 in the contact hole, the electrical characteristics of the semiconductor device are not impaired, the yield of the semiconductor device is improved, and it is possible to maintain a good yield rate.

[0025] Moreover, since the thermal oxide film 13 has the function of preventing the WF6 gas from reaching the silicon substrate as described above, it is necessary for the thermal oxide film 13 to have a thickness that is not completely etched during the formation of the metal plug 15. Specifically, the thermal oxide film 13 has a thickness of at least 1 nm. The thermal oxide film 13 also functions as a screen oxide film for ion implantation when forming the p-type base layer 5. For this function, the thermal oxide film 13 preferably has a thickness of 10 nm or more.

[0026] Furthermore, in the case of the function of preventing etching, a thick film thickness does not cause any problem, but in the case of functioning as a screen oxide film, if the film thickness is too thick, the efficiency of ion implantation decreases. Therefore, when the impurity to be ion-implanted is phosphorus (P), the thermal oxide film 13 is at least 200 nm or less, and preferably 120 nm or less in consideration of efficiency. On the other hand, when the impurity to be ion-implanted is arsenic (As), the thermal oxide film 13 needs to be further thinned. In this case, the thermal oxide film 13 is at least 50 nm or less, and preferably 35 nm or less in consideration of efficiency. In addition, the film thickness of the gate insulating film 8 is preferably 100 nm or more and 150 nm or less, and the thermal oxide film 13 is thinner than the gate insulating film 8.

[0027] As will be described in the following method of manufacturing a semiconductor device, before the thermal oxide film 13 is formed, n++ 6, p-type emitter region ++ When the p-type contact region 7 and the p-type base layer 5 are formed, the thermal oxide film 13 does not need to function as a screen oxide film. In this case, there is no problem even if the thermal oxide film 13 is thick.

[0028] (Method of Manufacturing a Semiconductor Device According to an Embodiment) Next, a method for manufacturing the semiconductor device according to the embodiment will be described. FIGS. 2 to 14 are cross-sectional views showing the semiconductor device according to the embodiment in the process of being manufactured. First, n - n-type drift layer 1 - A semiconductor substrate is prepared. - The material of the n-type semiconductor substrate may be silicon or silicon carbide (SiC). - The n-type semiconductor substrate is an n-type semiconductor substrate with an n-type - The n-type semiconductor layer may be epitaxially grown. - The following describes an example in which the mold semiconductor substrate is a silicon wafer. The state up to this point is shown in FIG.

[0029] Next, by photolithography and etching, - A trench 18 is formed so as not to penetrate the n-type drift layer 1. The trench 18 is formed to a depth of, for example, 5 μm or less. The state up to this point is shown in FIG. 3. Next, an n-type - A gate insulating film 8 is formed along the front surface of the drift layer 1 and the inner wall of the trench 18. Next, p-type impurities are injected by photolithography and ion implantation to form n - A p-type base layer 5 is formed on the front surface side of the drift layer 1. The p-type impurity is, for example, B. The state up to this point is shown in FIG.

[0030] Next, a polysilicon (poly-Si) layer is formed on the front surface of the p-type base layer 5 so as to fill the inside of the trench 18. Next, this polysilicon layer is, for example, etched back to leave a portion that will become the gate electrode 9 inside the trench 18. The state up to this point is shown in FIG.

[0031] Next, the gate insulating film 8 formed on the front surface of the p-type base layer 5 is removed. During ion implantation, heavy metals originating from the ion implantation device may get into the gate insulating film 8. If the gate insulating film 8 containing the heavy metals is left, the heavy metals will diffuse during high-temperature annealing (about 1000° C.) and create defects in the p-type base layer 5 that forms the channel, degrading the characteristics of the semiconductor device. For this reason, it is necessary to remove the gate insulating film 8 before annealing, and the gate insulating film 8 cannot be used in place of the thermal oxide film 13. The state up to this point is shown in FIG. 6.

[0032] It is also possible to form the p-type base layer 5 and then form the gate insulating film 8 after annealing. In this case, it is not necessary to remove the gate insulating film 8. However, since the p-type base layer 5 is affected by the gate insulating film 8 when the gate insulating film 8 is formed, it is necessary to strictly control the area and impurity concentration of the p-type base layer 5, which is difficult to realize and therefore it is not practical to use the gate insulating film 8 instead of the thermal oxide film 13.

[0033] Next, a heat treatment (annealing) is performed in an oxygen (O2) atmosphere to form a p-type base layer 5 A thermal oxide film 13 is formed on the front surface of the p-type base layer 5. Thermal oxidation can be performed by dry oxidation using oxygen or steam oxidation using H2O. Either method can be used since the etching rate for halogen is low in both methods, but dry oxidation is preferable for thermal oxidation because the thermal oxide film is denser and a reduction in the etching rate can be expected. The p-type impurities in the p-type base layer 5 may be activated and diffused by the heat treatment and the subsequent heat treatment. The state up to this point is shown in FIG. 7.

[0034] Next, p is formed on the surface of the p-type base layer 5 by photolithography and ion implantation. ++ Then, the p-type contact region 7 is selectively formed on the surface of the p-type base layer 5 by photolithography and ion implantation. ++ A type emitter region 6 is selectively formed.

[0035] Next, p ++ Type contact region 7 and n ++ A heat treatment (annealing) is performed to activate the type emitter region 6. The state up to this point is shown in FIG. 8. Here, as in the case of the annealing for forming the thermal oxide film 13, the heavy metal is converted into p ++ Type contact region 7 and n ++ However, compared with the case where heavy metals are diffused into the p-type base layer 5 in which the channel is formed, the influence on the characteristics of the semiconductor device is minor, and therefore the characteristics of the semiconductor device can be maintained at good values. ++ Type contact region 7 and n ++ The order in which the n-type emitter region 6 is formed can be changed in various ways. ++ Type emitter region 6 and p ++ It is preferred to form a mold contact region 7 .

[0036] Next, the interlayer insulating film 10 is formed so as to cover the thermal oxide film 13. The interlayer insulating film 10 is preferably formed by sequentially laminating an HTO film and a BPSG film. By forming a laminated structure of the HTO film and the BPSG film, the HTO film can prevent the dopant contained in the BPSG film from diffusing. The interlayer insulating film 10 may be formed of an HTO film or a BPSG film. The state up to this point is shown in FIG. 9.

[0037] Next, the thermal oxide film 13 and the interlayer insulating film 10 are patterned to form a plurality of contact holes penetrating the thermal oxide film 13 and the interlayer insulating film 10 in the depth direction. In a semiconductor device having a striped trench structure such as the IGBT shown in FIG. 1, the contact holes are grooves in a stripe or lattice shape. The depth direction refers to the direction in which the n - The direction is from the front surface to the back surface of the drift layer 1. ++ Type emitter region 6 and p ++ The mold contact region 7 is exposed. The state up to this point is illustrated in FIG.

[0038] Next, a barrier metal 14 is formed by sputtering so as to fill the contact hole. The barrier metal 14 is formed by, for example, stacking Ti and TiN. Next, a metal plug 15 is formed in the barrier metal 14. The metal plug 15 is formed by CVD using a metal halide. When the metal plug 15 is a tungsten plug, for example, it is formed by embedding tungsten using a reduction reaction of WF6 gas and H2 gas by CVD. The tungsten plug may also be formed by a reduction reaction of WCl6 (tungsten hexachloride) gas and H2 gas. The metal plug 15 may be a molybdenum plug, and in this case, the molybdenum plug is formed using MoF6 gas (molybdenum hexafluoride) or MoCl6 (molybdenum hexachloride) gas. The state up to this point is shown in FIG. 11.

[0039] Next, the emitter electrode 11 is formed on the barrier metal 14 and the metal plug 15. The emitter electrode 11 is connected to the p-type base layer 5, the n-type base layer 6, and the n-type base layer 7 via the barrier metal 14 and the metal plug 15. ++ Type emitter region 6 and p ++ The emitter electrode 11 is electrically connected to the contact region 7. The emitter electrode 11 is made of, for example, Al.

[0040] Next, n - The drift layer 1 is ground from the back side (back grinding) until it reaches the thickness of the product to be used as a semiconductor device. Next, n - The n-type drift layer 1 is placed on the back side. + Next, a n-type FS layer 3 is formed by photolithography and ion implantation. + On the surface of the FS layer 3, + A mold collector layer 2 is formed. The state up to this point is illustrated in FIG.

[0041] Next, p + A collector electrode 12 is formed on the entire surface of the mold collector layer 2. Thereafter, the semiconductor wafer is cut (diced) into chips to separate them, thereby completing the IGBT chips (semiconductor chips) shown in FIG.

[0042] In addition, in the method for manufacturing a semiconductor device according to the embodiment, before selectively removing the gate insulating film 8, ++ Type emitter region 6 and p ++ In this case, the n-type contact region 7 may be formed. - The process continues until a step of implanting p-type impurities into a portion that will become p-type base layer 5 on the front surface side of drift layer 1 (see FIG. 5).

[0043] Next, p is formed on the surface of the p-type base layer 5 by photolithography and ion implantation. ++ Then, the p-type contact region 7 is selectively formed on the surface of the p-type base layer 5 by photolithography and ion implantation. ++ The p-type emitter region 6 is selectively formed. ++ Type contact region 7 and n ++ The order in which the n-type emitter region 6 is formed can be changed in various ways. ++ Type emitter region 6 and p ++ It is preferable to form a mold contact region 7. The state up to this point is illustrated in FIG.

[0044] Next, n - The gate insulating film 8 formed on the front surface of the p-type drift layer 1 is removed. The state up to this point is shown in FIG. 14. Next, the p-type base layer 5 and the p ++ Type contact region 7 and n ++ A heat treatment (annealing) is performed to activate the p-type emitter region 6. By performing this heat treatment in an oxygen (O2) atmosphere, the p-type base layer 5 and the p ++ Type contact region 7 and n ++ A thermal oxide film 13 is formed on the front surface of the type emitter region 6. Thereafter, a step of forming an interlayer insulating film 10 (see FIG. 9) so as to cover the thermal oxide film 13 and subsequent steps are performed, thereby completing the IGBT chip (semiconductor chip) shown in FIG.

[0045] As described above, according to the embodiment, a thermal oxide film is provided between a silicon substrate and an interlayer insulating film. This significantly reduces the possibility that a halide gas will reach the silicon substrate even if the interlayer insulating film is etched by a halide gas or the like when forming a metal plug in an area where the sidewall of the barrier metal is thin and has a weak barrier property. This prevents the electrical characteristics of the semiconductor device from being impaired, improves the yield of the semiconductor device, and makes it possible to maintain a good yield rate.

[0046] The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-mentioned embodiments, for example, the dimensions and impurity concentration of each part are set in various ways according to the required specifications. In addition, in each of the above-mentioned embodiments, a trench gate type semiconductor device is described as an example, but the present invention is not limited to this and can be widely applied to semiconductor devices with a vertical planar gate structure. In each of the above-mentioned embodiments, an IGBT is described as an example, but the present invention is not limited to this and can be widely applied to various semiconductor devices that conduct and cut off current by gate drive control based on a predetermined gate threshold voltage. For example, by using a semiconductor substrate of a conductivity type different from that of an IGBT, the present invention can be applied to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In each of the above-mentioned embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0047] INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a trench semiconductor device according to the present invention is useful for manufacturing high-voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0048] 1, 101 n - Mold drift layer 2, 102 p. + Mold Collector Layer 3, 103 n + type FS layer 5, 105 p-type base layer 6, 106 n ++ Type Emitter Area 7, 107 p. ++ Mold Contact Area 8, 108 Gate insulating film 9, 109 Gate electrode 10, 110 Interlayer insulating film 11, 111 Emitter electrode 12, 112 Collector electrode 13 Thermal oxide film 14, 114 Barrier metal 15, 115 Metal plug 18, 118 Trench

Claims

1. A method for manufacturing a trench-type semiconductor device comprising: a trench formed on one surface side of a semiconductor substrate containing silicon; and a unit cell including a gate electrode embedded in the trench via a gate insulating film, the method comprising the steps of: forming a thermal oxide film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film on the thermal oxide film; forming a barrier metal such that at least a portion of a sidewall portion is in contact with the thermal oxide film; a step of embedding a metal plug in the barrier metal in the unit cell in which the surface of the semiconductor substrate is covered with the thermal oxide film and the barrier metal; Including, 2. The method for manufacturing a trench type semiconductor device, wherein in the step of forming the thermal oxide film, the thermal oxide film is formed by performing a heat treatment in an oxygen atmosphere.

2. forming a contact hole penetrating the thermal oxide film and the interlayer insulating film after the step of forming the interlayer insulating film; 2. The method for manufacturing a trench type semiconductor device according to claim 1, wherein the barrier metal is formed in the contact hole.

3. A method for manufacturing a trench-type semiconductor device as described in claim 1 or 2, characterized in that in the process of forming the thermal oxide film, the thermal oxide film is formed to have a thickness thinner than that of the gate insulating film.

4. A method for manufacturing a trench-type semiconductor device described in any one of claims 1 to 3, characterized in that the thermal oxide film is formed in a step subsequent to the step of forming the gate insulating film.

5. A method for manufacturing a trench-type semiconductor device described in any one of claims 1 to 4, characterized in that the gate insulating film is selectively removed in a step prior to the step of forming the thermal oxide film.

6. A step of forming a first high concentration region of a first conductivity type on a surface side of the semiconductor substrate, 6. The method for manufacturing a trench semiconductor device according to claim 1, wherein after the step of embedding the metal plug, the thermal oxide film and the interlayer insulating film are provided on at least a portion of the first high concentration region.

7. A method for manufacturing a trench-type semiconductor device as described in claim 6, characterized in that the step of forming the first high concentration region is performed between the step of forming the thermal oxide film and the step of forming the interlayer insulating film.

8. In the step of forming the thermal oxide film, the thermal oxide film is formed to a thickness of 200 nm or less, 8. The method for manufacturing a trench type semiconductor device according to claim 7, wherein in the step of forming the first high concentration region, the first high concentration region is formed by implanting phosphorus (P).

9. In the step of forming the thermal oxide film, the thermal oxide film is formed to a thickness of 50 nm or less, 8. The method for manufacturing a trench type semiconductor device according to claim 7, wherein in the step of forming the first high concentration region, the first high concentration region is formed by implanting arsenic (As).

10. A method for manufacturing a trench-type semiconductor device described in any one of claims 1 to 9, characterized in that it includes a step of forming a second high-concentration region of a second conductivity type on the surface side of the semiconductor substrate between the step of forming the thermal oxide film and the step of forming the interlayer insulating film.

11. A method for manufacturing a trench-type semiconductor device described in any one of claims 1 to 10, characterized in that in the process of forming the interlayer insulating film, an HTO film and a BPSG film are sequentially stacked on the thermal oxide film.

12. A method for manufacturing a trench-type semiconductor device comprising: a trench formed on one surface side of a semiconductor substrate containing silicon; and a unit cell including a gate electrode embedded in the trench via a gate insulating film, comprising: forming a first film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a portion of a sidewall portion is in contact with the first film; a step of embedding a metal plug in the barrier metal in the unit cell in which the surface of the semiconductor substrate is covered with the first film and the barrier metal; Including, the first film is denser than the interlayer insulating film, 2. A method for manufacturing a trench type semiconductor device, wherein in the step of forming the first film, the first film is formed by performing a heat treatment in an oxygen atmosphere.

13. A method for manufacturing a trench-type semiconductor device comprising: a trench formed on one surface side of a semiconductor substrate containing silicon; and a unit cell including a gate electrode embedded in the trench via a gate insulating film, comprising: forming a first film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a portion of a sidewall portion is in contact with the first film; a step of embedding a metal plug in the barrier metal in the unit cell in which the surface of the semiconductor substrate is covered with the first film and the barrier metal; Including, the first film has an etching rate with respect to halogen smaller than that of the interlayer insulating film; 2. A method for manufacturing a trench type semiconductor device, wherein in the step of forming the first film, the first film is formed by performing a heat treatment in an oxygen atmosphere.

14. A method for manufacturing a trench-type semiconductor device comprising: a trench formed on one surface side of a semiconductor substrate containing silicon; and a unit cell including a gate electrode embedded in the trench via a gate insulating film, the method comprising the steps of: forming a thermal oxide film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film on the thermal oxide film; forming a barrier metal such that at least a portion of a sidewall portion, which is thinner than a bottom portion, is in contact with the thermal oxide film; a step of embedding a metal plug in the barrier metal having the sidewall portion in the unit cell in which the surface of the semiconductor substrate is covered with the thermal oxide film and the barrier metal; 2. A method for manufacturing a trench type semiconductor device comprising the steps of:

15. A method for manufacturing a trench-type semiconductor device comprising: a trench formed on one surface side of a semiconductor substrate containing silicon; and a unit cell including a gate electrode embedded in the trench via a gate insulating film, the method comprising the steps of: forming a first film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a portion of a sidewall portion having a thickness thinner than that of a bottom portion is in contact with the first film; a step of embedding a metal plug in the barrier metal having a sidewall portion in the unit cell in which the surface of the semiconductor substrate is covered with the first film and the barrier metal; Including, 2. A method for manufacturing a trench type semiconductor device, wherein the first film is denser than the interlayer insulating film.

16. A method for manufacturing a trench-type semiconductor device comprising: a trench formed on one surface side of a semiconductor substrate containing silicon; and a unit cell including a gate electrode embedded in the trench via a gate insulating film, comprising: forming a first film separate from the gate insulating film on the one surface side of the semiconductor substrate and on the gate electrode; forming an interlayer insulating film as a second film on the first film; forming a barrier metal such that at least a portion of a sidewall portion having a thickness thinner than that of a bottom portion is in contact with the first film; a step of embedding a metal plug in the barrier metal having a sidewall portion in the unit cell in which the surface of the semiconductor substrate is covered with the first film and the barrier metal; Including, 2. A method for manufacturing a trench type semiconductor device, wherein the first film has an etching rate with respect to halogen that is smaller than that of the interlayer insulating film.

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