Switching device and method for manufacturing same

Abstract

To provide a switching device having a high performance and a method for manufacturing the same in which formation of a gallium oxide layer at an interface between a gate insulating film and a gallium nitride semiconductor layer can be suppressed.SOLUTION: A switching device 10 comprises a gallium nitride semiconductor substrate 12 and a gate insulating film 22, which is composed of silicon oxide and disposed on the gallium nitride semiconductor layer. There is no gallium oxide layer at an interface 30 between the gallium nitride semiconductor substrate and the gate insulating film, or a thickness of the gallium oxide layer at the interface between the gallium nitride semiconductor substrate and the gate insulating film is 1 nm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a switching device.

[0002] Patent Document 1 discloses a method for manufacturing a switching device. This manufacturing method includes a first gate insulating film forming step and a second gate insulating film forming step. In the first gate insulating film forming step, a first gate insulating film is formed on a gallium nitride semiconductor layer by ALD (atomic layer deposition) using ozone as an oxidizing agent. In the second step, a second gate insulating film is formed on the first gate insulating film by ALD using oxygen plasma as an oxidizing agent. A gate electrode is formed on the second gate insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-071497 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing method of Patent Document 1, in the second step, the first gate insulating film is exposed to oxygen plasma (oxygen gas in a plasma state). Since oxygen plasma has a high oxidizing power, the gallium nitride semiconductor layer below the first gate insulating film is oxidized in the second step. As a result, a gallium oxide layer is formed at the interface between the first gate insulating film and the gallium nitride semiconductor layer. As a result, interface states are generated at a high density at this interface, degrading the performance of the switching device. [Means for solving the problem]

[0005] The switching device disclosed in this specification includes a gallium nitride semiconductor layer, and a gate insulating film made of silicon oxide and disposed on the gallium nitride semiconductor layer, where no gallium oxide layer is present at the interface between the gallium nitride semiconductor layer and the gate insulating film, or the thickness of the gallium oxide layer present at the interface between the gallium nitride semiconductor layer and the gate insulating film is 1 nm or less.

[0006] The switching device may be any switching device having a gate insulating film, for example, a field effect transistor (FET) or a high electron mobility transistor (HEMT).

[0007] The gallium nitride semiconductor layer is a semiconductor layer mainly composed of gallium nitride. For example, the gallium nitride semiconductor layer may be made of gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or indium aluminum gallium nitride (InAlGaN).

[0008] Silicon oxide is a compound containing a bond between Si and O. For example, silicon oxide is SiO 2 Alternatively, it may be SiON.

[0009] In this switching device, there is no gallium oxide layer at the interface between the gallium nitride semiconductor layer and the gate insulating film, or the thickness of the gallium oxide layer at the interface between the gallium nitride semiconductor layer and the gate insulating film is 1 nm or less. Therefore, there are few interface states at the interface between the gallium nitride semiconductor layer and the gate insulating film. Therefore, this switching device has high performance.

[0010] This specification discloses a method for manufacturing a switching device. The method includes a step of forming a gate insulating film made of silicon oxide on a gallium nitride semiconductor layer by supplying a film-forming source containing silicon and an oxidizing gas in a non-plasma state to a surface of the gallium nitride semiconductor layer. The method does not include a step of exposing the gate insulating film to the oxidizing gas in a plasma state.

[0011] The oxidizing gas refers to a gas capable of oxidizing silicon, and may be, for example, oxygen gas, water vapor, ozone, or the like.

[0012] In this manufacturing method, since a non-plasma oxidizing gas is used in the step of forming the gate insulating film, oxidation of the gallium nitride semiconductor layer at the interface between the gate insulating film and the gallium nitride semiconductor layer can be suppressed. In addition, since this manufacturing method does not include a step of exposing the gate insulating film to a plasma oxidizing gas, oxidation of the gallium nitride semiconductor layer at the interface between the gate insulating film and the gallium nitride semiconductor layer can be suppressed even after the gate insulating film is formed. Therefore, according to this manufacturing method, it is possible to suppress the formation of a gallium oxide layer at the interface between the gate insulating film and the gallium nitride semiconductor layer. Therefore, according to this manufacturing method, a switching device having high performance can be manufactured. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a switching device 10. FIG. [Diagram 2] 3A to 3C are explanatory diagrams of a manufacturing method of the switching device 10. [Diagram 3] 3A to 3C are explanatory diagrams of a manufacturing method of the switching device 10. [Figure 4] 3A to 3C are explanatory diagrams of a manufacturing method of the switching device 10. [Diagram 5] 3A to 3C are explanatory diagrams of a manufacturing method of the switching device 10. [Figure 6] An explanatory diagram of the mist CVD method. [Figure 7]1 is a graph showing the results of XPS analysis of the interface between a gate insulating film and a gallium nitride semiconductor substrate. [Figure 8] 4 is a graph showing the mobility of the switching device 10 manufactured by the manufacturing method of the first embodiment. [Figure 9] 4 is a graph showing the mobility of a switching device 10 manufactured by a manufacturing method using oxygen plasma. [Figure 10] An explanatory diagram of the spray method. [Figure 11] FIG. [Figure 12] FIG. [Figure 13] FIG. 1 is an explanatory diagram of an ALD method using a non-plasma oxidizing gas. [Figure 14] 5 is a cross-sectional view of a switching device 500. FIG. [Figure 15] 5A to 5C are explanatory diagrams of a manufacturing method of the switching device 500. [Figure 16] 5A to 5C are explanatory diagrams of a manufacturing method of the switching device 500. [Figure 17] 5A to 5C are explanatory diagrams of a manufacturing method of the switching device 500. [Figure 18] 5A to 5C are explanatory diagrams of a manufacturing method of the switching device 500. [Figure 19] 5A to 5C are explanatory diagrams of a manufacturing method of the switching device 500. [Figure 20] 5A to 5C are explanatory diagrams of a manufacturing method of the switching device 500. [Figure 21] 5A to 5C are explanatory diagrams of a manufacturing method of the switching device 500. [Figure 22] 6 is a cross-sectional view of a switching device 600. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In the example of the method for manufacturing a switching device disclosed in the present specification, in the step of forming the gate insulating film, a solution containing the film-forming raw material dissolved therein and a solvent may be supplied to the surface of the gallium nitride semiconductor layer. In this case, in one configuration, a mist may be generated from the solution, and the mist may be supplied to the surface of the gallium nitride semiconductor layer together with the oxidizing gas. In another configuration, the oxidizing gas may be supplied to the surface of the gallium nitride semiconductor layer while the solution is spray-applied to the surface of the gallium nitride semiconductor layer. In another configuration, the oxidizing gas may be supplied to the surface of the gallium nitride semiconductor layer while the solution is applied to the surface of the gallium nitride semiconductor layer by an inkjet method. In another configuration, droplets of the solution may be generated by generating bubbles in the solution, and the droplets may be supplied to the surface of the gallium nitride semiconductor layer together with the oxidizing gas.

[0015] According to these configurations, the gate insulating film can be suitably formed on the gallium nitride semiconductor layer.

[0016] In another example of a method for manufacturing a switching device disclosed in this specification, in the step of forming the gate insulating film, a step of supplying a raw material gas containing the film-forming raw material to the surface of the gallium nitride semiconductor layer and a step of supplying the oxidizing gas to the surface of the gallium nitride semiconductor layer may be alternately repeated multiple times.

[0017] According to this configuration, the gate insulating film can be suitably formed on the gallium nitride semiconductor layer.

[0018] In any of the manufacturing methods disclosed in the present specification, the oxidizing gas may be ozone.

[0019] The switching device 10 of the embodiment shown in FIG. 1 is a metal oxide semiconductor field effect transistor (MOSFET). The switching device 10 has a gallium nitride semiconductor substrate 12. The gallium nitride semiconductor substrate 12 has a high-concentration n-type layer 14a, a buffer layer 14b, a drift layer 14c, a body layer 16, a source layer 18, and a drain layer 20. The high-concentration n-type layer 14a is provided in a range including the lower surface of the gallium nitride semiconductor substrate 12. The buffer layer 14b is an n-type layer having a lower n-type impurity concentration than the high-concentration n-type layer 14a, and is provided on the high-concentration n-type layer 14a. The drift layer 14c is an n-type layer having an n-type impurity concentration equivalent to that of the buffer layer 14b, and is provided on the buffer layer 14b. The body layer 16 is a p-type layer and is provided on the drift layer 14c. The source layer 18 and the drain layer 20 are n-type layers and are provided on the body layer 16. The source layer 18 and the drain layer 20 are provided in a range that partially includes the upper surface 12a of the gallium nitride semiconductor substrate 12. The source layer 18 and the drain layer 20 are separated from each other. That is, the body layer 16 is provided between the source layer 18 and the drain layer 20, and the source layer 18 is separated from the drain layer 20 by the body layer 16.

[0020] On the upper portion of the gallium nitride semiconductor substrate 12, a gate insulating film 22, a gate electrode 24, a source electrode 26, and a drain electrode 28 are disposed.

[0021] The gate insulating film 22 is made of silicon oxide (e.g., SiO 2 , SiON, etc.) The gate insulating film 22 is disposed on the gallium nitride semiconductor substrate 12. The gate insulating film 22 extends from the surface of the source layer 18 to the surface of the drain layer 20 on the upper surface 12a of the gallium nitride semiconductor substrate 12. The gate insulating film 22 is in contact with the source layer 18, the body layer 16, and the drain layer 20 on the upper surface 12a of the gallium nitride semiconductor substrate 12.

[0022] The gate electrode 24 is made of a conductor (for example, a metal or polysilicon). The gate electrode 24 is disposed on the gate insulating film 22. The gate electrode 24 extends from an upper portion of the source layer 18 to an upper portion of the drain layer 20. The gate electrode 24 faces the source layer 18, the body layer 16, and the drain layer 20 via the gate insulating film 22.

[0023] The source electrode 26 is made of a conductor. The source electrode 26 is disposed on the source layer 18. The source electrode 26 is in ohmic contact with the source layer 18.

[0024] The drain electrode 28 is made of a conductor. The drain electrode 28 is disposed on the drain layer 20. The drain electrode 28 is in ohmic contact with the drain layer 20.

[0025] When a potential equal to or higher than a threshold is applied to the gate electrode 24, a channel is formed in the drain layer 20 directly below the gate insulating film 22. The source layer 18 and the drain layer 20 are connected by the channel. In this state, when a potential higher than that of the source electrode 26 is applied to the drain electrode 28, electrons flow from the source layer 18 through the channel to the drain layer 20. That is, the switching device 10 is turned on. As will be described in detail later, in the switching device 10, the interface state density at the interface 30 between the gate insulating film 22 and the gallium nitride substrate 12 is low. Therefore, the channel mobility of the switching device 10 is high. EXAMPLES

[0026] Next, a method for manufacturing the switching device 10 of Example 1 will be described. Fig. 2 shows the gallium nitride semiconductor substrate 12 before processing. The switching device 10 is manufactured from the gallium nitride semiconductor substrate 12 of Fig. 2. The entire gallium nitride semiconductor substrate 12 shown in Fig. 2 is composed of a high-concentration n-type layer 14a. The high-concentration n-type layer 14a has a thickness of about 400 µm and a concentration of about 1 × 10 18 cm -3 The n-type impurity concentration is

[0027] First, as shown in FIG 3, a buffer layer 14b made of gallium nitride is epitaxially grown on a high-concentration n-type layer 14a. Here, the n-type impurity concentration of the buffer layer 14b is about 2×10 16 cm -3 The buffer layer 14b is formed so that the thickness of the buffer layer 14b is about 0.3 μm. Next, as shown in FIG. 3, the drift layer 14c made of gallium nitride is epitaxially grown on the buffer layer 14b. Here, the n-type impurity concentration of the drift layer 14c is about 2×10 16 cm -3 The drift layer 14c is formed so that the thickness of the drift layer 14c is about 1.0 μm. Next, as shown in FIG. 3, the body layer 16 made of gallium nitride is epitaxially grown on the drift layer 14c. Here, the body layer 16 is doped with a p-type impurity (e.g., magnesium) at a concentration of about 5×10 17 cm -3 The body layer 16 is formed so that the p-type impurity in the body layer 16 has a concentration of about 1.5 μm and the thickness of the body layer 16 is about 1.5 μm. The gallium nitride semiconductor substrate 12 is then annealed in a nitrogen atmosphere at about 850° C. for about 5 minutes to activate the p-type impurity in the body layer 16.

[0028] Next, n-type impurities (e.g., silicon) are selectively introduced into the body layer 16 from the upper surface 12a of the gallium nitride semiconductor substrate 12 at a concentration of about 3×10 15 cm -2 The gallium nitride semiconductor substrate 12 is then annealed in its entirety in a nitrogen atmosphere at about 1000° C. for about 5 minutes to activate the implanted n-type impurities. As a result, a source layer 18 and a drain layer 20 are formed in parts of the surface layer of the body layer 16, as shown in FIG.

[0029] Next, the upper surface 12a of the gallium nitride semiconductor substrate 12 is cleaned. Next, a gate insulating film forming step is performed. In the gate insulating film forming step, as shown in Fig. 5, a gate insulating film 22 made of silicon oxide is formed on the upper surface 12a. In the gate insulating film forming step of Example 1, the gate insulating film 22 is formed by mist CVD (chemical vapor deposition).

[0030] 6 shows a mist CVD apparatus 80 for carrying out the mist CVD method. The mist CVD apparatus 80 includes a furnace 82, a mist generator 84, a carrier gas supply source 86, and an oxidation gas supply source 88.

[0031] The furnace 82 has a chamber 82a. The gallium nitride semiconductor substrate 12 can be placed in the chamber 82a. The furnace 82 has a built-in heater and can heat the gallium nitride semiconductor substrate 12 in the chamber 82a.

[0032] The mist generating device 84 includes a mist generating tank 84a, a container 84b, and an ultrasonic vibrator 84c. A solution 84d is stored in the mist generating tank 84a. The solution 84d is obtained by dissolving a film-forming raw material in a solvent. The film-forming raw material contains silicon as an element. For example, polysilazane, tetraethoxysilane, triethoxysilane, hexamethyldisiloxane, hexamethyldisilazane, hexamethyldisilane, etc. can be used as the film-forming raw material. An organic solvent such as butyl acetate, dimethyl ether, methyl acetate, acetonitrile, dibutyl ether, etc. can be used as the solvent. The container 84b stores a liquid 84e (for example, water). The lower part of the mist generating tank 84a is immersed in the liquid 84e. An ultrasonic vibrator 84c is fixed to the bottom surface of the container 84b. The ultrasonic vibrator 84c applies ultrasonic waves to the liquid 84e. The ultrasonic waves applied to the liquid 84e are transmitted to the solution 84d in the mist generating tank 84a via the liquid 84e. Then, the liquid surface of the solution 84d vibrates, and mist 83 of the solution 84d is generated in the space above the solution 84d. In this manner, the mist generating device 84 generates mist 83 of the solution 84d in the mist generating tank 84a. The mist generating tank 84a is connected to the furnace 82 via a raw material supply pipe 94. The mist 83 is supplied from the mist generating tank 84a to the furnace 82 via the raw material supply pipe 94. The mist 83 that has flowed through the furnace 82 to the downstream end is discharged to the outside of the furnace 82.

[0033] The carrier gas supply source 86 is connected to the mist generating tank 84a via a carrier gas supply pipe 90. The carrier gas supply source 86 supplies a carrier gas (for example, an inert gas such as argon) to the mist generating tank 84a.

[0034] The oxidizing gas supply source 88 is connected to the middle of the raw material supply pipe 94 via an oxidizing gas supply pipe 92. The oxidizing gas supply source 88 supplies an oxidizing gas (ozone in this embodiment) to the raw material supply pipe 94.

[0035] In the gate insulating film forming process, first, the gallium nitride semiconductor substrate 12 is placed in the chamber 82a of the furnace 82. Here, the gallium nitride semiconductor substrate 12 is placed in the chamber 82a with the upper surface 12a exposed to the mist flowing in the chamber 82a. Next, the gallium nitride semiconductor substrate 12 is heated by the furnace 82. During the gate insulating film forming process, the temperature of the gallium nitride semiconductor substrate 12 is maintained at about 400°C. Next, the ultrasonic vibrator 84c is operated to generate the mist 83 from the solution 84d. At the same time, the supply of the carrier gas from the carrier gas supply source 86 to the mist generating tank 84a is started, and the supply of the oxidizing gas from the oxidizing gas supply source 88 to the raw material supply pipe 94 is started. The carrier gas flowing from the carrier gas supply pipe 90 into the mist generating tank 84a flows into the raw material supply pipe 94 together with the mist 83 in the mist generating tank 84a. In the raw material supply pipe 94, the mist 83 flows toward the furnace 82 together with the carrier gas. In the middle of the raw material supply pipe 94, the oxidizing gas flows from the oxidizing gas supply pipe 92 into the raw material supply pipe 94. Therefore, in the part of the raw material supply pipe 94 downstream of the junction with the oxidizing gas supply pipe 92, the mist 83 flows toward the furnace 82 together with the carrier gas and the oxidizing gas. When the mist 83, the carrier gas, and the oxidizing gas reach the downstream end of the raw material supply pipe 94, they flow into the chamber 82a of the furnace 82. A part of the mist 83 flowing in the chamber 82a adheres to the upper surface 12a of the gallium nitride semiconductor substrate 12. Then, the solvent contained in the mist 83 adhered to the upper surface 12a volatilizes, and the film forming raw material containing silicon adheres to the upper surface 12a. At the same time that the film forming raw material adheres to the upper surface 12a, the film forming raw material is oxidized by the oxidizing gas. The oxidized film forming raw material becomes silicon oxide. Therefore, the gate insulating film 22 made of silicon oxide grows on the upper surface 12a of the gallium nitride semiconductor substrate 12. Here, the gate insulating film 22 is formed to a thickness of about 100 nm in a film formation time of about 5 minutes.

[0036] After the gate insulating film 22 is formed, the gallium nitride semiconductor substrate 12 is annealed in a nitrogen atmosphere at about 800° C. for about five minutes.

[0037] 1, contact holes 26a, 28a are formed in the gate insulating film 22 above the source layer 18 and above the drain layer 20. Next, the gate electrode 24, the source electrode 26, and the drain electrode 28 are formed. Thereafter, if necessary, a hydrogen sintering process is performed on the gallium nitride semiconductor substrate 12. Through the above steps, the switching device 10 shown in FIG. 1 is completed.

[0038] As described above, in the first embodiment, the gate insulating film 22 is formed by the mist CVD method using a non-plasma oxidizing gas. That is, the film-forming raw material is oxidized by a non-plasma oxidizing gas on the gallium nitride semiconductor substrate 12 to form the gate insulating film 22 (i.e., a silicon oxide film). That is, in the manufacturing method of the first embodiment, a plasma oxidizing gas is not used in the gate insulating film forming step. Also, in the manufacturing method of the first embodiment, the gate insulating film 22 is not exposed to a plasma oxidizing gas after it is formed. As described below, this configuration can suppress the formation of a gallium oxide layer at the interface 30 between the gate insulating film 22 and the gallium nitride semiconductor substrate 12, thereby improving the channel mobility of the switching device 10.

[0039] Graphs A to C in FIG. 7 show the results of XPS analysis of GaLLM for three samples prepared as the switching device 10. Graph A shows the results of XPS analysis of the surface of the body layer 16 in a state where the gate insulating film 22 is not formed (the state of FIG. 4). That is, graph A shows the results of XPS analysis of the surface of the body layer 16 in a state where no gallium oxide layer exists. Graph B shows the results of XPS analysis of the interface 30 between the gate insulating film 22 and the body layer 16 formed by the gate insulating film forming step of Example 1 (i.e., the mist CVD method using ozone as the oxidizing gas). Graph C shows the results of XPS analysis of the interface 30 between the gate insulating film 22 and the body layer 16 formed by the ALD method using oxygen plasma (oxygen gas in a plasma state). In the measurements of graphs B and C, the thickness of the gate insulating film 22 was reduced from approximately 100 nm to approximately 5 nm by wet etching the gate insulating film 22, and then XPS analysis was performed on the interface 30 between the gate insulating film 22 and the body layer 16.

[0040] As shown in FIG. 7, graph B is almost identical to graph A, whereas graph C has a clear deviation from graph A. As shown in Noritake Isomura at el (2020). X-ray photoelectron spectroscopy insights on interfaces between SiO2 films and GaN substrates: differences due to depositional technique, Jpn. J. Appl. Phys. 59, 090902 (2020), by comparing the results of XPS analysis of the interface between the gate insulating film and the gallium nitride semiconductor, it is possible to detect whether or not a gallium oxide layer is present at the interface. According to this method, a gallium oxide layer having a thickness of more than 1 nm can be detected. As described above, graph A is the result of XPS analysis performed on the surface of the body layer 16 in a state in which no gallium oxide layer is present. Since graph B is identical to graph A, in the sample of graph B, no gallium oxide layer is present at the interface 30, or the thickness of the gallium oxide layer present at the interface 30 is 1 nm or less (below the detection limit). That is, when the gate insulating film 22 is formed by the mist CVD method using ozone as an oxidizing gas, a gallium oxide layer is not formed at the interface 30, or the thickness of the gallium oxide layer formed at the interface 30 is 1 nm or less. Since the graph C is shifted from the graph A, the sample of the graph C has a gallium oxide layer with a thickness of more than 1 nm at the interface 30. That is, when the gate insulating film 22 is formed by the ALD method using oxygen plasma, a gallium oxide layer with a thickness of more than 1 nm is formed at the interface 30.

[0041] As described above, according to the manufacturing method of Example 1, the formation of a gallium oxide layer at the interface 30 can be suppressed. The reason is presumed to be as follows. If an oxidizing gas in a plasma state is used when forming the gate insulating film 22, the oxidizing power of the oxidizing gas in the plasma state is too high, so that the surface of the gallium nitride semiconductor substrate 12 is oxidized and a gallium oxide layer is formed at the interface 30. In contrast, in the manufacturing method of Example 1, an oxidizing gas in a non-plasma state is used when forming the gate insulating film 22. Since the oxidizing power of the oxidizing gas in a non-plasma state is not so high, the formation of a gallium oxide layer at the interface 30 is suppressed. In addition, when the gate insulating film 22 is exposed to an oxidizing gas in a plasma state after the formation of the gate insulating film 22, a gallium oxide layer is formed at the interface 30. In contrast, in the manufacturing method of Example 1, there is no process in which the gate insulating film 22 is exposed to an oxidizing gas in a plasma state after the formation of the gate insulating film 22. Therefore, the formation of a gallium oxide layer at the interface 30 after the formation of the gate insulating film 22 is suppressed. Therefore, according to the manufacturing method of Example 1, it is possible to manufacture a switching device 10 in which no gallium oxide layer is present at interface 30, or in which the gallium oxide layer present at interface 30 has a thickness of 1 nm or less.

[0042] When the formation of a gallium oxide layer at the interface 30 is suppressed, the interface state density at the interface 30 can be reduced. In the switching device 10, a channel is formed along the interface 30, so that the channel mobility can be improved by reducing the interface state density at the interface 30. FIG. 8 shows the results of measuring the channel mobility of the switching device 10 manufactured by the manufacturing method of Example 1. As shown in FIG. 8, in this case, the channel mobility of 250 cm 2 A mobility exceeding 1000 .mu.m / Vs was obtained. Fig. 9 shows the results of measuring the channel mobility of the switching device 10 when the gate insulating film 22 was formed by the ALD method using oxygen plasma. As shown in Fig. 9, in this case, the mobility was about 56 cm at most. 2 / Vs. Thus, according to the manufacturing method of Example 1, the formation of a gallium oxide layer at the interface 30 can be suppressed, and a switching device 10 with high channel mobility can be manufactured.

[0043] Next, a description will be given of the manufacturing methods of Examples 2 to 5. Note that in the manufacturing methods of Examples 2 to 5, only the gate insulating film formation step is different from the manufacturing method of Example 1. Therefore, the gate insulating film formation step of Examples 2 to 5 will be described below. EXAMPLES

[0044] In the gate insulating film forming process of Example 2, the gate insulating film 22 is formed by a spray coating method. That is, here, while the gallium nitride semiconductor substrate 12 is heated, a solution 84d is spray-coated onto the upper surface 12a of the gallium nitride semiconductor substrate 12 as shown in FIG. 10. At the same time, an oxidation gas (here, ozone) is supplied to the upper surface 12a of the gallium nitride semiconductor substrate 12. The solvent evaporates from the solution 84d attached to the upper surface 12a, and the film forming raw material containing silicon is fixed to the upper surface 12a. At the same time that the film forming raw material is fixed to the upper surface 12a, the film forming raw material is oxidized by the oxidation gas. The oxidized film forming raw material becomes silicon oxide. Therefore, the gate insulating film 22 made of silicon oxide grows on the upper surface 12a of the gallium nitride semiconductor substrate 12. EXAMPLES

[0045] In the gate insulating film forming process of Example 3, the gate insulating film 22 is formed by the inkjet method. That is, here, while the gallium nitride semiconductor substrate 12 is heated, droplets of a solution 84d are discharged from an inkjet head 300 toward the upper surface 12a of the gallium nitride semiconductor substrate 12 as shown in FIG. 11. At the same time, an oxidation gas (here, ozone) is supplied to the upper surface 12a of the gallium nitride semiconductor substrate 12. The solvent evaporates from the solution 84d attached to the upper surface 12a, and the film forming raw material containing silicon is fixed to the upper surface 12a. At the same time that the film forming raw material is fixed to the upper surface 12a, the film forming raw material is oxidized by the oxidation gas. The oxidized film forming raw material becomes silicon oxide. Therefore, the gate insulating film 22 made of silicon oxide grows on the upper surface 12a of the gallium nitride semiconductor substrate 12. EXAMPLES

[0046] In the gate insulating film forming process of the fourth embodiment, the gate insulating film 22 is formed by a bubbling method. FIG. 12 shows a bubbling film forming apparatus 400 used for the bubbling method. The bubbling film forming apparatus 400 is obtained by replacing the mist generating device 84 of the mist CVD apparatus 80 of FIG. 6 with a bubbling tank 310. A solution 84d is stored in the bubbling tank 310. The downstream end of the carrier gas supply pipe 90 is immersed in the solution 84d in the bubbling tank 310. The upstream end of the raw material supply pipe 94 is disposed above the liquid surface of the solution 84d in the bubbling tank 310. When the gate insulating film 22 is formed by the bubbling film forming apparatus 400, a carrier gas is supplied from a carrier gas supply source 86 to a carrier gas supply pipe 90 while heating the gallium nitride semiconductor substrate 12, and an oxidizing gas (here, ozone) is supplied from an oxidizing gas supply source 88 to an oxidizing gas supply pipe 92. The carrier gas supplied to the bubbling tank 310 passes through the solution 84d as bubbles. This generates droplets of the solution 84d in the carrier gas. The droplets of the solution 84d are supplied to the upper surface 12a of the gallium nitride semiconductor substrate 12 in the furnace 82 together with the carrier gas and the oxidizing gas. When the droplets of the solution 84d adhere to the upper surface 12a, the solvent evaporates from the solution 84d, and the film-forming raw material containing silicon adheres to the upper surface 12a. At the same time that the film-forming raw material adheres to the upper surface 12a, the film-forming raw material is oxidized by the oxidizing gas. The oxidized film-forming raw material becomes silicon oxide. Therefore, the gate insulating film 22 made of silicon oxide grows on the upper surface 12a of the gallium nitride semiconductor substrate 12.

[0047] As described above, the manufacturing methods of Examples 2 to 4 are all techniques for supplying a solution 84d containing a dissolved film-forming material and a solvent to the surface 12a of a heated gallium nitride semiconductor substrate 12, similar to Example 1. In any of the manufacturing methods of Examples 2 to 4, a non-plasma oxidizing gas is used to form the gate insulating film 22. In addition, none of the manufacturing methods of Examples 2 to 4 includes a step of exposing the gate insulating film 22 to a plasma oxidizing gas after the gate insulating film 22 is formed. Therefore, in any of the manufacturing methods of Examples 2 to 4, the formation of a gallium oxide layer at the interface 30 between the gate insulating film 22 and the body layer 16 can be suppressed. In any of the manufacturing methods of Examples 2 to 4, a switching device 10 having high channel mobility can be manufactured. EXAMPLES

[0048] In the gate insulating film forming process of the fifth embodiment, the gate insulating film 22 is formed by the ALD method using a non-plasma oxidizing gas. In this gate insulating film forming process, as shown in FIG. 13, step S2 and step S4 are alternately repeated multiple times. In step S2, a raw material gas containing silicon as an element is supplied to the upper surface 12a of the gallium nitride semiconductor substrate 12 while heating the gallium nitride semiconductor substrate 12. As a result, a raw material containing silicon is deposited on the upper surface 12a of the gallium nitride semiconductor substrate 12. In step S4, an oxidizing gas (here, ozone) is supplied to the upper surface 12a of the gallium nitride semiconductor substrate 12 while heating the gallium nitride semiconductor substrate 12. As a result, the raw material containing silicon deposited on the upper surface 12a of the gallium nitride semiconductor substrate 12 is oxidized to become silicon oxide. By repeating step S2 and step S4, a gate insulating film (i.e., a silicon oxide film) is grown on the upper surface 12a of the gallium nitride semiconductor substrate 12. In the manufacturing method of the fifth embodiment, the gate insulating film 22 is also formed using a non-plasma oxidizing gas. The manufacturing method of Example 5 also does not include a step of exposing the gate insulating film 22 to an oxidizing gas in a plasma state after the gate insulating film 22 is formed. Therefore, the manufacturing method of Example 5 can also suppress the formation of a gallium oxide layer at the interface 30 between the gate insulating film 22 and the body layer 16. The manufacturing method of Example 5 can also manufacture a switching device 10 with high channel mobility. However, since this method is a film formation method at the atomic level in principle, it takes 10 hours or more to form a film of 100 nm, for example. Considering that the film formation time is at most several tens of minutes in a general CVD film formation method, even if an oxidizing gas in a plasma state is not used, a gallium oxide film is formed at the interface 30 during long film formation in the ALD method, so Example 5 is particularly effective when forming a film of 10 nm or less.

[0049] (Variation 1) Next, a switching device 500 according to a modified example shown in Fig. 14 will be described. The switching device 500 is a vertical MOSFET. Among the components of the switching device 500, those parts having the same functions as the switching device 10 are given the same reference numerals as the switching device 10.

[0050] As shown in FIG. 14, the gallium nitride semiconductor substrate 12 of the switching device 500 has a high-concentration n-type layer 14a, a buffer layer 14b, and a drift layer 14c, similar to the switching device 10. A plurality of body layers 16 are provided on the drift layer 14c. Each body layer 16 is provided in a range that partially includes the upper surface 12a of the gallium nitride semiconductor substrate 12. The plurality of body layers 16 are separated from each other. A drift layer 14c is provided between the two body layers 16, and the two body layers 16 are separated from each other by the drift layer 14c. Hereinafter, the drift layer 14c located between the two body layers 16 is referred to as a JFET layer 14d (junction field effect transistor layer). Each body layer 16 has a p-type high-concentration layer 16a and a p-type low-concentration layer 16b having a p-type impurity concentration lower than that of the high-concentration layer 16a. The high-concentration layer 16a is in contact with the drift layer 14c from above. The low concentration layer 16b contacts the high concentration layer 16a from above. A source layer 18 and a contact layer 510 are provided within an area surrounded by each low concentration layer 16b. Each source layer 18 is provided in an area that partially includes the upper surface 12a. Each source layer 18 is separated from the drift layer 14c by the body layer 16. Each contact layer 510 is a p-type layer having a higher p-type impurity concentration than the high concentration layer 16a. Each contact layer 510 is provided in an area that partially includes the upper surface 12a.

[0051] A gate insulating film 22, a gate electrode 24, a source electrode 26, and an interlayer insulating film 520 are disposed on the upper surface of the gallium nitride semiconductor substrate 12. The gate insulating film 22 covers a part of the upper surface 12a of the gallium nitride semiconductor substrate 12. The gate insulating film 22 covers a range of the upper surface 12a that spans the surface of the source layer 18, the surface of the low concentration layer 16b, and the surface of the JFET layer 14d. The gate electrode 24 is disposed on the gate insulating film 22. The gate electrode 24 faces the source layer 18, the body layer 16, and the JFET layer 14d through the gate insulating film 22. The upper portion of the gate electrode 24 is covered by the interlayer insulating film 520. The source electrode 26 covers the interlayer insulating film 520 and is in ohmic contact with the source layer 18 and the contact layer 510. A drain electrode 28 is provided on the lower surface of the gallium nitride semiconductor substrate 12. The drain electrode 28 is in ohmic contact with the high concentration n-type layer 14a.

[0052] When a potential equal to or higher than the threshold is applied to the gate electrode 24, a channel is formed in the low-concentration layer 16b directly below the gate insulating film 22. The channel connects the source layer 18 and the JFET layer 14d. In this state, when a potential higher than that of the source electrode 26 is applied to the drain electrode 28, electrons flow from the source layer 18 through the channel, the drift layer 14c, and the buffer layer 14b to the high-concentration n-type layer 14a. In other words, the switching device 500 is turned on.

[0053] The switching device 500 is manufactured from the gallium nitride semiconductor substrate 12 (the substrate entirely made up of the high-concentration n-type layer 14a) shown in FIG.

[0054] First, as shown in Fig. 15, a buffer layer 14b made of gallium nitride is epitaxially grown on a high-concentration n-type layer 14a. Here, the n-type impurity concentration of the buffer layer 14b is about 2 x 10 16 cm -3The buffer layer 14b is formed so that the thickness of the buffer layer 14b is about 0.3 μm. Next, as shown in FIG. 15, the drift layer 14c made of gallium nitride is epitaxially grown on the buffer layer 14b. Here, the n-type impurity concentration of the drift layer 14c is about 2×10 16 cm -3 The drift layer 14c is formed so that the thickness of the drift layer 14c is about 5.0 μm. Next, as shown in FIG. 15, the high concentration layer 16a made of gallium nitride is epitaxially grown on the drift layer 14c. Here, the p-type impurity concentration of the high concentration layer 16a is about 5×10 19 cm -3 The high concentration layer 16a is formed so that its thickness is about 0.5 μm. Next, as shown in FIG. 15, the low concentration layer 16b made of gallium nitride is epitaxially grown on the high concentration layer 16a. Here, the p-type impurity concentration of the low concentration layer 16b is about 5×10 17 cm -3 The low-concentration layer 16b is then formed to a thickness of about 1.5 μm. The gallium nitride semiconductor substrate 12 is then annealed in a nitrogen atmosphere at about 850° C. for about 5 minutes to activate the impurities in the gallium nitride semiconductor substrate 12.

[0055] 16, the upper surface 12a of the gallium nitride semiconductor substrate 12 is selectively dry-etched using an etching mask to form a recess 530 in the upper surface 12a. Here, the recess 530 is formed so that the width of the recess 530 is about 4 μm and the depth of the recess 530 reaches the drift layer 14c.

[0056] 17, an n-type layer 540 is epitaxially grown on the gallium nitride semiconductor substrate 12. Here, the n-type impurity concentration of the n-type layer 540 is about 2×10 16 cm -3The n-type layer 540 is formed so that the thickness of the n-type layer 540 is about 3.0 μm. When the n-type layer 540 is formed in this manner, the recess 530 is filled with the n-type layer 540. The n-type layer 540 in the recess 530 forms the JFET layer 14d.

[0057] 18, the upper surface 12a of the gallium nitride semiconductor substrate 12 is planarized by CMP (chemical mechanical polishing). Here, the upper surface 12a is planarized so that the low concentration layer 16b is exposed on the upper surface 12a.

[0058] Next, n-type impurities (e.g., silicon) are selectively introduced into the low concentration layer 16b from the upper surface 12a of the gallium nitride semiconductor substrate 12 at a concentration of about 3×10 15 cm -2 The gallium nitride semiconductor substrate 12 is then annealed in its entirety in a nitrogen atmosphere at about 1000° C. for about 5 minutes to activate the implanted n-type impurities. As a result, as shown in FIG. 19, a source layer 18 is formed in a part of the surface portion of the low concentration layer 16b.

[0059] 20, a gate insulating film 22 made of silicon oxide is formed on the upper surface 12a of the gallium nitride semiconductor substrate 12. Here, the gate insulating film 22 is formed so as to cover the entire upper surface 12a. The gate insulating film 22 can be formed by the gate insulating film formation process of any one of the above-mentioned Examples 1 to 5. Therefore, formation of a gallium oxide layer at the interface 30 between the gate insulating film 22 and the gallium nitride semiconductor substrate 12 is suppressed.

[0060] 20, the gate electrode 24 is formed on the gate insulating film 22. Here, the gate electrode 24 is formed so as to cover the entire upper surface of the gate insulating film 22.

[0061] Next, as shown in Fig. 21, the gate insulating film 22 and the gate electrode 24 are partially removed to expose the source layer 18 and a part of the low concentration layer 16b. Next, p-type impurities are ion-implanted into the low concentration layer 16b, and then activation annealing is performed to form a contact layer 510, as shown in Fig. 21. Thereafter, an interlayer insulating film 520 and a source electrode 26 are formed on the upper part of the gallium nitride semiconductor substrate 12, and a drain electrode 28 is formed on the lower part of the gallium nitride semiconductor substrate 12, thereby completing the switching device 500 shown in Fig. 14.

[0062] As described above, the gate insulating film 22 of the switching device 500 of the first modification is formed by the gate insulating film formation process of any one of the above-mentioned Examples 1 to 5. Therefore, the formation of a gallium oxide layer at the interface 30 between the gate insulating film 22 and the gallium nitride semiconductor substrate 12 is suppressed. That is, in the switching device 500 of the first modification, no gallium oxide layer is present at the interface 30, or the thickness of the gallium oxide layer present at the interface 30 is 1 nm or less. Therefore, in the switching device 500 of the first modification, the interface state density at the interface 30 is low. Therefore, the channel mobility of the switching device 500 of the first modification is high.

[0063] (Variation 2) The above-described switching devices 10 and 500 are MOSFETs. However, the technology disclosed in this specification may be applied to other switching devices. For example, the technology disclosed in this specification may be applied to a HEMT. FIG. 22 shows a switching device 600 of Modification 2 as an example of a HEMT. In FIG. 22, a gallium nitride semiconductor substrate 612 has a carrier travel layer 618 and a carrier supply layer 620. The carrier travel layer 618 is made of n-type gallium nitride (i.e., n-GaN). The carrier supply layer 620 is provided on the carrier travel layer 618. The carrier supply layer 620 is made of i-type aluminum gallium nitride (i.e., i-AlGaN). An interface 640 between the carrier travel layer 618 and the carrier supply layer 620 is a heterojunction surface, and two-dimensional electron gas is generated along the interface 640. A recess 650 is provided on the upper surface of the carrier supply layer 620, and a gate insulating film 622 and a gate electrode 624 are provided in the recess 650. The gate electrode 624 faces the carrier supply layer 620 via the gate insulating film 622. In addition, on the upper surface of the gallium nitride semiconductor substrate 612, a source electrode 626 and a drain electrode 628 are provided on both sides of the gate electrode 624.

[0064] In the switching device 600 (i.e., HEMT) of FIG. 22, the gate insulating film 622 can be formed by any of the gate insulating film forming steps of the above-mentioned Examples 1 to 5. By forming the gate insulating film 622 in this manner, it is possible to suppress the formation of a gallium oxide layer at the interface 630 between the gate insulating film 622 and the carrier supply layer 620. That is, in the switching device 600 of the second modification, no gallium oxide layer is present at the interface 630, or the thickness of the gallium oxide layer present at the interface 630 is 1 nm or less. Therefore, the interface state density at the interface 630 is low. The interface state density at the interface 630 has a large effect on the behavior of the two-dimensional electron gas directly below the interface 630. Therefore, by reducing the interface state density at the interface 630, the characteristics of the switching device 600 can be improved.

[0065] In the gate insulating film forming process of the above-mentioned Examples 1 to 5, ozone was used as the oxidizing gas. However, other gases capable of oxidizing silicon (for example, oxygen, water vapor, etc.) may be used as the oxidizing gas. However, since ozone has a higher oxidizing power than oxygen and water vapor, even if the heating temperature of the gallium nitride semiconductor substrate in the gate insulating film forming process is relatively low, the gate insulating film can be suitably formed. Furthermore, by setting the heating temperature of the gallium nitride semiconductor substrate to a relatively low temperature in this way, it is possible to suppress the diffusion of gallium from the gallium nitride semiconductor substrate to the gate insulating film during the gate insulating film forming process. This makes it possible to prevent the characteristics of the switching device from deteriorating.

[0066] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0067] 10: switching device, 12: gallium nitride semiconductor substrate, 16: body layer, 18: source layer, 20: drain layer, 22: gate insulating film, 24: gate electrode

Claims

1. 1. A method for manufacturing a switching device, comprising: The method includes a step of generating a mist (83) from a solution (84d) containing a silicon-containing film-forming raw material dissolved therein and containing a solvent, and supplying the mist together with a non-plasma state oxidizing gas to a surface of a gallium nitride semiconductor layer (12, 612) to form a gate insulating film (22, 622) made of silicon oxide on the gallium nitride semiconductor layer, The manufacturing method does not include a step of exposing the gate insulating film to an oxidizing gas in a plasma state.

2. 1. A method for manufacturing a switching device, comprising: The method includes a step of spraying a solution (84d) containing a film-forming raw material containing silicon and a solvent onto a surface of a gallium nitride semiconductor layer (12, 612) while supplying a non-plasma state oxidizing gas to the surface of the gallium nitride semiconductor layer, thereby forming a gate insulating film (22, 622) made of silicon oxide on the gallium nitride semiconductor layer, The manufacturing method does not include a step of exposing the gate insulating film to an oxidizing gas in a plasma state.

3. 1. A method for manufacturing a switching device, comprising: The method includes a step of forming a gate insulating film (22, 622) made of silicon oxide on the gallium nitride semiconductor layer by applying a solution (84d) containing a dissolved film-forming raw material including silicon and a solvent to the surface of the gallium nitride semiconductor layer by an ink-jet method while supplying a non-plasma oxidizing gas to the surface of the gallium nitride semiconductor layer, The manufacturing method does not include a step of exposing the gate insulating film to an oxidizing gas in a plasma state.

4. 1. A method for manufacturing a switching device, comprising: The method includes a step of generating droplets of a solution (84d) containing a silicon-containing film-forming raw material dissolved therein and containing a solvent by generating bubbles in the solution, and supplying the droplets together with a non-plasma state oxidizing gas to a surface of a gallium nitride semiconductor layer (12, 612) to form a gate insulating film (22, 622) made of silicon oxide on the gallium nitride semiconductor layer, The manufacturing method does not include a step of exposing the gate insulating film to an oxidizing gas in a plasma state.

5. The method according to any one of claims 1 to 4, wherein the oxidizing gas is ozone.

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