In-situ sealing of metal-insulator-metal (MIM) stacks for resistive random access memory (RERAM) cells

Abstract

Provided herein is a method for improving oxygen content control in a metal-insulator-metal (MIM) stack of a RERAM cell while maintaining throughput. More specifically, provided herein is a single-chamber solution for etching and sealing the MIM stack of a RERAM cell to control the oxygen content of the memory cell dielectric of the RERAM cell. According to one embodiment, an oxygen-free dielectric encapsulation layer is deposited in-situ on the MIM stack while the substrate remains in the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the encapsulation layer in the same processing chamber, the techniques described herein maintain throughput while minimizing exposure of the memory cell dielectric to oxygen.

Description

[Technical field]

[0001] Claiming priority This application claims priority to U.S. Provisional Patent Application No. 63 / 006,437, filed April 7, 2020, and entitled "In-situ Encapsulation of Metal-Insulator-Metal (MIM) stacks for Resistive Random Access Memory (RERAM) Cells," the disclosure of which is expressly incorporated by reference in its entirety. [Background technology]

[0002] The present disclosure relates to processing of a substrate. In particular, the present disclosure provides a method for etching a layer on a substrate.

[0003] Resistive random access memory (RRAM or RERAM) is a type of non-volatile random access memory that contains a metal-insulator-metal (MIM) stack that includes a top electrode, a memory cell dielectric, and a bottom electrode. Because a RERAM cell operates by changing the resistance of the memory cell dielectric, the resistive properties of the dielectric material used in the MIM stack have a significant impact on the performance of the RERAM cell.

[0004] The memory cell dielectric used in RERAM cells is typically made of hafnium oxide (HfO 2 In some high-k dielectric materials, oxygen vacancies in the dielectric material are a key factor in providing the desired resistance in the memory cell dielectric. Unfortunately, various substrate processing steps are known to affect the control of oxygen vacancies in the memory cell dielectric. For example, after etching of the MIM stack, the memory cell dielectric is susceptible to changes in the oxygen content of the memory cell dielectric, and thus the resistive properties of the RERAM cell. Thus, for example, to control the oxygen content of the memory cell dielectric, care should be taken to avoid oxygen ingress into the memory cell dielectric.

[0005] One technique for controlling the oxygen content of the memory cell dielectric is to encapsulate the MIM stack with an oxygen-free dielectric material after it is etched. For example, the MIM stack can be encapsulated in a silicon nitride (SiN) dielectric layer or other oxygen-free dielectric material to avoid oxygen ingress into the memory cell dielectric during subsequent processing steps.

[0006] 1A-1E illustrate a conventional process flow for forming at least a portion of a RERAM cell. In particular, FIGS. 1A-1E illustrate a conventional process flow for forming a metal-insulator-metal (MIM) stack of a RERAM cell. As shown in FIG. 1A, a RERAM cell can be fabricated by forming a bottom electrode 110 layer, a memory cell dielectric 115 layer, and a top electrode 120 layer on one or more underlying layers 105. The memory cell dielectric 115 layer can be formed of a high-k dielectric material (e.g., HfO 2 ). The top electrode 120 layer and the bottom electrode 110 layer may be implemented with a barrier metal material (e.g., TiN). As described in more detail below, the top electrode 120 layer, the memory cell dielectric 115 layer, and the bottom electrode 110 layer may be subsequently etched to form the MIM stack 100 of one or more RERAM cells.

[0007] The underlying layer 105 may include any number and / or type of layers and / or structures typically used to form a RERAM cell. For example, the underlying layer 105 may include one or more RERAM cell gates formed on a substrate that includes the source / drain regions of the RERAM cell. The underlying layer 105 may also include other layers, such as one or more dielectric layers formed on the substrate, and one or more conductive plugs that connect the subsequently formed MIM stack 100 and an overlying metal layer (not shown) to the source / drain regions of the RERAM cell.

[0008] Prior to etching the MIM stack 100 as shown in FIG. 1C, an organic planarization layer (OPL) 125, an anti-reflective coating (ARC) layer 130, and a patterning layer 140 may be formed on the top electrode 120 layer using well-known semiconductor processing steps. The patterning layer 140 may include a photoresist layer and / or a hard mask layer that are patterned for MIM stack formation. However, it will be understood that any of a wide variety of techniques may be utilized to form a pattern for etching the MIM stack 100. Once the patterning layer 140 is formed, the structure shown in FIG. 1A may be etched to form the MIM stack 100 of one or more RERAM cells.

[0009] 1B-1E illustrate exemplary process flow steps for etching a portion 150 of the structure shown in FIG. 1A to form the MIM stack 100 of one RERAM cell. The structure shown in FIG. 1A may be placed in an etch chamber to etch the MIM stack 100. The etch process used to form the MIM stack 100 may generally be performed as one or more etch process steps.

[0010] To prevent oxygen from entering the memory cell dielectric 115 during subsequent substrate processing steps, the top electrode 120, the memory cell dielectric 115, and the bottom electrode 110 may be encapsulated with a layer of oxygen-free dielectric material, such as silicon nitride (SiN). In the process steps shown in FIG. 1D, the structure including the etched MIM stack 100 (FIG. 1C) is transferred to another processing chamber (e.g., a deposition chamber) to deposit an encapsulation layer 145 on the MIM stack 100 and surrounding surfaces. The encapsulation layer 145 may generally include an oxygen-free dielectric material (e.g., SiN). Once the encapsulation layer 145 is deposited, the structure including the encapsulated MIM stack 100 (FIG. 1D) may be transferred back to an etching chamber so that a further etching process (e.g., a spacer etch) may be performed to remove the encapsulation layer 145 from the top surface of the MIM stack 100 and surrounding surfaces, as shown in FIG. 1E. The etch process used to perform the spacer etch may generally be performed as one or more etch process steps. By using a spacer etch, the encapsulation layer is left on the sidewalls of the MIM stack 100 but is removed from the top of the MIM stack 100 and from the top of the underlayer 105.

[0011] In a conventional RERAM process flow shown in Figures 1A-1E, the structure including the etched MIM stack 100 is transferred from an etch chamber to a deposition chamber for encapsulation with an encapsulation layer 145 including an oxygen-free dielectric material. Once the encapsulation layer 145 is deposited, the structure including the encapsulated MIM stack 100 is returned to the same or a different etch chamber for further processing. This process flow reduces throughput by requiring multiple trips to and from process chambers and can expose the memory cell dielectric to oxygen.

[0012] It would be desirable to provide an improved process for forming the MIM stack of a RERAM cell that minimizes exposure of the memory cell dielectric to oxygen while also maintaining throughput. Summary of the Invention

[0013] Provided herein is a method for improving oxygen content control of a metal-insulator-metal (MIM) stack of a RERAM cell while maintaining throughput. More specifically, provided herein is a single chamber solution for etching and sealing a MIM stack of a RERAM cell to control the oxygen content of the memory cell dielectric of the RERAM cell. According to one embodiment, an oxygen-free dielectric sealing layer is deposited in-situ on the MIM stack while the substrate remains in the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the sealing layer in the same processing chamber, the techniques described herein maintain throughput while minimizing exposure of the memory cell dielectric to oxygen.

[0014] In a first method, a method of forming a resistive random access memory (RERAM) is provided. The first method may include forming a first electrode layer, forming a memory cell dielectric layer, and forming a second electrode layer, the memory cell dielectric layer being disposed between the first electrode layer and the second electrode layer. The method further includes etching the first electrode layer, the memory cell dielectric layer, and the second electrode layer to form one or more metal-insulator-metal (MIM) stacks of one or more RERAM cells, the etching being performed in at least one plasma etch chamber, and depositing an encapsulation layer over the one or more MIM stacks and surrounding surfaces, the deposition being performed in the at least one plasma etch chamber.

[0015] In one embodiment of the first method, the memory cell dielectric layer comprises a metal oxide selected from the group including hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), tantalum oxide (TaOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), or titanium oxide (TiOx), and mixtures thereof. In another embodiment, the encapsulation layer comprises silicon (Si), silicon nitride (SiN), oxynitride (ON), or silicon oxynitride (SiON). In another embodiment, the encapsulation layer comprises an organic material.

[0016] In yet another embodiment of the first method, the depositing comprises delivering one or more precursors to at least one plasma etch chamber to deposit an encapsulation layer on the one or more MIM stacks and surrounding surfaces. In one embodiment, the one or more silicon precursors comprise a silicon-containing gas. In a further particular embodiment, the one or more silicon precursors comprise silicon tetrachloride (SiCl 4 ) and silicon tetrafluoride (SiF 4 ) is selected from the group including

[0017] In another embodiment of the first method, the method further includes performing a spacer etch process to remove the encapsulation layer from horizontal surfaces of the one or more MIM stacks and the surrounding surface. In one embodiment, the spacer etch also removes any etch byproducts remaining after etching the first electrode layer, the memory cell dielectric layer, and the second electrode layer. In another embodiment, said performing a spacer etch process includes using an oxygen-free plasma etch chemistry in at least one plasma etch chamber to remove the encapsulation layer from horizontal surfaces of the one or more MIM stacks and the surrounding surface. In yet another embodiment, said depositing of the encapsulation layer prevents oxygen ingress into the memory cell dielectric layer when removing the encapsulation layer from horizontal surfaces of the one or more MIM stacks and the surrounding surface by leaving the encapsulation layer on the sidewalls of the MIM stacks.

[0018] In a second method, a method of forming a resistive random access memory (RERAM) is provided. The second method may include forming a first electrode layer, forming a memory cell dielectric layer, and forming a second electrode layer, the memory cell dielectric layer being disposed between the first electrode layer and the second electrode layer. The method further includes etching the first electrode layer, the memory cell dielectric layer, and the second electrode layer to form one or more metal-insulator-metal (MIM) stacks of one or more RERAM cells, the etching being performed in at least one plasma etch chamber. The second method also includes depositing an encapsulation layer on the one or more MIM stacks and surrounding surfaces, the deposition being performed in at least one plasma etch chamber. The second method further includes removing the encapsulation layer from a top surface of the one or more MIM stacks and surrounding surfaces, the removal being performed in at least one plasma etch chamber. Various embodiments of the first method described above may also be used as embodiments of the second method. [Brief description of the drawings]

[0019] A more complete understanding of the present invention and its advantages can be obtained by referring to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features, in which: It should be noted, however, that the accompanying drawings depict only exemplary embodiments of the disclosed concepts and therefore should not be considered limiting in scope, as the disclosed concepts may also admit of other equally effective embodiments, in which:

[0020] [Figure 1A] 1A-1E (Prior Art) show a conventional process flow for forming an MIM stack of a RERAM cell. [Figure 1B] 1A-1E (Prior Art) show a conventional process flow for forming an MIM stack of a RERAM cell. [Figure 1C]1A-1E (Prior Art) show a conventional process flow for forming an MIM stack of a RERAM cell. [Figure 1D] 1A-1E (Prior Art) show a conventional process flow for forming an MIM stack of a RERAM cell. [Figure 1E] 1A-1E (Prior Art) show a conventional process flow for forming an MIM stack of a RERAM cell. [Figure 2A] 2A-2C illustrate an improved process flow for forming an MIM stack of a RERAM cell according to the techniques disclosed herein. [Figure 2B] 2A-2C illustrate an improved process flow for forming an MIM stack of a RERAM cell according to the techniques disclosed herein. [Figure 2C] 2A-2C illustrate an improved process flow for forming an MIM stack of a RERAM cell according to the techniques disclosed herein. [Diagram 3] 1 is a flow diagram illustrating one embodiment of a method for forming a MIM stack of a RERAM cell in accordance with the techniques disclosed herein. [Figure 4] FIG. 4 is a block diagram illustrating one embodiment of a plasma processing system 400 in which the process flows illustrated in FIGS. 2A-2C and the method illustrated in FIG. 3 may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Provided herein is a method for improving oxygen content control of a metal-insulator-metal (MIM) stack of a RERAM cell while maintaining throughput. More specifically, provided herein is a single chamber solution for etching and sealing a MIM stack of a RERAM cell to control the oxygen content of the memory cell dielectric of the RERAM cell. According to one embodiment, an oxygen-free dielectric sealing layer is deposited in-situ on the MIM stack while the substrate remains in the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the sealing layer in the same processing chamber, the techniques described herein maintain throughput while minimizing exposure of the memory cell dielectric to oxygen.

[0022] The technique described herein for protecting the integrity of the oxygen content of a RERAM cell can be used in a wide variety of RERAM cell designs, RERAM memory cell dielectrics, RERAM encapsulation dielectrics, and RERAM process flows. It will be understood that the RERAM cell designs, RERAM memory cell dielectrics, RERAM encapsulation dielectrics, and RERAM process flows shown herein are merely exemplary, and those skilled in the art will recognize that many other alternatives can still benefit from the techniques described herein. An example of an improved process flow for forming a MIM stack of a RERAM cell is shown in FIG. 2. However, other process flows can also be used.

[0023] Prior to the implementation of the techniques described herein, one or more layers used to form the RERAM cell may be provided on a substrate using any of a wide variety of substrate processing techniques to achieve the structures shown. The substrate used in the techniques disclosed herein may be any substrate on which it is desired to etch material. For example, in one embodiment, the substrate may be a semiconductor substrate having one or more semiconductor processing layers (all of which together may constitute a substrate) formed thereon. In one embodiment, the substrate may be a substrate that has been subjected to multiple semiconductor processing steps (all of which are well known in the substrate processing arts) resulting in a wide variety of structures and layers. In one embodiment, the substrate may be a semiconductor wafer that includes various structures and layers formed thereon.

[0024] 2A-2C show an example of an improved process flow for forming a metal-insulator-metal (MIM) stack of a RERAM cell according to the techniques described herein. Similar to the conventional process flow shown in FIGS. 1A-1E, FIGS. 2A-2C show exemplary process steps that may be performed on a portion 250 of a substrate having one or more layers formed thereon to form a MIM stack 200 of a RERAM cell. Although an example of such layers is shown in FIGS. 2A-2C, one of ordinary skill in the art will understand how the techniques described herein may be performed on a substrate having additional and / or alternative layers formed above and / or below the MIM stack layers.

[0025] As shown in FIG. 2A, the bottom electrode 210 layer, the memory cell dielectric 215 layer, and the top electrode 220 layer are formed on one or more underlying layers 205. As described above, the underlying layer 205 may include any number and / or type of layers and / or structures typically used to form RERAM cells. The underlying layer 205 may generally include a substrate on which one or more semiconductor processing layers are formed. The source / drain regions of one or more RERAM cells may be formed in the substrate, and one or more RERAM cell gates may be formed between each source / drain region on the substrate. The underlying layer 205 may also include other layers, such as one or more dielectric layers formed on the substrate, and one or more conductive plugs that connect the subsequently formed MIM stack 200 and an overlying metal layer (not shown) to the source / drain regions of the RERAM cells.

[0026] The memory cell dielectric 215 layer is implemented with a high-k dielectric material. Examples of suitable high-k dielectrics for the memory cell dielectric 215 layer include hafnium oxide (HfO 2 ), any doped HfO 2 Examples of suitable barrier metal materials include, but are not limited to, metal oxides such as hafnium zirconium oxide (HfZrO), tantalum oxide (TaOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), titanium oxide (TiOx), and mixtures thereof. In an exemplary embodiment, the top electrode 220 layer and the bottom electrode 210 layer may be implemented with a barrier metal material, such as TiN. However, it will be understood that TiN is merely an exemplary material and other electrode materials may be used, such as tantalum nitride, ruthenium, and the like. In one exemplary embodiment, the top electrode 220 layer includes 5-75 nm of TiN and the memory cell dielectric 215 layer includes 3-20 nm of HfO. 2 and the bottom electrode 210 layer includes 25 to 75 nm of TiN.

[0027] Although specific examples are described above, one of ordinary skill in the art will understand how other materials and / or layer thicknesses can be used to form the top electrode 220 layer, the memory cell dielectric 215 layer, and / or the bottom electrode 210 layer while practicing the techniques described herein. As described in more detail below, the top electrode 220 layer, the memory cell dielectric 215 layer, and the bottom electrode 210 layer can be subsequently etched to form the MIM stack 200 of one or more RERAM cells.

[0028] Prior to etching the MIM stack 200, one or more overlying layers may be formed on the top electrode 220 layer. In the exemplary embodiment shown in FIG. 2, an organic planarization layer (OPL) 225, an anti-reflective coating (ARC) layer 230, and a patterning layer 240 are formed on the top electrode 220 layer to pattern the stack. The OPL 225 may include, but is not limited to, 50-400 nm. The ARC layer 230 may include, but is not limited to, 5-50 nm. The ARC layer 230 may also be replaced with a dielectric layer with an ARC layer thereon, such as a low temperature oxide with a lower ARC layer thereon. The patterning layer 240 may be a patterned photoresist layer, a patterned hardmask layer, or another patterned layer. The OPL 225, the ARC layer 230, and the patterning layer 240 may be formed from a variety of materials commonly used for such purposes utilizing known semiconductor processing steps. Once the patterned layer 240 is formed, the layers shown in FIG. 2A may be etched to form the MIM stack 200 of one or more RERAM cells.

[0029] The etching process used to form the MIM stack 200 may be performed as one or more plasma etching process steps using one or more plasma etching chemistries. Additionally, the etching process may be performed in one or more plasma etching tools or plasma etching chambers. In one exemplary preferred embodiment, the etching of the MIM stack 200 is performed in a single plasma etching chamber. It will be appreciated that a wide variety of plasma etching tools may be used to etch the MIM stack 200. For example, the plasma etching tool may be an inductively coupled plasma (ICP) etching tool, a capacitively coupled plasma (CCP) etching tool, a microwave plasma etching tool, or other etching tool. Further examples of suitable plasma etching tools are described below with reference to FIG. 4.

[0030] In one example, the etchant used to etch the MIM stack 200 is boron trichloride (BCl 3 ), Chlorine (Cl 2 ), helium (He), argon (Ar), hydrogen (H 2 ), sulfur dioxide (SO 2 ), oxygen (O 2 ), nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), nitrogen (N 2 The etching may be plasma etching using any of a variety of etching gases, including but not limited to, SiO 2 ... and the like.

[0031] Once the top electrode 220, memory cell dielectric 215, and bottom electrode 210 layers have been etched to form the MIM stack 200, the MIM stack is encapsulated with an encapsulation layer 245. In some embodiments, the encapsulation layer 245 may include an oxygen-free dielectric material, such as, for example, silicon (Si) or silicon nitride (SiN). Other exemplary materials include organic polymers (e.g., SiO2, which can be oxidized in a plasma chamber using, for example, CH 4 , C 4 F 6, C 4 F 8 , C.H. 3 Examples of suitable dielectric layers include, but are not limited to, those made from precursors such as SiO2, SiO3, SiO4, and SiO5. In other embodiments, the encapsulation layer 245 may include an oxygen-containing dielectric material such as, for example, oxynitrides (ON), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN). As shown in FIG. 2B, the encapsulation layer 245 is deposited on the peripheral surfaces of the MIM stack 200 and the underlayer 205. In some embodiments, a relatively thin encapsulation layer 245 may be deposited, ranging from 2 to 50 nm, and even more preferably from 4 to 10 nm.

[0032] 2B, an encapsulation layer 245 is deposited in situ on the peripheral surfaces of the MIM stack 200 and the underlayer 205 while the substrate remains in the plasma etch chamber. The encapsulation layer 245 provides a layer of protection for the MIM stack from oxygen ingress that may occur in later process steps and also from ingress that may result from exposure of the MIM stack to atmospheric conditions.

[0033] The encapsulation layer 245 may be deposited in a single step, multiple steps, or repeated steps. In some embodiments, to deposit the encapsulation layer 245 on the MIM stack 200 (and surrounding surfaces) in a plasma etch chamber, one or more silicon-containing precursors (e.g., silicon tetrachloride (SiCl 4 ), silicon tetrafluoride (SiF 4 ), etc.) may be used. Other silicon precursors may be used, such as silane, other silicon tetrahalides, etc. In one exemplary embodiment, silicon tetrachloride (SiCl ) is used in a plasma etch chamber to deposit a silicon nitride (SiN) encapsulation layer 245. 4 ) precursors may be used. The sealing layer may include other materials such as, but not limited to, silicon oxynitride (SiON) or silicon. A variety of deposition processes may be used to form the layer, and in one embodiment, atomic layer deposition may be used. Atomic layer deposition may be performed in a plasma etch chamber.

[0034] For deposition of the encapsulation layer 245 in a plasma etch chamber, for example, a gas flow (e.g., SiCl 4 , SiF 4 , H 2 , Ar, N 2 , He, Cl 2 A wide range of parameters can be adjusted, including: high frequency (HF) / low frequency (LF) power settings, continuous wave / pulsed plasma, pressure settings, and chuck temperature. In one exemplary embodiment, process conditions for depositing the encapsulation layer 245 include 3-50 standard cubic centimeters per minute (SCCM) of SiCl 4 , 0~250SCCMH 2 and a gas flow of Ar of 200-500 SCCM; a pressure of 2-300 millitorr (mT); HF / LF power settings of 200-1000 W; and a chuck temperature of 0-100° C. The techniques used herein advantageously utilize the same process chamber to perform the deposition as that used to etch the MIM stack. Thus, the particular chemistry used to create the encapsulation layer may vary depending on the particular gases available in the etch process chamber. It will therefore be appreciated that the particular encapsulation layer deposited (and the process used for such deposition) may depend on the particular gases available in the etch chamber used to etch the MIM stack. Thus, one of ordinary skill in the art having the benefit of this disclosure will be able to coordinate the etch of the MIM stack (and the chemistry utilized) with the particular encapsulation deposition process (and the chemistry utilized therein).

[0035] In some embodiments, an optional post-deposition treatment may be performed in situ in a plasma etch chamber or ex-situ in another processing chamber to improve the deposition of the sealing layer 245. After depositing the sealing layer 245, for example, the sealing layer 245 may be etched with Ar, N 2 Alternatively, an in situ heat treatment can be performed in a plasma etch chamber to expose to He.

[0036] Once the encapsulation layer 245 has been deposited (and optionally treated), a further etching process (e.g., a spacer etch) may be performed in a plasma etch chamber to remove the encapsulation layer 245 from the top surface of the MIM stack 200 and the surrounding surfaces of the underlayer 205, as shown in FIG. 2C. The etch process used to perform the spacer etch may be performed as one or more plasma etch process steps using one or more plasma etch chemistries. The spacer etch may be performed in the same process chamber utilized to etch the MIM stack and deposit the encapsulation layer. Alternatively, the spacer etch may be performed in a different process chamber. The spacer etch may also remove remaining etch byproducts of the etch of the OPL 225, the etch of the ARC layer 230, or the etch of the MIM stack 200.

[0037] In some embodiments, the etch recipe used to etch the encapsulation layer 245 may include an oxygen-free plasma etch chemistry. In some embodiments, the oxygen-free plasma etch chemistry may be a hydrofluorocarbon or fluorocarbon based plasma etch chemistry. In one embodiment, the encapsulation dielectric is SiN and the plasma etch chemistry used for the spacer etch is C 4 H 9 F, H 2 , and Ar. Other etch chemistries may include Cl2, HBr, C4F8, CF4, C4F6, C4F8, etc. Etching the encapsulation layer 245 with an oxygen-free etch chemistry minimizes the impact of the spacer etch on oxygen vacancies in the memory cell dielectric 215.

[0038] In some embodiments, the RERAM cell formation may be completed by forming one or more dielectric layers over and around the MIM stack 200, forming trenches (or vias) in the dielectric layers, filling the trenches with conductors, and forming contacts to the MIM stack 200 of the RERAM cell and the source / drain regions of the RERAM cell. Other processing steps may also be performed as known in the art.

[0039] 3 illustrates an embodiment of a method 300 that can be used to form a MIM stack of a RERAM cell according to the technology disclosed herein. In some embodiments, the method 300 can form a first electrode layer (step 310), a memory cell dielectric layer (step 320), and a second electrode layer (step 330). The memory cell dielectric layer is disposed between the first electrode layer and the second electrode layer. The memory cell dielectric layer formed in step 320 can generally include a metal oxide selected from the group including hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), tantalum oxide (TaOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), or titanium oxide (TiOx), and mixtures thereof.

[0040] In step 340, the method 300 etches the first electrode layer, the memory cell dielectric layer, and the second electrode layer to form one or more metal-insulator-metal (MIM) stacks of one or more RERAM cells. As noted above, the etching performed in step 340 may be performed in at least one plasma etch chamber using one or more plasma etch chemistries.

[0041] In step 350, method 300 deposits an encapsulation layer on the one or more MIM stacks and surrounding surfaces. In some embodiments, the deposition performed in step 350 may be performed in situ in the same plasma etch chamber in which etching step 340 was performed (i.e., the at least one plasma etch chamber). In some embodiments, in step 350, one or more silicon precursors (silicon tetrachloride (SiCl)) are added to the at least one plasma etch chamber to deposit an encapsulation layer on the one or more MIM stacks and surrounding surfaces. 4 ) or silicon tetrafluoride (SiF 4 ) is provided. In some embodiments, the encapsulation layer deposited in step 350 can include an oxygen-free dielectric material, such as, for example, silicon (S) or silicon nitride (SiN). In other embodiments, the encapsulation layer can include an oxygen-containing dielectric material, such as, for example, an oxynitride (ON) or silicon oxynitride (SiON).

[0042] In step 360, method 300 removes the encapsulation layer from the top surface of the one or more MIM stacks and surrounding surfaces. In some embodiments, the removal performed in step 360 may be performed in-situ in the same plasma etch chamber in which etching step 340 and deposition step 350 were performed (i.e., the at least one plasma etch chamber). In some embodiments, an oxygen-free plasma etch chemistry may be used in the at least one plasma etch chamber to remove the encapsulation layer from the top surface of the one or more MIM stacks and surrounding surfaces. In some embodiments, the oxygen-free plasma etch chemistry may include a hydrofluorocarbon or fluorocarbon-based plasma etch chemistry.

[0043] The techniques described herein improve oxygen content control in RERAM cells while maintaining throughput. More specifically, the techniques described herein prevent oxygen ingress into memory cell dielectric 215 during subsequent substrate processing. Unlike the conventional process flow shown in Figures 1A-1E, the process flow shown in Figures 2A-2C and the method steps shown in Figure 3 improve throughput by depositing encapsulation layer 245 in-situ while the substrate remains in the plasma etch chamber used to etch MIM stack 200.

[0044] It should be noted that the techniques described herein may be utilized in a wide variety of processing equipment, including plasma processing systems, For example, the techniques may be utilized in plasma etch processing systems, plasma deposition processing systems, other plasma processing systems, and / or other types of processing systems.

[0045] 4 provides one exemplary embodiment of a plasma processing system 400 that may be used in connection with the disclosed technology and is provided for illustrative purposes only. The plasma processing system 400 may be a capacitively coupled plasma processing device, an inductively coupled plasma processing device, a microwave plasma processing device, a radial line slot antenna (RLSA™) microwave plasma processing device, an electron cyclotron resonance (ECR) plasma processing device, or other types of processing systems or combinations of systems. Thus, those skilled in the art will appreciate that the technology described herein may be utilized with any of a wide variety of plasma processing systems.

[0046] Plasma processing system 400 may be used for a wide variety of operations, including, but not limited to, etching, deposition, cleaning, plasma polymerization, plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), atomic layer etching (ALE), etc. The structure of plasma processing system 400 is well known, and the particular structure described herein is for illustrative purposes only. It will be understood that different and / or additional plasma processing systems may be implemented while still utilizing the techniques described herein.

[0047] 4, the plasma processing system 400 may include a process chamber 405. The process chamber 405 may be a pressure controlled chamber, as is known in the art. A substrate 410 (a semiconductor wafer in one example) may be held on a stage or chuck 415. As shown, an upper electrode 420 and a lower electrode 425 may be provided. The upper electrode 420 may be electrically connected to an upper radio frequency (RF) source 430 through an upper matching network 455. The upper RF source 430 provides an upper frequency voltage 435 at an upper frequency (f U The lower electrode 425 may be electrically connected to a lower RF source 440 through a lower matching network 457. The lower RF source 440 may provide a lower frequency voltage 445 at a lower frequency (f L ) Although not shown, one skilled in the art would know that a voltage may also be applied to the chuck 415.

[0048] The components of the plasma processing system 400 may be connected to and controlled by a control unit 470. The control unit 470 may further be connected to corresponding memory storage units and user interfaces (all not shown). Various plasma processing operations may be performed via the user interface and various plasma processing recipes and operations may be stored in the storage units. Thus, a given substrate may be processed using various micro-machining techniques in the plasma processing chamber. It will be appreciated that the control unit 470 may be coupled to the various components of the plasma processing system 400 to receive inputs from and provide outputs to the components.

[0049] The control unit 470 may be implemented in a wide variety of ways. For example, the control unit 470 may be a computer. In another example, the control unit may include one or more programmable integrated circuits programmed to provide the functions described herein. For example, one or more processors (e.g., microprocessors, microcontrollers, central processing units, etc.), programmable logic devices (e.g., complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), etc.), and / or other programmable integrated circuits may be programmed with software or other programming instructions to perform the functions of a prescribed plasma process recipe. Furthermore, it should be noted that the software or other programming instructions may be stored on one or more non-transitory computer-readable media (e.g., memory storage devices, flash memory, dynamic random access (DRAM) memory, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), as well as software or other programming instructions that, when executed by the programmable integrated circuit, cause the programmable integrated circuit to perform the processes, functions, and / or performance described herein. Other variations may also be implemented.

[0050] In operation, the plasma processing apparatus uses upper and lower electrodes to generate a plasma 460 in the process chamber 405 upon application of power to the system from an upper radio frequency (RF) source 430 and a lower RF source 440. Additionally, as is known in the art, ions generated in the plasma 460 may be attracted to the substrate 410. The generated plasma may be used to process a target substrate (such as the substrate 410 or any material to be processed) in various types of processes, such as, but not limited to, plasma etching and deposition.

[0051] Upon application of power, a high frequency electric field is generated between the upper electrode 420 and the lower electrode 425. The process gas delivered to the process chamber 405 may then be dissociated and converted into plasma. As shown in FIG. 4, the exemplary system described uses both an upper RF source and a lower RF source. For example, for an exemplary capacitively coupled plasma system, high frequency power in the range of about 3 MHz to 150 MHz or more may be applied from the upper RF source 430, and low frequency power in the range of about 0.2 MHz to 40 MHz may be applied from the lower RF source. Different operating ranges may also be used. Furthermore, it will be understood that the techniques described herein may be utilized in a variety of other plasma systems. In one exemplary system, the RF source may be switched (e.g., high frequency on the lower electrode and low frequency on the upper electrode). Furthermore, the dual source system is shown as merely an exemplary system, and it will be understood that the techniques described herein may be utilized in other systems where a frequency power source is provided to only one electrode, where a direct current (DC) bias source is used, or where other system components are used.

[0052] It should be noted that one or more deposition processes can be used to form one or more of the material layers described herein. For example, one or more depositions can be performed using chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other deposition processes. In one exemplary plasma deposition process, a precursor gas mixture including, but not limited to, silicon-containing gas, hydrocarbon, fluorocarbon, or nitrogen-containing hydrocarbon can be used in combination with one or more dilution gases (e.g., argon, nitrogen, etc.) at various pressure, power, flow rate, and temperature conditions. Furthermore, one or more etching processes can be performed using plasma etching processes, discharge etching processes, and / or other desired etching processes. For example, a plasma etching process can be performed using a plasma including fluorocarbon, oxygen, nitrogen, hydrogen, argon, and / or other gases.

[0053] Additionally, process step operating variables can be adjusted to control the various deposition and / or etching processes described herein. Operating variables can include, for example, chamber temperature, chamber pressure, gas flow rate, gas type, frequency and / or power applied to the electrode assembly in generating the plasma, and / or other operating variables of the processing steps. Variations can also be implemented while still utilizing the techniques described herein.

[0054] It should be noted that throughout this specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention, but do not indicate that it is present in all embodiments. Thus, the statements "in one embodiment" or "in an embodiment" in various places throughout this specification do not refer to the same embodiment of the invention. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. In alternative embodiments, various additional layers and / or structures may be included and / or described features may be omitted.

[0055] The term "substrate" as used herein means and includes a base material or structure on which a material is formed. It will be understood that a substrate may include a single material, multiple layers of different materials, one or more layers having regions of different materials or different structures, and the like. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, a substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate may be a conventional silicon substrate or other bulk substrate that includes a layer of semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates (e.g., silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates), epitaxial layers of silicon on a base semiconductor, and other semiconductor or optoelectronic materials (e.g., silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). The substrate may be doped or undoped.

[0056] Systems and methods for processing a substrate are described in various embodiments. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be a base substrate structure, such as a semiconductor substrate, or a layer on or overlying the base substrate structure, such as a thin film. Thus, the substrate is not intended to be limited to a particular base structure, underlying or overlying layer, patterned or unpatterned, but rather is intended to include any such layer or base structure and any combination of layers and / or base structures.

[0057] As will be appreciated by those skilled in the art, various embodiments may be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the various embodiments of the invention. Similarly, specific numbers, materials, and configurations are shown for purposes of explanation to provide a thorough understanding of the invention. However, the invention can be practiced without the specific details. Moreover, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0058] Further modifications and alternative embodiments of the described systems and methods will be apparent to those skilled in the art in view of this specification. It will therefore be understood that the described systems and methods are not limited by these exemplary configurations. It will be understood that the forms of the systems and methods shown and described herein should be construed as exemplary embodiments. Various changes can be made to the implementation. Thus, although the present invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention. Thus, the specification and figures should be considered in an illustrative rather than a restrictive sense, and such modifications are intended to be included within the scope of the present invention. Furthermore, any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not intended to be construed as critical, necessary, or essential features or elements of any or all of the claims.

Claims

1. 1. A method of forming a resistively-changeable random access memory (RERAM), comprising: forming a first electrode layer; forming a memory cell dielectric layer; forming a second electrode layer, the memory cell dielectric layer being disposed between the first electrode layer and the second electrode layer; etching the first electrode layer, the memory cell dielectric layer, and the second electrode layer to form one or more metal-insulator-metal (MIM) stacks of one or more RERAM cells, the etching being performed in at least one plasma etch chamber; depositing an encapsulation layer over the one or more MIM stacks and surrounding surfaces, said deposition being performed in the at least one plasma etch chamber; and Including, the depositing includes providing one or more silicon precursors to the at least one plasma etch chamber to deposit the encapsulation layer on the one or more MIM stacks and the surrounding surface. method.

2. 10. The method of claim 1, wherein the memory cell dielectric layer comprises a metal oxide selected from the group consisting of hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), tantalum oxide (TaOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), or titanium oxide (TiOx), and mixtures thereof.

3. 10. The method of claim 1, wherein the encapsulation layer comprises silicon (Si), silicon nitride (SiN), oxynitride (ON), or silicon oxynitride (SiON).

4. The method of claim 1, further comprising performing a thermal treatment on the sealing layer in the at least one plasma etching chamber.

5. The method of claim 1 , wherein the one or more silicon precursors comprise a silicon-containing gas.

6. The one or more silicon precursors may be silicon tetrachloride (SiCl ４ ) and silicon tetrafluoride (SiF ４ 2. The method of claim 1 , wherein the compound is selected from the group consisting of:

7. The method of claim 1 , further comprising performing a spacer etch process to remove the encapsulation layer from horizontal surfaces of the one or more MIM stacks and the surrounding surface.

8. A method for forming a resistively erasable random access memory (RERAM), comprising: forming a first electrode layer; forming a memory cell dielectric layer; forming a second electrode layer, the memory cell dielectric layer being disposed between the first electrode layer and the second electrode layer; etching the first electrode layer, the memory cell dielectric layer, and the second electrode layer to form one or more metal-insulator-metal (MIM) stacks of one or more RERAM cells, the etching being performed in at least one plasma etch chamber; depositing an encapsulation layer over the one or more MIM stacks and surrounding surfaces, said deposition being performed in the at least one plasma etch chamber; and performing a spacer etch process to remove the encapsulation layer from horizontal surfaces of the one or more MIM stacks and the surrounding surface; Including, the spacer etch also removes any etch by-products remaining after etching the first electrode layer, the memory cell dielectric layer, and the second electrode layer. method.

9. 9. The method of claim 7 or 8, wherein the performing a spacer etch process includes using an oxygen-free plasma etch chemistry in the at least one plasma etch chamber to remove the encapsulation layer from the horizontal surfaces of the one or more MIM stacks and the surrounding surface.

10. 9. The method of claim 7 or 8, wherein the deposition of an encapsulation layer prevents oxygen ingress into the memory cell dielectric layer when the encapsulation layer is removed from the horizontal surfaces of the one or more MIM stacks and the surrounding surface by leaving the encapsulation layer on sidewalls of the MIM stacks.

11. The method of claim 8, wherein the sealing layer comprises an organic material.

12. 1. A method of forming a resistively-changeable random access memory (RERAM), comprising: forming a first electrode layer; forming a memory cell dielectric layer; forming a second electrode layer, the memory cell dielectric layer being disposed between the first electrode layer and the second electrode layer; etching the first electrode layer, the memory cell dielectric layer, and the second electrode layer to form one or more metal-insulator-metal (MIM) stacks of one or more RERAM cells, the etching being performed in at least one plasma etch chamber; depositing an encapsulation layer over the one or more MIM stacks and surrounding surfaces, said deposition being performed in the at least one plasma etch chamber; and removing the encapsulation layer from a top surface of the one or more MIM stacks and the surrounding surface, the removing being performed in the at least one plasma etch chamber; Including, the depositing includes providing one or more silicon precursors to the at least one plasma etch chamber to deposit the encapsulation layer on the one or more MIM stacks and the surrounding surface. method.

13. 13. The method of claim 12, wherein the memory cell dielectric layer comprises a metal oxide selected from the group consisting of hafnium oxide (HfO), hafnium zirconium oxide (HfZrO), tantalum oxide (TaOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), or titanium oxide (TiOx), and mixtures thereof.

14. The method of claim 12 , wherein the encapsulation layer comprises silicon (Si) or silicon nitride (SiN).

15. The method of claim 12 , wherein the sealing layer comprises an oxynitride (ON) or a silicon oxynitride (SiON).

16. The method of claim 12, further comprising performing a thermal treatment on the sealing layer in the at least one plasma etching chamber prior to the removal.

17. The method of claim 12 , wherein the one or more silicon precursors comprise a silicon-containing gas.

18. The one or more silicon precursors may be silicon tetrachloride (SiCl ４ ) and silicon tetrafluoride (SiF ４ 13. The method of claim 12, wherein the compound is selected from the group consisting of:

19. The one or more silicon precursors may be silicon tetrachloride (SiCl ４ 13. The method of claim 12, comprising:

20. 13. The method of claim 12, wherein the removing comprises using an oxygen-free plasma etch chemistry in the at least one plasma etch chamber to remove the encapsulation layer from the top surface of the one or more MIM stacks and the surrounding surface.

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