Amorphous Silicon Base Removal and Seal EOT

Abstract

A sacrificial seal layer is formed on a high-k metal gate (HKMG) stack to inhibit oxidizing agents, such as oxygen and water, from affecting the metal gate stack, thus preserving the device EOT. The method integrated a process including forming an interface layer on a substrate, forming a high-k metal oxide layer on the interface layer, where the high-k metal oxide layer includes a dipole region adjacent to the interface layer, the dipole region, depositing a capping layer on the high-k metal oxide layer, and forming a sacrificial seal layer on the capping layer. The dipole region is formed by driving a dopant species of a dipole film, such as zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or a mixture thereof, into the high-k metal oxide layer to form a dipole region.

Description

[Technical field]

[0001]

[0003] Embodiments of the present disclosure generally relate to inhibiting oxidizing agents (e.g., atomic oxygen) from affecting a metal gate stack. In a particular embodiment, a sacrificial seal layer is formed on a high-k metal gate (HKMG) stack, the high-k metal gate stack including a high-k metal oxide layer including a dipole region. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased and geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] As device dimensions shrink, device geometries and materials have experienced difficulty maintaining switching speeds without incurring failure. Several new technologies have emerged that enable chip designers to continue to shrink device dimensions. Controlling the dimensions of device structures is a key challenge for current and future technology generations.

[0004] Microelectronic devices are fabricated on semiconductor substrates as integrated circuits in which various conductive layers are interconnected to allow electronic signals to propagate within the devices. One example of such a device is a complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) or MOSFET. A gate electrode is part of the integrated circuit. For example, a MOSFET comprises a gate structure disposed between a source region and a drain region formed in a semiconductor substrate. The gate structure or stack generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed on the gate dielectric to control the flow of charge carriers in a channel region formed between the drain region and the source region below the gate dielectric.

[0005] Easy-to-manufacture metals with electronegativity greater than hafnium (Hf, 1.3), such as aluminum (Al, 1.61), niobium (Nb, 1.6), titanium (Ti, 1.54), and tantalum (Ta, 1.5), can induce dipoles that are favorable for PMOS. To achieve the desired dipole effect, the desired elements are driven out of the deposited film with a spike anneal and removed after drive in. The spike anneal can potentially cause an equivalent oxide thickness (EOT) penalty as free oxygen atoms in the gate dielectric layer and the overlying dipole stack diffuse downward and oxidize the underlying silicon layer.

[0006] Therefore, a method is needed to prevent the equivalent oxide thickness penalty. Summary of the Invention

[0007] One or more embodiments of the present disclosure are directed to a method of forming a metal gate stack. In one or more embodiments, the method of forming a metal gate stack includes forming an interface layer on a surface of a substrate, depositing a high-k metal oxide layer on the interface layer, forming a dipole film on the high-k metal oxide layer, depositing a first capping layer on the substrate, forming a sacrificial seal layer on the first high-k metal oxide capping layer, exposing the substrate to a heat treatment at a temperature of at least 700° C. to drive the dipole film into the high-k metal oxide layer and to form a dipole region, and removing the sacrificial seal layer.

[0008] Additional embodiments of the present disclosure are directed to a method of scavenged an oxidant from a metal gate stack. In one or more embodiments, the method includes forming a sacrificial seal layer on a metal gate stack, the metal gate stack including a first capping layer on a dipole film on a high-k metal oxide layer on an interfacial layer on a surface of a substrate, exposing the metal gate stack to a heat treatment at a temperature of at least 700° C. to drive the dipole film into the high-k metal oxide layer and to form a dipole region, and removing the sacrificial seal layer.

[0009] So that the above recited features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical embodiments of the present disclosure and therefore should not be considered limiting of its scope, as the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0010] [Figure 1] AG are cross-sectional views of metal gate stacks according to one or more embodiments of the present disclosure. [Diagram 2] 1 is a flowchart of a method for forming a dipole region in accordance with one or more embodiments of the present disclosure. [Diagram 3] 2 is a flowchart of a method for forming a metal gate stack according to FIG. 1 in accordance with one or more embodiments of the present disclosure. [Figure 4] 1 is a cluster tool according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Before describing certain example embodiments of the present disclosure, it is to be understood that the disclosure is not limited to the details of structure or process steps set forth in the following description as the disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0012] The term "substrate" as used herein and in the appended claims refers to a surface or portion of a surface on which a process acts. Those skilled in the art will appreciate that a reference to a substrate may also refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, a reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0013] "Substrate" as used herein refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0014] The embodiments of the present disclosure advantageously provide a method to prevent the as-deposited dipole film from being oxidized. In one or more embodiments, a sealing layer is deposited on the top surface of the gate stack, which is then annealed to drive the dipole elements into the cap layer and the high-k layer. Without intending to be bound by theory, it is believed that the sealing layer can remove excess oxidizing agents (e.g., oxygen atoms, water, etc.) from the high-k layer and minimize the equivalent oxide thickness (EOT) increase. After annealing, the sealing layer is removed and the resulting gate stack is subjected to post-processing.

[0015] The gate stack can include one or more of a gate dielectric or high-k metal oxide layer having a dipole region, a capping layer, and a metal gate work function layer. The dipole region can be in the high-k metal oxide layer adjacent to the interfacial layer.

[0016] The equivalent oxide thickness (EOT) provides the characteristics of the interface layer and the high-k layer. Experiments targeting the equivalent oxide thickness (EOT) for Nb-containing dipole regions showed that depositing a seal capping layer on a metal gate state does not result in an EOT penalty (< about 0.2 Å). In the experiments, a seal layer containing amorphous silicon with a thickness ranging from 5 Å to 40 Å was deposited by atomic layer deposition on a metal gate stack. The dipole stack included a dipole film (e.g., niobium nitride (NbN) or titanium aluminum nitride (TiAlN)) on a high-k metal oxide layer containing hafnium oxide (HfO2), which was located on an interface layer of SiO2 on a substrate. A TiN capping layer was deposited in situ on the dipole film using ALD. After deposition of the amorphous silicon seal layer, the dipole film was driven into the high-k metal oxide layer by a heat treatment at a substrate temperature of at least 700°C.

[0017] One or more embodiments of the present disclosure provide devices, and methods of formation, that are particularly useful in forming positive metal oxide semiconductor (PMOS) integrated circuit devices, and will be described in that context. Other devices and applications are also within the scope of the invention.

[0018] 1A-1F illustrate cross-sectional views of an exemplary PMOS metal gate stack device 100 in accordance with one or more embodiments. With reference to FIG. 1A, device 100 includes a substrate 110 having a surface thereof oxidized to form an interfacial layer 115. Substrate 110 may include any suitable material known to those of skill in the art. In some embodiments, substrate 110 includes silicon. Interfacial layer 115 may include any suitable material known to those of skill in the art. In one or more embodiments, interfacial layer 115 is formed of a material selected from the group consisting of silicon dioxide, silicon germanium oxide (SiGeO), and the like. x ), germanium oxide (GeO x ), or silicon oxynitride (SiON). In one or more particular embodiments, the interface layer 115 comprises silicon dioxide. In some embodiments, the substrate includes additional electrical elements and materials, including, but not limited to, source regions, drain regions, conductive channels, and other electrical connectors.

[0019] 1B, a high-k metal oxide layer 120 is formed on the metal gate stack device 100. The high-k metal oxide layer 120 may include any suitable material known to those skilled in the art. In one or more embodiments, the high-k metal oxide layer 120 includes one or more of hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), hafnium silicon oxide (HfSiO), and hafnium silicon oxynitride (HfSiON). In one or more particular embodiments, the high-k metal oxide layer 120 includes hafnium oxide (HfO2).

[0020] In one or more embodiments, a dipole film 125 is formed on the high-k metal oxide layer 120. The dipole film 125 may include any suitable material known to one of skill in the art. In one or more embodiments, the dipole film 125 includes a nitride, carbide, oxide, carbonitride, or combination thereof, of a dipole metal. In one or more embodiments, the dipole metal includes zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or a mixture thereof. In one or more embodiments, the dipole film 125 includes niobium nitride (NbN). In other embodiments, the dipole film 125 includes titanium aluminum nitride (TiAlN).

[0021] 1C, a capping layer 130 is formed on the dipole film 125. The dipole film 125 is on the high-k metal oxide layer 120 adjacent to the capping layer 130.

[0022] The high-k metal oxide layer 120 and the metal gate work function layer 140 together may be referred to herein as a metal gate stack.

[0023] The capping layer 130 may comprise any suitable material known to those of skill in the art. In some embodiments, the capping layer 130 comprises or consists essentially of titanium nitride (TiN). In some embodiments, the capping layer 130 comprises or consists essentially of titanium silicon nitride (TiSiN). As used in this context, "consists essentially of" means that the stated element constitutes, on an atomic basis, greater than 95%, greater than 98%, greater than 99%, or greater than 99.5% of the stated material. For the avoidance of doubt, no stoichiometric ratio is implied by the identification of the materials disclosed herein. For example, a TiN material comprises titanium and nitrogen. These elements may or may not be present in a 1:1 ratio.

[0024] The capping layer 130 may have any suitable thickness. In some embodiments, the thickness of the capping layer 130 is in the range of 5 Å or more to 25 Å or less. In some embodiments, the thickness of the capping layer 130 is about 10 Å, including 10 ű10%, 10 ű5%, and / or 10 ű1%.

[0025] 1D , in one or more embodiments, a sacrificial sealing layer 150 is formed on the metal gate stack device 100. In one or more embodiments, the sacrificial sealing layer 150 is formed on the PMOS work function material 140. The sacrificial sealing layer 150 may comprise any suitable material known to those of skill in the art. In one or more embodiments, the sacrificial sealing layer 150 comprises amorphous silicon (a-Si).

[0026] The sacrificial sealing layer 150 can have any suitable thickness. In one or more embodiments, the sacrificial sealing layer 150 has a thickness in the range of 5 Å to 50 Å, including the range of 10 Å to 40 Å.

[0027] 1E, the metal gate stack device 100 is thermally treated to drive the dipole film 125 into the high-k metal oxide layer 120 and to form a dipole region 128 in the high-k metal oxide layer 120. The thermal treatment is performed to cause a dopant species, such as zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, to diffuse into the underlying high-k gate metal oxide layer 120.

[0028] The equivalent oxide thickness (EOT) provides a characteristic of the interface layer and the high-k layer. In one or more embodiments, a metal gate stack including a sacrificial seal layer 150 has an EOT increase of about 0.2 Å or less over a comparison metal gate stack without a sacrificial seal layer. When no sacrificial seal layer is present, a gate stack with dipole regions 128 has an EOT of about 10.0 to 10.5 Å. In embodiments in which a sacrificial seal layer is deposited, a gate stack with dipole regions 128 has an EOT in the range of about 8.6 Å to less than 9 Å.

[0029] 1F, after driving the dopants of the dipole film 125 into the high-k metal oxide layer 120 to form the dipole regions 128, the sacrificial seal layer 150 is removed, followed by removal of the capping layer 130. The result is a device 100 having a high-k metal oxide layer 120 with dipole regions 128 on the interfacial layer 115 on the substrate 110.

[0030] 1G, in some embodiments, a second capping layer 160, e.g., a high-k metal oxide capping layer, may be formed on the substrate, and a metal gate work function layer 140 is formed on the second capping layer 160. In other embodiments, the second capping layer 160 is not present. As used herein, the metal gate work function layer 140 is sometimes referred to as a "PMOS work function material."

[0031] The high-k metal oxide layer 120 electrically insulates the metal gate workfunction layer 140 from the substrate 110. The high-k metal oxide layer 120 and the metal gate workfunction layer 140 together may be referred to herein as a high-k metal gate stack.

[0032] The PMOS work function material 140 may include any suitable material. The PMOS work function material 140 may have any suitable thickness. In some embodiments, the thickness of the PMOS work function material 140 is in the range of 5 Å to 50 Å. In some embodiments, the thickness of the metal gate work function layer is about 15 Å, including 15 ű10%, 15 ű5%, and / or 15 ű1%. In some embodiments, the thickness of the metal gate work function layer is about 25 Å, including 25 ű10%, 25 ű5%, and / or 25 ű1%. In other embodiments, the thickness of the metal gate work function layer is about 40 Å, including 40 ű10%, 40 ű5%, and / or 40 ű1%.

[0033] In some embodiments, the metal gate stack device 100 further comprises a gate electrode 180. The gate electrode 180 may include multiple layers. In some embodiments, the gate electrode 180 includes a first layer including TiAl and a second layer including TiN. In some embodiments, the first layer has a thickness of 20 Å to 50 Å. In some embodiments, the first layer has a thickness of about 25 Å, including 25 ű10%. In some embodiments, the first layer has a thickness of about 40 Å, including 40 ű10%. In some embodiments, the second layer has a thickness of about 500 Å, including 500 ű10%, 500 ű5%, and / or 500 ű1%. The first and second layers may be deposited by any suitable method.

[0034] 2, another embodiment of the present disclosure relates to a method 200 of forming a gate stack. The method 200 begins in operation 210 by optionally providing a substrate to a processing chamber.

[0035] In operation 215, an interface layer is formed on the substrate. Formation of the interface layer may include a suitable thermal oxidation process, such as an enhanced in situ steam generation (eISSG) process using nitrous oxide (NO) gas. In one or more embodiments, the interface layer (e.g., 115 in FIG. 1) is a thin amorphous silicon oxide (SiO2) layer having a thickness between about 3 Å and about 10 Å, e.g., about 5 Å, corresponding to one or more monolayers of silicon oxide. In some embodiments, the interface layer may be formed by an in situ steam generation (ISSG) process using H2 and O2 gases, or by a rapid thermal oxidation (RTO) process using NH3 and O2 gases, or by a wet chemical oxidation process (e.g., Standard Clean 1 (SC1) solution including NH4OH (ammonium hydroxide), H2O2 (hydrogen peroxide), and H2O (water)), or by an ozone (O3) wet chemical process. The interfacial layer may act as a nucleation layer for a high-k gate dielectric layer (eg, 120 in FIG. 1) to be deposited thereon.

[0036] In operation 220, a high-k metal oxide layer is deposited on the interfacial layer. The high-k gate metal oxide layer may be formed from a high-k dielectric material such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), ytterbium oxide (YO3), aluminum oxide (Al2O3), or a ternary high-k dielectric film in which a third element is doped into an existing metal oxide high-k dielectric host material such as HfZrO, HfLaOx, or HfTiO. The deposition process may include an atomic layer deposition (ALD) process in which a metal-containing precursor and an oxygen-containing precursor are alternately delivered to the interfacial layer. In some embodiments, the metal-containing precursor is purged prior to delivering the oxygen-containing precursor. The metal may be a transition metal, such as hafnium (Hf), zirconium (Zr), or titanium (Ti), a rare earth metal, such as lanthanum (La), ytterbium (Yb), or yttrium (Y), an alkaline earth metal, such as strontium (Sr), or other metals, such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen-oxygen-containing precursor, plasma-enhanced oxygen, including locally or remotely enhanced oxygen, or any other material containing oxygen that can be incorporated with the metal to create a layer of oxide of the metal on the interfacial layer. In one example, to form a hafnium dioxide (HfO2) layer, the metal-containing precursor is hafnium tetrachloride (HfCl4) and the oxidant is water (H2O). The ALD process may be carried out at a temperature between 200°C and about 400°C, for example, about 270°C. The metal oxide layer deposited by the ALD process is amorphous and can have a thickness between about 10 Å and about 30 Å.

[0037] Beginning at operation 230, the substrate is not removed from the processing chamber. The system is integrated such that the substrate is not exposed to an atmosphere containing moisture, water (H2O), or oxygen (O2). At operation 230, a dipole film is prepared on the high-k metal oxide layer. In one or more embodiments, the dipole film comprises a nitride, carbide, oxide, carbonitride, or combination thereof, of a dipole metal. In one or more embodiments, the dipole metal comprises zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or a mixture thereof.

[0038] In one or more embodiments, the dipole film is one or more of a zinc-containing film, a vanadium-containing film, a tungsten-containing film, a molybdenum-containing film, a ruthenium-containing film, a tantalum-containing film, a titanium-containing film, a zirconium-containing film, an aluminum-containing film, or a niobium-containing film. The dipole film may be deposited by atomic layer deposition (ALD) at a substrate temperature in the range of 350° C. to 500° C. The ALD cycle may be repeated to obtain a desired thickness of the dipole metal-containing film, for example, 5 Å to 10 Å. In some embodiments, the deposition of the dipole film is performed by blanket deposition of the dipole film over the entire exposed surface of the high-k gate dielectric layer, followed by a lithography and etching process to pattern the dipole film (i.e., to form the dipole film in some regions of the semiconductor structure and not in some other regions of the semiconductor structure). In a subsequent thermal treatment (in operation 250), e.g., an annealing process, dopant species, e.g., Zn, V, W, Mo, Ru, Ta, Ti, Al, Zr, or Nb, from the dipole film diffuse and become incorporated into the underlying high-k gate dielectric layer to form dipole regions.

[0039] In one or more embodiments, the dipole film is prepared on the high dielectric constant metal oxide layer by exposing the surface of the substrate to a first precursor containing a dipole metal and, optionally, to a second precursor containing nitrogen, oxygen, or carbon, using atomic layer deposition at a first substrate temperature in the range of 350°C to 500°C. Generally, any suitable dipole metal precursor may be used. For NbN films, for example, niobium precursors may include, but are not limited to, NbCl5, NbB5, NbBr5, NbI5, NbF5, organic niobium compounds, and combinations thereof.

[0040] In one or more embodiments, the second precursor can include, but is not limited to, NH3, N2, N2H2, N2H4, nitrogen-containing plasma, and combinations thereof.

[0041] In one or more embodiments, the second precursor comprises a second compound selected from the group consisting of H2O, H2O2, O3, ethanol, and combinations thereof. In one or more embodiments, the second precursor comprises a second compound selected from the group consisting of CH4, ethanol, and H2. In one or more embodiments, the second precursor comprises a combination of two or more second compounds selected from the group consisting of NH3, CH4, ethanol, and H2.

[0042] In operation 240, a capping layer is deposited on the dipole film. In one or more embodiments, the capping layer is deposited by atomic layer deposition (ALD). In one or more embodiments, the capping layer comprises titanium nitride (TiN). An exemplary process for depositing TiN includes exposing a substrate to a first precursor comprising Ti and then to a second precursor comprising a nitrogen source to provide a TiN film. In some embodiments, the substrate is repeatedly exposed to the precursors to obtain a predetermined film thickness. In some embodiments, the substrate is maintained at a temperature between about 200° C. and about 700° C. during the ALD process.

[0043] In operation 245, a sacrificial seal layer is deposited on the substrate. In one or more embodiments, the sacrificial seal layer includes an amorphous silicon (a-Si) material. The sacrificial seal layer may physically and chemically protect the underlying high-k metal oxide layer and the first capping layer during a subsequent thermal treatment process in operation 250. The sacrificial seal layer may be formed from amorphous silicon, such as hydrogenated amorphous silicon (a-Si:H). Amorphous silicon may provide less diffusion of atoms compared to polycrystalline silicon, which includes grain boundaries that guide paths for diffusion.

[0044] The sacrificial sealing layer may be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process in which the semiconductor structure on which the first capping layer is formed is exposed to a silicon precursor. An example of a silicon precursor is polysilane (Si x H y For example, polysilanes are disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), isotetrasilane, neopentasilane (Si5H 12 ), cyclopentasilane (Si5H 10 ), Hexasilane (C6H 14 ), cyclohexasilane (Si6H 12 ), or generally, Si with x=2 or more x H y and combinations thereof. The sacrificial seal layer may have a thickness between about 5 Å and about 50 Å.

[0045] In operation 250, the substrate is thermally treated to drive the dipole film into the high-k metal oxide layer and to form dipole regions in the high-k metal oxide layer. The thermal treatment is performed to cause the dipole metal dopant species, such as Zn, V, W, Mo, Ru, Ta, Ti, Zr, Al, or Nb, or mixtures thereof, to diffuse into the underlying high-k gate metal oxide layer. In one or more embodiments, the thermal treatment of operation 250 includes a post cap anneal (PCA) process that is performed to harden and densify the first capping layer. Crystallization of the as-deposited first capping layer and the as-deposited sacrificial silicon cap layer can occur. The PCA process can include an annealing process. The annealing process may include a thermal annealing process in an inert environment, such as in a nitrogen (N2) and argon (Ar) environment, performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, California.

[0046] The thermal treatment of operation 250 may be carried out at a temperature between about 600° C. and about 1000° C., for example, about 900° C., and at a pressure between about 0.1 Torr and 100 Torr, for a time period between about 1 second and about 30 seconds.

[0047] In operation 260, the substrate may be removed from the processing chamber and exposed to moisture, water, or oxygen. According to one or more embodiments, in operation 260, the sacrificial seal layer and the remaining portions of the dipole film along with the capping layer are removed. The removal process may include a dry plasma etching process. The resulting structure, including the high-k metal oxide layer with doped regions, may then be further processed for a desired application.

[0048] An aspect of the present specification is a method of forming a metal gate stack, the method including providing an interfacial layer on a surface of a substrate, depositing a high-k metal oxide layer on the interfacial layer, and insulating the surface of the substrate using atomic layer deposition at a first substrate temperature in the range of 350° C. to 500° C. with a dipolar metal, for example, zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or a combination thereof. The method includes preparing a dipole film on the high-k metal oxide layer by exposing the substrate to a first precursor comprising these mixtures and, optionally, to a second precursor comprising nitrogen, oxygen, or carbon; depositing a first capping layer on the substrate; depositing an amorphous silicon layer on the substrate; and exposing the substrate to a heat treatment at a second substrate temperature of at least 700° C. to drive the dipole film into the high-k metal oxide layer and to form a dipole region comprising the dipole metal adjacent the interfacial layer.

[0049] In one or more embodiments, the method further includes removing the sacrificial sealing layer, removing a remaining portion of the dipole membrane, and removing the first capping layer.

[0050] Referring to Figure 3, another embodiment of the present disclosure relates to a method 300 of forming a metal gate stack device. The method 300 begins at 310 by optionally providing a substrate in a first processing chamber. At operation 315, an interface layer is formed on the substrate, following operation 215 described with respect to Figure 2. At operation 320, a high-k metal oxide layer is deposited on the interface layer, following operation 220 described with respect to Figure 2. At operation 330, a dipole film is provided on the high-k metal oxide layer, following operation 230 described with respect to Figure 2. At operation 340, a capping layer is deposited on the dipole film, following operation 240 described with respect to Figure 2.

[0051] In one or more embodiments, the capping layer is deposited on the bipolar membrane in situ, in that the same processing (first) chamber is used for both operation 330 and operation 340.

[0052] In operation 345, a sacrificial sealing layer is deposited over the substrate, following operation 245 described with respect to Figure 2. In one or more embodiments, the sacrificial sealing layer comprises an amorphous silicon (a-Si) material.

[0053] In operation 350, the substrate is thermally treated to drive the dipole film into the high-k metal oxide layer and to form dipole regions in the high-k metal oxide layer.

[0054] After deposition to thermally treat the substrate, according to one or more embodiments, the substrate may be transferred to a different (second) processing chamber for operation 360. In some embodiments, the first and second processing chambers are integrated. In some embodiments, method 300 is performed without breaking vacuum or exposing to ambient air.

[0055] In operation 360, the sacrificial seal layer and the remaining portion of the dipole film together with the capping layer are removed. Then, in operation 370, another (second) capping layer may be deposited on the high-k metal oxide layer. In some embodiments, depositing a second capping layer is optional. In operation 380, a PMOS work function material may be deposited on the second capping layer, or on the high-k metal oxide layer if no capping layer is present. In operation 390, a gate material is deposited on the PMOS work function material.

[0056] Many precursors fall within the scope of the present invention. Precursors can be plasmas, gases, liquids or solids at ambient temperature and pressure. However, in the ALD chamber, the precursors are volatilized. Organometallic compounds or complexes include any chemical that contains a metal and at least one organic group, such as alkyl, alkoxyl, alkylamide, and anilide. Precursors can be composed of organometallic compounds and inorganic / halide compounds.

[0057] Generally, any suitable titanium precursor can be used for the capping layer. Thus, titanium precursors can include, but are not limited to, TiCl4, TiBr4, TiI4, TiF4, tetrakisdimethylaminotitanium. Furthermore, any suitable nitrogen source precursor can be used. Examples include, but are not limited to, nitrogen gas, ammonia gas, N2H2, or N2H4.

[0058] An aspect of the present disclosure is a method of manufacturing a metal gate stack, the method including: providing an interfacial layer on a surface of a substrate in a first processing chamber; depositing a high-k metal oxide layer on the interfacial layer in the first processing chamber; and exposing the surface of the substrate to a first precursor comprising a dipolar metal, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, and optionally a second precursor comprising nitrogen, oxygen, or carbon, in the first processing chamber using atomic layer deposition at a first substrate temperature in the range of 350° C. to 500° C. the substrate in a first processing chamber; depositing a first capping layer on the substrate in a first processing chamber; forming a sacrificial seal layer on the substrate; exposing the substrate to a heat treatment at a second substrate temperature in the range of 700° C. to 1050° C. to drive the dipole film into the high-k metal oxide layer and to form a dipole region adjacent to the interfacial layer comprising a dipole metal, e.g., Zn, V, W, Mo, Ru, Ta, Ti, Zr, or Nb; transferring the substrate to a second processing chamber; and removing the sacrificial seal layer, removing the first capping layer, and removing a remaining portion of the dipole film.

[0059] In one or more embodiments, the method further includes depositing a second capping layer over the substrate.

[0060] In one or more embodiments, the method further includes depositing a PMOS work function material over the substrate.

[0061] In one or more embodiments, the method further includes depositing a gate material over the substrate.

[0062] In one or more embodiments, the first capping layer comprises titanium nitride (TiN), the high dielectric constant metal oxide layer comprises hafnium oxide (HfO2), and the interfacial layer comprises silicon dioxide (SiO2).

[0063] In one or more embodiments, the method further includes the second capping layer comprising TiN.

[0064] In one or more embodiments, preparing the interfacial layer includes oxidizing the surface of the substrate prior to depositing the high dielectric constant metal oxide layer.

[0065] The order in which the substrate is exposed to the precursors can be varied. The exposures can be repeated in a deposition cycle. Further, the exposures to the precursors can be repeated within a single deposition cycle.

[0066] The disclosed method may be carried out in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is transferred from the first chamber to a separate second chamber for further processing. The substrate may be transferred directly from the first chamber to a separate processing chamber, or the substrate may be transferred from the first chamber to one or more transfer chambers and then to a separate processing chamber. Thus, a suitable processing device may include multiple chambers in communication with a transfer station. This type of device may be referred to as a "cluster tool" or a "clustered system" or the like.

[0067] Generally, a cluster tool is a modular system with multiple chambers that perform various functions, including substrate center-finding and orientation, annealing, deposition, and / or etching. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber may house a robot that can shuttle substrates between processing chambers and load lock chambers. The transfer chamber is generally maintained in vacuum conditions and provides an intermediate stage for shuttling substrates from one chamber to another and / or to a load lock chamber located at the front end of the cluster tool. Two well-known cluster tools that may be adapted for the present disclosure are the Centura® and Endura®, both available from Applied Materials, Inc. of Santa Clara, Calif. However, the exact arrangement and combination of chambers may be varied for the purposes of performing the specific steps of the processes described herein. Other processing chambers that may be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal treatments such as RTP, plasma nitridation, annealing, orientation, hydroxylation, and other substrate processes. By performing processes in chambers on a cluster tool, surface contamination of the substrate by atmospheric impurities can be avoided without oxidation prior to depositing a subsequent film.

[0068] In some embodiments, the first processing chamber and the second processing chamber are part of the same clustered processing tool, and thus, in some embodiments, the method is an in-situ integrated method.

[0069] In some embodiments, the first processing chamber and the second processing chamber are different processing tools. Thus, in some embodiments, the method is an ex-situ integrated method.

[0070] According to one or more embodiments, the substrate is continuously under vacuum or "load-lock" conditions and is not exposed to ambient air as it is being transferred from one chamber to the next. The transfer chamber is therefore under vacuum and is "pumped down" under vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, the purge gas is injected at the outlet of the deposition chamber to prevent the reactants from transferring from the deposition chamber to the transfer chamber and / or to the additional processing chamber. Thus, the flow of the inert gas forms a curtain at the outlet of the chamber.

[0071] Substrates may be processed in single-substrate deposition chambers, where a single substrate is loaded, processed, and unloaded before another substrate is processed. Substrates may also be processed continuously, as with a conveyor system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and associated conveyor system may form a linear or curved path. Additionally, the processing chamber may be a carousel, where multiple substrates are moved about a central axis and exposed to deposition, etching, annealing, and / or cleaning processes throughout the carousel path.

[0072] The substrate may also be stationary or rotated during processing. A rotating substrate may be rotated continuously or in discreet steps. For example, the substrate may be rotated throughout the entire process, or the substrate may be rotated only small amounts between exposures to different reactive or purge gases. Rotating the substrate during processing (either continuously or in steps) may help create a more uniform deposition or etch, for example, by minimizing the effects of local variability in gas flow profiles.

[0073] In atomic layer deposition type chambers, the substrate can be exposed to a first precursor and a second precursor by either a spatially separated process or a temporally separated process. Temporal ALD is a traditional process in which a first precursor flows into the chamber and reacts with the surface. The first precursor is purged from the chamber before flowing the second precursor. In spatial ALD, both the first and second precursors are flowed into the chamber at the same time, but are spatially separated such that there is a region between their flows that prevents the precursors from mixing. In spatial ALD, the substrate is moved relative to the gas distribution plate, or vice versa.

[0074] In embodiments where one or more of the method parts are carried out in one chamber, the process may be a spatial ALD process. Although one or more of the chemistries described above may be incompatible (i.e., resulting in reaction other than on the substrate surface and / or deposition on the chamber), spatial separation ensures that the reagents are not exposed to each other in the gas phase. For example, temporal ALD involves purging the deposition chamber. However, in practice, it may not be possible to purge excess reagents from within the chamber before flowing in additional reagents. Thus, the remaining reagents in the chamber may react. With spatial separation, excess reagents do not need to be purged, limiting cross-contamination. Furthermore, more time may be used to purge the chamber, thus increasing throughput by eliminating the purge step.

[0075] With reference to FIG. 4, an additional embodiment of the present disclosure is directed to a processing tool 900 that can be used with one or more embodiment processing chambers to perform the described methods.

[0076] The cluster tool 900 includes at least one central transfer station 921, 931 with multiple sides. Robots 925, 935 are disposed within the central transfer stations 921, 931 and configured to move a robot blade and a wafer to each of the multiple sides.

[0077] The cluster tool 900 comprises a number of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. The various processing chambers provide separate processing regions isolated from adjacent process stations. The processing chambers may be any suitable chamber, including, but not limited to, pre-clean chambers, buffer chambers, transfer space(s), wafer orienter / degassing chambers, cool-down chambers, deposition chambers, annealing chambers, etching chambers, thermal processing (RTP) chambers, plasma oxidation chambers, plasma nitridation chambers, atomic layer deposition (ALD) chambers. The particular arrangement of process chambers and components may vary depending on the cluster tool and should not be taken as limiting the scope of the present disclosure.

[0078] 4, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front side 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one of ordinary skill in the art will understand that this represents only one possible configuration.

[0079] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary depending on, for example, the substrate being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette, in which multiple wafers are placed.

[0080] A robot 952 resides in the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 through the factory interface 950. The robot 952 can transfer wafers from a load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be appreciated by one of ordinary skill in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0081] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 disposed therein. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located with respect to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 in some embodiments is a multi-arm robot capable of independently moving two or more wafers at a time. In one or more embodiments, the first transfer chamber 921 includes two or more robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are transferred onto a wafer transport blade located at the distal end of the first robotic mechanism.

[0082] After processing the wafer in the first section 920, the wafer may be passed through a pass-through chamber to the second section 930. For example, the chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cool the wafer before processing in the second section 930 or to allow wafer cooling or post-processing before moving back to the first section 920.

[0083] A system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0084] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Also, some or all of the methods of the present disclosure may be performed in hardware. Thus, the processes may be implemented in software and executed in hardware using a computer system, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the chamber operation so that the processes are performed.

[0085] In some embodiments, the controller 990 controls multiple process chambers and metrology stations. the substrate comprises one or more configurations selected from a configuration for transferring the substrate on a robot to and from a robotic station, a configuration for loading and / or unloading the substrate from the system, a configuration for forming an interfacial layer on a surface of the substrate, a configuration for depositing a high-k metal oxide layer, a configuration for depositing a dipole metal (e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof) film, a configuration for depositing a first capping layer, a configuration for depositing a sacrificial sealing layer, a configuration for heat treating the substrate and driving the dipole-containing film into the high-k metal oxide layer, a configuration for removing a sacrificial sealing layer, a configuration for removing remaining dipole-containing films, a configuration for removing a first capping layer, a configuration for depositing a second capping layer, a configuration for depositing a PMOS work function material, and / or a configuration for depositing a gate electrode.

[0086] In one or more embodiments, a first processing chamber 910 may be configured for thermal oxidation to form an interface layer on the substrate. The substrate may be moved into and out of the processing chamber 910 by a robot 931 passing through a pass-through 922.

[0087] The processing chamber 908 may also be connected to the transfer station 931. In some embodiments, the processing chamber 908 comprises an atomic layer deposition chamber for depositing a high-k gate metal oxide layer and is in fluid communication with one or more reactive gas sources for providing a flow of reactive gas to the processing chamber 908. In some embodiments, the processing chamber 906 comprises an atomic layer deposition chamber for depositing a sacrificial seal layer and is in fluid communication with one or more reactive gas sources for providing a flow of reactive gas to the processing chamber 906. In some embodiments, the processing chamber 906 comprises an atomic layer deposition chamber for depositing a dipole film and is in fluid communication with one or more reactive gas sources for providing a flow of reactive gas to the processing chamber 906. In some embodiments, the processing chamber 908 comprises an atomic layer deposition chamber for depositing a high-k gate metal oxide capping layer and is in fluid communication with one or more reactive gas sources for providing a flow of reactive gas to the processing chamber 908. Substrates may be moved to and from the processing chamber 908 by the robot 931.

[0088] In some embodiments, the processing chamber 904 is connected to the transfer station 921 and configured to thermally process the substrate.

[0089] In some embodiments, other processing chambers may be configured to perform additional portions of the processing method, including removing the sacrificial seal layer, removing the remaining dipole film, and removing the first capping layer, depositing a second high-k capping layer, depositing a PMOS work function material, and depositing a gate electrode material. Those skilled in the art will recognize that the number and arrangement of individual processing chambers on a tool may be varied and that the embodiment shown in FIG. 4 represents only one possible configuration.

[0090] In some embodiments, the processing system 900 includes one or more metrology stations. For example, the metrology stations can be located in the transfer stations 931, 921, or in any of the individual processing chambers. The metrology stations can be in any location in the system 900 that allows the recess distance to be measured without exposing the substrate to an oxidizing environment.

[0091] In the context of describing the materials and methods described herein (particularly in the context of the claims below), the use of the terms "a" and "an" as well as "the" and similar referents should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by the context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better describe the materials and methods, and does not impose limitations on the scope, unless otherwise asserted. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0092] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described with respect to that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in certain embodiments," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0093] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will recognize that the described embodiments merely illustrate the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a metal gate stack, the method comprising: forming an interface layer on a surface of a substrate; depositing a high dielectric constant metal oxide layer on the interfacial layer; forming a dipole film on the high dielectric constant metal oxide layer; depositing a first capping layer over the substrate; forming a sacrificial seal layer over the first capping layer; exposing the substrate to a heat treatment at a temperature of at least 700° C. to drive the dipole film and form dipole regions in the high dielectric constant metal oxide layer; removing the sacrificial sealing layer; A method comprising:

2. The method of claim 1 , wherein the sacrificial sealing layer comprises amorphous silicon (a-Si).

3. The method of claim 1 , wherein the sacrificial sealing layer has a thickness in the range of 5 Å to 50 Å.

4. The method of claim 1 , wherein the dipolar film comprises a nitride, a carbide, an oxide, a carbonitride, or a combination thereof, of a dipolar metal.

5. 5. The method of claim 4, wherein the dipole metal comprises zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof.

6. The method of claim 1 further comprising removing a remaining portion of the dipole film and the first capping layer.

7. The method of claim 6 further comprising depositing a second capping layer over the substrate.

8. The method of claim 1 , wherein the first capping layer comprises titanium nitride (TiN) or titanium silicon nitride (TiSiN).

9. The high dielectric constant metal oxide layer is made of hafnium oxide (HfO ２ ), hafnium oxynitride (HfON), hafnium zirconium oxide (HfZrO), hafnium zirconium oxynitride (HfZrON), hafnium silicon oxide (HfSiO), and hafnium silicon oxynitride (HfSiON).

10. The interface layer is made of silicon dioxide (SiO ２ ), silicon germanium oxide (SiGeO ｘ ), germanium oxide (GeO ｘ 2. The method of claim 1 , further comprising one or more of: silicon oxynitride (SiON);

11. The method of claim 7 further comprising depositing a PMOS work function material on the substrate.

12. The method of claim 11 , further comprising depositing a gate material onto the substrate.

13. 1. A method for removing an oxidant from a metal gate stack, the method comprising: forming a sacrificial seal layer on the metal gate stack, the metal gate stack including a first capping layer on a dipole film on a high-k metal oxide layer on an interfacial layer on a surface of a substrate; exposing the metal gate stack to a heat treatment at a temperature of at least 700° C. to drive the dipole film in the high-k metal oxide layer and to form a dipole region; removing the sacrificial sealing layer; A method comprising:

14. The method of claim 13, wherein the sacrificial sealing layer comprises amorphous silicon (a-Si).

15. The method of claim 13 , wherein the sacrificial sealing layer has a thickness in the range of 5 Å to 50 Å.

16. The method of claim 13 further comprising removing the remaining portion of the dipole film and the first capping layer.

17. The method of claim 13 further comprising depositing a second capping layer over the substrate.

18. The method of claim 17 , further comprising depositing a PMOS work function material on the substrate.

19. The method of claim 18 , further comprising depositing a gate material onto the substrate.

20. 14. The method of claim 13, wherein the equivalent oxide thickness of the metal gate stack is less than 2 Å greater than the equivalent oxide thickness of a metal gate stack without a sacrificial seal layer thereon.

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