Thermally improved PCB for power semiconductor dies connected by via technology and assembly using such PCB - Patents.com

Abstract

1. A power module comprising: a power semiconductor die; and at least one substrate comprising an insulating layer in contact with a metallized connection surface of the die; and at least one conductive path on a conductive layer on a surface of the insulating layer opposite the metallized connection surface of the die, the insulating layer comprising vias filled with a conductive material to provide connection pads between the metallized connection surface of the die and the conductive path, the vias being arranged in a decreasing density from a location of at least one hot spot of the metallized connection surface when the die is in operation towards a peripheral area of ​​the metallized connection surface.

Description

[Technical field]

[0001] The present disclosure relates to improving the reliability and lifetime of connections between power semiconductor dies and PCBs, and in particular to semiconductor dies embedded in PCBs and connected through vias to conductive layers of such PCBs. [Background technology]

[0002] Due to the important position of power modules in power conversion systems and their high cost, one of the main concerns in power electronics today is the reliability of power modules. Therefore, in traditional power semiconductor modules, where the power semiconductors are connected to a PCB, the degradation of solder joints and wire bonds is mainly discussed in the literature. The technology of connecting the semiconductor dies with vias inside the PCB substrate can increase the reliability and efficiency of the power semiconductor dies. However, in certain environments, failures due to the difference in CTE (coefficient of thermal expansion) between different materials, e.g., copper, FR4 and Si, SiC or GaN, are inevitable. In such cases, mechanical stress due to the mismatch in thermal expansion properties can cause fatigue damage, which ultimately leads to delamination of the PCB and failure of the assembly.

[0003] As an example, in a prior art die embedded in or connected to a PCB with a uniform via pattern, the temperature on the surface of the power semiconductor die where the die is connected to the vias is not constant, which can cause premature degradation in areas where such power semiconductor die is hotter than areas where such power semiconductor die is connected to the PCB. In addition, as degradation progresses, the increased temperature on such areas further accelerates degradation, significantly reducing the reliability of the semiconductor die embedded in the PCB.

[0004] To reduce fatigue near the die, several solutions exist, such as using special solder interface techniques.

[0005] For example, when ball bonds are arranged in a specific pattern as disclosed in US Pat. No. 6,399,633, the tension applied to the die counteracts the mechanical stress caused by thermal deformation, thus reducing fatigue on the die and improving reliability.

[0006] Another technique, as disclosed in US Pat. No. 5,399,633, relates to a solution using several pads made of a flexible material that provide a flexible layer. On top of these pads, metal contacts are made with an additional layer. The flexible layer provides a soft layer that supports the components soldered on top of it with respect to mechanical variations. However, there is a clear CTE mismatch in the interconnect between the flexible layer and the substrate, which is a clear weakness of the solution.

[0007] US Patent No. 5,399,933 in the name of the present applicant discloses a technique for providing high density vias using conventional PCB manufacturing techniques such as laser via drilling and electrodeposition, thereby reducing the thermal connection between the die and the upper and lower copper layers. Furthermore, this document provides a PCB manufacturing process that allows for variable via placement on dedicated areas. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] U.S. Patent No. 8008786 [Patent Document 2] U.S. Patent No. 6,897,568 [Patent Document 3] European Patent Application Publication No. 3745828 Summary of the Invention

[0009] Aiming to solve the problem of premature degradation due to connections with high temperature areas of power semiconductor dies, the present disclosure proposes a connection pattern based on the temperature distribution on such a die to balance the mechanical stress on the actual power semiconductor die, which results in a more uniform distribution of temperature and therefore better performance and longer life.

[0010] More precisely, the present disclosure relates to a power module comprising a power semiconductor die, an insulating layer in contact with a metallized connection surface of the die, and at least one substrate comprising at least one conductive path on a conductive layer on a face of the insulating layer facing the metallized connection surface of the die, the insulating layer comprising vias filled with a conductive material to provide connection pads between the metallized connection surface of the die and the conductive paths, the vias being arranged in such a way that their density decreases from the location of a hot spot of the metallized connection surface towards the peripheral area of ​​the metallized connection surface when the die is in operation.

[0011] This reduces thermal stress on the bonding layer during operation, especially when temperature cycling occurs.

[0012] Preferably, the density of vias located in cooler regions within an operating semiconductor die is reduced.

[0013] This allows the R TH increases.

[0014] In a second embodiment, the vias are arranged as a peripheral region around at least one cavity in the insulating layer having a length and width greater than the diameter of the vias, and the vias and cavities are filled with a conductive material to form connection pads and connection blocks, respectively, that join the metallized connection surfaces and the conductive paths, and the connection pads and connection blocks provide mechanical, electrical and thermal bonding layers between the die and the conductive paths of the conductive layer in the module.

[0015] This allows for an area with low thermal resistance and a strong bond between the die and the conductive paths of the substrate.

[0016] The through hole cavity in the insulating layer may preferably have a length and width greater than or equal to the length and width of the four vias.

[0017] In such embodiments, the temperature of the connection above the large hot spot can be reduced, resulting in a stronger bond between the conductive paths on the substrate and the metallized connection surface of the die and a more uniform heat distribution at the bond.

[0018] The distribution of the vias and the size of the cavities affect the thermal resistance R of the bonding layer in the higher temperature areas of the metallized interface of the die. TH It can be specified to reduce the thermal resistance of the bonding layer in the lower temperature region of the connection surface and to increase the thermal resistance of the bonding layer in the lower temperature region of the connection surface, thereby increasing the temperature homogeneity of the bonding layer and the connection surface during operation of the power module.

[0019] The insulating layer may be a PCB insulating layer having at least one cut cavity filled with a conductive material to provide a connection block.

[0020] The PCB may be an epoxy resin and fiberglass combination PCB.

[0021] The conductive material may be electrodeposited copper.

[0022] This allows conventional PCB manufacturing techniques to be used.

[0023] The present disclosure also proposes a power module comprising a first substrate according to the present disclosure having upper conductive paths connected to an upper metallized connection surface of the power semiconductor die and a second substrate according to the present disclosure having lower conductive paths connected to a lower metallized connection surface of the power semiconductor die, wherein a spacer layer is provided around the side surfaces of the power semiconductor die between the insulating layers of the first substrate and the second substrate.

[0024] The die may have command contacts connected to one side of the module by one or more vias.

[0025] This allows the present invention to be used with transistors or other three terminal components.

[0026] The present disclosure further relates to a substrate for manufacturing a power module having a connection area where a metallized connection surface of a semiconductor die is mechanically, electrically and thermally connected, the substrate comprising a PCB insulating layer, the connection area comprising vias having a density decreasing towards an outer edge of the connection area, at least one cavity being surrounded by the vias, the substrate comprising a PCB conductive layer having at least one conductive path comprising the connection area.

[0027] The cavities and vias are preferably filled with a conductive material and are designed to provide a connection area of ​​at least one conductive path for connection between the connection block and the connection pad.

[0028] The vias preferably decrease in density from the center of the connection area towards the outer edge of the connection area.

[0029] The present disclosure further relates to a method for manufacturing the power module of the present disclosure, the method including the steps of providing at least one conductive path on one side of an insulating layer of a substrate facing a metallized connecting surface of a die, drilling holes in the insulating layer to form vias having a decreasing density from a center of the metallized connecting surface towards a peripheral region of the metallized connecting surface, and filling the vias with a conductive material, thereby providing a connection pad providing an electrical connection between the metallized connecting surface and the conductive path.

[0030] The method may include cutting at least one insulating layer to form at least one cavity surrounded by vias, and filling the cavity with a conductive material to form a connection block that, together with the connection pads, provides an electrical connection between the metallized connection surface and the conductive paths.

[0031] The die can be embedded in a PCB, and the method includes: providing a spacer layer on the first layer to form a lower layer having a housing; disposing a power semiconductor die within a housing; placing an insulating layer of woven fiberglass prepreg fabric impregnated with epoxy resin over the spacer layer and the die; press curing the prepreg layers to provide a top layer, the top layer and the bottom layer forming a laminate in which the die is embedded; drilling in a lower insulating layer to a first metallized side of the die to form a via or a via and a cut area, and drilling in an upper insulating layer to a second metallized side of the die to form a via or a via and a cut area; filling the vias or the vias and cut areas in the upper and lower insulating layers with a conductive material to provide a lower bonding layer in electrical contact with the first metallized surface and the lower conductive paths on the outer surface of the lower insulating layer and an upper bonding layer in electrical contact with the second metallized surface and the upper conductive paths on the outer surface of the upper insulating layer; Includes.

[0032] This results in homogenous thermal properties for the two junctions for a die embedded in a multi-layer PCB, a strong junction between the top metallized side of the die and the top conductive paths, and a strong junction between the bottom metallized side of the die and the bottom conductive paths.

[0033] The vias decrease in density from the center to the periphery of the bonding layer.

[0034] The steps of drilling and cutting the insulating layers to form the vias and cavities may be performed using a CO2 laser.

[0035] Additionally or independently, the step of filling the vias and cavities with conductive material to provide conductive paths may be performed by electrodeposition.

[0036] The method may also include removing a portion of the conductive layer above the via locations and cavity locations using a UV laser prior to drilling and cutting the insulating layer.

[0037] A detailed description of exemplary embodiments of the present invention is discussed below with reference to the accompanying drawings. [Brief description of the drawings]

[0038] [Figure 1A] FIG. 1 shows a top view of a prior art design. [Figure 1B] FIG. 1 is a side cutaway view of a prior art design. [Figure 2A] FIG. 1 is a top view of the first embodiment. [Figure 2B] FIG. 2 is a side cutaway view of the first embodiment. [Figure 2C] FIG. 13 is a top view of the second embodiment. [Figure 2D] FIG. 11 is a side cutaway view of the second embodiment. [Diagram 3] FIG. 13 is a side cutaway view of a power module with a die embedded in a PCB made in accordance with a second embodiment. [Figure 4A] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4B] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4C] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4D] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4E] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4F] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4G] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4H] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 4I] 4 illustrates exemplary manufacturing steps for the module of FIG. 3. [Figure 5A] 1A-1D are cutaway side views of manufacturing steps of the module of the first embodiment. [Figure 5B]1A-1D are cutaway side views of manufacturing steps of the module of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] The present disclosure relates to a power module in which power semiconductor dies are located or embedded in a substrate such as a PCB (Printed Circuit Board), preferably a multi-layer PCB. Figures 1A and 1B show a conventional design technique for such a module in which such dies are connected at a first side of the PCB with a conventional connection method E and connected to the other side of the PCB with connection pads D made of vias drilled in an insulating substrate A and filled with a conductive material such as electro-deposited copper.

[0040] Such pads D connect the metallized surface C1 of the power semiconductor die C to the PCB conductive paths B on the opposite side of the die with respect to the insulating layer A of the PCB. This connection is made by regularly spaced connection pads D. In FIG. 1A, the substrate is viewed from above and it can be seen that it has a die C shown in dotted lines under an insulating layer A, with connection pads made of filled vias arranged regularly spaced above or below the metallized surface of the die. In FIG. 1B, which is a side cutaway view at the level of the row of connection pads, it can be seen that vias filled with conductive material extend from the metallized surface C1 of the die C to the conductive paths B.

[0041] Although this conventional design provides a good connection between the metallized side of the die and the conductive paths, it is subject to thermal stresses during current cycling of the power semiconductors, which can cause the pads to break and lead to the module failing after some operation.

[0042] In such a uniform via pattern, the temperature is not constant on the power semiconductor die, which leads to premature degradation in the hotter areas of the power semiconductor die. This degradation can increase the temperature of the concerned area, which further accelerates the degradation and significantly reduces the reliability of the PCB-embedded die. Such a design does not address the reliability of the power module, which is one of the main concerns of today's power electronics due to its important position in the power conversion system and its high cost. Such a PCB-embedded die technology, where the die are connected only by vias inside the PCB substrate, can increase the reliability and efficiency of the power semiconductor die. However, in certain environments, failures due to the difference in the temperature expansion coefficients between different materials, e.g. copper, FR4 and Si, SiC or GaN, are inevitable. Therefore, mechanical stresses can cause fatigue damage, which ultimately leads to delamination of the PCB and failure of the assembly.

[0043] In the first embodiment of the present disclosure according to Figures 2A and 2B, in which the power module is similar to the power module of Figures 1A and 1B, the power semiconductor die 2 is also connected to the conductive paths 11a of the substrate 1a, which are located on the opposite side of the insulating layer 10a with respect to the die 2.

[0044] The substrate has connection areas 13 to conductive paths 11a on a conductive layer of the substrate. A metallized connection surface 21a of the semiconductor die is mechanically, electrically and thermally connected to such conductive paths 11a, as can be seen in FIG. 2B. In the present design, the connection areas of the insulating layer 10a comprise pads made of vias filled with conductive material and organized to provide a high density pad such as pad 41a in the center of the metallized surface to be connected, a first low density pad 41a' surrounding such center, and further low density pads 41a'' connected near the peripheral areas of the metallized surface.

[0045] According to this design, the vias are arranged in a decreasing density from the location of the hot spot of the metallized connecting surface when the die is in operation to the peripheral area of ​​the metallized connecting surface. Typically, the hot spot of an operating die is at the center of the die, but such spot may be off-center, in which case the high density via pattern will also be off-center.

[0046] In a second embodiment according to Figures 2C and 2D, a cavity, preferably having a length and width greater than or equal to the length and width of four vias, is created over the hot spot of the die, and the cavity and vias are filled with conductive material 7 to connect between the metallized connection surface of the power semiconductor die and the conductive path 11a, providing connection block 42a and connection pads 41a' and 41a'', respectively, of decreasing density.

[0047] The dimensions of the die used in power semiconductors are usually between 2mm x 2mm to 8mm x 8mm, and the hotspot area usually has a diameter of about 0.5mm to 1mm depending on the size of the component. And the cavity filled with conductive material to cover the hotspot, reduce the temperature and provide inspiration may have a length and width greater than 0.5mm, respectively, depending on the size of the hotspot, while the vias have a diameter of about 40μm to 0.5mm. The cavity may be square, rectangular or circular, depending on the configuration of the hotspot.

[0048] According to this second embodiment, the connection pads 41a and the connection blocks 42a joining the metallized connection surface 21a and the conductive paths 11a form a mechanical, electrical and thermal bonding layer between the die and the conductive paths of the conductive layers in the module.

[0049] In this design, the connection blocks correspond to the hotter areas of the die, resulting in a lower thermal resistance than the connection pads, and therefore a more homogenous temperature in the connection areas of the die to the conductive paths, thereby increasing the life of the module through reduced thermal stresses on the connections during thermal cycling of the power module during operation. Thus, the thermo-mechanical stresses are well redistributed on the assembly, reducing fatigue mechanisms caused by temperature fluctuations and improving the life of the PCB embedded die.

[0050] To improve the temperature homogeneity, the distribution of the vias 3a and the size of the cavities 5a are adjusted to reduce the thermal resistance R of the bonding layer in the higher temperature areas of the metallized connection surface of the die (e.g., the higher temperature area in the center of the die). TH The distribution is defined to reduce the thermal resistance of the bonding layer in the cooler regions of the connection surface (e.g., the periphery of the die) and to increase the thermal resistance of the bonding layer in the cooler regions of the connection surface (e.g., the periphery of the die), thus improving the temperature homogeneity of the bonding layer and the connection surface during operation of the power module. In particular, in the distribution as shown, the vias 3a are arranged in a decreasing density from the cavity 5a towards the outer edge of the peripheral region, so as to follow the decrease in temperature from the center towards the periphery of the surface of the die. In addition, the density of vias 3a located in the regions of decreasing temperature in the semiconductor die during operation may be decreased if the die comprises cold spots.

[0051] The insulating layer 10a may be a PCB insulating layer provided with a cavity 5a and filled with a conductive material 7 to provide said connection block 42a, which may be electrodeposited copper.

[0052] 3, a power module may embed a power semiconductor die 2 between two PCB substrates, and the module may comprise an upper substrate 10b having upper conductive paths 11b connected to an upper metallized connection surface 21b of the power semiconductor die 2, and a lower substrate 10a having lower conductive paths 11a connected to a lower metallized connection surface 21a of the power semiconductor die 2. In such a case, a spacer layer 6 is provided around the sides of the power semiconductor die between the insulating layers of the first substrate and the second substrate to keep the upper substrate and the lower substrate parallel.

[0053] The connection patterns on both the top side of the die and the bottom side of the die are similar, with an upper connection block 42b surrounded by upper connection pads 41b', 41b'' of decreasing density connecting the upper metallized surface 21b of the die (seen in FIG. 4A) to the upper conductive paths 11b, and a lower connection block 42a surrounded by lower connection pads 41a', 41a'' of decreasing density connecting the lower metallized surface 21a of the die to the lower conductive paths 11a.

[0054] The present disclosure also relates to a method for manufacturing a power module in which a die is embedded in a PCB, as disclosed in Figures 4A-4E and 5A, 5B for a first embodiment, and in Figures 4A-4I, 3 for a second embodiment. Figures 4A-4E relate to embedding a die in a three-layer PCB. Figure 4E relates to providing at least one conductive path 11a, 11b on one side of the insulating layer of the substrate 10a, 10b facing the metallized connection surface 21a, 21b of the die 2. Figures 4F and 4I relate to drilling holes in the insulating layer to form vias 3a, 3b, and cutting holes in at least one insulating layer to form cavities 5a, 5b. FIG. 4G relates to the step of filling the vias and cavities with conductive material 7, thereby providing connection blocks 42a, 42b and connection pads 41a', 41a'', 41b', 41b'', which provide electrical connections between the metallized connection surfaces and the conductive paths.

[0055] The cavities correspond to hot spots of the die having positions that are predetermined or pre-measured depending on the internal layout of the power semiconductor.

[0056] FIG. 4H illustrates the first step for realizing the bottom layer on which the conductive paths 11a are deposited.

[0057] FIG. 5A, a step following that of FIG. 4E according to the first embodiment, relates to drilling via holes 3b, 3b', 3b'' with decreasing density from the center to the boundary of the metallized connection surface area on the first side, in a step similar to FIG. 4F for the second embodiment. FIG. 5B shows the completed double-sided connection with variable density vias. The illustration of steps equivalent to those of FIGS. 4G-4I are omitted for those embodiments where the process is similar and the cavities are replaced by high density vias.

[0058] The variable density vias comprise high density vias 3a, 3b in the center, medium density vias 3a', 3b' in an intermediate position, and low density vias 3a'', 3b'' near the borders of the connection area on each side of the module.

[0059] In the case of an embedded power semiconductor die in a multi-layer substrate or PCB, the method for double-sided connection according to the second embodiment includes: As shown in FIG. 4A, a spacer layer 6 is provided on a first laminate layer 10a to form a lower layer having a housing 12; As shown in FIG. 4B, disposing a power semiconductor die 2 in a housing; 4C, placing an insulating layer 10c of woven fiberglass fabric impregnated with epoxy resin over the spacer layer and the die; press curing (51, 52, 53) the prepreg layers to provide an upper layer 10b, the upper layer 10b and the lower layer 10a forming a laminate in which the die is embedded, as shown in FIG. 4D; As shown in FIG. 4E, providing a conductive path 11b on an insulating layer 10b; Drilling holes in the upper insulating layer 10b to the first metallized side 21b of the die to provide vias 3b and cutting areas 5b, as shown in FIG. 4F; filling the vias 3b and the cut areas 5b in the upper insulating layer 10b with a conductive material 7 to provide an upper bonding layer having pads 41b' and connection blocks 42b in electrical contact with the first metallized surface, and providing lower conductive paths on the outer surface of the lower insulating layer; may include.

[0060] The lower bonding layer is then produced in a similar manner by providing the connection paths 11a of FIG. 4H, drilling the vias 3a and cavities 5a of FIG. 4I, and filling the vias and cavities with conductive material 7 as in FIG. 3, to obtain the completed module.

[0061] These steps of providing conductive paths and drilling and filling vias and cavities may be performed in the order shown in Figures 4F-4I or 5A-5B, or simultaneously on both sides of the laminate depending on the available processing means, such as metallization means and drilling and cutting means.

[0062] The steps of drilling holes in the insulating layer and cutting the insulating layer to form the cut areas are preferably performed with a CO2 laser that penetrates the insulating layer of the substrate but not the metallized side of the die.

[0063] If the conductive paths are on an insulating surface of the substrate, the step of drilling holes and cutting through the insulating layer may include the step of removing a portion of the conductive layer above the location of the holes and the location of the cut area using a UV laser. Filling the vias and the cut area with conductive material and providing the conductive paths may be performed by electrodeposition or other processes known in the art of PCB realization.

[0064] Additionally, connections to signal terminals may be provided for three terminal components such as transistors, as is known in the art.

[0065] The invention according to the following claims is not limited to the above description, in particular, one or more conductive paths may be provided before or after drilling the vias and cutting the cavities as described above. In addition, the PCB may be provided with further layers and more than one cavity may be considered in case of a die with more than one hot spot.

Claims

1. 1. A power module comprising a power semiconductor die and at least one substrate comprising an insulating layer in contact with a metallized connection surface of the power semiconductor die and at least one conductive path on a conductive layer on a surface of the insulating layer facing the metallized connection surface of the power semiconductor die, the insulating layer comprising vias filled with a conductive material to provide connection pads between the metallized connection surface of the power semiconductor die and the conductive paths, the vias being arranged in a decreasing density from a position of at least one hot spot of the metallized connection surface towards a peripheral area of ​​the metallized connection surface when the power semiconductor die is in operation, the vias providing a mechanical, electrical and thermal bonding layer between the power semiconductor die and the conductive paths of the conductive layer in the power module, The via is arranged in a peripheral region of at least one cavity in the insulating layer, the length and width of the cavity being greater than a diameter of the via, and the via and the cavity are filled with a conductive material to form connection pads and connection blocks, respectively, that join the metallized connection surface and the conductive path, and the connection pads and the connection blocks provide mechanical, electrical and thermal bonding layers between the power semiconductor die and the conductive path of the conductive layer in the power module.

2. 2. The power module of claim 1, wherein a density of the vias located in low temperature regions within the power semiconductor die during operation is lower than a density of the vias located in high temperature regions.

3. 3. The power module of claim 1, wherein the distribution of the vias and the size of the cavities are defined to reduce the thermal resistance of the bonding layer in hotter areas of the metallized connection surface of the power semiconductor die and to increase the thermal resistance of the bonding layer in cooler temperature areas of the connection surface, thereby increasing the temperature homogeneity of the bonding layer and the connection surface during operation of the power module.

4. A power module according to any one of claims 1 to 3, wherein the insulating layer is a PCB insulating layer having at least one cut cavity filled with a conductive material to provide the connection block.

5. The power module according to any one of claims 1 to 4, wherein the conductive material is electrodeposited copper.

6. A power module comprising: a power semiconductor die; an insulating layer in contact with a metallized connection surface of the power semiconductor die; and at least one substrate comprising at least one conductive path on a conductive layer on a surface of the insulating layer opposite the metallized connection surface of the power semiconductor die, wherein the insulating layer comprises vias filled with a conductive material to provide connection pads between the metallized connection surface of the power semiconductor die and the conductive path, the vias being arranged in a manner that decreases in density from a location of at least one hot spot on the metallized connection surface towards a peripheral area of ​​the metallized connection surface when the power semiconductor die is in operation, and the vias provide a mechanical, electrical and thermal bonding layer between the power semiconductor die and the conductive path of the conductive layer in the power module; 1. A power module comprising: a first substrate having an upper conductive path connected to an upper metallized connection surface of the power semiconductor die; and a second substrate having a lower conductive path connected to a lower metallized connection surface of the power semiconductor die, wherein a spacer layer is provided around a side of the power semiconductor die between the insulating layers of the first substrate and the second substrate.

7. A power module comprising a power semiconductor die, an insulating layer in contact with a metallized connection surface of the power semiconductor die, and at least one substrate comprising at least one conductive path on a conductive layer on a surface of the insulating layer opposite the metallized connection surface of the power semiconductor die, the insulating layer comprising vias filled with a conductive material to provide connection pads between the metallized connection surface of the power semiconductor die and the conductive path, the vias being arranged in a manner that decreases in density from a location of at least one hot spot on the metallized connection surface towards a peripheral area of ​​the metallized connection surface when the power semiconductor die is in operation, the vias providing a mechanical, electrical and thermal bonding layer between the power semiconductor die and the conductive path of the conductive layer in the power module, The power semiconductor die includes a command contact area connected to one side of the power module by one or more of the vias.

8. A substrate for manufacturing a power module according to any one of claims 1 to 7, comprising a connection area in which the metallized connection surfaces of the power semiconductor die are mechanically, electrically and thermally connected, the substrate comprising a PCB insulating layer, the connection area comprising vias whose density decreases in the direction of the outer edge of the connection area and at least one cavity surrounded by the vias, the substrate comprising a PCB conductive layer having at least one conductive path comprising the connection area.

9. The substrate of claim 8 , wherein the vias decrease in density from a center of the connection area to an outer edge of the connection area.

10. A method for producing a power module according to any one of claims 1 to 7, characterized in that it comprises the steps of providing at least one conductive path on one side of an insulating layer of the substrate facing the metallized connection surface of the power semiconductor die, drilling holes in the insulating layer to form the vias, the density of which decreases from the center of the metallized connection surface towards the peripheral area of ​​the metallized connection surface, and filling the vias with a conductive material, thereby providing connection pads providing an electrical connection between the metallized connection surface and the conductive paths, 11. A method for manufacturing a power module, comprising the steps of: cutting at least one of the insulating layers to form at least one cavity surrounded by the vias; and filling the cavity with a conductive material to form a connection block that, together with the connection pads, provides an electrical connection between the metallized connection surface and the conductive paths.

11. A method for manufacturing a power module as claimed in any one of claims 1 to 7, comprising the steps of: providing at least one conductive path on one side of an insulating layer of the substrate facing the metallized connection surface of the power semiconductor die; drilling holes in the insulating layer to form the vias, the density of which decreases from the centre of the metallized connection surface towards the peripheral region of the metallized connection surface; and filling the vias with a conductive material, thereby providing a connection pad providing an electrical connection between the metallized connection surface and the conductive path; The power semiconductor die is embedded in a PCB, and the manufacturing method includes: providing a spacer layer on the first lamination layer to form a lower insulating layer having a housing; placing the power semiconductor die in the housing; placing an epoxy resin impregnated woven fiberglass prepreg insulation layer over the spacer layer and the power semiconductor die; press curing the prepreg insulation layer to provide an upper insulation layer, the upper insulation layer and the lower insulation layer forming a laminate in which the power semiconductor die is embedded; drilling the vias with decreasing density in the lower insulating layer to a first metallized side of the power semiconductor die and drilling the vias with decreasing density in the upper insulating layer to a second metallized side of the power semiconductor die; filling the vias in the upper and lower insulating layers with a conductive material to provide a lower bonding layer in electrical contact with the first metallized surface and a lower conductive path on an outer surface of the lower insulating layer, and an upper bonding layer in electrical contact with the second metallized surface and an upper conductive path on an outer surface of the upper insulating layer; A method for manufacturing a power module, comprising:

12. The power semiconductor die is embedded in a PCB, and the manufacturing method includes: providing a spacer layer on the first layer to form a lower insulating layer having a housing; placing a power semiconductor die in the housing; placing an epoxy resin impregnated woven fiberglass prepreg insulation layer over the spacer layer and the power semiconductor die; press curing the prepreg insulation layer to provide an upper insulation layer, the upper insulation layer and the lower insulation layer forming a laminate in which the power semiconductor die is embedded; drilling in the lower insulating layer to a first metallized side of the power semiconductor die to form a via and at least one cut area and drilling in the upper insulating layer to a second metallized side of the power semiconductor die to form a via and at least one cut area; filling the vias and the cut areas in the upper and lower insulating layers with a conductive material to provide a lower bonding layer in electrical contact with the first metallized surface and a lower conductive path on an outer surface of the lower insulating layer, and an upper bonding layer in electrical contact with the second metallized surface and an upper conductive path on an outer surface of the upper insulating layer; The method for manufacturing the power module according to claim 10, comprising:

13. The steps of drilling and cutting the insulating layer to form the vias and the cavities are performed using a CO ２ 13. A method for manufacturing a power module according to claim 10 or 12, wherein the step of filling the vias and the cavities with a conductive material and providing the conductive paths is performed by electro-deposition, the step being performed using a laser.

14. 14. The method of claim 13, further comprising the step of removing a portion of the conductive layer above the location of the via and the location of the cavity using a UV laser prior to the step of drilling and cutting the insulating layer.

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