Semiconductor Device

Abstract

To provide a semiconductor device in which a plurality of wirings formed in parallel can be inspected.SOLUTION: A semiconductor device according to the present disclosure includes: first circuits connected to respective first positions of a plurality of wirings of a first wiring group including the plurality of wirings; second circuits connected to second positions to be respective ends of the plurality of wirings; and a plurality of connection portions formed between the first positions and the second positions of the plurality of wirings at the rate of 1 to 1 of the plurality of wirings to connect third circuits respectively to the plurality of wirings.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A pixel array is known in which a plurality of pixels, each of which includes one or more light receiving elements, are arranged in a matrix on a semiconductor substrate. The pixel array includes wiring for each pixel row and each pixel column, each of which is connected to each light receiving element. In addition, a technology is known in which a first semiconductor substrate on which the pixel array is formed is laminated with a second semiconductor substrate on which a circuit for performing signal processing on pixel signals read from each pixel included in the pixel array is formed, thereby forming a single image sensor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 04-180374 Summary of the Invention [Problem to be solved by the invention]

[0004] In the pixel array described above, the presence or absence of defects in the wiring for each pixel row and each pixel column affects the yield. Therefore, it is required to be able to inspect the presence or absence of defects in the wiring included in the pixel array before laminating the first semiconductor substrate and the second semiconductor substrate to form an image sensor.

[0005] An object of the present disclosure is to provide a semiconductor device capable of testing a plurality of wirings formed in parallel. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises: A semiconductor device including a first semiconductor substrate on which a plurality of pixels arranged in a matrix in a pixel array section and a first wiring group including a plurality of wirings connected to the plurality of pixels are formed, the first semiconductor substrate being bonded to a second semiconductor substrate on which a pixel control section for controlling the plurality of pixels is formed, A first wiring group including a plurality of wirings is connected to a first position of each of the plurality of wirings. for applying a voltage to each of the plurality of wiringsA first circuit and each of the plurality of wirings , distal to said first position Connected to the second position for detecting application of a voltage to each of the plurality of wirings; a second circuit, which is provided between the first position and the second position of each of the plurality of wirings in a one-to-one correspondence with each of the plurality of wirings; The pixel control unit A plurality of connection parts for connecting the At least one first external connection terminal which is a probe contact terminal including a terminal for supplying a test voltage and which is connected to the first circuit, and at least one second external connection terminal which is a probe contact terminal including a terminal for detecting a test voltage and which is connected to the second circuit. . [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram showing an outline of a basic configuration of a CMOS image sensor, which is an example of an imaging element applicable to each embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a pixel applicable to each embodiment. [Diagram 3] 1 is a block diagram showing an example of a configuration of a column-parallel AD conversion unit applicable to each embodiment. FIG. [Figure 4] FIG. 2 is an exploded perspective view showing an outline of a stacked chip structure of an image sensor applicable to each embodiment. [Diagram 5] 3A to 3C are diagrams illustrating specific configuration examples of a first semiconductor substrate according to each embodiment. [Figure 6] 2A to 2C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to the first embodiment. [Figure 7] FIG. 2 is a diagram for explaining open detection according to the first embodiment. [Figure 8A] 2 is a schematic diagram showing an electrode and its vicinity on a first semiconductor substrate. FIG. [Figure 8B] 1 is a cross-sectional view showing a first structural example in which a first semiconductor substrate and a second semiconductor substrate are bonded together to form a laminate. [Figure 8C] 11 is a cross-sectional view showing a second structural example in which a first semiconductor substrate and a second semiconductor substrate are bonded together to form a laminate. FIG. [Figure 9] 4A to 4C are diagrams illustrating an example of a configuration of a first semiconductor substrate according to a first modified example of the first embodiment. [Figure 10]4A to 4C are diagrams for explaining erroneous detection that may occur in open inspection using the configuration of the first embodiment. [Figure 11] FIG. 11 is a diagram for explaining an open inspection using a configuration of a first modified example of the first embodiment. [Figure 12] 6A to 6C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to a second modified example of the first embodiment. [Figure 13] 13A to 13C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to a third modified example of the first embodiment. [Figure 14] 13A to 13C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to a fourth modified example of the first embodiment. [Figure 15] 6A to 6C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to a second embodiment. [Figure 16A] FIG. 11 is a circuit diagram of an example of a switch circuit according to a second embodiment. [Figure 16B] FIG. 11 is a circuit diagram of an example of a transfer circuit according to a second embodiment. [Figure 17] 13A to 13C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to a third embodiment. [Figure 18] 13A to 13C are diagrams illustrating another example of the configuration of the first semiconductor substrate according to the third embodiment. [Figure 19A] 13A to 13C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to a fourth embodiment. [Figure 19B] FIG. 13 is a circuit diagram illustrating a configuration of an example of a switch decoder according to a fourth embodiment. [Figure 20] FIG. 13 is a circuit diagram illustrating a schematic configuration of an example of a bias unit according to a fourth embodiment. [Figure 21A] 13A to 13C are diagrams illustrating an example of the configuration of a first semiconductor substrate according to a fifth embodiment. [Figure 21B] FIG. 13 is a circuit diagram illustrating a configuration of an example of a switch decoder according to a fifth embodiment. [Figure 22] 13A to 13C are diagrams illustrating another example of the configuration of the first semiconductor substrate according to the fifth embodiment. [Figure 23A] FIG. 13 is a diagram showing an example of settings of a switch decoder ADR when an open inspection is performed in the configuration according to the fifth embodiment. [Figure 23B] 11A and 11B are diagrams illustrating the state of vertical signal lines during open inspection; [Figure 24] FIG. 13 is a diagram showing an example of settings of a switch decoder ADR when a first example of a short circuit inspection is performed in a configuration according to a fifth embodiment. [Diagram 25] FIG. 13 is a diagram showing an example of settings of a switch decoder ADR when a second example of a short circuit inspection is performed in the configuration according to the fifth embodiment. [Figure 26A] FIG. 1 is a circuit diagram showing an example of an application circuit according to existing technology. [Figure 26B] FIG. 6 is a circuit diagram showing an example of an application circuit 660 according to the existing technology. [Figure 27A] FIG. 13 is a circuit diagram illustrating an example of an application circuit according to a sixth embodiment. [Figure 27B] FIG. 13 is a circuit diagram illustrating a circuit formed on a first semiconductor substrate according to a sixth embodiment. [Figure 27C] FIG. 13 is a diagram illustrating a plan view of an example of a first semiconductor substrate according to a sixth embodiment. [Figure 28A] FIG. 23 is a circuit diagram illustrating an example of an application circuit according to a first modified example of the sixth embodiment. [Figure 28B] FIG. 23 is a circuit diagram illustrating a circuit formed on a first semiconductor substrate according to a first modified example of the sixth embodiment. [Figure 28C] FIG. 23 is a diagram illustrating a plan view of an example of a first semiconductor substrate according to a first modified example of the sixth embodiment. [Figure 29] FIG. 23 is a diagram illustrating a plan view of an example of a first semiconductor substrate according to a second modification of the sixth embodiment. [Diagram 30] FIG. 23 is a diagram illustrating a plan view of an example of a first semiconductor substrate according to a third modified example of the sixth embodiment. [Diagram 31] FIG. 1 is a diagram showing an example of a pixel circuit and a detection circuit for explaining an inspection in the case where an existing technique is used. [Figure 32A] 13A to 13C are diagrams for explaining the effects of the sixth embodiment and each of the modifications thereof. [Figure 32B]13A to 13C are diagrams for explaining the effects of the sixth embodiment and each of the modifications thereof. [Diagram 33] 1 is a cross-sectional view of a main portion of an image sensor wafer applicable to the present disclosure. [Diagram 34] 1A to 1C are diagrams illustrating examples of use of the embodiments and modified examples of the technology of the present disclosure. [Diagram 35] 1 is a block diagram showing a configuration of an example of an imaging device to which the technology according to the present disclosure can be applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0009] Hereinafter, embodiments of the present disclosure will be described in the following order. 1. Configurations Applicable to Each Embodiment 1-1.Example of CMOS image sensor configuration 1-2. Example of pixel circuit configuration 1-3. Example of column parallel AD conversion section 1-4. Chip structure example 1-5. Overview of inspection using existing technology 2. Overview of the Configuration According to Each Embodiment 3. First embodiment 3-0-1. Configuration example of first semiconductor substrate according to the first embodiment 3-0-2. Example of inspection method according to the first embodiment 3-0-3. Examples of the structure of the needle contact terminal applicable to each embodiment 3-1. First modified example of the first embodiment 3-1-1. Configuration example of first semiconductor substrate according to first modification of first embodiment 3-1-2. Example of inspection method according to the first modified example of the first embodiment 3-2. Second Modification of the First Embodiment 3-2-1. Configuration example of first semiconductor substrate according to second modification of first embodiment 3-2-2. Example of inspection method according to the second modified example of the first embodiment 3-3. Third Modification of the First Embodiment 3-4. Fourth Modification of the First Embodiment 4. Second embodiment 4-0-1. Configuration example of first semiconductor substrate according to the second embodiment 4-0-2. Example of inspection method according to the second embodiment 4-0-3. Detailed Description of the Bias Circuit According to the Second Embodiment 5. Third embodiment 5-0-1. Configuration example of first semiconductor substrate according to the third embodiment 5-0-2. Example of inspection method according to the third embodiment 5-1. Another example of the third embodiment 6. Fourth embodiment 6-0-1. Configuration example of first semiconductor substrate according to the fourth embodiment 6-0-2. Example of the configuration of the switch decoder according to the fourth embodiment 6-0-3. Example of inspection method according to the fourth embodiment 7. Fifth embodiment 7-0-1. Configuration example of first semiconductor substrate according to the fifth embodiment 7-0-2. Example of inspection method according to the fifth embodiment 7-0-2-1. Example of open inspection according to the fifth embodiment 7-0-2-2. Example of short circuit inspection according to the fifth embodiment 8. Sixth embodiment 8-1. Existing technologies 8-2. Configuration according to the sixth embodiment 8-3. First modified example of the sixth embodiment 8-4. Second modification of the sixth embodiment 8-5. Third modification of the sixth embodiment 8-6. Effects of the sixth embodiment and its modifications 9. Other Embodiments 10. Structures Applicable to Each Embodiment 11. Application Examples of the Technology of the Present Disclosure

[0010] [1. Configuration applicable to each embodiment] First, the basic configuration of an imaging element to which the technology of the present disclosure can be applied will be described. Here, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of XY address type imaging element, will be taken as an example of the imaging element. A CMOS image sensor is an image sensor that is manufactured by applying or partially using a CMOS process.

[0011] (1-1. Example of CMOS image sensor configuration) FIG. 1 is a block diagram showing an outline of the basic configuration of a CMOS image sensor, which is an example of an image sensor applicable to each embodiment.

[0012] The imaging element 1 shown in Fig. 1 has a pixel array section (cell array) 11 in which pixels (cells) 2 including photoelectric conversion sections are arranged in row and column directions, i.e., two-dimensionally in a matrix array, and a peripheral circuit section of the pixel array section 11. Here, the row direction refers to the arrangement direction (horizontal direction) of the pixels 2 in a pixel row, and the column direction refers to the arrangement direction (vertical direction) of the pixels 2 in a pixel column. The pixels 2 generate and accumulate electric charges according to the amount of light received by performing photoelectric conversion.

[0013] In the example of FIG. 1, the peripheral circuit section of the pixel array section 11 includes, for example, a row selection section 12, a constant current source section 13, an analog-to-digital conversion section 14, a horizontal transfer scanning section 15, a signal processing section 16, and a timing control section 17.

[0014] In the pixel array section 11, the control lines 321 to 322 are connected to each pixel row for the pixel arrangement in a matrix. n are wired in the row direction. Also, vertical signal lines 311 to 31 m are wired in the column direction. m When there is no need to particularly distinguish between the vertical signal lines 311 to 31 m In the following description, the control lines 321 to 32 are referred to as vertical signal lines 31. nWhen there is no need to distinguish between the control lines 321 and 32 n will be described as control line 32 where appropriate.

[0015] The control line 32 transmits a drive signal for driving the pixel 2 when reading out a signal. In Fig. 1, the control line 32 is illustrated as a single wire, but the control line 32 is not limited to a single wire and may include a plurality of wires. One end of the control line 32 is connected to an output terminal corresponding to each row of the row selection unit 12.

[0016] Next, each circuit portion of the peripheral circuit section of the pixel array section 11, that is, the row selection section 12, the constant current source section 13, the analog-to-digital conversion section 14, the horizontal transfer scanning section 15, the signal processing section 16 and the timing control section 17 will be described.

[0017] The row selection unit 12 is composed of a shift register, an address decoder, etc., and controls scanning of pixel rows and addresses of pixel rows when selecting each pixel 2 included in the pixel array unit 11. Although the specific configuration of the row selection unit 12 is not shown in the figure, the row selection unit 12 is generally configured to have two scanning systems, a read scanning system and a sweep scanning system.

[0018] The readout scanning system sequentially selects and scans the pixels 2 in the pixel array section 11 row by row to read out pixel signals from the pixels 2. The pixel signals read out from the pixels 2 are analog signals. The sweep scanning system performs sweep scanning on the readout rows to be read out scanned by the readout scanning system, prior to the readout scanning by the shutter speed.

[0019] The sweep-out scanning by this sweep-out scanning system sweeps out unnecessary charges from the photoelectric conversion units of the pixels 2 in the readout row, thereby resetting the photoelectric conversion units. Then, by sweeping out (resetting) the unnecessary charges by this sweep-out scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of discarding the charges in the photoelectric conversion units and starting a new exposure (starting the accumulation of charges).

[0020] The constant current source unit 13 supplies vertical signal lines 311 to 31 m The constant current source section 13 supplies current to each of the vertical signal lines 311 to 31 for each pixel 2 in the pixel row selected and scanned by the row selection section 12. m A bias current is provided through each of the

[0021] The analog-digital conversion unit 14 includes a plurality of analog-digital converters provided corresponding to the pixel columns of the pixel array unit 11, for example, provided for each pixel column. The analog-digital conversion unit 14 connects vertical signal lines 311 to 31 for each pixel column. m The analog-to-digital conversion unit 14 is a column-parallel analog-to-digital conversion unit that converts analog pixel signals output through each of the column-parallel analog-to-digital conversion units 14 into N-bit digital signals. Hereinafter, the analog-to-digital conversion unit 14 will be referred to as the column-parallel analog-to-digital conversion unit 14.

[0022] As the analog-digital converter included in the column-parallel analog-digital conversion unit 14, for example, a single-slope analog-digital converter, which is an example of a reference signal comparison type analog-digital converter, can be used. However, this is not limited to this example, and as the analog-digital converter included in the column-parallel analog-digital conversion unit 14, a successive approximation type analog-digital converter, a delta-sigma modulation type (ΔΣ modulation type) analog-digital converter, or the like can be used.

[0023] The horizontal transfer scanning unit 15 is composed of a shift register, an address decoder, etc., and controls the scanning of pixel columns and the addresses of pixel columns when reading out signals from each pixel 2 in the pixel array unit 11. Under the control of this horizontal transfer scanning unit 15, the pixel signals converted into digital signals by the column-parallel analog-to-digital conversion unit 14 are read out to a horizontal transfer line 18 with a width of 2N bits for each pixel column.

[0024] The signal processing unit 16 performs predetermined signal processing on the digital pixel signals supplied through the horizontal transfer line 18 to generate two-dimensional image data. For example, the signal processing unit 16 can perform various signal processing on the supplied pixel signals, such as correcting vertical line defects and point defects, and clamping the signals. The signal processing unit 16 can also perform signal processing on the supplied pixel signals, such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing unit 16 outputs the generated image data to a downstream device as an output signal of the image sensor 1.

[0025] The timing control unit 17 generates various timing signals, clock signals, control signals, etc., and based on these generated signals, performs drive control of the row selection unit 12, the constant current source unit 13, the column parallel analog-to-digital conversion unit 14, the horizontal transfer scanning unit 15, and the signal processing unit 16, etc.

[0026] (1-2. Example of pixel circuit configuration) 2 is a circuit diagram showing an example of a circuit configuration of a pixel 2 applicable to each embodiment. The pixel 2 has, for example, a photodiode 21 as a photoelectric conversion unit. The pixel 2 has a pixel configuration including a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21.

[0027] In the example of FIG. 2, the four transistors, ie, the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, are, for example, N-channel MOS type field effect transistors (FETs). Hereinafter, the N-channel MOS type field effect transistors are referred to as NMOS transistors. By configuring the pixel 2 only with NMOS transistors, it is possible to optimize the area efficiency and the process reduction perspective. Note that the combinations of the conductivity types of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 shown in FIG. 2 are merely examples, and are not limited to these combinations.

[0028] For this pixel 2, a plurality of control lines are wired in common to each pixel 2 in the same pixel row as the above-mentioned control line 32. These control lines are connected on a pixel row basis to output terminals of the row selection unit 12 corresponding to each pixel row. The row selection unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of control lines.

[0029] The photodiode 21 has an anode electrode connected to a low potential power supply (for example, ground potential), and photoelectrically converts received light into charges (here, photoelectrons) with an amount of charge corresponding to the amount of light, and accumulates the charges. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region to which the gate electrode of the amplification transistor 24 is electrically connected is the floating diffusion region FD. The floating diffusion region FD is a charge-voltage converter that converts charges into voltage.

[0030] A high level (for example, V DD A transfer signal TRG, whose input signal level is active, is supplied from the row selection unit 12. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, and transfers the charge that is photoelectrically converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffusion region FD.

[0031] The reset transistor 23 is connected to a power supply V DD A reset signal RST, which is active at a high level, is supplied to the gate electrode of the reset transistor 23 from the row selection unit 12. In response to the reset signal RST, the reset transistor 23 becomes conductive and transfers the charge in the floating diffusion region FD to the power supply V DD The floating diffusion region FD is reset by dumping the potential at node

[0032] The gate electrode of the amplifier transistor 24 is connected to the floating diffusion region FD, and the drain electrode is connected to the power supply V DDThe amplification transistor 24 serves as an input section of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, the source electrode of the amplification transistor 24 is connected to a vertical signal line 31 via a selection transistor 25. The amplification transistor 24 and a current source I connected to one end of the vertical signal line 31 configure a source follower that converts the voltage of the floating diffusion region FD into the voltage of the vertical signal line 31.

[0033] The selection transistor 25 has a drain electrode connected to the source electrode of the amplification transistor 24, and a source electrode connected to the vertical signal line 31. A selection signal SEL that is active at a high level is supplied to a gate electrode of the selection transistor 25 from the row selection unit 12. The selection transistor 25 becomes conductive in response to the selection signal SEL, thereby selecting the pixel 2 and transmitting a signal output from the amplification transistor 24 to the vertical signal line 31.

[0034] The readout process in the pixel 2 shown in Fig. 2 will be briefly described. In the initial state, the selection signal SEL, the reset signal RST, and the transfer signal TRG are all low. In addition, the photodiode 21 is exposed to light, and the transfer transistor 22 is turned off by the low-state transfer signal TRG, so that the charge generated by the exposure is accumulated in the photodiode 21.

[0035] At a predetermined timing, the selection signal SEL is set to a high state, and the selection transistor 25 is turned on. Next, the reset signal RST is set to a high state, and the charge of FD is changed to a voltage V DD The potential of the FD is reset to a predetermined potential by discharging the electric potential of the FD to the power supply line of the FD. A predetermined time after the reset signal RST is returned to the low state, the transfer signal TRG is set to the high state, and the electric charge accumulated in the photodiode 21 by exposure is supplied to the FD and accumulated therein. A voltage corresponding to the electric charge accumulated in the FD is generated, and this voltage is amplified by the amplifier transistor 24 and transmitted to the vertical signal line 31 as a pixel signal via the selection transistor 25.

[0036] Here, a signal A of a reset level (black level) output to the vertical signal line 31 at the timing when the state of the FD stabilizes, for example, a predetermined time after the reset signal RST is set to a high state, is converted to a digital value by a corresponding analog-digital converter included in the analog-digital conversion unit 14, and is temporarily stored, for example, in a register of the analog-digital converter. This signal A is offset noise. Reading out this signal A is called a P-phase (Pre-Charge) readout, and the period during which the P-phase readout is performed is called a P-phase period.

[0037] Furthermore, after a processing time from the timing when the transfer signal TRG is set to a high state, for example when the state of the FD is stabilized, a signal B having a signal level output to the vertical signal line 31 is converted to a digital value by an analog-digital converter and temporarily stored, for example, in a register of the analog-digital converter. This signal B is a signal that includes offset noise and a pixel signal. Reading out this signal B is called a D-phase (Data Phase) readout, and the period during which the D-phase readout is performed is called a D-phase period.

[0038] The analog-to-digital converter obtains the difference between the stored signals A and B. This makes it possible to obtain a pixel signal from which offset-related noise has been removed.

[0039] Next, a general description will be given of the sweep scanning by the sweep scanning system in the pixel of Fig. 2. In the sweep scanning, the transfer signal TRG and the reset signal RST are set to a high level, the selection signal SEL is set to a low level, and the cathode electrode of the photodiode 21 is connected to the power supply V DD This connects the charge on the cathode electrode of the photodiode 21 to the power supply V DD After this sweep scan, the transfer signal TRG is set to low level to connect the photodiode 21 to the power supply V DD By disconnecting the photodiode 21 from the photodiode 22, an electronic shutter operation is performed, and accumulation of charge by photoelectric conversion in the photodiode 21 can start.

[0040] The selection transistor 25 is connected to the power supply V DD A circuit configuration may also be applied in which the node is connected between the drain electrode of the amplifier transistor 24 and the drain electrode of the amplifier transistor 24. In the example of Fig. 2, a 4Tr configuration consisting of four transistors (Tr), that is, the transfer transistor 22, the reset transistor 23, the amplifier transistor 24, and the selection transistor 25, is exemplified as the pixel circuit of the pixel 2, but the present invention is not limited to this. For example, a 3Tr configuration may be adopted in which the selection transistor 25 is omitted and the amplifier transistor 24 has the function of the selection transistor 25, or a 5Tr or more configuration may be adopted in which the number of transistors is increased as necessary.

[0041] (1-3. Example of column-parallel analog-to-digital conversion section) Next, a configuration example of the column-parallel analog-digital conversion unit 14 will be described. FIG. 3 is a block diagram showing an example of the configuration of the column-parallel analog-digital conversion unit 14 applicable to each embodiment. The analog-digital conversion unit 14 in the image sensor 1 of the present disclosure has vertical signal lines 311 to 31 m Here, the n-th column of single-slope analog-to-digital converters 140 will be described as an example.

[0042] Single-slope analog-digital converter 140 has a circuit configuration including comparator 141, counter circuit 142, and latch circuit 143. Single-slope analog-digital converter 140 uses a reference signal having a so-called RAMP waveform (slope waveform) whose voltage value changes linearly over time. The reference signal having the ramp waveform is generated by reference signal generating unit 19. Reference signal generating unit 19 can be configured using, for example, a digital-analog conversion circuit.

[0043] The comparator 141 receives an analog pixel signal read from the pixel 2 as a comparison input, receives a reference signal of a ramp waveform generated by the reference signal generating unit 19 as a reference input, and compares the two signals. When the reference signal is greater than the pixel signal, the output of the comparator 141 goes to a first state (e.g., high level), for example, and when the reference signal is equal to or less than the pixel signal, the output goes to a second state (e.g., low level). As a result, the comparator 141 outputs a pulse signal that corresponds to the signal level of the pixel signal, specifically, has a pulse width corresponding to the magnitude of the signal level, as a comparison result.

[0044] The counter circuit 142 receives a clock signal CLK from the timing control unit 17 at the same timing as the start timing of supplying the reference signal to the comparator 141. The counter circuit 142 performs a counting operation in synchronization with the clock signal CLK to measure the period of the pulse width of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation. The count result (count value) of the counter circuit 142 becomes a digital value obtained by digitizing the analog pixel signal.

[0045] The latch circuit 143 holds (latches) a digital value that is a count result of the counter circuit 142. The latch circuit 143 also performs CDS (Correlated Double Sampling), which is an example of noise removal processing, by taking the difference between a D-phase count value corresponding to a pixel signal at a signal level and a P-phase count value corresponding to a pixel signal at a reset level. Then, the latch circuit 143 outputs the latched digital value to the horizontal transfer line 18 under the drive of the horizontal transfer scanning unit 15.

[0046] As described above, in the column-parallel analog-digital conversion unit 14 including a collection of single-slope analog-digital converters 140, a digital value is obtained from time information until a change in the magnitude relationship between a linearly changing analog reference signal generated by the reference signal generation unit 19 and an analog pixel signal output from the pixel 2. Note that, in the above example, a single-slope analog-digital conversion unit 14 in which analog-digital converters 140 are arranged in a one-to-one relationship with a pixel column is illustrated, but it is also possible to use an analog-digital conversion unit 14 in which single-slope analog-digital converters 140 are arranged for each pixel column.

[0047] (1-4. Chip structure example) Next, an example of the chip structure of a CMOS image sensor as the imaging element 1 having the above-mentioned configuration will be described. The chip (semiconductor integrated circuit) structure of the imaging element 1 having the above-mentioned configuration is a stacked chip structure (stacked chip). As for the structure of the pixels 2, when the substrate surface on which the wiring layer is formed is the front surface (front), the pixel structure can be a back-illuminated pixel structure in which light is irradiated from the back surface side on the opposite side, or a front-illuminated pixel structure in which light is irradiated from the front surface side.

[0048] 4 is an exploded perspective view showing an outline of a stacked chip structure of the imaging element 1 applicable to each embodiment. As shown in FIG. 4, the stacked chip structure of the imaging element 1 is a structure in which at least two semiconductor substrates, a first semiconductor substrate 41 and a second semiconductor substrate 42, are stacked and bonded together. In this stacked structure, the first semiconductor substrate 41 in the first layer includes the pixels 2 of the pixel array section 11, the control lines 321 to 322, and the like. n , and vertical signal lines 311 to 31 mis formed. A pixel control unit including a row selection unit 12, a constant current source unit 13, an analog-digital conversion unit 14, a horizontal transfer scanning unit 15, a signal processing unit 16, a timing control unit 17, and a reference signal generation unit 19 is formed on a second semiconductor substrate 42 of the second layer. Note that in FIG. 4, the signal processing unit 16 and the reference signal generation unit 19 are omitted to avoid complication. The pixel control unit is a peripheral circuit unit of the pixel array unit 11. The first semiconductor substrate 41 of the first layer and the second semiconductor substrate 42 of the second layer are electrically connected by connection units 43 and 44 such as TCV (Through Chip Via) and Cu-Cu hybrid bonding.

[0049] With this stacked structure imaging element 1, the first semiconductor substrate 41 in the first layer only needs to be large enough (area) to form the pixel array section 11, so the size (area) of the first semiconductor substrate 41 and therefore the size of the entire chip can be reduced. Furthermore, a process suitable for fabricating the pixels 2 can be applied to the first semiconductor substrate 41 in the first layer, and a process suitable for fabricating the pixel control section can be applied to the second semiconductor substrate 42 in the second layer, so there is also the advantage that the process can be optimized when manufacturing the imaging element 1. In particular, advanced processes can be applied when fabricating the pixel control section.

[0050] Although a two-layer structure formed by stacking the first semiconductor substrate 41 and the second semiconductor substrate 42 has been exemplified here, the stacked structure is not limited to a two-layer structure, and may be a structure of three or more layers. In the case of a stacked structure of three or more layers, the pixel control unit including the row selection unit 12, the constant current source unit 13, the analog-digital conversion unit 14, the horizontal transfer scanning unit 15, the signal processing unit 16, the timing control unit 17, and the reference signal generation unit 19 can be formed in a distributed manner on the semiconductor substrates from the second layer onward.

[0051] (1-5. Overview of inspection using existing technology) By the way, in sorting the image pickup device 1 into good and bad products, the control lines 321-32 n and vertical signal lines 311 to 31 mInspection is performed to check for the presence or absence of open (disconnected) wiring such as those described above, and the presence or absence of short (short circuit) between adjacent wiring. In the case of a three-dimensional stacked chip structure in which a first semiconductor substrate 41 on which a pixel array section 11 is formed and a second semiconductor substrate 42 on which a pixel control section is formed are bonded together as described with reference to Fig. 4, it is common to perform inspection to separate non-defective and defective products in the wafer state which is the final shape after the first semiconductor substrate 41 and the second semiconductor substrate 42 are bonded together.

[0052] There are several methods for stacking stacked chips, including bonding wafers together (WOW: Wafer On Wafer) and bonding a wafer to a good chip (COW: Chip On Wafer). Unlike the WOW method, the COW method of stacking chips allows for selective combination of good chips to increase yield. Also, with the WOW method, it is possible to bond the optimal combination of wafers at the position of the good chip.

[0053] In the case of the stacked chip structure shown in Fig. 4, the pixel circuit is configured only with NMOS transistors on the first semiconductor substrate 41 side as shown in Fig. 2, due to optimization from the viewpoint of area efficiency and process reduction. The pixel control unit, which is the peripheral circuit of the pixel array unit 11, is formed on the second semiconductor substrate 42 side. In other words, the pixel control unit is not mounted on the first semiconductor substrate 41 side. Therefore, in the case of the stacked chip of the COW method, it is difficult to select good and bad products on the first semiconductor substrate 41 side, which is the sensor substrate (pixel chip), before bonding, and the yield improvement effect is suppressed.

[0054] As described above, the first semiconductor substrate 41 and the second semiconductor substrate 42 are electrically connected to each other at the connection parts 43 and 44 by TCV or Cu-Cu hybrid bonding, and the connection parts 43 and 44 are connected to the control lines 321 to 32. n and vertical signal lines 311 to 31 mThe number of connection nodes of the connection parts 43 and 44 is proportional to the number of pixels of the pixel array section 11, and amounts to several tens of thousands. By providing pin contact terminals to all of these connection nodes, the control lines 321 to 32 n and vertical signal lines 311 to 31 m It is also possible to inspect the wiring for open / short circuits. However, the size of the needle contact terminals is several tens of times larger than the terminal pitch and number of terminals, and it is not realistic in terms of area to install needle contact terminals at all connection nodes. In addition, installing a large number of large needle contact terminals adds unnecessary parasitic capacitance, which may degrade performance.

[0055] [2. Overview of the Configuration According to Each Embodiment] Next, an outline of the configuration according to each embodiment will be described. In recent imaging devices with a stacked structure, in order to increase the number of pixels and the speed, the defect rate of the control lines 321 to 322 is higher than that of individual pixels. n and vertical signal lines 311 to 31 m There is a tendency for the defective rate to be high for the wiring and the connection nodes of the connection parts 43 and 44. Therefore, in each embodiment of the present disclosure, in the first semiconductor substrate 41 which is the sensor substrate on which the pixel array unit 11 is formed, the focus is on checking only the wiring layer, and by adding a minimum amount of circuitry, it becomes possible to inspect the presence or absence of open / short circuits in the wiring with a small number of probe terminals.

[0056] 5 is a diagram showing a specific configuration example of a first semiconductor substrate 41 according to each embodiment. In the first semiconductor substrate 41, a first wiring is formed corresponding to a first pixel row, and a second wiring is formed corresponding to a second pixel row. Hereinafter, the wiring formed corresponding to a pixel row is appropriately referred to as a row wiring. Hereinafter, the first row wiring formed corresponding to a pixel row refers to the control line 321 formed corresponding to the first pixel row, and the second row wiring formed corresponding to a pixel row refers to the control line 32 formed corresponding to the nth pixel row. n Between the first row wiring and the second row wiring, control lines 322 to 32 n-1 There are a number of row wirings shown as

[0057] In addition, a first column wiring is formed in the first semiconductor substrate 41 corresponding to the first pixel column, and a second column wiring is formed in the first pixel column. Hereinafter, the wiring formed in correspondence with the pixel column is referred to as a column wiring as appropriate. The first column wiring formed in correspondence with the pixel column refers to the vertical signal line 311 formed in correspondence with the first pixel column, and the second column wiring formed in correspondence with the pixel column refers to the vertical signal line 311 formed in correspondence with the m-th pixel column. m In addition, vertical signal lines 312 to 313 are provided between the first column wiring and the second column wiring. m-1 There are a number of column wirings shown as

[0058] As described in FIG. 4, the first semiconductor substrate 41 has wiring (control lines 321 to 32 n and vertical signal lines 311 to 31 m ) and a pixel control unit formed on a second semiconductor substrate 42, which is a second substrate, are provided with connection portions 43A and 43B and connection portions 44A and 44B. Here, when the circuit of the pixel control unit to be connected is present on only one side in the vertical direction, it is sufficient to provide only one of the connection portions 43A and 43B. For example, the vertical signal lines 311 to 31 m and the analog-digital conversion unit 14 are connected via a connection unit 43A. Similarly, when the circuit of the pixel control unit to be connected is present on only one side in the horizontal direction, only one of the connection units 44A and 44B may be provided. For example, the control lines 321 to 32 n and row selection unit 12 are connected via connection portion 44A. In the following, when there is no need to distinguish between connection portions 43A and 43B, these connection portions 43A and 43B will be collectively referred to as connection portion 43.

[0059] On the first semiconductor substrate 41, further provided are a detection portion 45A, a bias portion 45B corresponding to the detection portion 45A, and a detection portion 46A, and a bias portion 46B corresponding to the detection portion 46A.

[0060] The first semiconductor substrate 41 is further provided with the following terminals and electrodes in association with the detection unit 45A and bias unit 45B, and the detection unit 46A and bias unit 46B. That is, the first semiconductor substrate 41 is provided with terminals 47A and 47C, an electrode 47D, and a control terminal 49A, each of which is connected to the detection unit 45A. The first semiconductor substrate 41 is further provided with terminals 48A and 48C, an electrode 48D, and a control terminal 50A, each of which is connected to the detection unit 46A. The first semiconductor substrate 41 is further provided with a control terminal 49B and an electrode 47B, each of which is connected to the bias unit 45B. The first semiconductor substrate 41 is further provided with a control terminal 50B and an electrode 48B, each of which is connected to the bias unit 46B.

[0061] The terminals, electrodes and control terminals provided on the first semiconductor substrate 41 are probe contact terminals used for testing in the wafer state.

[0062] The bias unit 45B (first circuit) is m The bias unit 45B includes a bias circuit for applying a voltage to the control terminal 49B. When a predetermined voltage is applied to the control terminal 49B, the bias unit 45B is connected to the control terminal 49B and the vertical signal lines 311 to 31. m The vertical signal lines 311 to 31 are connected to some or all of the vertical signal lines 311 to 31. m At the far end of the bias unit 45B, vertical signal lines 311 to 31 m A detection unit 45A for detecting application of a voltage to the vertical signal lines 311 to 31 is connected to the control terminal 49A. The detection unit 45A (second circuit) can monitor, for example, the voltage at the terminal 47A from the terminal 47C. In addition, in the detection unit 45A, when a predetermined voltage is applied to the control terminal 49A, the electrode 49D and the vertical signal lines 311 to 31 m Connect some or all of the following:

[0063] Similarly, the control lines 321 to 32 n Each of the control lines 321 to 32 n A bias unit 46B for applying a voltage to each of the control lines 321 to 32 nA detection unit 46A for detecting the application of a voltage to the

[0064] Incidentally, the detection units 45A and 46A and the bias units 45B and 46B arranged on the first semiconductor substrate 41 are generally not used after the first semiconductor substrate 41 and the second semiconductor substrate 42 are bonded together to form a laminate.

[0065] According to each embodiment of the present disclosure, in the three-dimensional stacked structure imaging element 1, it is possible to realize inspection for the presence or absence of open / short circuits by adding a small-scale circuit including detection units 45A and 46A, bias units 45B and 46B, terminals 47A, 47C, 48A and 48C, electrodes 47B, 47D, 48B and 48D, and control terminals 49A, 49B, 50A and 50B. This makes it possible to both suppress an increase in chip area and improve yield.

[0066] [3. First embodiment] Next, a first embodiment of the present disclosure will be described. In the first embodiment, vertical signal lines 311 to 31 m 1 is an example of an imaging element 1 for easily inspecting whether or not there is an open circuit (disconnection).

[0067] (3-0-1. Configuration Example of First Semiconductor Substrate According to First Embodiment) 6 is a diagram showing an example of the configuration of a first semiconductor substrate 41a according to the first embodiment. In FIG. 6, the first semiconductor substrate 41a corresponds to the first semiconductor substrate 41 shown in FIG. 5, and is laminated with a second semiconductor substrate 42 to configure the imaging element 1. In FIG. 6, each pixel 2 included in the pixel array section 11 and each control line 321-322 shown in FIG. n 6, the configuration related to the pixel rows (the control lines 321 to 322) among the configurations shown in FIG. n The configurations related to the above are omitted as appropriate.

[0068] In FIG. 6, the connection section 43A has connection nodes N1a , N 2a , N 3a , N 4a , …, N (m-2)a , N (m-1)a , N ma Similarly, the connection section 43B includes connection nodes N 1b , N 2b , N 3b , N 4b , …, N (m-2)b , N (m-1)b , N mb Includes.

[0069] Each connection node N 1b ~N mb 3, the vertical signal lines 311 to 31 m Similarly, one end of each connection node N 1a ~N ma 3, the vertical signal lines 311 to 31 m The other end of the

[0070] The first semiconductor substrate 41 and the second semiconductor substrate 42 have respective connection nodes N 1a ~N ma , or each connected node N 1b ~N mb Thus, they are electrically connected.

[0071] The bias unit 45Ba includes, as a bias circuit, switch elements SW1, SW2, SW3, SW4, . . . , SW (m-2) , S.W. (m-1) , S.W. m , each of the switch elements SW1 to SW m Each of the switch elements SW1 to SW m Each of the drains is connected to the electrode 47B in common, and the source is connected to the connection node N 1b ~N mb Each of the vertical signal lines 311 to 31 m is connected one-to-one to one end of the

[0072] Each switch element SW1 to SW m A control terminal 49B is commonly connected to the control ends (gates) of the switch elements SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW22, SW30, SW41, SW50, SW61, SW72, SW83, SW94, SW12, SW13, SW14, SW15, SW26, SW27, SW31, SW42, SW51, SW6 1b ~SW mb is turned on (conductive), and the electrode 47B and each of the vertical signal lines 311 to 31 m and the voltage applied to the electrode 47B is connected to each of the vertical signal lines 311 to 31 m That is, the voltage is applied to each of the switch elements SW1 to SW m The vertical signal lines 311 to 31 m Here, each switch element SW 1b ~SW mb Although a voltage drop occurs at the threshold value, the effect of the voltage drop can be suppressed by increasing the voltage applied to the control terminal 49B within the range permitted by the withstand voltage.

[0073] The detection unit 45Aa has transfer elements TR1, TR1, TR1, TR1, . . . , TR (m-2) , T.R. (m-1) , T.R. m , each of the transfer elements TR1 to TR m Each of the transfer elements TR1 to TR2 is configured of an NMOS transistor, for example, similar to the pixel 2. m For each gate, each connection node N 1a ~N ma Through the vertical signal lines 311 to 31 m are connected one-to-one.

[0074] That is, each of the transfer elements TR1 to TR m The vertical signal lines 311 to 31 m The transfer elements TR1 to TR2 can be considered as input circuits to which the voltages applied to the transfer elements TR1 to TR2 are input. m has the function of a switch whose conductive / non-conductive state is controlled according to the voltage input (applied) to the gate.

[0075] In addition, each of the transfer elements TR1 to TR m are connected in series, with terminal 47A connected to one end of the series connection and terminal 47C connected to the other end.

[0076] More specifically, each of the transfer elements TR1 to TR m 6, the terminal 47A is connected to the drain of the transfer element TR1 located at the left end in FIG. 6, and the source is connected to the drain of the transfer element TR2 adjacent to the transfer element TR1. The source of the transfer element TR2 is connected to the drain of the transfer element TR3 adjacent to the transfer element TR2, and the source of the transfer element TR3 is connected to the drain of the transfer element TR4 adjacent to the transfer element TR3. In this manner, each of the transfer elements TR1 to TR (m-1) The source of each transfer element is connected to the drain of the adjacent transfer element. (m-1) The source of the transfer element TR m- The drain of the transfer element TR m The source of is connected to terminal 47C.

[0077] With this configuration, each of the transfer elements TR1 to TR m The electrode 47B is connected to the gate of this transistor.

[0078] In the following, each of the switch elements SW1 to SW m In the case where it is not necessary to distinguish between the transfer elements TR1 to TR2, the transfer elements TR3 to TR4 are represented by the switch element SW. m When it is not necessary to distinguish between them, the following description will be given by using the transfer element TR as a representative.

[0079] As shown in FIG. 6, each transistor (transfer elements TR1 to TR m) are connected in sequence to adjacent transistors via their drains and sources, which is called a series connection. In a series connection, when a voltage is applied to the gate of each transistor, the output is determined by the logical product of the state of each gate. In other words, when at least one of the series-connected transistors is off (non-conducting), both ends of the series connection are non-conducting.

[0080] In addition, although specific examples will be described later, a configuration in which multiple transistors are connected in common at their drains and sources and in which the gates of each transistor are connected independently is called a parallel connection. In a parallel connection, when a voltage is applied to the gate of each transistor, the output is determined by the logical sum of the state of each gate. In other words, when at least one of the transistors connected in parallel is in an on (conducting) state, both ends of the parallel connection (between the source and drain connected in common) are in a conducting state.

[0081] (3-0-2. Example of inspection method according to the first embodiment) In the configuration according to the first embodiment, the vertical signal lines 311 to 31 m A method for inspecting whether or not there is an open circuit (hereinafter, referred to as open circuit inspection as appropriate) will be described in more detail. In the case of the first embodiment, during inspection, a probe (inspection needle) connected to a predetermined inspection device is applied to terminals 47A and 47C, electrode 47B, and control terminal 49A. The inspection device sets electrode 47B to a predetermined high-level voltage (3 [V]), and also sets control terminal 49B to a predetermined high-level voltage (3 [V]). In this case, each of vertical signal lines 311 to 31 m If there is no open circuit in each of the transfer elements TR1 to TR m Each switch element SW1 to SW m A voltage attenuated by the threshold (for example, 2 [V]) is applied.

[0082] In addition, each of the transfer elements TR1 to TR mThe voltage attenuated by the threshold value, for example, 2 [V], is set as a high-level voltage, and the transfer elements TR1 to TR2 are turned on (conductive) when this high-level voltage is applied to the gate. m A voltage lower than this voltage and a predetermined voltage is set to a low level and the transistor is in an off (non-conducting) state.

[0083] In this state, a voltage VB of, for example, 1 [V] is applied to the terminal 47A as a test voltage by the test device, and the voltage VM of the terminal 47C is monitored (measured). m If there is no open circuit (disconnection), a voltage VM of 1 [V] is detected at terminal 47C.

[0084] On the other hand, each of the vertical signal lines 311 to 31 m If even one open (disconnected) portion exists in terminal 47A, voltage VB applied to terminal 47A is not conducted from terminal 47A to terminal 47C, and voltage VM at terminal 47C becomes unstable.

[0085] 7 is a diagram for explaining the open inspection according to the first embodiment. In the example of FIG. 7, in the first semiconductor substrate 41a, each of the vertical signal lines 311 to 31 m An open portion exists in one of the vertical signal lines 313. In this case, due to the open (disconnection) of the vertical signal line 313, a predetermined voltage is not applied to the gate of the transfer element TR3 whose gate is connected to the vertical signal line 313, and the transfer element TR3 is turned off (conductive). As a result, m The path formed by the series connection is cut off, and the voltage VM at the terminal 47C becomes unstable.

[0086] Therefore, according to the configuration of the first embodiment, by monitoring the voltage VM of the terminal 47C, m It is thus possible to determine whether an open portion exists in any of the first semiconductor substrates 41a, thereby making it possible to determine whether the first semiconductor substrate 41a is a non-defective product or a defective product.

[0087] (3-0-3. Examples of the structure of the needle contact terminal applicable to each embodiment) Next, a structural example of the needle contact terminal according to each embodiment will be described. The following description will be given by taking the first semiconductor substrate 41 as an example unless otherwise specified. The terminals 47A, 47C, 48A, and 48C, the electrodes 47D, 47B, 48B, and 48D, and the control terminals 49A, 49B, 50A, and 50B in the first semiconductor substrate 41 shown in FIG. 5 are all needle contact terminals for contacting the probe. In the example of FIG. 6, the terminals 47A and 47C, the electrode 47B, and the control terminal 49B are the needle contact terminals.

[0088] The voltage of these probe terminals needs to be fixed when the inspection is completed and the semiconductor substrate is laminated with the second semiconductor substrate 42. One method for fixing the voltage of the probe terminals is to wire bond the probe terminals as external pads. This method may result in an increase in chip area, an increase in the time required for the bonding process, and a loss in yield during bonding.

[0089] In each embodiment of the present disclosure, a first semiconductor substrate 41 on which the needle contact terminal is provided and a second semiconductor substrate 42 are stacked together, so that the needle contact terminal can be connected to a predetermined voltage and the voltage of the needle contact terminal can be fixed.

[0090] 8A to 8C are diagrams for explaining examples of the structure of the needle contact terminal according to each embodiment. Fig. 8A is a schematic diagram showing, for example, an electrode 47B and its vicinity in the first semiconductor substrate 41. In Fig. 8A, a connection terminal 510A connected to the electrode 47B is disposed on the first semiconductor substrate 41, and a connection terminal 510B that is not connected to the electrode 47B and the connection terminal 510A in the first semiconductor substrate 41 is provided in the vicinity of the connection terminal 510A. Here, the connection terminals 510A and 510B are intended to be connected to a connection terminal (described later) provided on the second semiconductor substrate 42 by Cu-Cu hybrid bonding.

[0091] The inspection is performed on the first semiconductor substrate 41 alone, without being stacked with the second semiconductor substrate 42. Therefore, the connection terminal 510A and the connection terminal 510B are mutually separate nodes.

[0092] Here, by laminating the first semiconductor substrate 41 and the second semiconductor substrate 42 together, the second semiconductor substrate 42 is configured so that the connection terminals 510A and the connection terminals 510B are electrically connected to each other.

[0093] 8B is a cross-sectional view showing a first structural example in which connection terminal 510A and connection terminal 510B are electrically connected when first semiconductor substrate 41 and second semiconductor substrate 42 are laminated by bonding them together. In FIG. 8B, connection terminals 511A and 511B are provided on second semiconductor substrate 42 at positions corresponding to connection terminals 510A and 510B, respectively. These connection terminals 511A and 511B are connected by wiring 512 on second semiconductor substrate 42. In addition, terminal 513 connected to connection terminal 510B is provided on first semiconductor substrate 41.

[0094] In this configuration, by bonding the first semiconductor substrate 41 and the second semiconductor substrate 42 together, the connection terminals 510A and 511A, and the connection terminals 510B and 511B are connected to each other. This connects the connection terminal 510A, i.e., the electrode 47B, to the terminal 513 via the connection terminals 510A and 511A, the wiring 512, and the connection terminals 510B and 511B. By applying a predetermined voltage to the terminal 513, the voltage of the electrode 47B can be fixed.

[0095] 8C is a cross-sectional view showing a second structural example in which connection terminal 510A and connection terminal 510B are electrically connected when first semiconductor substrate 41 and second semiconductor substrate 42 are laminated together. In this second structural example, connection terminal 510B is provided on second semiconductor substrate 42 at a position corresponding to connection terminal 510A. Also, terminal 514 connected to connection terminal 510B is provided on second semiconductor substrate 42.

[0096] In such a configuration, by bonding the first semiconductor substrate 41 and the second semiconductor substrate 42 together, the connection terminal 510A and the connection terminal 510B are connected. As a result, the connection terminal 510A, i.e., the electrode 47B, is connected to the terminal 514 via the connection terminals 510B and 511B. By applying a predetermined voltage to the terminal 514, the voltage of the electrode 47B can be fixed. This second structure is effective, for example, when an intermediate voltage (a specific example will be described later) is supplied from a power supply line arranged on the second semiconductor substrate 42.

[0097] (3-1. First Modification of the First Embodiment) Next, a first modified example of the first embodiment will be described. In the first modified example of the first embodiment, the detection unit 45A and the bias unit 45B each include two systems of circuits, and the vertical signal lines 311 to 31 m 1 is an example of an imaging element 1 for easily inspecting whether there is an open circuit (disconnection) and whether there is a short circuit (short circuit) between adjacent wirings.

[0098] (3-1-1. Configuration Example of First Semiconductor Substrate According to First Modification of First Embodiment) Fig. 9 is a diagram showing an example of the configuration of a first semiconductor substrate 41b according to a first modified example of the first embodiment. Fig. 9 corresponds to Fig. 6 described above, and the first semiconductor substrate 41b is laminated with a second semiconductor substrate 42 to configure the image sensor 1.

[0099] 9, the bias unit 45Bb includes, as a bias circuit, switch elements SW1, SW2, SW3, SW4, . . . , SW5, each of which is configured of, for example, an NMOS transistor, the number of which corresponds to the number (m) of columns of the pixel array unit 11. (m-2)b , S.W. (m-1) , S.W. m , including.

[0100] In a first modification of the first embodiment, two electrodes 47B1 and 47B2 and two control terminals 49B1 and 49B2 are connected to a bias unit 45Bb. A bias circuit of the bias unit 45Bb includes two systems of circuits, a first system including the electrode 47B1 and the control terminal 49B1, and a second system including the electrode 47B2 and the control terminal 49B2.

[0101] In the first system, the electrode 47B1 is connected to the switch elements SW1 to SW m A control terminal 49B1 is connected to one end (drain) of a plurality of switch elements (m / 2 switch elements when m is an even number) selected every other one from the switch elements SW1 to SW m The control ends (gates) of a plurality of switch elements (m / 2 switch elements when m is an even number) selected every other one from are commonly connected.

[0102] In the second system, the electrode 47B2 is connected to the switch elements SW1 to SW m A control terminal 49B2 is connected in common to one end (drain) of a plurality of switch elements selected so as not to overlap with the switch element commonly connected to the electrode 47B1. m 3, is commonly connected to the control ends (gates) of a plurality of switch elements selected so as not to overlap with the switch elements commonly controlled by the voltage applied to the control terminal 49B1.

[0103] For example, in FIG. 9, each of the switch elements SW1 to SW m The leftmost switch element SW1 is numbered 1, and the rightmost switch elements SW1 to SW m In this case, the first system is made up of odd-numbered switch elements SW1, SW3, ..., SW (m-1) , an electrode 47B1 is commonly connected to one end of each of the odd-numbered switch elements SW1, SW3, . . . , SW (m-1) A control terminal 49B1 is commonly connected to the control ends of these.

[0104] The second system includes even-numbered switch elements SW2, SW4, . . . , SW m , an electrode 47B2 is commonly connected to one end of each of the even-numbered switch elements SW2, SW4, . . . , SW m A control terminal 49B2 is commonly connected to the control ends of these.

[0105] Each switch element SW1 to SW m The other end of each of the connection nodes N 1b ~N mb Through the vertical signal lines 311 to 31 m Each of these is connected one-to-one.

[0106] 9, the detection unit 45Ab includes transfer elements TR1, TR1, TR1, TR1, . . . , TR2, each of which is made of, for example, an NMOS transistor, the number of which corresponds to the number (m) of columns of the pixel array unit 11. (m-2) , T.R. (m-1) , T.R. m , each of the transfer elements TR1 to TR m For each gate, there is a one-to-one correspondence between each connection node N 1a ~N ma is connected.

[0107] Here, each of the transfer elements TR1 to TR m Each of the transfer elements TR1 to TR m A first group is formed by connecting a plurality of transfer elements (m / 2 transfer elements when m is an even number) alternately selected from the transfer elements TR1 to TR2. m The first group is connected to a second group in which transfer elements not included in the first group are connected in series, and one end and the other end of each series connection are connected in common. One end common to the first group and the second group is connected to terminal 47A, and the other common end is connected to terminal 47C. The first group corresponds to the above-mentioned first system, and the second group corresponds to the above-mentioned second system.

[0108] In the example of FIG. 9, each connection node N 1a ~N ma Each of the transfer elements TR1 to TRm For the leftmost connection node N 1a The transfer element TR1 connected to the transfer element TR1 is numbered as the first, and the numbers of the transfer elements TR1 to TR m When the odd-numbered transfer elements TR1, TR3, ..., TR (m-1) are connected in series as a first group. m are connected in series as the second group.

[0109] For each of the first and second groups, the drains of the transfer elements with the smallest numbers are commonly connected to a terminal 47A, and the sources of the transfer elements with the largest numbers are commonly connected to a terminal 47C. In the example of FIG. 9, the drains of the transfer elements TR1 and TR2 are commonly connected to a terminal 47A, and the source of the transfer element TR (m-1) and T.R. m The sources of these are commonly connected to terminal 47A.

[0110] (3-1-2. Example of inspection method according to the first modified example of the first embodiment) In the configuration according to the first modification of the first embodiment, the vertical signal lines 311 to 31 m A method for inspecting whether there is an open between adjacent wirings (hereinafter, referred to as open inspection) will be described more specifically.

[0111] Before describing the open testing in the configuration related to the first modified example of the first embodiment, in order to facilitate understanding, a case in which a false detection occurs in the open testing in the configuration of the first embodiment, as explained using FIG. 6, will be described.

[0112] 10 is a diagram for explaining erroneous detection that may occur in an open test using the configuration (first semiconductor substrate 41a) of the first embodiment. In FIG. 10, it is assumed that an open portion exists in the vertical signal line 313. In the configuration shown in FIG. 10, a high-level voltage is applied to the control terminal 49B during testing to turn on each of the switch elements SW1 to SW m are turned on, and each of the vertical signal lines 311 to 31m A predetermined voltage is applied to the vertical signal line 313. The vertical signal line 313 is in a floating state between the open portion and the gate of the transfer element TR3.

[0113] Here, each of the vertical signal lines 311 to 31 m If the interval between the vertical signal line 313 and the vertical signal line 314 is narrower than a certain level, coupling may occur between the vertical signal line 313 and an adjacent wiring, for example, the vertical signal line 314. If this coupling occurs, the voltage of the vertical signal line 313 increases between the open portion of the vertical signal line 313 in a floating state and the transfer element TR3 due to the influence of the voltage of the vertical signal line 314. This may cause the transfer element TR3 to be turned on, resulting in a conductive state between the terminal 47A and the terminal 47C. In this case, the open state of the vertical signal line 313 will not be detected correctly.

[0114] In the configuration according to the first modification of the first embodiment, the vertical signal lines 311 to 31 m A method for performing the open inspection will be described in more detail below. Fig. 11 is a diagram for explaining the open inspection using the configuration (first semiconductor substrate 41b) of the first modified example of the first embodiment.

[0115] In the first modification of the first embodiment, the open inspection is performed on each of the vertical signal lines 311 to 31 m On the other hand, the odd-numbered vertical signal lines 311, 313, . . . , 31 m-1 , and each of the even-numbered vertical signal lines 312, 314, ..., 31 m-2 , 31 m Open inspections for, and, will be conducted separately.

[0116] For example, each of the odd-numbered vertical signal lines 311, 313, . . . , 31 m-1When performing an open test on the terminals 47A and 47C, the electrodes 47B1 and 47B2, and the control terminals 49A1 and 49A2, for example, a probe connected to a predetermined test device is applied to the terminals 47A and 47C, the electrodes 47B1 and 47B2, and the control terminals 49A1 and 49A2. The test device sets the electrode 47B1 to a predetermined voltage (assumed to be 3 [V]) and the electrode 47B2 to 0 [V]. The control terminals 49B1 and 49B2 are each set to a predetermined voltage (assumed to be 3 [V]).

[0117] In this case, the odd-numbered vertical signal lines 311, 313, . . . , 31 m-1 , TR1, TR2, . . . , TR3, . . . (m-1) Each gate is connected to odd-numbered switch elements SW1, SW3, ..., SW (m-1) A voltage attenuated by the threshold (for example, 2 [V]) is applied.

[0118] On the other hand, each of the even-numbered transfer elements TR2, TR4, . . . , TR (m-2) b, T.R. m A voltage of 0 [V] is applied to each gate in accordance with the setting of the electrode 47B2. Therefore, each of the even-numbered transfer elements TR2, TR4, ..., TR (m-2) b, T.R. m are all in the off state.

[0119] In this state, a voltage VB of, for example, 1 [V] is applied to the terminal 47A by the inspection device, and the voltage VM of the terminal 47C is monitored (measured). (m-1) If there are no opens in any of these, a voltage VM of 1 [V] is detected at terminal 47C.

[0120] On the other hand, the odd-numbered vertical signal lines 311, 313, . . . , 31 (m-1) If an open circuit exists in at least one of the vertical signal lines (assumed to be the vertical signal line 313), the voltage VB applied to the terminal 47A is not conducted from the terminal 47A to the terminal 47C, and the voltage VM of the terminal 47C becomes indefinite.

[0121] 11, a voltage of 0 [V] is applied to the vertical signal lines 312 and 314 adjacent to both sides of the vertical signal line 313 where the open portion exists. Therefore, for example, erroneous detection due to coupling of the vertical signal line 314 with the vertical signal line 313 can be prevented.

[0122] Even-numbered vertical signal lines 312, 314, ..., 31 (m-2) , 31 m The open test of odd-numbered terminals is performed in the same manner. In this case, electrode 47B1 is set to 0 [V], and electrode 47B2 is set to a predetermined voltage (for example, 3 [V]). Note that control terminals 49B1 and 49B2 are each set to a predetermined voltage (3 [V]) in the same manner as in the odd-numbered open test.

[0123] 11, the control terminals 49B1 and 49B2 may be shared to perform the same open inspection as described above. (m-1) and even-numbered vertical signal lines 312, 314, . . . , 31 (m-2) , 31 m An open inspection similar to that described above can also be performed by dividing the test into

[0124] According to the first modification of the first embodiment, the vertical signal lines 311 to 31 m In the above-mentioned open inspection, it is possible to inspect whether there is a short circuit between adjacent wirings in each of the vertical signal lines 311 to 31 m This means that a voltage of 2 [V] or 0 [V] is applied to every other wire. Therefore, by measuring the current of electrode 47B1 or 47B2, it is possible to detect the presence or absence of a short circuit between adjacent wires.

[0125] In the first modification of the first embodiment, the voltage of a vertical signal line adjacent to a vertical signal line to be inspected for open circuit can be set to 0 [V]. Therefore, even if there is a vertical signal line that is in a floating state due to an open circuit, it is possible to suppress erroneous detection due to a voltage rise caused by coupling between the vertical signal line and the adjacent vertical signal line.

[0126] (3-2. Second Modification of the First Embodiment) Next, a second modification of the first embodiment will be described. In the second modification of the first embodiment, similarly to the above, the vertical signal lines 311 to 31 m 1 is an example of an image sensor 1 for easily inspecting whether there is an open circuit (disconnection) and whether there is a short circuit (short circuit) between adjacent wirings. Here, in the second modification of the first embodiment, the detection unit 45Ac and the bias unit 45B each include two circuits, and the bias unit 45B has a common electrode connected to the two circuits. The detection unit 45Ac also detects the vertical signal lines 311 to 31 m A reset element RS is provided to reset the floating state of the transistor.

[0127] (3-2-1. Configuration Example of First Semiconductor Substrate According to Second Modification of First Embodiment) Fig. 12 is a diagram showing an example of the configuration of a first semiconductor substrate 41c according to a second modified example of the first embodiment. Fig. 12 corresponds to Fig. 6 described above, and the first semiconductor substrate 41c is laminated with a second semiconductor substrate 42 to configure the image sensor 1.

[0128] 12, the bias unit 45Bc includes, as a bias circuit, switch elements SW1, SW2, SW3, SW4, . . . , SW5, each of which is configured of an NMOS transistor, the number of which corresponds to the number (m) of columns of the pixel array unit 11. (m-2) , S.W. (m-1) , S.W. m , including.

[0129] In the second modified example of the first embodiment, an electrode 47B and two control terminals 49B1 and 49B2 are connected to a bias section 45Bc.

[0130] The bias circuit of the bias unit 45Bc includes two circuits, a first circuit using a control terminal 49B1 and a second circuit using a control terminal 49B2. The electrode 47B is connected to each of the switch elements SW1, SW2, SW3, SW4, ..., SW (m-2)b , S.W. (m-1) , S.W. m One end (drain) of each of the switch elements SW1 to SW m The other end (source) of each is the connection node N 1b ~N mb Through vertical signal lines 311 to 31 m is connected to one end of the

[0131] In the bias unit 45Bc, the switch elements SW1 to SW m The control terminals (gates) of a plurality of switch elements (when m is an even number, m / 2 switch elements) selected every other one from the control terminal 49B1 are commonly connected. m Therefore, the control ends of a plurality of switch elements selected so as not to overlap with the switch element commonly connected to the control terminal 49B1 are commonly connected.

[0132] In the example of FIG. 12, odd-numbered switch elements SW1, SW3, . . . , SW (m-1) The control ends of the even-numbered switch elements SW 2b , SW4, …, SW (m-2) , S.W. m The control ends of these are commonly connected to a control terminal 49B2.

[0133] In the detection unit 45Ac according to the second modification of the first embodiment, a connection unit 43B is provided with reset elements RS1, RS2, RS3, RS4, ..., RS5, each of which is, for example, an NMOS transistor, in a number corresponding to the number (m) of columns of the pixel array unit 11. (m-2) , R.S. (m-1) , R.S. m, are added. Terminals 47A and 47C, an electrode 47D, and control terminals 49A1 and 49A2 are connected to detection unit 45Ac.

[0134] Each reset element RS1 to RS m The drains of the 1a ~N ma and each transfer element TR1 to TR m The reset elements RS1 to RS m The sources of the transistors 47A and 47B are commonly connected to the electrode 47D.

[0135] Each reset element RS1 to RS m The gates of a plurality of reset elements RS (m / 2 elements when m is an even number) selected every other one from the reset elements RS1 to RS2 are commonly connected to a control terminal 49A1. m The gates of a plurality of reset elements RS selected so as not to overlap with the reset element RS to which the control terminal 49A1 is connected are commonly connected to the control terminal 49A2.

[0136] In the example of FIG. 12, odd-numbered reset elements RS1, RS3, . . . , RS (m-1) , and the gates of the even-numbered reset elements RS2, RS4, ..., RS (m-2) , R.S. m , each gate is commonly connected to a control terminal 49A2.

[0137] (3-2-2. Example of Inspection Method According to Second Modification of First Embodiment) In the configuration according to the first modification of the first embodiment, the vertical signal lines 311 to 31 m A method for inspecting whether there is an open in the adjacent wiring space (hereinafter, referred to as open inspection) will be described in more detail.

[0138] In the second modified example of the first embodiment, similarly to the first modified example of the first embodiment described above, the open inspection is performed on each of the vertical signal lines 311 to 31m On the other hand, the odd-numbered vertical signal lines 311, 313, . . . , 31 m-1 , and each of the even-numbered vertical signal lines 312, 314, ..., 31 m-2 , 31 m Open inspections for, and, will be conducted separately.

[0139] As an example, each of the odd-numbered vertical signal lines 311, 313, . . . , 31 m-1 When performing an open test on the terminals 47A and 47C, the electrodes 47B and 47D, and the control terminals 49A1 and 49A2, for example, a probe connected to a predetermined test device is applied to the terminals 47A and 47C, the electrodes 47B and 47D, and the control terminals 49A1 and 49A2. The test device sets the electrode 47B to a predetermined voltage (assumed to be 3 [V]), the control terminal 49B1 to 3 [V], and the control terminal 49B2 to a predetermined voltage (assumed to be 0 [V]).

[0140] Voltage VS of electrode 47D connected to detection unit 45Ac is set to a ground voltage, for example, 0 [V]. Furthermore, control terminal 49A1 is set to a predetermined voltage (assumed to be 0 [V]), and control terminal 49A2 is set to 3 [V].

[0141] In this case, in the same manner as in the first modification of the first embodiment described above, the odd-numbered vertical signal lines 311, 313, . . . , 31 m-1 , TR1, TR2, . . . , TR3, . . . (m-1) Each gate is connected to odd-numbered switch elements SW1, SW3, ..., SW (m-1) A voltage attenuated by the threshold (for example, 2 [V]) is applied.

[0142] On the other hand, each of the even-numbered transfer elements TR2, TR4, . . . , TR (m-2) , T.R. m A voltage of 0 [V] is applied to each gate in accordance with the setting of the control terminal 49A2. Therefore, each of the even-numbered transfer elements TR2, TR4, ..., TR (m-2) b, T.R. m are all in the off state.

[0143] In this state, a voltage VB of, for example, 1 [V] is applied to the terminal 47A by the inspection device, and the voltage VM of the terminal 47C is monitored (measured). (m-1) If there are no opens in any of these, a voltage VM of 1 [V] is detected at terminal 47C.

[0144] On the other hand, the odd-numbered vertical signal lines 311, 313, . . . , 31 (m-1) If an open circuit exists in at least one of the vertical signal lines (assumed to be the vertical signal line 313), the voltage VB applied to the terminal 47A is not conducted from the terminal 47A to the terminal 47C, and the voltage VM of the terminal 47C becomes indefinite.

[0145] Even-numbered vertical signal lines 312, 314, ..., 31 (m-2) , 31 m The open test of is performed in the same manner. In this case, electrode 47B is set to a predetermined voltage (for example, 3 [V]). The settings of control terminals 49B1 and 49B2 are set by swapping the voltages used in the odd-numbered tests. Specifically, the voltage of control terminal 49A1 is set to 0 [V], and the voltage of control terminal 49A2 is set to 3 [V]. Accordingly, the voltage of control terminal 49B2 connected to detection unit 45Ac is set to 3 [V], and the voltage of control terminal 49B2 is set to 0 [V].

[0146] Here, in the second modified example of the first embodiment, the voltages set for the control terminals 49A1 and 49A2, and the control terminals 49B1 and 49B2 are complementary voltages at the gates of the switch element SW and the reset element RS connected to the same vertical signal line 31.

[0147] Specifically, taking the vertical signal line 312 as an example, a switch element SW2 and a reset element RS2 are connected to the vertical signal line 312. A voltage of, for example, 0 [V] is set to the control terminal 49B1 connected to the gate of the switch element SW2, and a voltage of, for example, 3 [V] is set to the control terminal 49A1 connected to the gate of the reset element RS2. On the other hand, when a voltage of, for example, 3 [V] is set to the control terminal 49B1 connected to the gate of the switch element SW2, a voltage of, for example, 0 [V] is set to the control terminal 49A1 connected to the gate of the reset element RS2.

[0148] Here, an example will be described in which a voltage of 0 [V] is set for control terminal 49B1 and a voltage of 3 [V] is set for control terminal 49A1. In the absence of reset element RS3, 0 [V] is applied to the gate of switch element SW2, so that vertical signal line 312 connected to the source is in a floating state and the voltage is undefined.

[0149] In contrast, in the second modified example of the first embodiment, the drain of the reset element RS2 is connected to the vertical signal line 312. At this time, the voltage VS of the source of the reset element RS2 is set to 0 [V] (or ground potential), the voltage of the gate is set to 3 [V], and the reset element RS2 is set to an ON state. This fixes the voltage of the vertical signal line 312 to 0 [V], and prevents the vertical signal line 312 that is not being inspected from being in a floating state.

[0150] According to the second modification of the first embodiment, similarly to the first modification of the first embodiment described above, the vertical signal lines 311 to 31 m In the above-mentioned open inspection, it is possible to perform a short circuit inspection between adjacent wirings in each of the vertical signal lines 311 to 31 m This means that a voltage of 2 [V] or 0 [V] is applied to every other wire. Therefore, by measuring the current of electrode 47B or 47D, it is possible to detect the presence or absence of a short circuit between adjacent wires.

[0151] In the second modification of the first embodiment, the voltage of a vertical signal line adjacent to a vertical signal line to be inspected for open circuit can be set to 0 [V]. Therefore, even if there is a vertical signal line that is in a floating state due to an open circuit, it is possible to suppress erroneous detection due to a voltage rise caused by coupling between the vertical signal line and the adjacent vertical signal line.

[0152] In addition, in the second modified example of the first embodiment, by applying complementary voltages to the gates of the switch element SW and the reset element RS connected to the same vertical signal line 31, the floating state of the vertical signal line 31 can be avoided, enabling more stable testing.

[0153] 12, the complementary voltages for the control terminals 49A1 and 49B1 and the control terminals 49A2 and 49B2 are set by the control of the inspection device, but this is not limited to the example. That is, a circuit may be formed on the first semiconductor substrate 41c to generate, for example, one voltage input, the voltage and a voltage complementary to the voltage.

[0154] (3-3. Third Modification of the First Embodiment) Next, a third modified example of the first embodiment will be described. The third modified example of the first embodiment is an example in which a terminal for inputting a voltage VB for inspection or for extracting a voltage VM for monitoring is added to the configuration according to the second modified example of the first embodiment described above.

[0155] 13 is a diagram showing an example of the configuration of a first semiconductor substrate according to a third modified example of the first embodiment. A first semiconductor substrate 41d according to the third modified example of the first embodiment is an example in which a terminal is added to an intermediate portion of the first and second groups of the series connection of the detection units 45Ac according to the second modified example of the first embodiment described above.

[0156] More specifically, as shown in FIG. 13, in a first semiconductor substrate 41d according to the third modification of the first embodiment, odd-numbered transfer elements TR1, TR3, . . . , TR(m-1) The midpoint of the series connection of the first group according to (m-2) , TR m The midpoint of the series connection of the second group of

[0157] In the example of FIG. 13, for the sake of explanation, in the first group, between the transfer element TR3 and the next transfer element, and in the second group, between the transfer element TR4 and the next transfer element, the terminal 47E is shown to be commonly connected. Also, the vertical signal lines adjacent to the left and right of the midpoint are, with 1 < k < m, the vertical signal lines 31 k-1 and 31 k respectively (not shown).

[0158] The terminal 47E can be used as a terminal to which the inspection voltage VB is applied. Not limited to this, the terminal 47E can also be used as a terminal from which the monitor voltage VM is taken out. When the terminal 47E is used as a terminal to which the inspection voltage VB is applied, the terminals 47A and 47C can be used as terminals for taking out the monitor voltage VM. Also, when the terminal 47E is used as a terminal from which the monitor voltage VM is taken out, the terminals 47A and 47C can be used as terminals to which the inspection voltage VB is applied.

[0159] In any case, among the vertical signal lines 311 to 31 m , from the leftmost vertical signal line 311 to the vertical signal line 31 k-1 and from the vertical signal line 31 k to the vertical signal line 31 m respectively, it is possible to independently perform an open inspection. This makes it easy to identify the open position and reduces the burden during analysis.

[0160] In the example of FIG. 13, one terminal 47E is added between the terminals 47A and 47C, but this is not limited to this example, and two or more terminals may be added. This makes it possible to specify the open position in more detail. Also, the position of the terminal 47E is not limited to the center of the series connection of the first group and the second group, but may be a position closer to the left or right. Furthermore, when the number of transfer elements TR connected in series is very large, the monitoring time can be shortened by providing one or more terminals 47E to divide the function of the detection unit 45Ac'.

[0161] (3-4. Fourth Modification of the First Embodiment) Next, a fourth modified example of the first embodiment will be described. In the fourth modified example of the first embodiment, the transfer elements TR1 to TR2 of the detection unit 45Aa described with reference to FIG. m are connected in series, the transfer elements TR1 to TR m In this example, one or more specific transfer elements can be short-circuited.

[0162] 14 is a diagram showing an example of the configuration of a first semiconductor substrate according to a fourth modification of the first embodiment. In a first semiconductor substrate 41e shown in FIG. 14, a detection unit 45Ad is provided with a short-circuit element ST 11 , S.T. 12 , … , S.T. 1(m / 2-1) , S.T. 1(m / 2) and short element ST 21 , … , S.T. 2(m / 3) and short element ST X 6. Furthermore, in the detection unit 45d, terminals A0, A1, and A2 for specifying addresses are added to the detection unit 45Aa shown in FIG.

[0163] Of these, each short-circuit element ST 21 , S.T. 22 , … , S.T. 2(m / 2-1) , S.T. 2(m / 2) The sources and drains of the transfer elements TR1 to TR mFor each alternately selected transfer element TR, for example, transfer elements TR1, TR3, ..., TR 2(m-3) , T.R. 2(m-1) The short element ST 21 , S.T. 22 , … , S.T. 2(m / 2-1) , S.T. 2(m / 2) The gates of the transistors 111 and 112 are commonly connected to the terminal A0.

[0164] That is, by setting the terminal A0 to a high state, each short-circuit element ST 21 , S.T. 22 , … , S.T. 2(m / 2-1) , S.T. 2(m / 2) The source and drain of each of the transfer elements TR1, TR3, ..., TR 2(m-3) , T.R. 2(m-1) are addressed, and each of the transfer elements TR1, TR3, ..., TR 2(m-3) , T.R. 2(m-1) Therefore, the sources and drains of the vertical signal lines 311 to 31 m Among them, the transfer elements TR1 to TR m Among these, the transfer elements TR2, TR4, ..., TR m Vertical signal lines 311, 313, . . . , 31 (m-2) , 31 m An open inspection can be selectively performed on

[0165] On the other hand, each short element ST 11 , … , S.T. 1(m / 3) The source and drain of each of the transfer elements TR1 to TR m In the example of FIG. 14, pairs of adjacent transfer elements TR1 to TR2 are connected to both ends of the series connection of the pairs of transfer elements selected every other pair of transfer elements TR1 to TR2. m Among them, the pair TR1 and TR2, ..., TR 2(m-3) and T.R. 2(m-2) Also, the short element ST 11 , … , S.T. 1(m / 3)The gates of the transistors 111 and 112 are commonly connected to the terminal A1.

[0166] That is, by setting the terminal A1 to a high state, each short-circuit element ST 11 , … , S.T. 1(m / 3) The source and drain of each transfer element is turned on (conductive). 2(m-3) and T.R. 2(m-2) , . . . , TR 2(m-3) and T.R. 2(m-2) Therefore, each of the vertical signal lines 311 to 31 m Among them, the transfer elements TR1 to TR m Among the transfer elements TR3, TR4, ..., TR (m-1) and T.R. m , 31 (m-1) , 31 m An open inspection can be selectively performed on

[0167] Shorting element ST X , ... are similar. That is, the short-circuit element ST X , . . . are the transfer elements TR1 to TR m In the example of FIG. 14, pairs of adjacent transfer elements TR1 to TR2 are connected to both ends of the series connection of pairs of transfer elements selected every third pair of transfer elements. m Among them, the sets of TR1 to TR4 are connected to the source and drain of each. X . . . The gates of each of the transistors are commonly connected to terminal A2.

[0168] That is, by setting the terminal A2 to a high state, each short element ST X , . . . are addressed, and each of the sets of transfer elements TR1 to TR4, . . . is short-circuited.m Among them, the transfer elements TR1 to TR m An open circuit inspection can be selectively performed on the vertical signal lines 31 connected to each set of four transfer elements TR whose sources and drains are not short-circuited among the vertical signal lines 31 connected to each set of four transfer elements TR.

[0169] In this manner, in the fourth modification of the first embodiment, the transfer elements TR1 to TR m One or more specific transfer elements TR among the vertical signal lines 311 to 31 can be addressed and short-circuited. m In the above example, the open circuit inspection for the vertical signal line 31 connected to the specific transfer element TR can be disabled, and the open circuit location can be easily identified. m Among them, the open check for the odd-numbered vertical signal lines 311, 313, . . . can be disabled, and the open check for the even-numbered vertical signal lines 312, 314, .

[0170] In the above description, the open circuit inspection for the vertical signal line 31 connected to the transfer element TR is enabled / disabled by shorting the transfer element TR using the short-circuit element ST, but this is not limited to this example. For example, the open circuit inspection for the vertical signal line 31 can be enabled / disabled by using other methods, such as forcibly setting the gate of the transfer element TR to, for example, 3 V.

[0171] [4. Second embodiment] Next, a second embodiment of the present disclosure will be described. In the first embodiment described above, the vertical signal lines 311 to 31 m In contrast, in the second embodiment, the control lines 321 to 32 n Perform open and short tests on the device.

[0172] (4-0-1. Configuration Example of First Semiconductor Substrate According to Second Embodiment) Fig. 15 is a diagram showing an example of the configuration of a first semiconductor substrate according to the second embodiment. The configuration of a first semiconductor substrate 45f shown in Fig. 15 can be applied in combination with the configurations of the first semiconductor substrates described in the above-mentioned first embodiment and each of the modifications thereof.

[0173] 15, the pixels 2 included in the pixel array unit 11 and the vertical signal lines 311 to 311 shown in FIG. m 15, the components related to the pixel columns (vertical signal lines 311 to 31 m The configurations related to the above are omitted as appropriate.

[0174] In the example of FIG. 15, in the first semiconductor substrate 41f, the control lines 321 to 32 n Each of the control lines 321 to 322 includes three control lines. n Each of the control lines 321 to 322 includes a first control line for transferring a reset signal RST, a second control line for transferring a transfer signal TRG, and a third control line for transferring a selection signal SEL. n may each include four or more control lines.

[0175] In the first semiconductor substrate 41f, the bias section 46B includes the control lines 321-32 n n switch circuits 51B1, 51B2, ..., 51B n Switch circuits 51B1 to 51B n For each of the above, control lines 321 to 32 each including three control lines n are connected one-to-one. The bias section 46B includes an electrode 48B and a control terminal 50B. R , 50B T and 50B S and control terminal 50C R , 50C T and 50C S and are connected.

[0176] Electrode 48B and control terminal 50BR , 50B T and 50B S and control terminal 50C R , 50C T and 50C S and each of the switch circuits 51B1 to 51B n By applying a predetermined voltage (for example, 3 [V]) to the electrode 48B, each of the switch circuits 51B1 to 51B n and control lines 321-32 n The electrode 48B is connected to the control terminal 50B. R , 50B T and 50B S , and control terminal 50C R , 50C T and 50C S Each may be made independent.

[0177] Each control line 321~32 n are connected to the connection node R, each of which has three control lines included therein, which are included in the connection portion 44B. 1b , T 1b and S 1b , R 2b , T 2b and S 3b , R 3b , T 3b and S 3b , R 4b , T 4b and S 4b , … , R (n-1)b , T (n-1)b and S (n-1)b , R nb , T nb and S nb , and is further connected to a connection portion 44A.

[0178] At the connection portion 44A, each of the control lines 321 to 32 n are connected to the connection node R, each of which has three control lines included therein, which is included in the connection portion 44A. 1a , T 1a and S 1a , R 2a , T 2a and S 3a , R3a , T 3a and S 3a , R 4a , T 4a and S 4a , … , R (n-1)a , T (n-1)a and S (n-1)a , R na , T na and S na , and is connected to the detection unit 46A via the

[0179] The detection unit 46A detects the control lines 321 to 32 n n transfer circuits 51A1, 51A2, . . . , 51A n The transfer circuits 51A1 to 51A n For each of the above, control lines 321 to 32 each including three control lines n The detection unit 46A includes an electrode 48D, terminals 48A and 48C, and a control terminal 50A. R , 50A T and 50A S and are connected.

[0180] In the following, each of the switch circuits 51B1 to 51B n In the case where it is not necessary to distinguish between the transfer circuits 51A1 to 51A, the transfer circuits 51A1 to 51A are represented by the switch circuit 51B as appropriate. n When it is not necessary to distinguish between them, the transfer circuit 51A will be used as a representative for the description.

[0181] Electrode 48D and control terminal 50A R , 50A T and 50A S and each of the transfer circuits 51A1 to 51A n The terminals 48A and 48C are connected in common to the transfer circuits 51A1 to 51A. n The transfer circuits 51A1 and 51A n With this configuration, each of the transfer circuits 51A1 to 51A n Terminals 48A and 48C are connected to a transfer circuit group including:

[0182] 16A is a circuit diagram of an example of a switch circuit 51B1 according to the second embodiment. n has the same configuration as the switch circuit 51B1, the following description will be given using the switch circuit 51B1 as a representative.

[0183] The switch circuit 51B1 includes a switch element SW R1 , S.W. T1 and S.W. S1 and the switch element SW R2 , S.W. T2 and S.W. S2 A set of switch elements SW R2 , S.W. T2 and S.W. S2 The drains of the switch elements SW R2 , S.W. T2 and S.W. S2 Each source is a switch element SW R1 , S.W. T1 and S.W. S1 The switch element SW R1 , S.W. T1 and S.W. S1 The respective sources are connected to a first control line, a second control line and a third control line via terminals Rb, Tb and Sb, respectively.

[0184] Switch element SW R1 , S.W. T1 and S.W. S1 For each gate, control terminal 50B R , 50B T and 50B S Similarly, the switch element SW R2 , S.W. T2 and S.W. S2 For each gate, control terminal 50C R , 50C T and 50C S Each of these is connected.

[0185] That is, the voltage set at electrode 48B is R and 50C R When the voltage of the switch element SW R2 and S.W. R1 The voltage set at the electrode 48B is applied to the first control line that transfers the reset signal RST via the control terminal 50B. T and 50C T When the voltage of the switch element SW T2 and S.W. T1 The voltage set at the electrode 48B is applied to the second control line that transfers the transfer signal TRG via the control terminal 50B. S and 50C S When the voltage of the switch element SW S2 and S.W. S1 The selection signal SEL is applied to the third control line through the switch element SW S2 and S.W. S1 functions as an output section that outputs a voltage to the third control line.

[0186] In this manner, the switch circuit 51B1 is connected to the control terminal 50B R and 50C R and control terminal 50B T and 50C T and control terminal 50B S and 50C S By setting predetermined voltages to each of the pairs of electrodes 48A and 48B, it is possible to select whether the voltage applied to electrode 48D is to be applied to the first control line, the second control line, or the third control line.

[0187] 16B is a circuit diagram of an example of a transfer circuit 51A1 according to the second embodiment. n Since the transfer circuit 51A1 has the same configuration as the transfer circuit 51A1, the transfer circuit 51A1 will be used as a representative in the following description.m That is, the detection unit 46A applies a predetermined voltage VB (for example, 1 [V]) to the terminal 48A and monitors the voltage VM at the terminal 48C, thereby detecting the voltage VB of each of the control lines 321 to 32C. n Perform an open check on the

[0188] In the transfer circuit A1, the transfer elements TR R , T.R. T and T.R. S The first control line, the second control line, and the third control line are connected to the gates of the transfer circuits 51A1, 51A2, ..., 51A n For example, each transfer element TR R , 51A n Each of the other transfer elements TR T and T.R. S Similarly, each of the transfer circuits 51A1, 51A2, . . . , 51A n are connected in series through

[0189] Each of the transfer circuits 51A1, 51A2, . . . , 51A n Each transfer element TR R , T.R. T and T.R. S The drain side ends of the series connection are commonly connected to a terminal 47C, and the source side ends are commonly connected to a terminal 47A.

[0190] The transfer circuit 51A1 includes a reset element RS R1 , R.S. T1 and R.S. S1 and a reset element RS R2 , R.S. T2 and R.S. S2 For example, a reset element RS R2 The source of the reset element RS is connected to the first control line via the terminal Ra, and the drain of the reset element RS is connected to the first control line via the terminal Ra. R1 The reset element RS is connected to the source of the R1The drain of the other reset element RS T1 and R.S. S1 The drains of the first and second transistors are connected in common to electrode 48D.

[0191] In addition, the reset element RS R1 The gate is controlled by the 50A terminal R connected to the reset element RS R2 The gate is controlled by terminal 50D R The reset element RS T1 and R.S. T2 , and a reset element RS S1 and R.S. S2 Similarly, the gate of each of the control terminals A T and A S are connected to the

[0192] For example, control terminal 50A R and 50D R By setting both to a high level (e.g. 3 V), the reset element RS R1 and R.S. R2 are each turned on, and a voltage set at electrode 48D is applied from terminal Ra to the first control line.

[0193] As an example, in the above-mentioned switch circuit 51B1, the control terminal 50B R and 50C R When the voltage at the control terminal 50A is 0 [V], the first control line that transfers the reset signal RST among the control lines 321 connected to the switch circuit 51B1 is in a floating state. In this state, 0 [V] is applied to the electrode 48D, and R and 50D R By setting a voltage of, for example, 3 [V] to the first control line, the voltage of electrode 48D can be applied to the first control line, and the voltage of the first control line can be fixed at 0 [V].

[0194] (4-0-2. Example of inspection method according to the second embodiment) Next, a description will be given of an example of an inspection method according to the second embodiment. Here, an open inspection will be described for the first control line that transfers the reset signal RST among the three control lines included in the control line 321.

[0195] In the switch circuit 51B1, a predetermined voltage (for example, 3 [V]) is applied to the electrode 48B, and the control terminal 50B R and 50C R Set the voltage to a high level (e.g. 3 [V]) on control terminal 50B. T and C T , and control terminal B S and C S On the other hand, in the transfer circuit 51A1, a predetermined voltage (for example, 0 [V]) is applied to the electrode 48D, and the control terminal 50A R and 50D R Set the voltage at a low level (for example, 0 [V]) to each of the control terminals 50A and 50B. T and 50D T , and control terminal 50A S and control terminal 50D S Set a high level voltage (e.g. 3V) to each of these.

[0196] In this state, a test voltage VB of, for example, 1 V is set at terminal 48A, and voltage VM at terminal 48C is monitored.

[0197] Here, each of the switch circuits 51B1 to 51B n In each of the transfer circuits 51A1 to 51A, the switch elements T1 and S1, and the switch elements T2 and S2 are in the off state. n In the reset element RS T1 and R.S. S1 , and a reset element RS T2 and R.S. S2 are turned on, and a voltage of 0 [V] is applied to the electrode 48D. n In each transfer element TRT and T.R. S are all turned off, while each transfer element TR R are all in the on state (if there are no opens).

[0198] Therefore, by monitoring the voltage VM of the terminal 48C, each of the control lines 321 to 32 n A check can be performed on at least one of the control lines whether a first control line transmitting a reset signal RST is open.

[0199] (4-0-3. Detailed Description of the Bias Circuit According to the Second Embodiment) In the switch circuit 51B1 shown in FIG. 16A, for example, two switch elements SW R1 and S.W. R2 are connected in series. The reason for this will be explained below.

[0200] In controlling the transfer transistor 22, reset transistor 23, and selection transistor 25 of the pixel 2, a voltage higher than the breakdown voltage of the transistor may be applied. For example, a voltage of 3 [V] is applied at the time of high voltage, whereas a voltage of -1 [V] is applied at the time of low voltage. This does not cause a problem during testing, but a problem occurs during actual circuit operation when the first semiconductor substrate 41 (first semiconductor substrate 41e) and the second semiconductor substrate 42 are laminated together.

[0201] The reset transistor 23 will be taken as an example. For example, a voltage of -1 [V] is applied to the terminals Ra and Rb for applying a reset signal RST to the reset transistor 23. At this time, the voltages of the electrodes 48D and 48B are preferably fixed at -1 [V]. Also, the control terminal 50B R and control terminal 50C R At least one of the control terminals 50A and 50B must be fixed at -1 V. R and control terminal 50D RAt least one of these electrodes must have a fixed voltage of −1 V. This can prevent leakage to electrode 48B or electrode 48D.

[0202] Consider the case where 3 [V] is applied at the time of high voltage. Here, for example, the gate withstand voltage of the reset transistor 23 is assumed to be about 3 [V]. As described above, a voltage of -1 [V] is applied to the terminals Ra and Rb for applying the reset signal RST to the reset transistor 23. At this time, for example, the control terminal 50B R and control terminal 50D R If the voltage at the gate of the reset transistor 23 is fixed at −1 V, the potential difference across the gate of the reset transistor 23 will be 4 V, which may cause reliability concerns.

[0203] As a countermeasure, control terminal 50B R and control terminal 50D R The voltage of the control terminal 50C is fixed to a voltage higher than -1 [V]. This may be 0 [V] or a low voltage used in the circuit, for example, 1 [V]. At this time, from the viewpoint of leakage, R and control terminal 50A R The voltage of control terminal 50B needs to be fixed at -1 [V]. R and control terminal 50D R This causes the voltage to drop, making it possible to prevent a potential difference exceeding the withstand voltage from being applied.

[0204] If the withstand voltage of the transistor is sufficient, the two switch elements SW R1 and S.W. R2 The series connection of the two switch elements SW is not essential, and one switch element SW may be applied to one control line. R1 and S.W. R2 The series connection configuration of the vertical signal lines 311 to 311 described in the first embodiment and each of the modified examples thereof is the same as that of the vertical signal lines 311 to 311. m The present invention can also be applied to the bias unit 45B for applying a voltage to the

[0205] [5. Third embodiment] (5-0-1. Configuration Example of First Semiconductor Substrate According to Third Embodiment) Next, a third embodiment of the present disclosure will be described. In the third embodiment, vertical signal lines 311 to 31 m A plurality of pixels 2 included in one pixel row are used as a bias circuit that applies a voltage to the pixels 2.

[0206] 17 is a diagram showing an example of the configuration of a first semiconductor substrate according to the second embodiment. In the first semiconductor substrate 41g shown in FIG. 17, the bias section 45Be includes m pixels 2' connected to the first row (the upper end row of the pixel array section 11) of the pixel array section 11. Note that the same configuration as that described using FIG. 2 can be applied to the configuration of the pixels 2', and therefore the description here is omitted. For example, a row included in a region called an optical black region on the outer periphery of the pixel region in which the pixels 2 of the pixel array section 11 are arranged can be used as the bias section 45Be.

[0207] In the configuration of FIG. 17, each pixel 2′ included in the bias section 45Be is a switch circuit 51B1 to 51B2 included in the bias section 46B for applying a bias to each row, which has been described with reference to FIGS. 15, 16A, and 16B. n , is controlled by a switch circuit 51B1 corresponding to the first row.

[0208] The bias section 46C is connected to control terminals 50B1 and 50C1, and each pixel 2' included in the bias section 45Be is controlled by voltages applied to the control terminals 50B1 and 50C1. Here, in FIG. 17, the control terminal 50B1 corresponds to the control terminal 50B1 described in FIG. 16B. R , 50B T and 50B S Similarly, the control terminal 50C1 includes the control terminal 50C described in FIG. R , 50C T and 50C S Includes.

[0209] The detector 45Ae may have any of the configurations of the detectors 45Aa to 45Ad described in the first embodiment and the modifications thereof.

[0210] (5-0-2. Example of inspection method according to the third embodiment) Each vertical signal line 311 to 31 m When performing an open circuit test, the settings of the control terminals 50B1 and 50C1 are, for example, as follows: DD The voltage of the switch element SW connected to the gate of the reset transistor 23 is set to 3 [V]. R1 and S.W. R2 and a switch element SW connected to the gate of the selection transistor 25. S1 and S.W. S2 and each control terminal 50B connected to the gate of R and 50C R and each control terminal 50B S and 50C S The voltage of the switch element SW connected to the transfer transistor 22 is set to 3 [V]. T1 and S.W. T2 Each control terminal 50B connected to the gate of T and 50C T Fix the voltage to 0[V].

[0211] In this manner, each control terminal 50B R , 50B T and 50B S , and each control terminal 50C R , 50C T and 50C S By setting the voltage of the power supply V DD and the vertical signal line 31 are connected, and the potential of the vertical signal line 31 can be set to a high level through the pixel 2'.

[0212] Furthermore, when the voltage to be applied to the gate of the selection transistor 25 of each pixel 2′ can be set individually for, for example, the odd-numbered vertical signal lines 311, 313, . . . and the even-numbered vertical signal lines 312, 314, . . ., the vertical signal lines 311 to 31m High and low levels can be set for two adjacent vertical signal lines 31, respectively. Therefore, short circuit inspection becomes possible.

[0213] Also, according to the configuration of the third embodiment, since it is not necessary to arrange the bias section 45B outside the pixel array section 11 with respect to the first semiconductor substrate 41, it is possible to effectively utilize the substrate area.

[0214] (5-1. Another example of the third embodiment) In the example of FIG. 17, although the bias section 45Be is shown to include m pixels 2' connected to the first row of the pixel array section 11, this is not limited to this example. The bias section 45Be can be configured in any row among the rows included in the pixel array section 11.

[0215] FIG. 18 is a diagram showing another example of the configuration of the first semiconductor substrate according to the third embodiment. The first semiconductor substrate 41g' shown in FIG. 18 is constituted by a plurality of pixels 2' included in the k-th row (1 < k < n) of the pixel rows included in the first to n-th row of the pixel array section 11, and the bias section 45Be' is configured. Also, each pixel 2' included in the bias section 45Be is controlled by the switch circuit 51B corresponding to the k-th row among the switch circuits 51B included in the bias section 46B. k It is controlled by.

[0216] As an example, it is possible to set the bias section 45Be' at the center of the pixel array section 11, for example, and arrange the detection sections 45A above and below the pixel array section 11, respectively. For example, for the purpose of speeding up the reading from the pixel 2, the vertical signal lines 311 to 31 m may be separated at the center in the vertical direction of the pixel array section 11. In such a case, since it is difficult to arrange the dedicated bias section 45Ba outside the pixel array section 11 as described in the first embodiment, for example, another example of the third embodiment becomes effective.

[0217] It is also possible to provide a plurality of bias portions 45Be'. By providing a plurality of bias portions 45Be', it becomes possible to specify the open position.

[0218] [6. Fourth embodiment] Next, a fourth embodiment of the present disclosure will be described. In the fourth embodiment, vertical signal lines 311 to 311 are provided in a detection unit 45A on a first semiconductor substrate. m The transfer elements TR1 to TR m In the fourth embodiment, the vertical signal lines 311 to 31 m An addressing section is provided for selecting a particular vertical signal line 31 from the vertical signal line 31.

[0219] (6-0-1. Configuration Example of First Semiconductor Substrate According to Fourth Embodiment) 19A is a diagram illustrating an example of the configuration of a first semiconductor substrate according to the fourth embodiment. In a first semiconductor substrate 41h illustrated in FIG. 19A, a bias unit 45Bg is provided between the vertical signal lines 311 to 31 m For each of these, the switch decoder ADR 1b , ADR 2b , ADR 3b , ADR 4b , …, ADR (m-2)b , ADR (m-1)b , ADR mb is provided on a one-to-one basis.

[0220] Each switch decoder ADR 1b ~ADR mb One or more of the vertical signal lines 311 to 31 are selected according to a voltage applied to the control terminal 52B. m The vertical signal lines 311 to 311 are connected to the terminals, the number of which is such that a bit string corresponding to the number of vertical signal lines 311 to 311 can be set. m In the case where the number of vertical signal lines 311 to 31 can be expressed by 10 bits, 20 control lines are connected to the control terminal 52B to specify a bit value of "1" and a bit value of "0", respectively. mOne additional bit may be used to collectively specify odd and even numbers, and in the above example of m=1024, 22 control lines, including the two control lines for specifying this one bit, are connected to control terminal 52B.

[0221] More specifically, each of the vertical signal lines 311 to 31 m , AXB / AXS for individually specifying the odd and even numbers, and a voltage set ODD / EVEN for collectively specifying the odd and even numbers, respectively, are applied.

[0222] The electrode 47B is connected to each switch decoder ADR 1b ~ADR 1m Each switch decoder ADR is connected in common to each voltage input terminal of the 1b ~ADR 1m Each of the voltage output terminals of each connection node N 1b ~N mb 3 through the vertical signal lines 311 to 31 m Each of these is connected one-to-one.

[0223] Each vertical signal line 311 to 31 m is the number of nodes N 1a ~N ma The detection unit 45Ag is connected to the detection unit 45Ag via reset elements RS1 to RS m Similarly, the transfer elements TR1 to TR m Here, the reset elements RS1 to RS m The configuration is the same as that described with reference to FIG. 12, so the description thereof will be omitted here.

[0224] In the detection unit 45A, each of the transfer elements TR1 to TR m The drains and sources of the transfer elements TR1 to TR2 are connected in common, and are connected in parallel. m The gates of the vertical signal lines 311 to 31 mTherefore, each of the transfer elements TR1 to TR m The vertical signal lines 311 to 31 m The terminal 47A for applying the test voltage VB is connected to each of the transfer elements TR1 to TR m A terminal 47C for extracting a voltage VM to be monitored is connected to the drains of the transfer elements TR1 to TR m The sources of the two inputs are commonly connected.

[0225] (6-0-2. Configuration Example of Switch Decoder According to Fourth Embodiment) Here, each switch decoder ADR 1b ~ADR mb A configuration example of the switch decoder ADR 1b ~ADR mb have the same configuration, so here, the switch decoder ADR 1b The following description will be given by taking each switch decoder ADR as an example. 1b ~ADR mb If there is no need to distinguish between the switch decoders ADR 1b ~ADR mb Here, the description will be given assuming that the switch decoder ADR is used.

[0226] FIG. 19B shows a switch decoder ADR according to the fourth embodiment. 1b As shown in FIG. 19B, a switch decoder ADR 1b are NMOS transistors, and multiple switch elements A 11 , A.D. 12 , A.D. 13 , A.D. 14 , … , A.D. 1X Includes.

[0227] Of these, the switch element AD 11 Vertical signal lines 311 to 31 m The voltage ODD / EVEN is applied to the gate of the switch element AD11 is not an essential configuration, for example, the switch element AD 11 The function of the switch element AD 12 It can also be substituted by the switch element AD 12 ~AD 1X Vertical signal lines 311 to 31 m The switch elements AD are used to individually specify the voltages A0B / A0S, A1B / A1S, A2B / A2S, ..., AXB / AXS. 11 ~AD 1X When all of these are turned on (conductive), the voltage of the electrode 47B is applied to the vertical signal line 311.

[0228] 20 is a circuit diagram showing an example of a configuration of a bias unit 45Bg according to the fourth embodiment. For the sake of explanation, in FIG. 20, the vertical signal lines 311 to 31 m A switch element (for example, switch element AD 11 ) is omitted.

[0229] In FIG. 20, a switch decoder ADR 1b As described above, the switching element A 12 ~ 1X Includes switch decoder ADR 2b , ADR 3b and ADR 4b Similarly, the switch elements A, B, and C are connected in series. 22 ~AD 2X , switch element AD 32 ~AD 3X , and a switch element AD 42 ~AD 4X , respectively.

[0230] In the following, the switch element AD 12 ~ 1X , switch element AD 22 ~AD 2X , switch element AD 32 ~AD 3X , and a switch element AD 42 ~AD4X If there is no need to distinguish between these switch elements A and D, 12 ~ 1X , switch element AD 22 ~AD 2X , switch element AD 32 ~AD 3X , and a switch element AD 42 ~AD 4X In the following description, the switching element AD is used as a representative.

[0231] Each switch decoder ADR 1b , ADR 2b , ..., two control lines are provided in pairs for each switch element AD corresponding to the bit position. The two control lines consist of a control line (referred to as control line B) for specifying a bit value "0" and a control line (referred to as control line S) for specifying a bit value "1". Control line B specifies a bit value "0" when it is at a high level, for example. Similarly, control line S specifies a bit value "1" when it is at a high level, for example.

[0232] In the example of FIG. 20, for example, the switch element AD 12 , A.D. 22 , A.D. 32 , A.D. 42 , ..., these switch elements A.D. 12 , A.D. 22 , A.D. 32 , A.D. 42 , . . . , a control line S to which a voltage A0S is applied and a control line B to which a voltage A0B is applied are provided. 12 and A.D. 32 The gate of the switch element A 22 and A.D. 42 The gate of the switch element A.D. is connected to the control line S. Therefore, by setting the control line S to a high level to specify a bit value of "1", the switch element A.D. 22 and A.D. 42 Similarly, when the control line B for specifying the bit value "0" is set to a high level, the switch element A 12 and A.D. 32is turned on.

[0233] The states of the paired control lines B and S are exclusively controlled. That is, the control line S paired with the control line B set to high level is set to low level. Also, the control line B paired with the control line S set to high level is set to low level. It is also possible to select a plurality of control lines B and S each set to high level.

[0234] If we look at this in terms of the direction of the series connection of each switch element AD, for example, the switch decoder ADR 4b In the switch element AD 42 and A.D. 43 A control line S is connected to the gate of each of the switch elements AD 44 ~AD 4X Assume that a control line B is connected to each gate.

[0235] In this state, the switch element AD 42 and A.D. 43 Each control line S connected to each gate of the switch element AD 44 ~AD 4X Each control line B connected to each gate of each switch element A to B is set to high level (voltages A to B are set to high level). 42 ~AD 4X is turned on, and each switch element A 42 ~AD 4X This is because both ends of the series connection of the switch elements A 42 ~AD 4X For switch element AD 4X This is equivalent to giving the bit string "0...011" with the LSB (Least Significant Bit) at the beginning.

[0236] On the other hand, in the same state as above (voltages A0S and A1S at high levels, and voltages A2B to AXB at high levels), the other switch decoder ADR 1b , ADR 2band ADR 3b In this case, the switch decoder ADR 1b Now, the switch element AD to which the control line B is connected 12 and A.D. 13 The gates of the switch elements AD 12 and A.D. 13 Therefore, each switch element A.D. 12 ~AD 1X Similarly, the switch decoder ADR 2b Now, the switch element AD to which the control line B is connected 23 The gate of the switch element AD 23 Therefore, each switch element A.D. 22 ~AD 2X The two ends of the switch decoder ADR 3b Now, the switch element AD to which the control line B is connected 32 The gate of the switch element AD 32 Therefore, each switch element A.D. 32 ~AD 3X There is no continuity between both ends of the resistor.

[0237] In this way, the control line S or the control line B is connected to the gate of each switch element AD included in the switch decoder ADR according to a bit string corresponding to the address of the vertical signal line 31 connected to the switch decoder ADR. As a result, the vertical signal lines 311 to 31 are connected to the gate of each switch element AD included in the switch decoder ADR according to the bit string corresponding to the address of the vertical signal line 31 connected to the switch decoder ADR. m Therefore, it is possible to specify a specific vertical signal line 31.

[0238] (6-0-3. Example of inspection method according to the fourth embodiment) In the configuration according to the fourth embodiment, the vertical signal lines 311 to 31 m The method of performing the open circuit inspection and short circuit inspection will now be described in more detail.

[0239] Each vertical signal line 311 to 31 m Switch decoder ADR connected to 1b ~ADR mb A different address combination is specified for the gate of each switch element AD included in the vertical signal line 31 by each control line B and control line S. Therefore, a voltage can be applied from the electrode 47B to one specific vertical signal line 31 in accordance with the specified combination.

[0240] If the specified vertical signal line 31 is a specific even-numbered vertical signal line 31, the other even-numbered vertical signal lines 31 are in a floating state, and 0 [V] is applied to the odd-numbered vertical signal lines 31. For example, a voltage VS of 0 [V] is applied to the electrode 47D, and a voltage of 3 [V] is set to the control terminal 49A1, and a voltage of 0 [V] is set to the control terminal 49A2.

[0241] In this state, for example, 1 [V] is applied as voltage VB to terminal 47A, and voltage VM at terminal 47C is monitored.

[0242] Transfer elements TR1 to TR of the detection unit 45Ag m are connected in parallel. Therefore, if there is no open circuit (disconnection) in the vertical signal line 31 designated by the switch decoder ADR, 1 [V] is detected at the terminal 47C. On the other hand, if there is an open circuit (disconnection) in the vertical signal line 31, the voltage VS of the terminal 47A is not conducted to the terminal 47C, and the state of the terminal 47C becomes indefinite.

[0243] At this time, the voltage of the vertical signal line 31 (odd-numbered vertical signal line 31) adjacent to the vertical signal line 31 (even-numbered vertical signal line 31) specified by the switch decoder ADR is set to 0 V. Therefore, by monitoring the current of the electrode 47B or the electrode 47D, it is also possible to check for a short circuit in the vertical signal line 31 specified by the switch decoder ADR.

[0244] In the first and third embodiments described above, the vertical signal lines 311 to 31 mIn the past, it was only possible to detect the presence or absence of an open or short circuit for each vertical signal line 31. In contrast, in the fourth embodiment, it is possible to specify the vertical signal line 31 in which an open or short circuit has occurred by appropriately scanning the addresses and changing the specified vertical signal line 31. As a result, when later analyzing the cause of the defect, for example, it becomes easier to specify the defective part, which contributes to improving the efficiency of the analysis.

[0245] Each pair of voltages A0B / A0S, A1B / A1S, A2B / A2S, ..., AXB / AXS corresponding to an address is basically complementary to each other, and if one is set to 0 [V], the other is set to 3 [V]. For example, in the pair of voltages A0B / A0S, if the voltage A0B is set to 0 [V], the voltage A0S is set to 3 [V].

[0246] Not limited to this, it is possible to set the same voltage (for example, 3 [V]) to the two voltages in the above-mentioned pair. For example, in the pair of voltages A0B / A0S, the voltages A0B and A0S are each set to 3 [V]. In this case, for example, if all addresses (voltages A0B / A0S, A1B / A1S, A2B / A2S, ..., AXB / AXS) are set to 3 [V], it is possible to apply voltages to all even-numbered vertical signal lines 312, 314, ... or all odd-numbered vertical signal lines 311, 313, ..., as in the third modified example of the first embodiment described using FIG. 13. However, in this case, it is preferable that the configuration of the detection unit 45Ag is not parallel-connected but series-connected as in the third modified example of the first embodiment.

[0247] Furthermore, depending on the setting of the applied voltage of the address, it is also possible to apply a voltage only to the vertical signal line 31 selected by the voltage A0B, or only to the vertical signal line 31 selected by the voltages A0B and A1S.

[0248] [7. Fifth embodiment] Next, a fifth embodiment of the present disclosure will be described. The fifth embodiment is an example of combining the configuration of the fourth embodiment described above, in which a specific vertical signal line 31 can be specified using a switch decoder ADR, with the example of the third embodiment described above, in which a plurality of pixels 2 included in one pixel row are used as bias circuits that apply voltages to the vertical signal lines 31.

[0249] (7-0-1. Configuration Example of First Semiconductor Substrate According to Fifth Embodiment) Fig. 21A is a diagram showing an example of the configuration of a first semiconductor substrate according to the fifth embodiment. In the first semiconductor substrate 41i shown in Fig. 21A, the bias unit 45Bh includes m pixels 2' connected to the first row (the uppermost row of the pixel array unit 11) of the pixel array unit 11. Note that the same configuration as that described with reference to Fig. 2 can be applied to the pixel 2', and therefore the description thereof will be omitted here.

[0250] In addition, in FIG. 21A, the detection unit 45Ah detects the vertical signal lines 311 to 31 m A switch decoder ADR is provided for each 1a , ADR 2a , ADR 3a , …, ADR (m-2)a , ADR (m-1)a , ADR ma , the electrode 47D to which the voltage VS is applied is connected to each switch decoder ADR 1a ~ADR ma In addition, each switch decoder ADR 1a ~ADR ma For this, each set of voltages A0B / A0S, A1B / A1S, A2B / A2S, . . . , AXB / AXS, and ODD / EVEN are input as addresses.

[0251] Furthermore, the detection unit 45Ah detects the vertical signal lines 311 to 31 m Transfer elements TR1, TR2, TR3, ..., TR (m-2) , T.R. (m-1) , T.R. m The detector circuit 500 includes:

[0252] A terminal 47A for setting a voltage VB for testing is provided for each of the transfer elements TR1 to TR m A terminal 47C for extracting a voltage VM to be monitored is connected to the drains of the transfer elements TR1 to TR m The sources of the two inputs are commonly connected.

[0253] FIG. 21B shows a switch decoder ADR according to the fifth embodiment. 1a 1 is a circuit diagram showing an example of a configuration of a switch decoder ADR 1a ~ADR ma Since the switch decoder ADR 1a This will be explained using the following example.

[0254] As shown in FIG. 21B, the switch decoder ADR1a has a configuration similar to that of the switch decoder ADR1b described with reference to FIG. 19B, and includes a plurality of switch elements ADR1a, each of which is an NMOS transistor, connected in series. 11 , A.D. 12 , A.D. 13 , A.D. 14 , … , A.D. X1 Switching element AD 11 The drain of the pixel is connected to the vertical signal line 311 .

[0255] Of these, the switch element AD 11 Vertical signal lines 311 to 31 m The purpose of this is to set an open circuit test or a short circuit test for each odd-numbered and even-numbered switch element AD. A voltage O_even / S_odd is applied to the gate. 12 ~AD 1X Vertical signal lines 311 to 31 m The switch elements AD are used to individually specify the voltages A0B / A0S, A1B / A1S, A2B / A2S, ..., AXB / AXS. 11 ~AD 1X When all of these are turned on (conductive), the voltage of the electrode 48B is applied to the vertical signal line 311.

[0256] Switch Decoder ADR 1a further includes a switch element EO and a switch element SO. The switch element EO has a drain connected to the vertical signal line 311, a source connected to an electrode 47D (not shown), and a voltage VS is applied to the switch element EO. ​​A voltage EVEN / ODD for collectively specifying even numbers and odd numbers is applied to the gate of the switch element EO.

[0257] Furthermore, the switch decoder ADR1a includes a switch element AD 1X The source of short detection element SO, which is an NMOS transistor, is connected to the source of . The drain of short detection element SO is connected to electrode 47D and is applied with voltage VS. The gate of short detection element SO is applied with voltage SHORT / OPEN for setting either short test or open test.

[0258] In the example of FIG. 21B, the switch decoder ADR 1a The gate of the transfer element TR1 is connected to the switch element AD 1X The drain of the transfer element TR1 is connected to a connection point where the source of the transfer element TR1 is connected to the source of the short detection element SO. The drain of the transfer element TR1 is connected to a terminal 47A and a voltage VB is applied to the terminal 47A. Although not shown in the figure, the source of the transfer element TR1 is connected to a terminal 47C.

[0259] In FIG. 21A, the configurations of the detection section 46A and the bias section 46B for inspecting the control lines 321 to 32n can be the same as those described in the second embodiment.

[0260] Also, in the example of FIG. 21A, although it is shown that the bias section 45Bh is composed of m pixels 2' connected to the first row of the pixel array section 11, this is not limited to this example. Similar to the other examples of the third embodiment described with reference to FIG. 18, the bias section 45Bh can be configured in any row among the rows included in the pixel array section 11. For example, as shown as the first semiconductor substrate 41i' in FIG. 22, a plurality of pixels 2' included in the k-th row (1 < k < n) among the pixel rows of the first to n-th rows included in the pixel array section 11 can constitute the bias section 45Bh'.

[0261] Thus, by changing the position of the bias section 45Bh', it becomes possible to more specifically identify the open location. For example, after detecting an open when the first row of the pixel array section 11 is the bias section 45Bh, an open inspection is performed again by the bias section 45Bh' in the k-th row in the middle section. If no open is detected by the open inspection using this bias section 45Bh, there is a defective location between the k-th row and the first row, and if an open is detected, it can be specified that there is a defective location between the k-th row and the n-th row. This is the same for the configuration according to the other examples of the third embodiment described with reference to FIG. 18.

[0262] (7-0-2. Example of the inspection method according to the fifth embodiment) In the configuration according to this fifth embodiment, a method for performing an open inspection and a short inspection on the vertical signal lines 311 to 31 m will be described.

[0263] (7-0-2-1. Example of the open inspection according to the fifth embodiment) First, an example of performing an open inspection will be described with reference to FIGS. 23A and 23B. FIG. 23A is a diagram showing an example of the setting of the switch decoder ADR when performing an open inspection in the configuration according to the fifth embodiment. FIG. 23B is a diagram schematically showing the state of the vertical signal lines during the open inspection. The open inspection is performed on the vertical signal lines 311 to 31 mThis is carried out by selecting the vertical signal line 31 to which a high-level voltage is to be applied.

[0264] As an example, when an open inspection is performed on the odd-numbered vertical signal lines 311, 313, . . . , the odd-numbered vertical signal lines 311, 313, .

[0265] For example, in the switch decoder ADR of a non-voltage application column (in this example, the even-numbered vertical signal lines 312, 314, ...) to which a high level is not applied, the gate of the switch element EO is set to a high level, a voltage VS of 0 [V] is applied to the non-voltage application column, and the non-voltage application column is reset to 0 [V]. Also, the gate of the short detection element SO is set to a low level and is turned off. As a result, a voltage from the vertical signal line 31 whose address is specified by the switch decoder ADR is applied to the gate of the transfer element TR connected to the switch decoder ADR.

[0266] Each switch decoder ADR 1a ~ADR ma A specific vertical signal line 31 is selectively connected to a transfer element TR by a combination of addresses in . In this case, an address is specified so that any of the odd-numbered vertical signal lines 311, 313, ... is specified. Also, in this example in which an open test is performed, the voltage O_even / S_odd is set to a high level in the switch decoder ADR corresponding to the application column. A low level is applied to the gate of each transfer element TR corresponding to an address not specified by the switch decoder ADR, and each transfer element TR is turned off.

[0267] In this state, for example, 1 [V] is applied as a voltage VB to the terminal 47A, and the voltage VM of the terminal 47C is monitored. mare connected in parallel, so if there is no open circuit (disconnection) in the selected vertical signal line 31, 1 [V] is detected as the voltage VM of the terminal 47C. If there is an open circuit in the selected vertical signal line 31, the voltage VB of the terminal 47A is not conducted, and the voltage VM of the terminal 47C becomes indefinite.

[0268] In the example of FIG. 23B, in the detection unit Ah, the switch decoder ADR 3a If there is no open portion in the vertical signal line 313, the high-level voltage applied to the vertical signal line 313 through the pixel 2′, as shown by the thick line as path A in the figure, is applied to the switch decoder ADR 110 which is addressed to select the vertical signal line 313. 3a This switches the transfer element TR3 on, and the 1 V applied as the voltage VB to the terminal 47A appears as the voltage VM at the terminal 47C via the drain and source of the transfer element TR3.

[0269] (7-0-2-2. Example of short circuit inspection according to the fifth embodiment) It is also possible to perform a short-circuit inspection using the configuration of FIG. 21A. For example, as described in the first modification of the first embodiment, m Among them, adjacent vertical signal lines 31 are set to have different potential settings. Then, in the detection unit 45Ah, the current of the electrode 47D is monitored, thereby making it possible to check for shorts in the vertical signal line 31 addressed by the switch decoder ADR. An example of the setting of the switch decoder ADR in this case is shown in FIG. 24. However, it is also possible to check for shorts between adjacent vertical signal lines 31 by monitoring the voltage VM of the terminal 47C. An example of the setting of the switch decoder ADR in this case is shown in FIG. 25.

[0270] In the configuration according to the fifth embodiment, it is possible to specify the vertical signal line 31 in which an open or short circuit occurs by appropriately scanning the addresses and changing the vertical signal line 31 to be inspected. This makes it easier to specify the defective part when analyzing the cause of the defect later, for example, and contributes to improving the efficiency of the analysis.

[0271] [8. Sixth embodiment] Next, a sixth embodiment of the present disclosure will be described. The sixth embodiment is applicable to each of the above-mentioned embodiments and modifications, and is an example of a configuration and structure for maximizing the range of the applied voltage in the bias unit 45B (bias units 45Ba to 45Bh) and 46B according to each of the embodiments and modifications. In the following, the bias unit 45B (bias units 45Ba to 45Bh) and 46B will be described as an application circuit, taking into consideration that the bias unit 45B (bias units 45Ba to 45Bh) and 46B are circuits that apply a voltage to a detection target.

[0272] (8-1. Existing Technology) 26A and 26B are circuit diagrams showing an example of an application circuit 660 according to the existing technology. Taking FIG. 26A as an example, the application circuit 660 includes transistors 6611 and 6612, which are NMOS transistors. The drain of the transistor 6611 is connected to an input terminal 663, and the source is connected to the drain of the transistor 6612. The source of the transistor 6612 is connected to the detection target by a pixel wiring 710. The gates of the transistors 6611 and 6612 are connected to control terminals 6621 and 6622, respectively. By applying a high-level voltage to the gates of the control terminals 6621 and 6622, the transistors 6611 and 6612 are turned on, and the voltage input to the input terminal 663 is applied to the pixel wiring 710.

[0273] The pixel wiring 710 corresponds to, for example, the above-mentioned vertical signal line 31 or the control line 32. In the example of Fig. 26A, two transistors 6611 and 6612 are connected in series in the drain-source direction to improve the voltage resistance performance of the circuit.

[0274] Here, the well potential 664 applied to the back gates of the transistors 6611 and 6612 is generally set to the same potential as the lowest potential used in the circuit. This is because if it is not set in this way, a forward current will flow between the source and well or between the drain and well. For example, in the case where it is assumed that up to -1.2 [V] is applied to the pixel wiring 710, as shown in Fig. 26A, the well potential 664 applied to the back gates of the transistors 6611 and 6612 is set to -1.2 [V].

[0275] From the viewpoint of the withstand voltage of the transistors 6611 and 6612, when the voltage applied between the gate and well and between the gate and drain is set not to exceed the voltage Vdd (=4.5V), the gate potential of the application circuit 660 (potential applied to the control terminals 6621 and 6622) is restricted to a maximum of 3.3 [V] as shown in Fig. 26B. Considering the voltage drop (Vth drop) of the drain-source threshold voltage Vth in the NMOS transistor, only a maximum voltage of about 2.6 [V] can be applied to the pixel wiring 710. Therefore, the range of the voltage that can be applied to the pixel wiring 710 is -1.2 [V] to 2.6 [V].

[0276] 26A and 26B, although the voltage Vdd is 4.5 [V], only a maximum of 2.6 [V] can be applied to the pixel wiring 710. If the range of voltages applied to the pixel wiring 710 is small, the circuit operation range during testing is restricted, and there is a risk that sufficient testing cannot be performed.

[0277] (8-2. Configuration according to the sixth embodiment) Next, the sixth embodiment will be described with reference to Figures 27A, 27B, and 27C. Figure 27A is a circuit diagram showing an example of an application circuit according to the sixth embodiment. The application circuit 600 shown in Figure 27A includes two transistors 6101 and 6102, which are NMOS transistors and connected in series in the drain-source direction, similar to the application circuit 660 described with reference to Figure 26A.

[0278] The drain of the transistor 6101 is connected to an input terminal 621, and the source is connected to the drain of the transistor 6102. The source of the transistor 6102 is connected to the detection target by a wiring 710. The gates of the transistors 6101 and 6102 are connected to control terminals 6201 and 6202, respectively.

[0279] 27A, a well terminal 630 is provided which is directly connected to the wells of the transistors 6101 and 6102, and a voltage input to the well terminal 630 can be applied to the back gates of the transistors 6101 and 6102. This makes it possible to make the well potential follow the input voltage input to the input terminal 621, and makes it possible to apply a voltage up to voltage Vdd (=4.50 [V]), which is the maximum voltage of the withstand voltage of the transistors 6101 and 6102, to the input terminal 621 and the control terminals 6201 and 6202.

[0280] 27A, a voltage of 4.50 [V], which is the same voltage as the voltage Vdd, is input to the input terminal 621, the well terminal 630, and the control terminals 6201 and 6202. In this case, it is possible to apply a voltage of up to 4.00 [V] to the pixel wiring 710, including a Vth drop.

[0281] Furthermore, in the sixth embodiment, wells in which a plurality of application circuits 600 are formed adjacent to pixel wiring 710 that applies a voltage are electrically independent. The configuration according to the sixth embodiment will be described with reference to Figures 27B and 27C. Note that in Figures 27B and 27C, only parts of the configuration on the first semiconductor substrate 41 that are closely related to the sixth embodiment are extracted and shown in a schematic manner, and other parts are omitted.

[0282] Fig. 27B is a circuit diagram illustrating a circuit formed on the first semiconductor substrate 41 according to the sixth embodiment. In Fig. 27B, the application unit 670a corresponds to, for example, the bias unit 45B or the bias unit 46B described above, and includes a plurality of application circuits 600a, 600b, and 600c.

[0283] Each of the application circuits 600a, 600b, and 600c has the same configuration as the application circuit 600 shown in Fig. 27A. That is, the application circuit 600a includes transistors 610a1 and 610a2 connected in series in the source-drain direction, an input terminal 621a is connected to the drain of the transistor 610a1, and control terminals 620a1 and 620a2 are connected to the gates of the transistors 610a1 and 610a2, respectively. Also, a voltage input to a well terminal 630a can be applied to the back gates of the transistors 610a1 and 610a2.

[0284] Similarly, the application circuit 600b includes transistors 610b1 and 610b2 connected in series in the source-drain direction, and the gates of the transistors 610b1 and 610b2 are connected to control terminals 620b1 and 620b2, respectively, the drain of the transistor 610b1 is connected to an input terminal 621b, and the source of the transistor 610b2 is connected to a pixel wiring 710b. Also, a voltage input to a well terminal 630b can be applied to the back gates of the transistors 610b1 and 610b2.

[0285] Similarly, the application circuit 600c includes transistors 610c1 and 610c2 connected in series in the source-drain direction and having control terminals 620c1 and 620b2 connected to their gates, respectively. An input terminal 621c is connected to the drain of the transistor 610c1, and a pixel wiring 710c is connected to the source of the transistor 610c2. A voltage input to a well terminal 630c can be applied to the back gates of the transistors 610c1 and 610c2.

[0286] The application circuits 600a, 600b, and 600c apply voltages to the pixel wirings 710a, 710b, and 710c from the sources of the transistors 610a2, 610b2, and 610c2, respectively.

[0287] The pixel circuit section 700 corresponds to, for example, the above-mentioned pixel array section 11, and includes a plurality of pixel transistors 720a connected to a pixel wiring 710a, a plurality of pixel transistors 720b connected to a pixel wiring 710b, and a plurality of pixel transistors 720c connected to a pixel wiring 710c. Each of the pixel transistors 720a, 720b, and 720c is capable of applying a voltage input to a well terminal 730 to each back gate.

[0288] Note that the pixel transistors 720a, 720b, and 720c may be, for example, any of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 shown in Fig. 2, or any of the transistors when the pixel 2 has a configuration different from that shown in Fig. 2. Without being limited to this, the pixel wirings 710a, 710b, and 710c may not be connected to the pixel transistors 720a, 720b, and 720c included in the pixel circuit section 700.

[0289] Each of the pixel wirings 710a, 710b, and 710c is connected to a detection circuit section 800 via a pixel circuit section 700. The detection circuit section 800 corresponds to, for example, the above-mentioned detection section 45A or detection section 46A.

[0290] 27B, for the sake of explanation, the detection circuit unit 800 is shown to include transistors 810a, 810b, and 810c corresponding to the pixel wirings 710a, 710b, and 710c, respectively, but this is a schematic diagram for explanation, and in reality, the detection circuit unit 800 has the same configuration as each of the detection circuits described up to the fifth embodiment. Each of the transistors 810a, 810b, and 810c included in the detection circuit unit 800 is capable of applying a voltage input to the well terminal 720 to each back gate.

[0291] In this configuration, the transistors 610a1 and 610a2 are transistors for applying a voltage to each pixel wiring 710a during testing. They are controlled according to the voltages applied to the control terminals 620a1 and 620a2, respectively, and apply the voltage input to the input terminal 621a to the pixel wiring 710a.

[0292] The same is true for transistors 610b1 and 610b2, and transistors 610c1 and 610c2 for applying voltages to pixel wirings 710b and 710c during testing. Transistors 610b1 and 610b2, and transistors 610c1 and 610c2 are controlled according to voltages applied to control terminals 620b1 and 620b2, and control terminals 620c1 and 620c2, respectively, and apply voltages input to input terminals 621b and 621c to pixel wirings 710b and 710c.

[0293] As described above, the detection circuit section 800 detects whether or not a defect has occurred in each of the pixel wirings 710a, 710b, and 710c by using the voltages applied to the pixel wirings 710a, 710b, and 710c.

[0294] Fig. 27C is a diagram illustrating a schematic plan view of an example of the first semiconductor substrate 41 according to the sixth embodiment. In Fig. 27C, the two transistors 610a1 and 610a2 included in the application circuit 600a in Fig. 27B are collectively shown as a transistor 610a. Similarly, for the application circuits 600b and 600c, the transistors 610b1 and 610b2 are collectively shown as a transistor 610b, and the transistors 610c1 and 610c2 are collectively shown as a transistor 610c.

[0295] 27C, the application circuit 600a includes a transistor 610a formed on a well 601a. ​​In the transistor 610a, a control terminal 620a is connected to a gate 611a, an input terminal 621a is connected to a drain 612a via a connection portion 613a, and a pixel wiring 710a is connected to a source 612c via a connection portion 613c. A well terminal 630a is connected to the well 601a via a connection portion 617a.

[0296] Similarly, the application circuits 600b and 600c include transistors 610b and 610c formed on wells 601b and 601c, respectively. The transistor 610b has a gate connected to a control terminal 620b, a drain connected to an input terminal 621b, and a source connected to a pixel wiring 710b. The well terminal 630b is connected to the well 601b via a connection portion 617b. The transistor 610c has a gate connected to a control terminal 620c, a drain connected to an input terminal 621c, and a source connected to a pixel wiring 710c. The well terminal 630c is connected to the well 601c via a connection portion 617c.

[0297] Here, a well 601a in which an application circuit 600a is formed, a well 601b in which an application circuit 600b is formed, and a well 601c in which an application circuit 600c is formed are electrically isolated from one another. That is, pixel wiring that applies a voltage separates the wells in which adjacent application circuits are formed.

[0298] Further, each of the wells 601a, 601b, and 601c is electrically isolated from a well 701 in which each of the pixel transistors 720a, 720b, and 720c in the pixel circuit section 700 is formed, and to which a voltage is applied via pixel wirings 710a, 710b, and 710c. A well potential voltage is applied to the well 701 from a well terminal 730 via a connection section 731.

[0299] The well potential of the transistor 610a is biased (applied) from a well terminal 630a of the application circuit 600a, and the well potential of the pixel transistor 720a to which a voltage is applied by the application circuit 600a is biased from a well terminal 731 on a well 701 in which the pixel circuit section 700 is formed, and they can be biased at different potentials. Similarly, the wells 601b and 601c formed in the application circuits 600b and 600c adjacent to the application circuit 600a are electrically separated, so that the well potentials of each can also be biased at different potentials.

[0300] As a result, for example, when it is desired to apply a high voltage to pixel wiring 710a, by raising the potential of the well terminal 630a and the control terminal 620a in conjunction with raising the potential of the input terminal 621a, it is possible to apply a high voltage to pixel wiring 710a within a range that takes into account the voltage drop from Vdd to Vth while maintaining the withstand voltage of the transistor 610a.

[0301] Furthermore, when applying a higher voltage to the pixel wiring 710a and simultaneously applying a lower voltage to the pixel wiring 710b adjacent to the pixel wiring 710a, the potential of the well terminal 630a and the control terminal 620b is lowered in accordance with lowering the potential of the voltage input to the input terminal 621b. By doing this, even if a voltage is applied to the pixel wiring 710b up to the negative voltage range, it is possible to control so that a forward current does not flow to the well 601b.

[0302] In the example of FIG. 27C, furthermore, well 801 in which detection circuit section 800 is formed is electrically isolated from wells 601a, 601b, and 601c, and well 701, and a voltage can be applied to well 801 from well terminal 820 via connection section 821. That is, the well potential of each of transistors 810a, 810b, and 810c included in detection circuit section 800 can also be biased from well terminal 820, independently of pixel circuit section 700 and each application circuit 600a, 600b, and 600c. Therefore, when it is preferable to change the well potential for convenience of operation of detection circuit section 800 (for example, advantageous in terms of withstand voltage, operating point, and operating range), it is also possible to change and optimize the well potential independently of pixel circuit section 700 and each application circuit 600a, 600b, and 600c.

[0303] (8-3. First Modification of the Sixth Embodiment) Next, a first modified example of the sixth embodiment will be described. Fig. 28A is a circuit diagram showing an example of an application circuit according to the first modified example of the sixth embodiment.

[0304] 27A, the application circuit 680 shown in Fig. 28A has an input terminal 621 connected to the drain of the transistor 6101 and to the back gates of the transistors 6101 and 6102. More specifically, as described later, the input terminal 621 is directly connected to wells in which the transistors 6101 and 6102 are formed.

[0305] As a result, the potential of the voltage applied to the back gate of each of the transistors 6101 and 6102 becomes the same as the potential of the voltage input to the input terminal 621. Therefore, it becomes possible to make the well potential follow the input voltage input to the input terminal 621, and it becomes possible to apply a voltage up to the voltage Vdd (=4.50 [V]), which is the maximum voltage of the withstand voltage of the transistors 6101 and 6102, to the input terminal 621 and the control terminals 6201 and 6202.

[0306] In the example of Fig. 28A, a voltage of 4.50 [V], which is the same voltage as the voltage Vdd, is input to the input terminal 621 and the control terminals 6201 and 6202. In this case, as in the case of Fig. 27A described above, it is possible to apply a voltage of up to 4.00 [V] to the pixel wiring 710, including a Vth drop.

[0307] The configuration according to the first modified example of the sixth embodiment will be described with reference to Figures 28B and 28C. Note that in Figures 28B and 28C, only the parts of the configuration on the first semiconductor substrate 41 that are closely related to the first modified example of the sixth embodiment are extracted and shown roughly, and other parts are omitted.

[0308] FIG. 28B is a circuit diagram that shows a schematic diagram of a circuit formed on the first semiconductor substrate 41 according to the first modification of the sixth embodiment. In FIG. 28B, the application unit 670b includes a plurality of application circuits 680a, 680b, and 680c, similar to the application unit 670a shown in FIG. 27B. The application circuit 680b has an input terminal 621b connected to the drain of the transistor 610b1 and to the back gates of the transistors 610b1 and 610b2. Similarly, the application circuit 680c has an input terminal 621c connected to the drain of the transistor 610c1 and to the back gates of the transistors 610c1 and 610c2. The other configurations are the same as those in FIG. 27B, and therefore will not be described here.

[0309] Fig. 28C is a schematic plan view of an example of a first semiconductor substrate 41 according to a first modified example of the sixth embodiment. In Fig. 28C, similar to Fig. 27C described above, two transistors 610a1 and 610a2 included in the application circuit 680a in Fig. 27C are collectively shown as transistor 610a. Similarly, for application circuits 680b and 680c, transistors 610b1 and 610b2 are collectively shown as transistor 610b, and transistors 610c1 and 610c2 are collectively shown as transistor 610c.

[0310] In FIG. 28C, application circuit 680a includes a transistor 610a formed on well 601a, with input terminal 621a connected to the drain of transistor 610a and to well 601a via connection 617a.

[0311] Similarly, the application circuits 680b and 680c include transistors 610b and 610c formed on the wells 601b and 601c, respectively. The transistor 610b has a gate connected to a control terminal 620b, a drain connected to an input terminal 621b, and a source pixel wiring 710b, respectively. The input terminal 621b is connected to the well 601b via a connection portion 617b. Similarly, the transistor 610c has a gate connected to a control terminal 620c, a drain connected to an input terminal 621c, and a source pixel wiring 710c, respectively. The input terminal 621c is connected to the well 601c via a connection portion 617c.

[0312] With this configuration, in each of the application circuits 680a, 680b, and 680c, the well potential is biased according to the voltage input to each of the input terminals 621a, 621b, and 621c without separately biasing the well potential. Therefore, even with the configuration according to the first modification of the sixth embodiment, it is possible to apply a high voltage to each of the pixel wirings 710a, 710b, and 710c within a range that takes into account the drop in Vth from the voltage Vdd while maintaining the withstand voltage of each of the transistors 610a, 610b, and 610c.

[0313] In the sixth embodiment described above, if the bias lines for applying voltages to the wells 601a, 601b, and 601c were wired independently, latch-up could occur. Therefore, it was necessary to take care of the layout, for example, by shortening the wiring length from the transistor 610a to the well terminal 630c. In contrast, in the first modification of the sixth embodiment, since the well terminal 630a is not used, such care is not necessary. For example, it is possible to connect the well 601a to the source and drain immediately adjacent to the transistor 610a.

[0314] In the sixth embodiment described above, the input voltage and the well voltage can be set independently, which is advantageous in that the degree of freedom in setting is high. In contrast, in the first modified example of the sixth embodiment, the well voltage is automatically determined according to the input voltage, which makes it difficult to perform detailed optimization. Therefore, it is preferable to appropriately select either the configuration of the sixth embodiment or the configuration of the first modified example of the sixth embodiment according to the purpose and specifications of the inspection.

[0315] (8-4. Second Modification of the Sixth Embodiment) Next, a second modified example of the sixth embodiment will be described. FIG. 29 is a diagram that shows a schematic plan view of an example of a first semiconductor substrate 41 according to a second modified example of the sixth embodiment. The circuit formed on the first semiconductor substrate 41 according to the second modified example of the sixth embodiment can be the circuit described using FIG. 28B as it is, and therefore the description here is omitted. In addition, in FIG. 29, the description of each application circuit 680a, 680b, and 680c is appropriately omitted in common with the above-mentioned FIG. 28C.

[0316] In the sixth embodiment and its first modification described above, the well 701 in which the pixel circuit section 700 is formed and the well 801 in which the detection circuit section 800 is formed are separated, and different well voltages can be set for the wells 701 and 801. In contrast, in the second modification of the sixth embodiment, the pixel circuit section 700 and the detection circuit section 800 are formed on a common well 702.

[0317] That is, depending on the driving method for the inspection and the configuration of the detection circuit section 800, there may be cases where it is not necessary to independently change the well potential of the detection circuit section 800. In that case, the well of the detection circuit section 800 and the well of the pixel circuit section 700 can be the same well 702 as shown in FIG.

[0318] In the example of FIG. 29, the application circuit 680 according to the first modified example of the sixth embodiment is applied as the application circuit, but this is not limited to this example, and the application circuit 600 according to the sixth embodiment may be applied as the application circuit.

[0319] (8-5. Third Modification of the Sixth Embodiment) Next, a third modified example of the sixth embodiment will be described. FIG. 30 is a diagram that shows a schematic plan view of an example of the first semiconductor substrate 41 according to the third modified example of the sixth embodiment. The circuit formed on the first semiconductor substrate 41 according to the third modified example of the sixth embodiment can be the circuit described using FIG. 27B as it is, and therefore the description here is omitted. In addition, in FIG. 30, the description of each application circuit 680a, 680b, and 680c is appropriately omitted in common with the above-mentioned FIG. 27C.

[0320] In the sixth embodiment described above, the application circuits 600a, 600b, and 600c are formed in wells 601a, 601b, and 601c that are separated from each other. In contrast, the third modified example of the sixth embodiment is an example in which some of the multiple application circuits are formed in the same well, and the other application circuits are formed in wells separated from the wells.

[0321] In the example of Fig. 30, application circuits 600a and 600c are formed in the same well 602a, and application circuit 600b is formed in well 602b separated from well 602a. In well 602a, a well voltage is applied to well 602a from well terminal 630d. In addition, since application circuits 600a and 600b are formed in the same well 602a, it is also possible to share input terminals 621a and 621c.

[0322] That is, in the sixth embodiment and its first and second modifications, the well voltages of the application circuits 600a to 600c or the application circuits 680a to 680c can be biased independently. On the other hand, depending on the driving method for the test, a high voltage that requires consideration of the withstand voltage of each transistor included in the application circuit may be applied to only some pixel wirings, and a voltage within the normal withstand voltage range may be applied to the other pixel wirings.

[0323] In such a case, a configuration as shown in Figure 30 can be used in which only the application circuit to which a high voltage is to be applied is able to control the well potential according to the applied voltage, and for the other application circuits, the well can be treated as a common well and a fixed voltage can be applied to that well.

[0324] 30, among the application circuits 600a to 600c, the application circuits 600a and 600c are formed in a common well 602a. On the other hand, the application circuit 600b to which a high voltage is to be applied is formed in a well 602b separated from the well 602a, so that the well potential can be controlled independently for the application circuits 600a and 600c.

[0325] In this way, by limiting the separation of the wells of the application circuits to the minimum necessary and sharing the wells of the other application circuits, it is possible to suppress an increase in layout area due to the separation of the wells.

[0326] (8-6. Effects of the sixth embodiment and its modifications) Here, the effects of the sixth embodiment and each of its modifications will be described with reference to the first modification as an example. Fig. 31 is a diagram showing an example of a pixel circuit and a detection circuit for explaining an inspection in the case where an existing technique is used.

[0327] 31, application circuit 660 is the same as application circuit 660 described in FIG. 26A and FIG. 26B, and therefore description thereof will be omitted here. Also, pixel circuit section 700′ and detection circuit section 800′ are for the purpose of explanation, and have configurations different from pixel circuit section 700 and detection circuit section 800 described above.

[0328] In this example, the pixel circuit section 700' includes transistors 750a, 750b, 750c, and 750d. Note that in this figure, components such as a photodiode and a floating diffusion region FD that are not directly related to the inspection here are omitted.

[0329] The transistor 750a is turned on / off by a signal FDG applied to its gate, its drain is connected to a terminal 752a that supplies power, and its source is connected to the drain of the transistor 750b. The transistor 750b is turned on / off by a reset signal RST, and its source is connected to the gate of the transistor 750c.

[0330] The drain of the transistor 750c is connected to a terminal 752b that supplies power, and the source is connected to the drain of the transistor 750d. The gate of the transistor 750c is connected to the source of the transistor 750b and to a floating diffusion region FD (not shown), and the transistor 750c amplifies a signal obtained by converting the charge accumulated in the floating diffusion region FD into a voltage and outputs the amplified signal from the source. The transistor 750d is turned on / off by a selection signal SEL applied to the gate, and the source is connected to the vertical signal line VSL.

[0331] In this example, a voltage of 0.00 [V] is applied to the back gate of each of the transistors 750a to 750d.

[0332] In this example, the detection circuit unit 800' includes transistors 850a and 850b. The transistor 850a has a gate connected to the vertical signal line VSL and a drain connected to a terminal 851a that supplies power. The source of the transistor 850a is connected to the gate of the transistor 850b. The drain of the transistor 850b is connected to a test terminal 851b that supplies a test voltage, and the source is connected to a monitor terminal 852 for monitoring the detection result.

[0333] In this example, a voltage of 0.00 [V] is applied to the back gate of each of the transistors 850a and 850b.

[0334] In this example, a case will be considered in which a test is performed by writing a high-level voltage (Hi voltage) to the vertical signal line VSL via the pixel circuit section 700'.

[0335] As described above, in the application circuit 660, the potential 664 applied to the back gates of the transistors 6611 and 6612 is set to −1.2 [V], and the upper limit of the voltage that can be applied to the control terminals 6621 and 6622 and the input terminal 663 is set to 3.30 [V] due to the withstand voltage limitations of the transistors 6611 and 6612. Therefore, the maximum potential of the signal output from the application circuit 660 remains at 2.60 [V] due to the Vth drop of the NMOS transistors.

[0336] An application circuit 660 is provided for each of the signal FDG, the reset signal RST, and the selection signal SEL, and the signal FDG, the reset signal RST, and the selection signal SEL, each of which has a maximum potential of 2.60 [V], are applied from each application circuit 660 to the gates of the transistors 750a, 750b, and 750d, respectively. The output of the transistor 750b is input to the gate of the transistor 750c, and the output of the transistor 750c is supplied to the vertical signal line VSL via the transistor 750d. At this time, the voltage of the signal supplied to the vertical signal line VSL drops to, for example, 2.00 [V] due to the Vth drop of each transistor. In this case, the potential of the high voltage of the vertical signal line VSL may be insufficient.

[0337] Furthermore, if the potential of the vertical signal line VSL is insufficient, the detection circuit unit 800' may obtain only an output voltage of, for example, about 0.80 [V] at the monitor terminal 852, making it difficult to ensure an operating margin and resulting in insufficient test results. Thus, when the circuit is configured using only NMOS transistors, it is necessary to make it possible for the application circuit 660 to apply as high a voltage as possible.

[0338] Figures 32A and 32B are diagrams for explaining the effects of the sixth embodiment and each of its modified examples. Figures 32A and 32B each show an example in which an application circuit 680 according to a first modified example of the sixth embodiment is applied instead of the application circuit 660 in Figure 31. In Figures 32A and 32B, the configurations of a pixel circuit section 700' and a detection circuit section 800' are the same as those shown in Figure 31, so their description will be omitted here.

[0339] FIG. 32A shows an example of the case where the application circuit 600 outputs an application voltage when it is desired to turn on the pixel circuit section 700'. As described above, the application circuit 680 applies the voltage input to the input terminal 621 to the well 601 separated for each application circuit 680, and makes the well voltage follow the input voltage. Therefore, a voltage up to the voltage Vdd (=4.50 [V]) can be applied to the input terminal 621 and the control terminals 6201 and 6202. Furthermore, the substrate bias effect of each of the transistors 6611 and 6612 is eliminated, and the potential of the Vth drop is also reduced. Therefore, it is expected that the transistors 6611 and 6612 can pass a higher voltage. In this example, the application circuit 680 is capable of outputting a voltage up to a maximum of 4.00 [V].

[0340] In this example, an application circuit 680 is provided for each of the signal FDG, the reset signal RST, and the selection signal SEL, and the signal FDG, the reset signal RST, and the selection signal SEL, each of which has a maximum potential of 4.00 [V], are applied from each application circuit 680 to the gates of the transistors 750a, 750b, and 750d, respectively. The output of the transistor 750b is input to the gate of the transistor 750c, and the output of the transistor 750c is supplied to the vertical signal line VSL via the transistor 750d. At this time, the voltage of the signal supplied to the vertical signal line VSL due to the Vth drop of each transistor is set to, for example, 3.70 [V], which is about 1.70 [V] higher than the example of FIG. 31, and the potential of the high voltage of the vertical signal line VSL is sufficient.

[0341] If the potential of the vertical signal line VSL is sufficient, an output voltage of, for example, about 2.50 [V] can be obtained at the monitor terminal 852 in the detection circuit unit 800', the operating margin can be expanded, and sufficient test results can be obtained.

[0342] 32B shows an example of the case where application circuit 600 outputs an application voltage for turning pixel circuit unit 700' off. In this case, the voltage input to input terminal 621 is, for example, -1.20 [V]. The well voltage follows the input voltage and becomes -1.20 [V], and 3.30 [V], for example, is applied to control terminals 6201 and 6202. Application circuit 680 outputs the voltage of -1.20 [V] input to input terminal 621 as an output voltage.

[0343] The voltages of the signal FDG, the reset signal RST, and the selection signal SEL are each set to -1.20 [V], the transistors 750a, 750b, and 750d are each set to an off state, and the potential of the vertical signal line VSL is also set to 0.00 [V]. Therefore, the transistors 850a and 850b of the detection circuit unit 800' are each set to an off state, and the output voltage of the monitor terminal 852 is also set to 0.00 [V].

[0344] 9. Other Embodiments In the above-described embodiments and modifications, the detection unit 45A (detection units 45Aa to 45Ah) and the bias unit 45B (bias units 45Ba to 45Bh) are arranged on the first semiconductor substrate 41 (first semiconductor substrates 41a to 41i), but this is not limited to this example. For example, one or both of the detection unit 45A and the bias unit 45B may be arranged on the second semiconductor substrate 42. In this case, it becomes possible to inspect for disconnection or short circuit of the connection between the first semiconductor substrate 41 and the second semiconductor substrate 42, such as Cu-Cu hybrid bonding.

[0345] As an example, the detection unit 45A (detection units 45Aa to 45Ah) and the bias unit 45B (bias units 45Ba to 45Bh) can be separately arranged on the first semiconductor substrate 41b and the second semiconductor substrate 42. mInstead, one end and the other end of a connection portion (VIA or Cu-Cu hybrid bonding) that connects the first semiconductor substrate 41b and the second semiconductor substrate 42 are connected. In this case, it becomes possible to perform an open circuit inspection or a short circuit inspection for the connection portion.

[0346] In the above description, each element (transistor) is configured with an NMOS transistor, but this is not limited to this example. That is, each element may be configured with a PMOS transistor or a CMOS element. Furthermore, each element may be configured with other elements.

[0347] Furthermore, in the above description, the technology of the present disclosure has been described as being applied to the image sensor 1 including the pixel array unit 11, but this is not limited to this example. The technology of the present disclosure can also be applied to other elements, such as semiconductor memories, as long as the element has a cell array in which cells including predetermined circuits are arranged in a matrix and signal lines are connected to each cell in the row and column directions.

[0348] The technology disclosed herein is suitable for use in devices in which wiring layers are densely packed. For example, the technology disclosed herein can be used to inspect defects in the wiring layers of memories such as NAND flash memories and DRAMs (Dynamic RAMs) and defects in the wiring layers of MEMS (Micro Electro Mechanical Systems) devices.

[0349] [10. Structures Applicable to Each Embodiment] Next, the structures of the first semiconductor substrate 41 (first semiconductor substrates 41a to 41i) and the second semiconductor substrate 42 applicable to each embodiment will be described. Fig. 33 is a cross-sectional view of a main part of an image sensor wafer applicable to the present disclosure. An image sensor wafer 60 applicable to the present disclosure has a three-dimensional structure in which the first semiconductor substrate 41, which is a sensor substrate on which the pixel array section 11 is formed, and the second semiconductor substrate 42, which is a circuit substrate on which a peripheral circuit section of the pixel array section 11 is formed, are laminated and bonded together.

[0350] When viewed in a plan view, the image sensor wafer 60 is made up of a chip region 61 and a division region 62. The chip region 61 is made up of a pixel region 63 and a peripheral region 64.

[0351] A wiring layer 71 and a protective film 72 covering the wiring layer 71 are provided on the surface side opposite to the light receiving surface A of the first semiconductor substrate 41, i.e., on the surface facing the second semiconductor substrate 42. Meanwhile, a wiring layer 73 and a protective film 74 covering the wiring layer 73 are provided on the surface side of the second semiconductor substrate 42, i.e., on the surface facing the first semiconductor substrate 41. In addition, a protective film 75 is provided on the back surface side of the second semiconductor substrate 42. The first semiconductor substrate 41 and the second semiconductor substrate 42 are bonded together between the protective film 72 and the protective film 74.

[0352] An anti-reflection film 81, an interface state suppression film 82, an etching stop film 83, a wiring groove formation film 84, wiring 85, a cap film 86, and a light-shielding film 87 are provided on the back surface side of the first semiconductor substrate 41, i.e., on the light-receiving surface A. Then, a transparent protective film 88, a color filter 89, and an on-chip lens 90 are laminated in this order on the light-shielding film 87.

[0353] In the imaging element wafer 60 having the layer configuration described above, the second semiconductor substrate 42 in the chip region 61 is provided with device terminals 93, which are connected to a drive circuit on the second semiconductor substrate 42 side. Furthermore, the wiring layer 73 in the divided region 62 is provided with inspection terminals 55 used to inspect each imaging element in the wafer as a whole, which are connected to embedded wiring 97 of the drive circuit extended from the wiring layer 73 in the chip region 61. Furthermore, the divided region 62 is provided with an opening 62a opening on the light receiving surface A side, which opening 62a is formed as a through hole that exposes the inspection terminal 55.

[0354] Next, in the image sensor wafer 60 configured as described above, the configuration of each layer of the first semiconductor substrate 41, the configuration of each layer of the second semiconductor substrate 42, and the configuration of each layer on the light-receiving surface A will be described in detail in order.

[0355] (First semiconductor substrate / sensor substrate) The first semiconductor substrate 41 is, for example, a thin film of a single crystal silicon substrate. In a pixel region 63 in each chip region 61 in the first semiconductor substrate 41, a plurality of photodiodes (photoelectric conversion units) 21 are arranged along a light receiving surface A. The photodiodes 21 are, for example, configured with a laminated structure of an n-type diffusion layer and a p-type diffusion layer. The photodiodes 21 are provided for each pixel, and FIG. 33 illustrates a cross-sectional structure for one pixel.

[0356] In addition, in the chip region 61 of the first semiconductor substrate 41, on the surface side opposite the light-receiving surface A, there are provided a floating diffusion region FD consisting of an n+ type impurity layer, a source / drain region 65 of the transistor Tr, other impurity layers not shown here, and an element isolation region 66.

[0357] Furthermore, in the chip region 61 of the first semiconductor substrate 41, a through via 67 penetrating the first semiconductor substrate 41 is provided in a peripheral region 64 outside the pixel region 63. The through via 67 is made of a conductive material embedded in a connection hole formed penetrating the first semiconductor substrate 41 via an isolation insulating film 68.

[0358] In the chip region 61 of the wiring layer 71 provided on the surface of the first semiconductor substrate 41, a transfer gate TG, a gate electrode 69 of the transistor Tr, and other electrodes not shown here are provided on the interface side with the first semiconductor substrate 41 via a gate insulating film not shown here. Here, the transfer gate TG corresponds to the gate electrode of the transfer transistor 22 in the pixel circuit of FIG. 2, and the transistor Tr corresponds to the other transistor.

[0359] The transfer gate TG and the gate electrode 69 are covered with an interlayer insulating film 76, and embedded wiring 77 made of, for example, copper (Cu) is provided as multi-layer wiring in a groove pattern provided in the interlayer insulating film 76. These embedded wirings 77 are connected to each other by vias, and some of them are connected to the source / drain region 65, the transfer gate TG, and further to the gate electrode 69. The embedded wiring 77 is also connected to a through via 67 provided in the first semiconductor substrate 41, and a pixel circuit is formed by the transistor Tr and the embedded wiring 77, etc.

[0360] An insulating protective film 72 is provided on the interlayer insulating film 76 on which the above-described embedded wiring 77 is formed. Then, on the surface of the protective film 72, the first semiconductor substrate 41, which is a sensor substrate, is laminated on the second semiconductor substrate 42, which is a circuit substrate.

[0361] (Second semiconductor substrate / circuit substrate) The second semiconductor substrate 42 is, for example, a thin film of a single crystal silicon substrate. In the chip region 61 of the second semiconductor substrate 42, a source / drain region 91 of the transistor Tr, an impurity layer not shown in the figure, an element isolation region 92, and the like are provided in the surface layer on the first semiconductor substrate 41 side.

[0362] Furthermore, in the chip region 61 of the second semiconductor substrate 42, a device terminal 93 penetrating the second semiconductor substrate 42 is provided. The device terminal 93 is made of a conductive material embedded in a connection hole formed penetrating the second semiconductor substrate 42 via an isolation insulating film 94.

[0363] The chip region 61 of the wiring layer 73 provided on the surface of the second semiconductor substrate 42 has a gate electrode 95 provided on the interface side with the second semiconductor substrate 42 via a gate insulating film (not shown here), and further has other electrodes (not shown here). These gate electrodes 95 and other electrodes are covered with an interlayer insulating film 78, and buried wiring 97 using, for example, copper (Cu) is provided as multilayer wiring in a groove pattern provided in the interlayer insulating film 78. These buried wiring 97 are connected to each other by vias, and some of them are connected to the source / drain regions 91 and the gate electrode 95. In addition, the buried wiring 97 is also connected to a device terminal 93 provided on the second semiconductor substrate 42, and a drive circuit is configured by the transistor Tr and the buried wiring 97, etc.

[0364] Furthermore, aluminum wiring 98 is provided on the second semiconductor substrate 42 side of the multilayer wiring. The aluminum wiring 98 is connected to the embedded wiring 97 by vias, and is covered with an interlayer insulating film 78. The surface of the interlayer insulating film 78 has an uneven shape corresponding to the aluminum wiring 98, and a planarizing film 79 is provided to cover this uneven surface, and the surface of the planarizing film 79 is flat.

[0365] An insulating protective film 74 is provided on the planarization film 79 as described above, and the second semiconductor substrate 42, which is a circuit substrate, is laminated on the first semiconductor substrate 41, which is a sensor substrate, on the surface of the protective film 74. In addition, a protective film 75 that covers the second semiconductor substrate 42 is provided on the back surface side of the second semiconductor substrate 42, which is opposite to the front surface side on which the wiring layer 73 is provided.

[0366] (Each layer on the light receiving surface A, etc.) Next, the layers on the light-receiving surface A, namely, the anti-reflection film 81, the interface state suppression film 82, the etching stop film 83, the wiring groove formation film 84, the wiring 85, the cap film 86, the light-shielding film 87, the transparent protective film 88, the color filter 89, and the on-chip lens 90 will be described.

[0367] In the peripheral region 64 of the chip region 61, an antireflection film 81, an interface state suppression film 82, an etching stop film 83, and a wiring groove formation film 84 are provided on the light-receiving surface A of the first semiconductor substrate 41 in this order from the light-receiving surface A side. Furthermore, a wiring 85 is provided in the wiring groove formation film 84, and a cap film 86 is provided to cover this wiring 85.

[0368] In the pixel region 63 of the chip region 61, an antireflection film 81, an interface state suppression film 82, and a light-shielding film 87 are provided on the light-receiving surface A of the first semiconductor substrate 41. In the division region 62, the antireflection film 81 and the interface state suppression film 82 are provided on the light-receiving surface A of the first semiconductor substrate 41.

[0369] In each layer of the above configuration, the following materials can be used as the material of each layer. The anti-reflection film 81 is made of an insulating material having a higher refractive index than silicon oxide, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), or silicon nitride. The interface state suppression film 82 is made of, for example, silicon oxide (SiO2). The etching stop film 83 is made of a material that has a low etching selectivity relative to the material constituting the upper wiring groove formation film 84, and is made of, for example, silicon nitride (SiN). The wiring groove formation film 84 is made of, for example, silicon oxide (SiO2). The cap film 86 is made of, for example, silicon nitride (SiN).

[0370] (Wiring 85) The wiring 85 is provided on the light-receiving surface A in the peripheral region 64 of the chip region 61 as a buried wiring buried in a wiring groove formation film 84. The wiring 85 is formed by being buried integrally with the through vias 67, and connects between the through vias 67. The upper part of the wiring 85 is covered with a cap film 86.

[0371] (Through Via 67) The through via 67 is provided in the peripheral region 64 of the chip region 61, penetrating from the wiring 85 on the light-receiving surface A through the etching stop film 83, the interface state suppression film 82, and the anti-reflection film 81, and further through the first semiconductor substrate 41 to reach the wiring layer 71. A plurality of through vias 67 are provided, and are connected to the embedded wiring 77 of the first semiconductor substrate 41 and the aluminum wiring 98 or embedded wiring 97 of the second semiconductor substrate 42.

[0372] The wiring 85 and through via 67 are integrally formed by embedding copper (Cu) in the wiring groove and the connection hole via an isolation insulating film 68 that continuously covers the wiring groove formed in the wiring groove formation film 84 and the inner wall of the connection hole at the bottom of the wiring groove and the connection hole. Here, the wiring groove portion corresponds to the wiring 85, and the connection hole portion corresponds to the through via 67. The isolation insulating film 68 is formed using a material having a copper (Cu) diffusion prevention function, such as silicon nitride (SiN).

[0373] In this manner, by connecting the through vias 67 with the wiring 85, the buried wirings 77 of the first semiconductor substrate 41 to which the through vias 67 are respectively connected are electrically connected to the aluminum wiring 98 or the buried wiring 97 of the second semiconductor substrate 42. In other words, by connecting the through vias 67 with the wiring 85, the drive circuit of the first semiconductor substrate 41 and the drive circuit of the second semiconductor substrate 42 are connected.

[0374] (Light-shielding film 87) The light-shielding film 87 is provided on the interface state suppression film 82 on the light-receiving surface A in the pixel region 63 of the chip region 61, and has a plurality of light-receiving openings 87a corresponding to the respective photodiodes (photoelectric conversion units) 21. Such a light-shielding film 87 is made of a conductive material with excellent light-shielding properties such as aluminum (Al) or tungsten (W), and is provided in a state where it is grounded to the first semiconductor substrate 41 at the openings 87b.

[0375] (Transparent protective film 88) The transparent protective film 88 is provided in the chip region 61 and the division region 62 in a state where it covers the cap film 86 and the light-shielding film 87 on the light-receiving surface A. This transparent protective film 88 is made of an insulating material, such as an acrylic resin.

[0376] (Color filter 89 and on-chip lens 90) In the pixel region 63 of the chip region 61, color filters 89 and on-chip lenses 90 corresponding to each photodiode 21 are provided on a transparent protective film 88. The color filters 89 are configured in colors corresponding to each photodiode 21. The arrangement of the color filters 89 of each color is not particularly limited. The on-chip lenses 90 focus incident light onto each photodiode 21. Meanwhile, in the peripheral region 64 and the divided region 62 of the chip region 61, an on-chip lens film 90a that is integrated with the on-chip lens 90 is provided on the transparent protective film 88.

[0377] In the image sensor wafer 60 having the above-described structure, the through via 67 that penetrates the first semiconductor substrate 41 and reaches the wiring layer 71 and is connected to the embedded wiring 77 is, for example, a connection node N of the connection parts 43A and 43B shown in FIG. 1a ~N ma , and the connection node N 1b ~N mb The through vias 67 are connected to the transfer elements TR1 to TR2 of the detection unit 45A via embedded wiring 77. m , and the switch elements SW1 to SW m will be connected.

[0378] In the image sensor wafer 60, for example, the transfer elements TR1 to TR m , and the switch elements SW1 to SW mIn terms of the process, it is more preferable to use, as the transistor 20, a transistor of the same conductivity type (an N-channel transistor in the case of FIG. 2) as the transistors constituting the pixel 2 (the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 in FIG. 2) than to use a transistor of a different conductivity type.

[0379] A source / drain region 201 of the transistor 20 as a switching element is provided in the chip region 61 of the first semiconductor substrate 41 on the surface side opposite to the light-receiving surface A. The same is true for other impurity layers and element isolation regions 202, which are not shown here. In addition, the gate electrode 203 of the transistor 20 is provided in the chip region 61 of the wiring layer 71 provided on the surface of the first semiconductor substrate 41, on the interface side with the first semiconductor substrate 41, via a gate insulating film, which is not shown here.

[0380] Furthermore, in the chip region 61 of the first semiconductor substrate 41, a measurement pad 26 is provided in the same layer as the protective film 72 covering the wiring layer 71. The measurement pad 26 is an electrode pad corresponding to the terminals 47A, 47C and the electrode 47B in Fig. 6 etc., and the control terminals 49A1 and 49A2, and the control terminals 49B1 and 49B2 in Fig. 8 etc. The measurement pad 26 is a probe contact terminal used to inspect for open / short circuits in the wiring on the first semiconductor substrate 41 side, at a stage before the first semiconductor substrate 41 and the second semiconductor substrate 42 are bonded together.

[0381] [11. Application Examples of the Technology of the Present Disclosure] Next, an application example of the technology of the present disclosure will be described. Fig. 34 is a diagram showing a usage example using each of the above-mentioned embodiments and each of the modified examples according to the technology of the present disclosure.

[0382] The imaging element 1 to which the technology of the present disclosure is applied described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.

[0383] -Digital cameras, mobile devices with camera functions, and other devices that take images for viewing. Devices used for traffic purposes, such as on-board sensors that photograph the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, and for recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliance in accordance with those gestures. - Equipment used for medical or healthcare purposes, such as endoscopes and devices that take blood vessel images by receiving infrared light. - Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. - Equipment used for beauty purposes, such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp. Equipment used for sports, such as action cameras and wearable cameras for sports purposes. Agricultural equipment, such as cameras for monitoring fields and crop conditions.

[0384] (Example of application to imaging devices) Next, an example of application of the technology according to the present disclosure to an imaging device will be described. Fig. 35 is a block diagram showing a configuration of an example of an imaging device to which the technology according to the present disclosure can be applied. In Fig. 35, the imaging device 100 includes an optical unit 101, an imaging unit 102, an image processing unit 103, a frame memory 104, a CPU (Central Processing Unit) 105, a ROM (Read Only Memory) 106, a RAM (Random Access Memory) 107, a storage 108, an operation unit 109, a display unit 110, and a power supply unit 111. Among these, the image processing unit 103, the frame memory 104, the CPU 105, the ROM 106, the RAM 107, the storage 108, the operation unit 109, the display unit 110, and the power supply unit 111 are connected to each other by a bus 120 so as to be able to communicate with each other.

[0385] The storage 108 is a storage medium capable of storing data in a non-volatile manner, and may be, for example, a flash memory or a hard disk drive. The CPU 105 controls the overall operation of the imaging device 100 according to a program stored in advance in the ROM 106 or the storage 108, and uses the RAM 107 as a work memory.

[0386] The operation unit 109 includes various operators that allow the user to operate the imaging device 100, and passes control signals corresponding to user operations to the CPU 105. The display unit 110 includes a display device using an LCD (Liquid Crystal Display) or an organic EL (Electro-Luminescence), and a drive circuit that drives the display device. The display unit 110 displays a screen on the display device corresponding to a display signal passed by the CPU 105 via the bus 120, for example. The power supply unit 111 supplies power to each unit of the imaging device 100.

[0387] The optical unit 101 includes one or more lenses and mechanisms such as an aperture and focus, and causes light from a subject to enter the imaging unit 102. The imaging unit 102 includes an image sensor 1 according to the technology of the present disclosure, and the light incident from the optical unit 101 is irradiated onto a pixel array unit 11. In the pixel array unit 11, each pixel 2 outputs a pixel signal corresponding to the irradiated light. The imaging unit 102 supplies image data based on the pixel signals output from each pixel 2 to an image processing unit 103.

[0388] The image processing unit 103 includes, for example, a DSP (Digital Signal Processor), and performs predetermined image processing such as white balance processing and gamma correction processing on the image data supplied from the imaging unit 102 using a frame memory 104. The image data processed by the image processing unit 103 is stored in, for example, a storage 108.

[0389] By applying the imaging element 1 according to the technique of the present disclosure to the imaging section 102, the wiring formed for each pixel row or each pixel column can be inspected with a minimum of additional circuits, thereby suppressing an increase in chip area. Therefore, using the imaging element 1 according to the technique of the present disclosure as the imaging section 102 can contribute to further miniaturization of the imaging device 100. In addition, since the first semiconductor substrate 41 can be inspected individually, the yield of the imaging element 1 can be improved, and the cost of the imaging device 100 can be reduced.

[0390] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0391] The present technology can also be configured as follows. (1) a first circuit connected to a first position of each of a first wiring group including a plurality of wirings; a second circuit connected to a second position that is an end of each of the plurality of wirings; a plurality of connection parts provided in a one-to-one correspondence with each of the plurality of wirings between the first position and the second position, for connecting a third circuit to each of the plurality of wirings; A semiconductor element comprising: (2) at least one first external connection terminal connected to the first circuit for connecting the first circuit to an external device; at least one second external connection terminal connected to the second circuit for connecting the second circuit to an external device; The semiconductor element according to (1) above, further comprising: (3) the first external connection terminal and the second external connection terminal are disposed on a first surface of a first semiconductor substrate; the first semiconductor substrate is bonded to a second semiconductor substrate at a second surface that is a back surface of the first semiconductor substrate; The first external connection terminal and the second external connection terminal are The first surface is connected to the second surface by a through hole, The second semiconductor substrate comprises: electrodes are provided at positions corresponding to the first external connection terminal and the second external connection terminal on a surface that comes into close contact with the second surface when the first semiconductor substrate is bonded to the first semiconductor substrate; The semiconductor element according to (2) above. (4) The first circuit comprises: an output circuit that outputs a voltage to each of the plurality of wirings; The second circuit includes: A voltage is input from the plurality of wirings, and the plurality of input circuits are provided in a one-to-one correspondence with the plurality of wirings and connected in sequence, and external connection terminals for connecting to an external device are connected to one end and the other end of the sequentially connected terminals, respectively. A semiconductor element according to any one of (1) to (3). (5) Each of the plurality of input circuits a first control terminal to which one of the plurality of wirings is connected; a first switch section whose conductive / non-conductive state is controlled in response to a voltage input to the first control end; Including, The second circuit includes: The first switch units of the plurality of input circuits are connected in series. The semiconductor element according to (4) above. (6) The second circuit includes: the external connection terminals are connected to one end and the other end at which the first switch units of each of the plurality of input circuits are connected in series; The semiconductor element according to (5) above. (7) The second circuit includes: a first input circuit group including a plurality of input circuits, each of which has a plurality of wirings selected every other one of the plurality of wirings connected to the first control terminal and the first switch unit connected in series; a second input circuit group including a plurality of input circuits in which a plurality of wirings among the plurality of wirings that are not connected to the first input circuit group are connected to the first control terminal and the first switch units are connected in series; one end and the other end, to which the first switch units of each of the first input circuits are connected in series, are connected to one end and the other end, to which the first switch units of each of the second input circuits are connected in series, The semiconductor element according to (5) above. (8) The output circuit includes: a second switch section whose conductive / non-conductive state is controlled in response to a voltage input to a second control end; The first circuit comprises: a first output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to each of a plurality of wirings selected from among the plurality of wirings, the other end of the second switch section connected to an external connection terminal for connecting to an external device, and the second control end connected to an external connection terminal for connecting to an external device; a second output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to a plurality of wirings among the plurality of wirings that are not connected to the first output circuit group, the other end of the second switch section connected to an external connection terminal for connecting to an external device, and the second control end connected to an external connection terminal for connecting to an external device; Including, The semiconductor element according to (7) above. (9) The output circuit includes: a second switch section whose conductive / non-conductive state is controlled in response to a voltage input to a second control end; The first circuit comprises: a first output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to each of a first plurality of wirings selected every other one of the plurality of wirings, has the other end of the second switch section connected to an external connection terminal for connecting to an external device, and has the second control end connected to an external connection terminal for connecting to an external device; a second output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to a second plurality of wirings among the plurality of wirings that are not connected to the first output circuit group, the other end of the second switch section connected in common to an external connection terminal to which the other end of the second switch section included in the first output circuit group is connected, and the second control end connected to an external connection terminal for connection to an external device; Including, The second circuit includes: a reset unit including a third switch unit whose conductive and non-conductive states are controlled in response to a voltage input to a third control end; a first reset circuit group including a plurality of the reset units, each of which has one end of the third switch unit connected to each of the first plurality of wirings in a one-to-one relationship, the other end of the third switch unit connected to an external connection terminal for connecting to an external device, and the third control end connected to an external connection terminal for connecting to an external device; a second reset circuit group including a plurality of the reset units, each of which has one end of the third switch unit connected to each of the second plurality of wirings in a one-to-one relationship, the other end of the third switch unit connected to an external connection terminal for connecting to an external device, and the third control end connected to an external connection terminal for connecting to an external device; Including, The semiconductor element according to (7) above. (10) an external connection terminal for connecting to an external device is connected to an intermediate portion of the series connection of each of the first input circuit group and the second input circuit group; The semiconductor device according to any one of (7) to (9). (11) a cell array section in which a plurality of cells each performing a predetermined function are arranged in a matrix, and each of the plurality of wirings is connected to a plurality of cells among the plurality of cells that are aligned in a column in the array; Further equipped with The first circuit comprises: a plurality of cells arranged in rows in the array of the plurality of cells of the cell array unit are used as the output circuit; A semiconductor element according to any one of (5) to (10) above. (12) The second circuit includes: a short-circuiting unit that shorts one or more of the first switch units in response to an instruction from an external device; The semiconductor element according to (5) above, further comprising: (13) The second circuit includes: A plurality of the short-circuiting units each having a different number of the first switch units to be short-circuited; The semiconductor element according to (12) above, (14) Each of the plurality of input circuits a fourth control terminal to which one of the plurality of wirings is connected; a fourth switch unit whose open / closed state is controlled in response to a voltage input to the fourth control terminal; Including, The second circuit includes: the fourth switch units of the plurality of input circuits are connected in parallel; The semiconductor element according to (4) above. (15) The second circuit includes: an external connection terminal for connecting to an external device is commonly connected to one end of the fourth switch section of each of the plurality of input circuits; an external connection terminal for connecting to an external device is commonly connected to the other end of the fourth switch section of each of the plurality of input circuits; The semiconductor element according to (14) above. (16) The output circuit includes: a decode unit that designates one or more wirings that output the voltage among the plurality of wirings in accordance with address information; Including, The semiconductor element according to (14) above. (17) a cell array section in which a plurality of cells each performing a predetermined function are arranged in a matrix, and each of the plurality of wirings is connected to a plurality of cells among the plurality of cells that are aligned in a column in the array; Further equipped with The first circuit comprises: a plurality of cells arranged in rows in the array of the plurality of cells in the cell array portion are included as the output circuit; The second circuit includes: a decode unit that designates one or more wirings to which the voltage is to be input among the plurality of wirings in accordance with address information; Including, The semiconductor element according to (14) above. (18) a pixel array section in which a plurality of pixels, each including one or more light receiving elements, are arranged in a matrix, and each of the plurality of wirings is connected to a signal line that reads out pixel signals from a plurality of pixels aligned in a column in the array among the plurality of pixels; Further comprising: A semiconductor element according to any one of (1) to (17). (19) The third circuit includes: an analog-to-digital converter connected to each of the plurality of wirings; A semiconductor element according to any one of (1) to (18) above. (20) a fourth circuit including a plurality of wiring bundles each including a plurality of wirings, the fourth circuit being connected to one end of a second wiring group arranged along a direction different from that of the first wiring group, and including an output section that outputs a voltage to each of the plurality of wirings included in the second wiring group; a fifth circuit including an input circuit connected to the other end of the second wiring group and receiving a voltage from a plurality of wirings included in the second wiring group; Equipped with The fourth circuit and the fifth circuit each include A wiring designation unit that designates one wiring from among a plurality of wirings included in the wiring bundle, A semiconductor element according to any one of (1) to (19). (twenty one) The output unit is The switch includes a plurality of switch sections connected in series, each of which is controlled to be conductive or non-conductive in response to a voltage applied to a control end, The switch unit is one end of the plurality of switch units connected in series is connected to one wiring included in the second wiring group, and a voltage output by the output unit is applied to the other end of the plurality of switch units; The semiconductor element according to (20) above. (twenty two) The third circuit includes: a selection circuit that selects one wiring group from the second wiring group; The semiconductor element according to (20) above. (twenty three) A first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; a plurality of connection portions penetrating and connecting the first semiconductor substrate and the second semiconductor substrate; Further equipped with one of the first circuit and the second circuit is disposed on the first semiconductor substrate, and the other is disposed on the second semiconductor substrate; One end of the plurality of connection parts is connected to the first circuit, and the other end is connected to the second circuit. A semiconductor element according to any one of (1) to (22). (twenty four) a cell array section in which a plurality of cells each performing a predetermined function are arranged in a matrix, and each of the plurality of wirings is connected to a plurality of cells among the plurality of cells that are aligned in a column in the array; Further equipped with The first circuit comprises: an output circuit that outputs a voltage to each of the plurality of wirings; a well in which the output circuit is arranged and a well in which the cell array section is arranged are separated from each other; 24. The semiconductor device according to any one of (1) to (23). (twenty five) the output circuit includes a plurality of output sections each configured using a transistor; Among the plurality of output units, a well in which a first output unit is arranged and a well in which a second output unit is arranged are separated from each other. The semiconductor device according to (24) above. (26) Among the plurality of wirings, a first wiring connected to the first output unit; a second wiring connected to the second output unit; are adjacent, The semiconductor device according to (25) above. (27) Each of the plurality of output units is an input terminal for inputting an input voltage for determining a voltage to be output to a corresponding one of the plurality of wirings; A potential of each well in which each of the plurality of output units is arranged is applied from the input terminal of each of the plurality of output units. The semiconductor device according to (25) or (26) above. (28) The second circuit includes: a plurality of input circuits each configured using a transistor, each of which is provided in a one-to-one correspondence with a respective one of the plurality of wirings and receives a voltage from the plurality of wirings; a well in which the plurality of input circuits are arranged is separated from at least one of a well in which the output circuit is arranged and a well in which the cell array section is arranged; 28. The semiconductor device according to any one of (24) to (27). [Explanation of symbols]

[0392] 1. Image sensor 2,2' pixels 11 Pixel array section 31,311,312,313,314,31 m-1 ,31 m Vertical Signal Line 321,322,32 n Control Line 41a, 41b, 41c, 41d, 41e, 41f, 41g, 41h First semiconductor substrate 42 Second semiconductor substrate 43A, 43B, 44A, 44B Connections 45A, 45Aa, 45Ab, 45Ac, 45Ad, 45Ae, 45Af, 45Ag, 45Ah Detection unit 45B, 45Ba, 45Bb, 45Bc, 45Bd, 45Be, 45Be', 45Bf, 45Bg, 45Bh, 45Bh' Bias section 47A, 47C, 47E, 48A, 48C terminals 47B,47D,48B,48D electrode 49A, 49A1, 49A2, 49B, 50A, 50A R ,50A T ,50A S ,50B,50B1,50B R ,50B T ,50B S ,50C1,50C R ,50C T ,50C S Control Terminal

Claims

1. A semiconductor device comprising a first semiconductor substrate on which a plurality of pixels arranged in a matrix in a pixel array portion and a first wiring group including a plurality of wirings respectively connected to the plurality of pixels are formed, a second semiconductor substrate is bonded to the first semiconductor substrate, the second semiconductor substrate having a pixel control unit for controlling the plurality of pixels formed thereon; The first semiconductor substrate comprises: a first circuit connected to a first position of each of the plurality of wirings of a first wiring group including the plurality of wirings, for applying a voltage to each of the plurality of wirings; a second circuit connected to each of the plurality of wires at a second location remote from the first location, for detecting application of a voltage to each of the plurality of wires; a plurality of connection parts for connecting the pixel control unit to each of the plurality of wirings, the connection parts being provided in a one-to-one correspondence with each of the plurality of wirings between the first position and the second position; At least one first external connection terminal, which is a probe contact terminal including a terminal for supplying a test voltage and is connected to the first circuit; At least one second external connection terminal, which is a probe contact terminal including a terminal for detecting a test voltage and is connected to the second circuit; having Semiconductor element.

2. the first semiconductor substrate is bonded to a second semiconductor substrate at a second surface on the back side of a first surface on which the first external connection terminals and the second external connection terminals are arranged; The first external connection terminal and the second external connection terminal each include a through hole is used to connect the first surface to a connection terminal on the second surface; The second semiconductor substrate comprises: an electrode is provided at a position on a surface that comes into close contact with the second surface when the first semiconductor substrate is bonded to the first semiconductor substrate, the position being in contact with a connection terminal that is connected from the first external connection terminal using a through hole, and the position being in contact with a connection terminal that is connected from the second external connection terminal using a through hole; The semiconductor device according to claim 1 .

3. The first circuit includes: an output circuit that outputs a voltage to each of the plurality of wirings; The second circuit includes: a plurality of input circuits are provided in a one-to-one correspondence with the plurality of wirings and connected in series, and a voltage is input from the plurality of wirings; and external connection terminals, which are needle contact terminals, are connected to one end and the other end of the plurality of input circuits connected in series, respectively; The semiconductor device according to claim 1 .

4. Each of the plurality of input circuits a first control terminal to which one of the plurality of wirings is connected; a first switch section whose conductive / non-conductive state is controlled in response to a voltage input to the first control end; Including, The second circuit includes: the first switch units of the plurality of input circuits are connected in series; The semiconductor device according to claim 3 .

5. The second circuit includes: the external connection terminals are connected to one end and the other end at which the first switch units of each of the plurality of input circuits are connected in series; The semiconductor device according to claim 4 .

6. The second circuit includes: a first input circuit group including a plurality of input circuits, each of which has a plurality of wirings selected every other one of the plurality of wirings connected to the first control terminal and has the first switch unit connected in series; a second input circuit group including a plurality of input circuits in which a plurality of wirings among the plurality of wirings that are not connected to the first input circuit group are connected to the first control terminal and the first switch units are connected in series; one end and the other end, to which the first switch units of each of the first input circuits are connected in series, are connected to one end and the other end, to which the first switch units of each of the second input circuits are connected in series, The semiconductor device according to claim 4 .

7. The output circuit includes: a second switch section whose conductive / non-conductive state is controlled in response to a voltage input to a second control end; The first circuit includes: a first output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to each of a plurality of wirings selected from among the plurality of wirings, the other end of the second switch section connected to an external connection terminal that is a needle contact terminal, and the second control end connected to the external connection terminal that is the needle contact terminal; a second output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to a plurality of wirings among the plurality of wirings that are not connected to the first output circuit group, has the other end of the second switch section connected to an external connection terminal that is a needle contact terminal, and has the second control end connected to the external connection terminal that is the needle contact terminal; Including, The semiconductor device according to claim 6.

8. The output circuit includes: a second switch section whose conductive / non-conductive state is controlled in response to a voltage input to a second control end; The first circuit includes: a first output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to each of a first plurality of wirings selected every other one of the plurality of wirings, has the other end of the second switch section connected to an external connection terminal which is a needle contact terminal, and has the second control end connected to the external connection terminal which is a needle contact terminal; a second output circuit group including a plurality of the output circuits, each of which has one end of the second switch section connected in a one-to-one relationship to a second plurality of wirings among the plurality of wirings that are not connected to the first output circuit group, the other end of the second switch section being commonly connected to an external connection terminal to which the other end of the second switch section included in the first output circuit group is connected, and the second control end being connected to an external connection terminal that is a needle contact terminal; Including, The second circuit includes: a reset unit including a third switch unit whose conductive and non-conductive states are controlled in response to a voltage input to a third control end, a first reset circuit group including a plurality of the reset units, each of which is connected in a one-to-one relationship to each of the first plurality of wirings, one end of the third switch unit is connected between the first control end of the first switch unit of each of the plurality of input circuits included in the first input circuit group and the plurality of connection units, the other end of the third switch unit is connected to a common external connection terminal which is a needle contact terminal, and the third control end is connected to the external connection terminal which is a needle contact terminal; a second reset circuit group including a plurality of the reset units, each of which is connected in a one-to-one relationship to each of the second plurality of wirings, one end of the third switch unit is connected between the first control end of the first switch unit of each of the plurality of input circuits included in the second input circuit group and the plurality of connection units, the other end of the third switch unit is connected to the common external connection terminal which is a needle contact terminal, and the third control end is connected to the external connection terminal which is a needle contact terminal; Including, The semiconductor device according to claim 6.

9. an external connection terminal, which is a needle contact terminal, is connected to an intermediate portion of the series connection of each of the first input circuit group and the second input circuit group; The semiconductor device according to claim 6.

10. a pixel array section in which a plurality of pixels each performing a predetermined function are arranged in a matrix, and each of the plurality of wirings is connected to a plurality of pixels aligned in a column in the array among the plurality of pixels; Further equipped with The first circuit includes: a plurality of pixels arranged in a row in the array of the plurality of pixels of the pixel array unit are used as the output circuit; The semiconductor device according to claim 4 .

11. The second circuit includes: a shorting unit that shorts one or more of the first switch units depending on whether or not each of one or more address designation terminals is in a high state; The semiconductor device of claim 4 further comprising:

12. The second circuit includes: A plurality of the short-circuiting units each having a different number of the first switch units to be short-circuited; The semiconductor device of claim 11 .

13. Each of the plurality of input circuits a fourth control terminal to which one of the plurality of wirings is connected; a fourth switch unit whose open / closed state is controlled in response to a voltage input to the fourth control terminal; Including, The second circuit includes: the fourth switch units of the plurality of input circuits are connected in parallel; The semiconductor device according to claim 3 .

14. The second circuit includes: an external connection terminal which is a needle contact terminal is commonly connected to one end of the fourth switch section of each of the plurality of input circuits; an external connection terminal which is a needle contact terminal is commonly connected to the other end of the fourth switch unit of each of the plurality of input circuits; The semiconductor device according to claim 13.

15. The output circuit includes: a decoder section for designating one or more wirings from among the plurality of wirings to which the voltage is to be output in accordance with address information for selecting a particular wiring from among the plurality of wirings; Including, The semiconductor device according to claim 13.

16. the pixel array unit is a cell array unit in which a plurality of cells each performing a predetermined function are arranged in a matrix, and each of the plurality of wirings is connected to a plurality of cells among the plurality of cells that are aligned in a column in the array, The first circuit includes: a plurality of cells arranged in rows in the array of the plurality of cells in the cell array portion are included as the output circuit; The second circuit includes: a decoder section for designating one or more wirings among the plurality of wirings to which the voltage is to be input in accordance with address information for selecting a specific wiring among the plurality of wirings; Including, The semiconductor device according to claim 13.

17. The pixel array section, A plurality of pixels, each including one or more light receiving elements, are arranged in a matrix, and each of the plurality of wirings is connected to a signal line that reads out pixel signals from a plurality of pixels aligned in a column in the array among the plurality of pixels. The semiconductor device according to claim 1 .

18. The pixel control unit an analog-to-digital converter connected to each of the plurality of wirings; The semiconductor device according to claim 1 .

19. A fourth circuit including a plurality of wiring bundles each including a plurality of wirings for controlling a plurality of pixels aligned in a row among the plurality of pixels arranged in a matrix in the pixel array section, the fourth circuit being connected to one end of a second wiring group aligned in a direction different from that of the first wiring group, and including an output section for outputting a voltage to each of the plurality of wirings included in the second wiring group; a fifth circuit including an input circuit connected to the other end of the second wiring group and receiving a voltage from a plurality of wirings included in the second wiring group; a plurality of connection parts for connecting the pixel control unit to each of the plurality of wirings included in the second wiring group, the connection parts being provided in a one-to-one correspondence with each of the plurality of wirings at one end of the second wiring group and the other end of the second wiring group; a plurality of third external connection terminals, each of which is a probe contact terminal including a terminal for supplying a test voltage, connected to the fourth circuit; a plurality of fourth external connection terminals, each of which is a probe contact terminal including a terminal for detecting a test voltage, connected to the fifth circuit; Equipped with The fourth circuit and the fifth circuit each include a wiring designation unit that designates one wiring from among a plurality of wirings included in the wiring bundle; The semiconductor device according to claim 1 .

20. The output unit is The switch includes a plurality of switch sections connected in series, each of which is controlled to be conductive or non-conductive in response to a voltage applied to a control end, The switch unit is one end of the plurality of switch units connected in series is connected to one wiring included in the second wiring group, and a voltage output by the output unit is applied to the other end of the plurality of switch units; 20. The semiconductor device of claim 19.

21. The fourth circuit includes: a selection circuit that selects one wiring bundle from the plurality of wiring bundles included in the second wiring group; 20. The semiconductor device of claim 19.

22. The pixel array section, a cell array section in which a plurality of cells each performing a predetermined function are arranged in a matrix, and each of the plurality of wirings is connected to a plurality of cells aligned in a column in the array among the plurality of cells, Further equipped with The first circuit includes: an output circuit that outputs a voltage to each of the plurality of wirings; a well in which the output circuit is arranged and a well in which the cell array section is arranged are separated from each other; The semiconductor device according to claim 1 .

23. the output circuit includes a plurality of output sections each configured using a transistor; Among the plurality of output units, a well in which a first output unit is arranged and a well in which a second output unit is arranged are separated from each other.

23. The semiconductor device of claim 22.

24. Among the plurality of wirings, a first wiring connected to the first output section; a second wiring connected to the second output section; are adjacent, 24. The semiconductor device of claim 23.

25. Each of the plurality of output units is an input terminal for inputting an input voltage for determining a voltage to be output to a corresponding one of the plurality of wirings; A potential of each well in which each of the plurality of output units is arranged is applied from the input terminal of each of the plurality of output units.

24. The semiconductor device of claim 23.

26. The second circuit includes: a plurality of input circuits each configured using a transistor, each of which is provided in a one-to-one correspondence with a respective one of the plurality of wirings and receives a voltage from the plurality of wirings; a well in which the plurality of input circuits are arranged is separated from at least one of a well in which the output circuit is arranged and a well in which the cell array section is arranged; 23. The semiconductor device of claim 22.

Images