Passivation structure for semiconductor devices

Abstract

Disclosed is a semiconductor device, particularly a passivation structure for a semiconductor device. The semiconductor device can include an active area, an edge termination region disposed along the periphery of the active area, and a passivation structure capable of forming a die seal along the edge termination region. The passivation structure can include several passivation layers arranged in an arrangement that improves the mechanical strength and adhesion of the passivation structure along the edge termination region. The interface formed by at least one of the passivation layers can be patterned to more evenly distribute forces associated with thermal expansion and contraction during power cycling, thereby reducing cracking and delamination of the passivation structure. The patterned layer can be at least partially embedded within the passivation structure in an arrangement that forms a pattern corresponding to an overlying portion of the passivation structure.

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices, and more particularly to passivation structures for semiconductor devices. [Background technology]

[0002] Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide bandgap semiconductor material systems such as gallium nitride (GaN) and silicon carbide (SiC) are increasingly being utilized in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Examples include discrete devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, high electron mobility transistors (HEMTs), and integrated circuits such as monolithic microwave integrated circuits (MMICs) that contain one or more discrete devices.

[0003] Semiconductor devices are typically formed in an active area of ​​a semiconductor die. In semiconductor dies fabricated to support high voltages and high currents, electric field concentrations can interfere with proper operation of the semiconductor die. Electric field concentrations are particularly problematic at the edges of the semiconductor die. Thus, an edge termination region surrounds the active area near the periphery of the semiconductor die to reduce the electric field at the edge of the die. Without the edge termination region, the electric field would concentrate at the edge of the die and would degrade the performance of the die. For example, the breakdown voltage, leakage current, and / or die reliability may be significantly degraded. Specifically, the die may suffer from leakage current under reverse bias when subjected to thermal stresses (e.g., temperatures greater than 150° C.) that may accompany high operating voltages. Several edge termination structures have been proposed to reduce the electric field concentrations at the edge of the die, but many of the proposed structures may not be suitable to withstand the thermal shock and power cycling associated with high temperature and high voltage operating conditions.

[0004] Technology continues to seek improved edge termination structures for semiconductor devices that can overcome the challenges associated with conventional semiconductor devices. Summary of the Invention [Means for solving the problem]

[0005] The present disclosure relates to semiconductor devices, and in particular to passivation structures for semiconductor devices. The semiconductor device may include an active area, an edge termination region disposed along a periphery of the active area, and a passivation structure capable of forming a die seal along the edge termination region. The passivation structure may include several passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces associated with thermal expansion and contraction during power cycling, thereby reducing cracking and delamination of the passivation structure. The pattern may include several protrusions and recesses in at least one of the multiple passivation layers. The patterned layer may be at least partially embedded within the passivation structure to form a pattern in an overlying portion of the passivation structure.

[0006] In one aspect, a semiconductor device comprises: a drift region, an active region including a portion of the drift region, an edge termination region in the drift region and disposed along a periphery of the active region, a passivation structure on the edge termination region, and a patterned layer formed in the passivation structure. In an embodiment, the patterned layer is embedded in the passivation structure. In an embodiment, the patterned layer comprises polysilicon. The passivation structure can include a first passivation layer on the drift region and a second passivation layer on the first passivation layer. In an embodiment, the patterned layer is disposed between the first passivation layer and the second passivation layer. In an embodiment, the second passivation layer forms at least one protrusion aligned with at least a portion of the patterned layer.

[0007] The passivation structure of the semiconductor device may further comprise a third passivation layer on the second passivation layer, where at least one protrusion of the second passivation layer extends into the third passivation layer. In an embodiment, the at least one protrusion comprises a plurality of protrusions, and a top surface of the third passivation layer is flat at least in some portions of the passivation structure. The passivation structure may further comprise a fourth passivation layer on the third passivation layer, where a top surface of the third passivation layer forms an interface with the fourth passivation layer. In an embodiment, the edge termination region further comprises a plurality of guard rings in the drift region, where at least one portion of the patterned layer is aligned with an individual guard ring of the plurality of guard rings. In an embodiment, at least one portion of the patterned layer is aligned with at least two individual guard rings of the plurality of guard rings. At least one guard ring of the plurality of guard rings may have no portion directly overlying the patterned layer. In an embodiment, at least one guard ring of the plurality of guard rings is disposed closer to the active region than all other guard rings of the plurality of guard rings. In an embodiment, at least one portion of the patterned layer forms a field plate within the passivation structure. At least one portion of the patterned layer is aligned with an individual guard ring of the plurality of guard rings at a vertically offset position. In an embodiment, the patterned layer is disposed on the first passivation layer, the patterned layer further extending past a sidewall of the first passivation layer in a direction toward an outer edge of the edge termination region.

[0008] In some embodiments, the patterned layer forms at least one continuous ring around a perimeter of the active area. In some embodiments, the patterned layer forms at least one segmented ring around a perimeter of the active area. The at least one segmented ring comprises a first segmented ring and a second segmented ring of the patterned layer, where the ring segments of the first segmented ring are laterally offset relative to the ring segments of the second segmented ring.

[0009] In one embodiment, the drift region comprises silicon carbide (SiC). In one embodiment, the active region comprises a SiC metal-oxide-semiconductor field effect transistor (MOSFET).

[0010] In another aspect, a semiconductor device comprises: a drift region, an active region including a portion of the drift region, an edge termination region in the drift region and disposed along a periphery of the active region, and a passivation structure on the edge termination region, wherein a passivation layer of the passivation structure forms at least one protrusion that extends partially into an additional passivation layer of the passivation structure. The at least one protrusion can form at least one protrusion ring around the periphery of the active region. In some embodiments, the at least one protrusion ring is continuous around the periphery of the active region. In some embodiments, the at least one protrusion ring is segmented around the periphery of the active region.

[0011] In some embodiments, the at least one protrusion includes a plurality of protrusions, the passivation layer forms a plurality of recesses between adjacent protrusions of the plurality of protrusions, and a portion of the additional passivation layer extends into each recess of the plurality of recesses. In some embodiments, at least a portion of a top surface of the additional passivation layer opposite the plurality of recesses is flat. In some embodiments, the plurality of recesses includes a first recess and a second recess, the first recess having a width greater than a width of the second recess, and the first recess is disposed closer to an outer edge of the edge termination region than the second recess.

[0012] The semiconductor device may further comprise a patterned layer within the passivation structure, the patterned layer being aligned with the at least one protrusion. In one embodiment, the patterned layer comprises polysilicon. In one embodiment, the at least one protrusion comprises a plurality of protrusions, and a discontinuous portion of the patterned layer is aligned with each protrusion of the plurality of protrusions. In one embodiment, the edge termination region comprises a plurality of guard rings within the drain region, and a discontinuous portion of the patterned layer is aligned with each guard ring of the plurality of guard rings.

[0013] In another aspect, any of the above aspects, individually or together, and / or various separate aspects and features as described herein may be combined to further advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein to the contrary.

[0014] Those skilled in the art will appreciate the scope of the present disclosure and realize further aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures.

[0015] The accompanying drawing figures, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure. [Brief description of the drawings]

[0016] [Figure 1A] 1 is a top view illustration of an exemplary semiconductor device according to the present disclosure. [Figure 1B] 1B is a cross-sectional view of a portion of the semiconductor device of FIG. 1A for an embodiment in which the semiconductor device includes a MOSFET. [Figure 2A] FIG. 1C is a partial cross-sectional view of a semiconductor device similar to that of FIG. 1B, providing a more detailed view of the edge termination region. [Figure 2B] FIG. 2B is a top view of the semiconductor device of FIG. 2A. [Diagram 3] 2B is a partial cross-sectional view of a semiconductor device similar to that of FIG. 2A and further including a passivation layer arrangement in an edge termination region that provides improved structural stability. [Figure 4] 4 is a partial cross-sectional view of a semiconductor device similar to that of FIG. 3, but in which individual portions of a patterned layer are aligned with more than one of a plurality of guard rings. [Diagram 5] 4 is a partial cross-sectional view of a semiconductor device similar to the semiconductor device of FIG. 3, but without a portion of a patterned layer aligned with an overlying arrangement of at least one guard ring. [Figure 6] 4 is a partial cross-sectional view of a semiconductor device similar to that of FIG. 3, but with at least one guard ring electrically connected to a portion of the patterned layer that penetrates the first passivation layer. [Figure 7] 4 is a partial cross-sectional view of a semiconductor device similar to that of FIG. 3, except that portions of a patterned layer are aligned with an underlying guard ring in a vertically offset manner. [Figure 8A] 1 is a top view of a portion of a semiconductor device in which patterned layers form one or more continuous rings around the periphery of the active area in accordance with the principles of the present disclosure. [Figure 8B]FIG. 1 is a top view of a portion of a semiconductor device in which patterned layers form one or more segmented rings around the periphery of the active area in accordance with the principles of the present disclosure. [Figure 9] 4 is a partial cross-sectional view of a semiconductor device similar to that of FIG. 3, but with the patterned layer forming a ring around the periphery of the first passivation layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The embodiments described below represent the necessary information to enable one skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, one skilled in the art will understand the concepts disclosed and will recognize applications of these concepts not specifically addressed herein. It should be understood that these concepts and applications are within the scope of this disclosure and the appended claims.

[0018] Although terms such as first, second, etc. may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it should be understood that it may be directly on or extending into the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "over" or extending "upon" another element, it should be understood that it may be directly on or extending into the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0021] The terminology used herein is merely for the purpose of describing particular embodiments and is not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0022] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is further understood that the terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and the relevant art, and may not be interpreted in an idealized or overly formal manner unless expressly so defined herein.

[0023] The embodiments are described herein with reference to schematic illustrations of the disclosed embodiments. As such, actual dimensions of layers and elements may vary and variations from the shapes of the illustrations are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, regions shown or described as square or rectangular may have rounded or curved profiles, and regions shown as straight may have some irregular shapes. As such, the regions shown in the figures are schematic, and their shapes are not intended to illustrate the exact shape of the regions of the device, nor are they intended to limit the scope of the disclosure. In addition, the size of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes, and thus are provided to illustrate the general structure of the subject matter, and may or may not be drawn to scale. Common elements between multiple figures may be indicated herein with common element numbers and may not be described again thereafter.

[0024] The present disclosure relates to semiconductor devices, and in particular to passivation structures for semiconductor devices. The semiconductor device may include an active area, an edge termination area disposed along a periphery of the active area, and a passivation structure capable of forming a die seal along the edge termination area. The passivation structure may include several passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination area. An interface formed by at least one of the multiple passivation layers may be provided with a pattern that serves to more evenly distribute forces associated with thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. The pattern may include multiple protrusions and recesses in at least one of the multiple passivation layers. The patterned layer may be at least partially embedded in the passivation structure to form a pattern in an overlying portion of the passivation structure.

[0025] FIG. 1A is a top view illustration of an exemplary semiconductor device 10 according to the present disclosure. The semiconductor device 10 includes an active area 12 and an edge termination region 14 surrounding the active area 12 near the periphery of the semiconductor device 10. Depending on the particular application, the active area 12 may include one or more semiconductor devices or semiconductor device cells formed within the active area, such as one or more metal-oxide-semiconductor field effect transistors (MOSFETs), diodes, Schottky diodes, Junction Barrier Schottky (JBS) diodes, PiN diodes, and Insulated Gate Bipolar Transistors (IGBTs), among others. The semiconductor device 10 may include a wide bandgap semiconductor device, e.g., a silicon carbide (SiC) based device. The edge termination region 14 is configured to reduce electric field crowding at the edge of the semiconductor device 10 to improve the performance of the semiconductor device. For example, the edge termination region 14 may increase the breakdown voltage of the semiconductor device 10 and reduce the leakage current of the semiconductor device 10 over time, as discussed in more detail below. By way of example, edge termination region 14 may include one or more guard rings, junction termination extensions (JTEs), and combinations thereof.

[0026] FIG. 1B illustrates a cross-sectional view of a portion of semiconductor device 10 of FIG. 1A for an embodiment in which semiconductor device 10 includes a MOSFET. While an exemplary MOSFET is described, the principles of the present disclosure are applicable to other semiconductor devices listed above, including diodes, Schottky diodes, JBS diodes, PiN diodes, and IGBTs, among others. Semiconductor device 10 includes a substrate 16 and a drift region 18 on substrate 16. Drift region 18 may embody one or more drift layers of a wide bandgap semiconductor material, such as SiC. An inner edge 14A of edge termination region 14 is shown by a vertical dashed line to delineate edge termination region 14 from active region 12. An outer edge 14B of edge termination region 14 may correspond to a peripheral edge of semiconductor device 10. In edge termination region 14, several guard rings 20 are provided in drift region 18. Specifically, the guard rings 20 are provided adjacent, or even directly adjacent, the top surface 18A of the drift region 18 opposite the substrate 16. The guard rings 20 may be formed by ion implantation, the implants used may include aluminum (Al), boron (B), or any other suitable p-type dopant when the drift region 18 is configured as an n-type layer. Each guard ring 20 forms a subregion in the edge termination region 14 having a doping type that is opposite to that of the drift region 18. In this example, the drift region 18 is an n-type layer, while the guard rings 20 are p-type subregions. However, the principles of the present disclosure apply equally to devices having an opposite polarity configuration, where the doping types may be reversed, as illustrated in FIG. 1B. For illustrative purposes, five guard rings 20 are illustrated in FIG. 1B. In various embodiments, the number of guard rings 20 may be 5 or more, or 10 or more, or 20 or more, or in the range of 5 to 20, or in the range of 10 to 20, depending on the application.

[0027] When a voltage is supported by the drift region 18, the electric field concentration at the outer edge 14B of the edge termination region 14 tends to be substantially greater than at the inner edge 14A of the edge termination region 14. In one embodiment, a surface depletion protection region 22 may also be provided in the drift region 18 at the outer edge 14B of the edge termination region 14. The surface depletion protection region 22 may have the same doping type as the drift region 18, but a higher doping concentration than the doping concentration of the drift region 18. In this manner, the surface depletion protection region 22 may prevent depletion at the top surface 18A of the drift region 18 to further improve the performance of the semiconductor device 10. In one embodiment, the surface depletion protection region 22 is provided by implantation. A passivation layer 24 may be provided on the top surface 18A of the drift region 18 opposite the substrate 16 to passivate the top surface 18A of the drift region 18. Passivation layer 24 may be embodied with one or more layers of insulating material of any suitable material, such as one or more layers of oxide and / or nitride based dielectric layers, hi one embodiment, passivation layer 24 may be embodied with a multi-layer structure including one or more of a field oxide layer, one or more intermetal dielectric layers, and a top insulating layer.

[0028] Substrate 16 is 1 x 10 17 cm -3 and 1×10 20 cm -3 In various embodiments, the doping concentration of the substrate 16 may be between 1×10 17 cm -3 and 1×10 20 cm -3 For example, the doping concentration of substrate 16 may be in any small range between 1×10 18 cm -3 and 1×10 20 cm -3 Between 1×10 19 cm -3 and 1×10 20 cm -3 Between 1×10 17 cm -3 and 1×10 19 cm-3 Between 1×10 17 cm -3 and 1×10 18 cm -3 Between and 1×10 18 cm -3 and 1×10 19 cm -3 It may be between.

[0029] The drift region 18 is 1×10 14 cm -3 and 1×10 18 cm -3 In various embodiments, the doping concentration of drift region 18 may be between 1×10 14 cm -3 and 1×10 18 cm -3 For example, the doping concentration of drift region 18 may be in any subrange between 1×10 15 cm -3 and 1×10 18 cm -3 Between 1×10 16 cm -3 and 1×10 18 cm -3 Between 1×10 17 cm -3 and 1×10 18 cm -3 Between 1×10 14 cm -3 and 1×10 17 cm -3 Between 1×10 14 cm -3 and 1×10 16 cm -3 Between 1×10 14 cm -3 and 1×10 15 cm -3 Between 1×10 15 cm -3 and 1×10 17 cm -3 Between 1×10 15 cm -3 and 1×10 16 cm -3 Between and 1×10 16cm -3 and 1×10 17 cm -3 The surface depletion protection region 22 may have a doping concentration that is higher than the doping concentration of the drift region 18. In various embodiments, the surface depletion protection region 22 may have a doping concentration that is between 2 and 10 times the doping concentration of the drift region 18. 5 The doping concentration may range from 100 to 200 .mu.m.

[0030] Guard Ring 20, 5 x 10 16 cm -3 and 1×10 21 cm -3 In various embodiments, the doping concentration of the guard ring 20 may be between 5×10 16 cm -3 and 1×10 21 cm -3 For example, the doping concentration of the guard ring 20 may be in any small range between 5×10 18 cm -3 and 1×10 21 cm -3 Between 5×10 19 cm -3 and 1×10 21 cm -3 Between 5×10 20 cm -3 and 1×10 21 cm -3 Between 5×10 16 cm -3 and 1×10 20 cm -3 Between 5×10 16 cm -3 and 1×10 19 cm -3 Between and 5×10 16 cm -3 and 1×10 20 cm -3 It may be between.

[0031] As discussed above, the active region 12 may include one or more semiconductor devices. In the example of FIG. 1B, the active region 12 includes at least one MOSFET cell 26, e.g., a SiC-based MOSFET in which the drift region 18 includes one or more layers of SiC. The MOSFET cell 26 includes a substrate 16 and a drift region 18. A number of junction implants 28 are provided in the drift region 18, specifically on the top surface 18A of the drift region 18 opposite the substrate 16. The junction implants 28 include a first well region 28A having a doping type opposite to that of the drift region 18 and a second well region 28B having a doping type the same as that of the drift region 18. The junction implants 28 are separated from each other by a JFET region 30. The JFET region 30 has a doping type the same as that of the drift region 18 and a doping concentration higher than that of the drift region 18. A source contact 32 is provided on the top surface 18A of the drift region 18 opposite the substrate 16 over each one of the plurality of junction implants 28 such that the source contact 32 contacts a portion of the first well region 28A and a portion of the second well region 28B. A gate oxide layer 34, which may comprise other insulating materials for other semiconductor devices, is provided on the top surface 18A of the drift region 18 opposite the substrate 16 over the JFET region 30 and a portion of each one of the plurality of junction implants 28 such that the gate oxide layer 34 overlaps a respective one of the plurality of second well regions 28B. A gate contact 36 is provided on the gate oxide layer 34. A drain contact 38 is provided on the surface of the substrate 16 opposite the drift region 18. The MOSFET cells 26 may be arranged across the entire surface of the active region 12 or may be arranged in a desired pattern with one or more other semiconductor devices (e.g., diodes) to provide a desired function.

[0032] FIG. 2A is a partial cross-sectional view of a semiconductor device 40 similar to the semiconductor device 10 of FIG. 1B and provides a more detailed view of the edge termination region 14. The edge termination region 14 can include a surface charge compensation region 42 formed on the top surface 18A of the drift region 18 between the guard rings 20. The surface charge compensation region 42 may be formed by ion implantation and can have a doping type that is opposite to the doping type of the drift region 18. In this manner, the surface charge compensation region 42 has the same doping type as the guard rings 20 but a lower doping concentration than the guard rings 20. In this example, the drift region 18 is an n-type layer, while the surface charge compensation region 42 and the guard rings 20 have p-type doping. However, the principles of this disclosure apply equally to devices having the opposite polarity configuration. The surface charge compensation region 42 can have a thickness relative to the top surface 18A of the drift region 18 that is equal to or less than the corresponding thickness of the guard rings 20. The surface charge compensation region 42 can reduce the sensitivity of the guard ring 20 to surface charges at the interface between the first passivation layer 24-1 and the drift region 18.

[0033] As shown, a first passivation layer 24-1 may be formed on the top surface 18A of the drift region 18 and the guard ring 20. The first passivation layer 24-1 may include an oxide layer or other insulating layer formed in the same manufacturing step and including the same material as the gate oxide layer 34 of FIG. 1B. In some embodiments, the first passivation layer 24-1 may have a thickness greater than the thickness of the gate oxide layer 34 of FIG. 1B. For example, the thickness of the first passivation layer 24-1 may be from 2 to 100 times the thickness of the gate oxide layer 34 of FIG. 1B. For MOSFET applications, the first passivation layer 24-1 may include silicon dioxide. In other embodiments, the first passivation layer 24-1 includes a different dielectric material than the gate oxide layer 34 of FIG. 1B. In various applications, the first passivation layer 24-1 may be referred to as a field oxide for the semiconductor device 40. A second passivation layer 24-2 may be provided over the first passivation layer 24-1. In one embodiment, the second passivation layer 24-2 may include one or more dielectric layers, which may include a combination of silicon dioxide and silicon nitride layers, that serve as an intermetal dielectric to electrically isolate the multiple metal interconnect lines and also serve as an interlayer dielectric to electrically isolate the polysilicon gate and lines from the metal interconnect lines. In the semiconductor device 40, one or more portions of the second passivation layer 24-2 in the active region 12 serve to at least partially define and isolate the gate interconnect 36' and the source interconnect 32'. In this cross-section of FIG. 2A, the source contact (32 in FIG. 1B) is not visible because the source interconnect 32' is configured as a runner or bus that electrically connects with the source contact (32 in FIG. 1B) in a different portion of the semiconductor device 40. As shown, the second passivation layer 24-2 may overlap the first passivation layer 24-1 in a direction toward the outer edge 14B and may contact the top surface 18A of the drift region 18 and the surface depletion protection region 22.A third passivation layer 24-3 may be provided over the second passivation layer 24-2, the gate interconnect 36', and the source interconnect 32'. The third passivation layer 24-3 may include one or more dielectric layers, which may include a combination of silicon dioxide and silicon nitride layers, and the dielectric layers may form a diffusion barrier and / or a moisture barrier for the underlying portions of the semiconductor device 40. The third passivation layer 24-3 may overlap the second passivation layer 24-2 in a direction toward the outer edge 14B and may contact the top surface 18A of the drift region 18 and the surface depletion protection region 22. Finally, a fourth passivation layer 24-4 may be provided over the third passivation layer 24-3. In one embodiment, the fourth passivation layer 24-4 can include a material having chemical, mechanical, and high temperature stability, such as a polyimide that can form a scratch-resistant coating for the semiconductor device 40. Additionally, the passivation layers 24-1 through 24-4 may not extend completely to the outer edge 14B of the edge termination region 14 to provide room for saw or scribe streets when the semiconductor device 40 is singulated. The combination of one or more of the passivation layers 24-1 through 24-4 may be referred to as a passivation structure and / or die seal for the semiconductor device 40. Although in this example, the drift region 18 is an n-type layer while the guard ring 20 is a p-type subregion, the reverse polarity configuration is also applicable to the present disclosure.

[0034] When the semiconductor device 40 is electrically operated, the potential from the backside of the drift region 18 (e.g., drain contact 38 in FIG. 1B) tends to concentrate an electric field along the edge termination region 14. When the semiconductor device 40 is in a blocking mode, the voltage supported by the drift region 18 tends to be higher at the outer edge 14B and decreases in a direction toward the inner edge 14A at each of the guard rings 20. In this regard, the higher operating temperatures involved may introduce thermal stresses into the edge termination region 14 and may promote structural failure in one or more of the passivation layers 24-1 through 24-4. For example, thermal shock and power cycling during operating conditions and / or qualification testing may result in delamination and / or cracking of one or more of the passivation layers 24-1 through 24-4, causing catastrophic device failure. In particular, delamination and / or cracking may be more problematic when adjacent ones of the passivation layers 24-1 through 24-4 having dissimilar and / or different material properties undergo thermal expansion and contraction during power cycling. Dissimilar material properties may include, among other things, mismatches in coefficient of thermal expansion (CTE). By way of illustration, delamination and / or cracking may occur at the interface between the second passivation layer 24-2 and the third passivation layer 24-3 in an arrangement in which the second passivation layer 24-2 comprises silicon dioxide and the third passivation layer comprises silicon nitride. The likelihood of such structural failure may be higher when the interface between the second passivation layer 24-2 and the third passivation layer 24-3 is substantially planar throughout the majority of the edge termination region 14. In this regard, forces associated with thermal stresses will act in and along the plane of the successive planar portions of the second and third passivation layers 24-2, 24-3. This can become particularly problematic as semiconductor device 40 is scaled to larger device sizes suitable for handling higher operating powers in applications such as automotive drivetrains.

[0035] FIG. 2B is a top view illustration of the semiconductor device 40 of FIG. 2A. FIG. 2B is provided to generally illustrate the relative position of edge termination region 14 with respect to active region 12. Active region 12 may include inner region 12' and outer region 12". Inner region 12', sometimes referred to as the device core, may include source contact 32 and gate contact 36 as illustrated in FIG. 1B, and outer region 12" may include gate interconnect 36' and source interconnect 32' as illustrated in FIG. 2A. Edge termination region 14 may include inner region 14' and outer region 14". Outer region 14" is free of passivation layers 24-1 to 24-4 of FIG. 2A, thereby forming a portion of a saw street or scribe street as previously described.

[0036] FIG. 3 is a partial cross-sectional view of a semiconductor device 44 similar to the semiconductor device 40 of FIG. 2A and further including an arrangement of passivation layers 24-1 through 24-4 within the edge termination region 14 to provide enhanced structural stability. Any combination of the passivation layers 24-1 through 24-4 may be referred to as a passivation structure or die seal for the semiconductor device 44. As shown, a top surface of the second passivation layer 24-2 opposite the first passivation layer 24-1 is formed with several protrusions 24-2′ and several corresponding recesses 24-2″ formed between adjacent ones of the plurality of protrusions 24-2′ to form a non-planar or patterned interface with the third passivation layer 24-3. Portions of the third passivation layer 24-3 are formed within the recesses 24-2″ and above the protrusions 24-2′ to cover the second passivation layer 24-2. In this manner, the interface between the second passivation layer 24-2 and the third passivation layer 24-3 is subdivided into a series of contiguous and non-planar segments, which may serve to improve adhesion by decoupling the forces associated with thermal expansion and contraction during power cycling, thereby reducing cracking and delamination. The protrusions 24-2' and recesses 24-2" may alternate in one or more lateral directions in a concave-convex pattern. Because the edge termination region 14 may be provided around the periphery of the active area 12 as shown in FIG. 2B, the protrusions 24-2' and recesses 24-2" may embody a ring of protrusions and recesses that either partially or completely surround the active area 12. For purposes of illustration, protrusions 24-2' and recesses 24-2" are depicted with square profiles; however, protrusions 24-2' and recesses 24-2" may have rounded, curved, and / or angled profiles, and the straight line boundaries may have some irregularity.

[0037] In one embodiment, a patterned layer 46 is provided on the first passivation layer 24-1 to facilitate the formation of protrusions 24-2′ and recesses 24-2″ in the second passivation layer 24-2 in a corresponding pattern. In particular, the discontinuous portions of the patterned layer 46 may be aligned with one or more of the guard rings 20. When the second passivation layer 24-2 is formed over the first passivation layer and the patterned layer 46, portions of the second passivation layer 24-2 may be conformally formed over the patterned layer 46 to form the protrusions 24-2′. In addition, other portions of the second passivation layer 24-2 are conformal over the first passivation layer 24-1 and within the spaces formed between the discontinuous portions of the patterned layer 46 to form the recesses 24-2″. As shown, the patterned layer 46 may be embedded or partially embedded within the second passivation layer 24-2, except for the portions of the patterned layer 46 that are in contact with the first passivation layer 24-1. In this manner, the patterned layer 46 may be embedded within a passivation structure formed by one or more of the passivation layers 24-1 through 24-4. A third passivation layer 24-3 may then be formed on the second passivation layer 24-2 in a manner that fills the recesses 24-2" and covers the protrusions 24-2'. In one embodiment, the relative spacing between adjacent ones of the discontinuous portions of the patterned layer 46 may increase in a direction from the inner edge 14A to the outer edge 14B of the edge termination region 14. In this manner, the relative width of the recesses 24-2" may also increase from the inner edge 14A to the outer edge 14B, such that the recesses 24-2" near the outer edge 14B are wider and filled with more of the third passivation layer 24-3 than the recesses 24-2" near the inner edge 14A. Such a configuration may provide increased structural stability near the outer edge 14B, which may be prone to cracking and delamination.As shown, depending on the width of the recess 24-2', the third passivation layer 24-3 can form a planar upper surface or a planar interface with the fourth passivation layer 24-4, as shown above the portion of the patterned layer 46 closest to the active area 12. The third passivation layer 24-3 can also form a top surface that is conformal to the underlying second passivation layer 24-2, or an interface with the fourth passivation layer 24-4, as shown above the portion of the patterned layer 46 closest to the outer edge 14B. For example, the recess 24-2" closest to the outer edge 14B is wide enough for a portion of the fourth passivation layer 24-4 to extend or protrude downward into the portion of the third passivation layer 24-3 that is conformal to the recess 24-2". In some embodiments, the shape of the top surface of the third passivation layer 24-3 may be further controlled by adjusting the overall thickness of the third passivation layer 24-3, where an increased thickness should generally promote a flatter top surface and a decreased thickness should generally promote a more conformal top surface. In this manner, the pattern of protrusions 24-2' may not extend through the entirety of the passivation structure (e.g., all four passivation layers 24-1 to 24-4 in FIG. 3). Rather, the pattern of protrusions 24-2' may ultimately be smoothed throughout by the overlying passivation layers (e.g., portions 24-3 and 24-4 in FIG. 3), depending on one or more of the spacings of the patterned layer 46 and / or the relative thicknesses of one or more of the overlying passivation layers 24-3, 24-4. In other embodiments, the spacing of the patterned layer 46 and / or the relative thicknesses of one or more of the overlying passivation layers 24-3, 24-4 may be arranged to allow a pattern of protrusions 24-2' to be formed throughout the entire passivation structure (24-1 through 24-4). In yet further embodiments, the pattern of protrusions 24-2' may be smoothed throughout only within certain portions of the semiconductor device 44.For example, the third passivation layer 24-3 is planarized over the portion of the pattern of protrusions 24-2' near the inner edge 14A, while other portions of the third passivation layer 24-3 are conformal near the outer edge 14B in FIG.

[0038] The patterned layer 46 may include any material that is non-reactive with the first and second passivation layers 24-1, 24-2. In some embodiments, the patterned layer 46 includes a material that exhibits improved mechanical stability under thermal stress than the surrounding passivation layers 24-1 to 24-3. For example, the patterned layer 46 may have a greater elastic modulus than any of the passivation layers 24-1 to 24-4 to resist deformation under thermal cycling. In this manner, the patterned layer 46 may also reduce the expansion and contraction of the second passivation layer 24-2. In some embodiments, the patterned layer 46 may include polysilicon, which may be doped n-type or p-type, and in other embodiments, the patterned layer 46 may include polysilicon that is lightly doped or undoped. In one embodiment, the patterned layer 46 can include the same material (e.g., polysilicon) as the gate contact 36, thereby providing the advantage of forming the patterned layer 46 in the same manufacturing step as the gate contact 36. In other embodiments, the patterned layer 46 can include other materials, such as other passivation or dielectric materials, and metal layers. In yet further embodiments, the patterned layer 46 can embody a multi-layer structure, including multiple layers of any of the materials and combinations thereof described above.

[0039] The patterned layer 46 may include a conductive material or a non-conductive material depending on the embodiment. When the patterned layer 46 includes a conductive material, such as a doped polysilicon layer or a metal layer, each discontinuous portion of the patterned layer 46 may be aligned with one of the guard rings 20 as illustrated in FIG. 3. In this manner, the discontinuous portion of the patterned layer 46 may be capacitively coupled to the corresponding guard ring 20 to stabilize the electric field in the semiconductor device 44. In some embodiments, the discontinuous portion of the patterned layer 46 may have a width that is either the same as or smaller than the width of the corresponding guard ring 20 as measured in a direction parallel to the drift region 18. In other embodiments, the discontinuous portion of the patterned layer 46 may have a width that is greater than the width of the corresponding guard ring 20. In still further embodiments, the width of the discontinuous portion of the patterned layer 46 may be smaller, larger, or the same elsewhere as compared to the outer edge 14B of the edge termination region 14. The width of the discontinuous portions of patterned layer 46 compared to the width of the corresponding guard ring 20 may be tailored for the electric field in a particular application. As explained above, guard ring 20 may be formed as a ring around the periphery of active area 12. In one embodiment, the discontinuous portions of patterned layer 46 form a corresponding ring of patterned layer 46 that is also formed around the periphery of active area 12.

[0040] 4 is a partial cross-sectional view of a semiconductor device 48 similar to semiconductor device 44 of FIG. 3, but with individual portions of patterned layer 46 aligned with more than one of the guard rings 20. In FIG. 4, the discontinuous portions of patterned layer 46 are disposed to extend over two separate adjacent guard rings 20. In further embodiments, the discontinuous portions of patterned layer 46 may be disposed to extend over three or more separate guard rings 20 without departing from the principles of the present disclosure. As shown, the spacing between adjacent guard rings 20 may gradually increase in a direction from the inner edge 14A to the outer edge 14B of the edge termination region 14. Thus, the width of each discrete portion of the patterned layer 46 and the corresponding recesses 24-2″ in the second passivation layer 24-2 may also increase in the direction toward the outer edge 14B. As previously described, the patterned layer 46 may comprise a conductive material or a non-conductive material. For a conductive material, the patterned layer 46 may be aligned with multiple guard rings 20 to tailor the electric field. For a non-conductive material, the patterned layer 46 may be provided throughout the portions of the drift region 18 that are between the guard rings 20 with minimal impact on the electric field of the semiconductor device 48. In one embodiment, portions of the patterned layer 46 may be provided as described with respect to FIG. 3 in combination with other portions of the patterned layer 46 as described with respect to FIG. 4 depending on the electric field requirements of a particular application.

[0041] 5 is a partial cross-sectional view of a semiconductor device 50 similar to the semiconductor device 44 of FIG. 3, but without a portion of the patterned layer 46 aligned with at least one guard ring 20 in an overlying arrangement. As shown, the portion of the patterned layer 46 is not aligned with the guard ring 20 disposed closest to the active region 12. In some arrangements, particularly when the patterned layer 46 includes a conductive material, having a portion of the patterned layer 46 disposed too close to the active region 12 may cause insulation weakness or breakdown near the source interconnect 32'. In this regard, the patterned layer 46 may not be disposed directly above one or more of the guard rings 20 disposed closest to the active region 12. In such an arrangement, the recess 24-2" closest to the source interconnect 32' may be wider than the others of the plurality of recesses 24-2", while the widths of the other recesses 24-2" may then gradually increase in a direction toward the outer edge 14B as previously described. Having a wider recess 24-2" closer to the active area 12 can serve to further enhance the mechanical strength of the passivation structure in combination with the other protrusions 24-2' and recesses 24-2". In other embodiments, the patterned layer 46 may not be disposed over the other guard rings 20 providing a different pattern of protrusions 24-2' and recesses 24-2". For example, patterned layer 46 may be provided only over every other guard ring 20 to provide wider recesses 24-2" between protrusions 24-2'. Such an alternating arrangement may also be utilized to provide different electric field patterns for semiconductor device 50. In one embodiment, portions of patterned layer 46 of semiconductor device 50 may also be provided as described above with respect to FIG. 4, depending on the electric field requirements of a particular application.

[0042] FIG. 6 is a partial cross-sectional view of a semiconductor device 52 similar to the semiconductor device 44 of FIG. 3, but with at least one guard ring 20 electrically connected to a portion of the patterned layer 46 that penetrates the first passivation layer 24-1. In FIG. 6, a portion 46' of the patterned layer 46 closest to the active area 12 is electrically connected to the underlying guard ring 20 through an opening formed in the first passivation layer 24-1. In addition, the portion 46' of the patterned layer 46 is electrically connected to the underlying guard ring 20 and extends above the passivation layer 24-1 to form a field plate 54 that is otherwise surrounded by the passivation layers 24-1, 21-2. In other embodiments, the field plate 54 may not be directly electrically connected to the corresponding guard ring 20, such that the first passivation layer 24-1 extends completely between the field plate 54 and the guard ring 20. The dimensions of the resulting field plate 54 may be determined to tailor the electric field profile along the edge termination region 14 for improved efficiency. Because the field plate 54 is aligned with the underlying guard ring 20, the field plate 54 may form a continuous field plate ring or a segmented field plate ring around the active region 12. Depending on the application, one or more of the other portions of the patterned layer 46 may also form field plates or field plate rings that are aligned with corresponding underlying guard rings 20. In further embodiments, one or more of the plurality of field plates 54 may extend above adjacent ones of the plurality of guard rings 20. As illustrated in FIG. 6, no portion of the patterned layer 46 is disposed above the guard ring 20 closest to the active region 12 as described with respect to FIG. 5. In other embodiments, portions of the patterned layer 46 of the semiconductor device 52 may also be disposed as described with respect to FIG. 3 and / or FIG. 4 in combination with FIG. 6 depending on the electric field requirements of a particular application.

[0043] FIG. 7 is a partial cross-sectional view of a semiconductor device 56 similar to semiconductor device 44 of FIG. 3, but with portions of patterned layer 46 aligned with underlying guard ring 20 in a vertically offset manner. As shown, each discontinuous portion of patterned layer 46 is positioned above a corresponding one of the guard rings 20 in an offset manner such that each discontinuous portion of patterned layer 46 also extends above a portion of first passivation layer 24-1 adjacent guard ring 20. The relative position and dimensions of patterned layer 46 may be determined to tailor the electric field profile along edge termination region 14 for improved efficiency in a similar manner as described with respect to field plate 54 of FIG. 6. While all portions of patterned layer 46 are illustrated in an offset manner relative to guard ring 20, other embodiments may include a single portion of offset patterned layer 46, or multiple, but not all, portions of offset patterned layer 46. In this regard, portions of patterned layer 46 may be provided as illustrated in FIG. 7 in combination with any of the arrangements of patterned layer 46 as illustrated in any of FIGS. 3, 4, 5, and 6, depending on the electric field requirements of a particular application.

[0044] The patterned layer 46 of any of the previously described embodiments can form one or more continuous rings or one or more segmented rings around the active area 12. FIG. 8A is a top view of a portion of a semiconductor device 58 in which the patterned layer 46 forms one or more continuous rings around the periphery of the active area 12. FIG. 8B is a top view of a portion of a semiconductor device 60 in which the patterned layer 46 forms one or more segmented rings around the periphery of the active area 12. In both FIGS. 8A and 8B, a portion of the source interconnect 32' can be seen next to the edge termination region 14. The views provided in FIGS. 8A and 8B may be taken anywhere along the periphery edge of the edge termination region 14 as illustrated in FIG. 2B. For purposes of illustration, the second, third, and fourth passivation layers 24-2 through 24-4 are omitted to show the arrangement of the patterned layer 46. Additionally, although FIGS. 8A and 8B depict four rings to illustrate the principles of the present disclosure, patterned layer 46 can form any number of rings, including one or more, or five or more, or ten or more, or twenty or more, or in the range of 1 to 20, or in the range of 5 to 20, or in the range of 10 to 20, depending on the application.

[0045] As illustrated in FIG. 8A, the patterned layer 46 forms a series of separated rings, each of which is continuous within the edge termination region 14. As previously described, each of the rings of the patterned layer 46 can form a corresponding protrusion in the overlying passivation layer, and the space between each of the rings of the patterned layer 46 can form a corresponding recess in the overlying passivation layer for improved mechanical stability under thermal stress. In this regard, the protrusions corresponding to each of the rings of the patterned layer 46 can also form a continuous ring protrusion around the active region 12. Thus, the edge termination region 14 is provided with alternating protrusions and recesses in a direction from the inner edge 14A toward the outer edge 14B.

[0046] As illustrated in FIG. 8B, patterned layer 46 forms a series of ring segments that extend through edge termination region 14 and around active area 12. Rather than forming a continuous ring as illustrated in FIG. 8A, patterned layer 46 forms discontinuous or segmented rings within edge termination region 14 and around active area 12. In this manner, edge termination region 14 is provided with alternating protrusions and recesses in at least two directions, e.g., a first direction from inner edge 14A to outer edge 14B and a second direction perpendicular to the first direction. As further illustrated in FIG. 8B, the relative positions of the ring segments within each segmented ring of patterned layer 46 are laterally offset from the relative positions of the ring segments within adjacent segmented rings in a direction toward outer edge 14B to further enhance mechanical stability under thermal stress.

[0047] FIG. 9 is a partial cross-sectional view of a semiconductor device 62 similar to semiconductor device 44 of FIG. 3, but with patterned layer 46 forming a ring around the periphery of first passivation layer 24-1. In FIG. 9, gate contact 36 and a portion of gate oxide layer 34 are seen in active region 12. In edge termination region 14, patterned layer 46 is provided on the top surface of first passivation layer 24-1 and along the sidewalls of first passivation layer 24-1 that are disposed closest to outer edge 14B of edge termination region 14. In this manner, patterned layer 46 may extend past and overlap first passivation layer 24-1. In some embodiments, the overlapped portion of patterned layer 46 may be in direct contact with drift region 18 and / or surface charge compensation region 42 of drift region 18, when present. In other embodiments, the overlapped portion of patterned layer 46 may be separated from drift region 18 by insulating layer 64. The insulating layer 64 may comprise the same material formed in the same manufacturing step as the gate oxide layer 34, or the insulating layer 64 may comprise a different material than the gate oxide layer 34. By providing the patterned layer 46 in an overlapping manner with respect to the first passivation layer 24-1, the corresponding protrusion 24-2' of the second passivation layer 24-2 may be provided closer to the outer edge 14B for embodiments where thermal stresses may be greater at this location. In some embodiments, the patterned layer 46 of FIG. 9 may be provided in combination with any of the arrangements of the patterned layer 46 as illustrated in any of FIGs. 3, 4, 5, 6, and 7, depending on the electric field requirements of a particular application. In addition, the patterned layer 46 as illustrated in FIG. 9 may form continuous or discontinuous rings as illustrated in FIGs. 8A and 8B.

[0048] While the present disclosure provides exemplary embodiments including MOSFETs, the principles of the present disclosure are also applicable to other semiconductor devices, such as diodes, Schottky diodes, JBS diodes, PiN diodes, and edge termination structures for IGBTs, among others. The semiconductor devices of the present disclosure can embody wide bandgap semiconductor devices, such as SiC-based devices.

[0049] It is contemplated that any of the above aspects, and / or various separate aspects and features as described herein may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments, unless otherwise indicated herein.

[0050] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are believed to be within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A drift region; an active region including a portion of the drift region; an edge termination region disposed within the drift region and along a periphery of the active region; a passivation structure on the edge termination region, the passivation structure comprising: a first passivation layer on the drift region, a second passivation layer on the first passivation layer, a third passivation layer on the second passivation layer, and a fourth passivation layer on the third passivation layer; a patterned layer formed within the passivation structure; and A semiconductor device comprising:

2. 2. The semiconductor device of claim 1, wherein the patterned layer is disposed between the first passivation layer and the second passivation layer, the second passivation layer forming at least one protrusion aligned with at least one portion of the patterned layer and extending into the third passivation layer.

3. The semiconductor device of claim 2, wherein the at least one protrusion of the second passivation layer extends into the third passivation layer, the at least one protrusion includes multiple protrusions, and an upper surface of the third passivation layer is flat in at least some portions of the passivation structure.

4. the edge termination region further comprising a plurality of guard rings within the drift region; 3. The semiconductor device of claim 2, wherein the at least one portion of the patterned layer is aligned with an individual guard ring of the plurality of guard rings.

5. The semiconductor device of claim 4, wherein at least one guard ring of the plurality of guard rings does not have a portion of the patterned layer aligned with the at least one guard ring in an overlying arrangement.

6. The semiconductor device of claim 4, wherein the patterned layer is disposed on the first passivation layer, and the patterned layer further extends through an outer sidewall of the first passivation layer in a direction toward an outer edge of the edge termination region.

7. The semiconductor device of claim 1, wherein the interface between the third passivation layer and the fourth passivation layer is conformal to the second passivation layer above a portion of the patterned layer closest to an outer edge of the semiconductor device.

8. The semiconductor device of claim 1, wherein the patterned layer has a higher modulus of elasticity than any of the first through fourth passivation layers.

9. The semiconductor device of claim 4, wherein the drift region has a first conductivity type, and the edge termination region further comprises a surface charge compensation region of a second conductivity type formed on an upper surface of the drift region between the guard rings.

10. The semiconductor device of claim 9, wherein the thickness of the surface charge compensation region is less than or equal to the thickness of the guard ring.

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