Semiconductor device, system, and equipment

Abstract

To improve accuracy of AD conversion of a semiconductor device.SOLUTION: A semiconductor device includes: a voltage generator for generating a voltage; a first AD converter for converting an analog value based on a voltage generated by the voltage generator into a first digital value; and a second AD converter for converting an analog value based on the voltage generated by the voltage generator into a second digital value. The voltage generator generates a voltage by dividing a power supply voltage by a resistor element.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a system and device using the same. [Background technology]

[0002] Signal processing such as amplification and AD conversion is performed in various semiconductor devices. In order to achieve a wide dynamic range, some solid-state imaging devices (semiconductor devices) apply multiple gains to a single pixel signal generated by a pixel. The pixel signal amplified by the amplifier circuit is converted into a digital signal by an AD converter, and the digital signal is debugged according to the gain applied by the amplifier circuit, expanding the dynamic range of the solid-state imaging device.

[0003] Patent Document 1 describes a means for acquiring a correction value for correcting a gain error that an amplifier circuit that amplifies a pixel signal has. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-79464 A Summary of the Invention [Problem to be solved by the invention]

[0005] In order to obtain a more accurate correction value, technology is needed to reduce the effects of individual variations in AD conversion gain caused by manufacturing variability and fluctuations in AD conversion values ​​caused by fluctuations in the power supply voltage.

[0006] The present invention has been made in consideration of the above problems, and has an object to provide a technique that is advantageous in improving the accuracy of AD conversion. [Means for solving the problem]

[0007] The first aspect of the present invention is A voltage generating unit that generates a voltage; a first AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a first digital value; a second AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a second digital value; A signal generating unit that generates a signal in response to an external input; a third AD converter that converts an analog value based on the signal into a third digital value; a signal processing circuit that corrects the third digital value in accordance with a ratio between the first digital value and the second digital value; having The semiconductor device is characterized in that A second aspect of the present invention is A voltage generating unit that generates a voltage; a first AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a first digital value; a second AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a second digital value; a first amplifier that amplifies the voltage generated by the voltage generating unit to a first analog value with a first gain; a second amplifier that amplifies the voltage generated by the voltage generating unit to a second analog value with a second gain; having The first AD converter comprises: Amplified by the first amplifier converting the first analog value to the first digital value; The second AD converter comprises: Amplified by the second amplifier converting the second analog value to the second digital value; A plurality of resistance elements are connected in series between a power supply voltage node and a ground voltage node; The voltage generating unit generates a power supply voltage The above A voltage is generated by dividing the voltage using multiple resistor elements. an input node of the first amplifier is electrically connected between a power supply voltage node and one of the plurality of resistive elements; The input node of the second amplifier is The aboveelectrically connected between a ground voltage node and the one resistive element; The semiconductor device is characterized in that

[0008] The present invention three The embodiment of the present invention is as follows: A signal generating unit that generates a signal in response to an external input; A voltage generating unit that generates a voltage; a first AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a first digital value; a second AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a second digital value; a third AD converter that converts an analog value based on the signal generated by the signal generating unit into a third digital value; having the third digital value is corrected according to a ratio between the first digital value and the second digital value. It is a system. Effect of the Invention

[0009] According to the present invention, it is possible to provide a technique that is advantageous in improving the accuracy of AD conversion. [Brief description of the drawings]

[0010] [Figure 1] 1 is a circuit diagram of a semiconductor device according to a first embodiment; [Diagram 2] 1 is a circuit diagram of a unit pixel according to a first embodiment; [Diagram 3] 1 is a circuit diagram of a correction value output circuit according to a first embodiment; [Figure 4] 1 is a circuit diagram of a semiconductor device according to a modification of the first embodiment; [Diagram 5] 1 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention; [Figure 6] 11 is a circuit diagram of a correction value output circuit according to a second embodiment of the present invention; [Figure 7] 1 is a circuit diagram of a semiconductor device according to a modification of the second embodiment; [Figure 8]FIG. 13 is a block diagram showing the configuration of an imaging system according to a third embodiment. [Figure 9] FIG. 13 is a diagram showing a configuration of an imaging system and a transportation device according to a fourth embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] <First embodiment> FIG. 1 is a circuit diagram of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 is a photoelectric conversion device such as a CMOS area sensor, and includes a signal generating unit 102 in which unit pixels 101 are arranged in a two-dimensional matrix. The signal generating unit 102 can also be called a pixel unit or a pixel array. The photoelectric conversion device can be used in an imaging device, a distance measuring device, a photometry device, and the like, and an imaging device will be described as an example of the semiconductor device 100. The semiconductor device to which this embodiment can be applied is not limited to an imaging device, and can be applied to various signal processing devices such as an audio device, a display device, and a measurement device. The signal generating unit 102 generates a signal according to an input from the outside, and in this embodiment, generates a signal according to incident light from the outside. The semiconductor device 100 also includes a vertical scanning circuit 103, a vertical output line 104, a comparator 105, a reference signal generating circuit 106, a counter circuit 107, a memory unit 108, a horizontal scanning circuit 109, a signal processing circuit 110, and a correction value output circuit 111. Furthermore, inside the correction value output circuit 111, a voltage generating unit 112 is disposed.

[0012] 2, the configuration of the unit pixel 101 will be described. The unit pixel 101 includes a photodiode 201, a transfer gate 202, a floating diffusion section 203, a floating diffusion amplifier 204, a reset switch 205, and a pixel selection switch 206. The unit pixel 101 outputs a pixel value (pixel output), which is an analog value corresponding to incident light on the photodiode 201, as a pixel signal.

[0013] A photodiode (hereinafter referred to as PD) 201 photoelectrically converts an incident light signal and accumulates a charge according to the amount of exposure. When a signal tx is set to a high level, a transfer gate 202 transfers the charge accumulated in the PD 201 to a floating diffusion (hereinafter referred to as FD) section 203. The FD section 203 is connected to the gate of a floating diffusion amplifier 204 (hereinafter referred to as FD amplifier). The FD amplifier 204 converts the amount of charge transferred from the PD 201 into a voltage amount. A reset switch 205 is a switch for resetting the FD section 203, and the FD section 203 is reset to a reset voltage Vres by setting a signal res to a high level. Furthermore, when resetting the charge of the PD 201, the signals res and tx are simultaneously set to a high level. As a result, both the transfer gate 202 and the FD reset switch 205 are turned on, and the PD 201 is reset to the reset voltage Vres via the FD section 203. A pixel selection switch 206 is connected to a gate of a floating diffusion amplifier 204 (hereinafter referred to as FD amplifier). When sel goes to high level, the pixel value Vout converted into a voltage by the FD amplifier 204 is output as a pixel signal.

[0014] 1, the vertical scanning circuit 103 supplies drive signals such as res, tx, and sel that control the switches of the unit pixels 101 to each unit pixel 101. These drive signals are common to each row.

[0015] The pixel output Vout is connected to a comparator 105 via a vertical output line 104 for each column. The comparator 105 arranged for each column receives the output Vout and a reference signal of a ramp waveform generated and supplied by a reference signal generating circuit 106. The comparator 105 includes a differential input comparator, compares the magnitude of the voltage of the output Vout with that of the reference signal, and transitions the output from a high level to a low level or from a low level to a high level when the magnitude relationship of the signal voltages is inverted. The reference signal generating circuit 106 is commonly connected to the multiple comparators 105. The counter circuit 107 is commonly connected to multiple storage units 108, performs a counting operation in accordance with the output of the reference signal from the reference signal generating circuit 106, and outputs a count value. The storage unit 108 stores the count value output from the counter circuit 107 as digital data at the timing when the output voltage of the corresponding comparator 105 is inverted. That is, the comparator 105, the reference signal generating circuit 106, the counter circuit 107, and the storage unit 108 constitute an AD converter (third AD converter) that converts the analog pixel output Vout into a digital value.

[0016] The digital data stored in the storage unit 108 is sequentially transferred by a horizontal scanning circuit 109 to a signal processing circuit 110 for each column.

[0017] A series of operations relating to reading out pixel values ​​from these pixels is performed while the vertical scanning circuit 103 selects pixel rows in the signal generating unit 102. Note that pulses required for each circuit and a timing generator that controls their timing are omitted in Figures 1 and 2.

[0018] The configuration of the correction value output circuit 111 will be described with reference to Fig. 3. The correction value output circuit 111 includes a voltage generating section 112, comparators 303a and 303b, and storage sections 304a and 304b.

[0019] The voltage generating unit 112 generates a predetermined voltage used as a reference voltage. The voltage generating unit 112 is configured to generate a reference voltage only by passive elements, i.e., without using any active elements. That is, the voltage generating unit 112 does not need to include any active elements. The voltage generating unit 112 can be configured only by passive elements such as resistive elements and capacitive elements. The reason why the voltage generating unit 112 is configured only by passive elements is that active elements have smaller variations in characteristics than passive elements. The voltage generating unit 112 generates and outputs reference voltages Vvola and Vvolb of analog values ​​by dividing the power supply voltage with resistive elements. The voltage generating unit 112 includes, for example, resistive elements Rl, R2, and R3 having resistance values ​​r1, r2, and r3, respectively, voltage followers 301a and 301b having a gain of 1, and switches 302a and 302b. The voltage generating unit 112 is supplied with a power supply voltage Vdd from a voltage source. The voltage source of the voltage generating unit 112 is different from the voltage source of the signal generating unit 102. The power supply voltage Vdd is divided by the resistors Rl, R2, and R3 in a ratio of rl:r2:r3, and a voltage Vvola expressed by equation (1) is input to the voltage follower 301a, and a voltage Vvolb expressed by equation (2) is input to the voltage follower 301b. The voltages Vvola and Vvolb correspond to the voltages generated by the voltage generating unit 112 (the first voltage and the second voltage). Vvola=(r2+r3) / (rl+r2+r3)×Vdd...(1) Vvolb=r3 / (rl+r2+r3)×Vdd (2)

[0020] That is, the voltage input to the voltage followers 301a and 301b is determined by the ratio of the resistors Rl, R2, and R3. In general, the amount of variation in resistance value due to manufacturing variations is equal between adjacent resistive elements, so even if the resistance value itself varies, the resistance values ​​rl, r2, and r3 do not vary, and an approximately constant voltage value is always input to the voltage followers 301a and 301b. The voltage followers 301a and 301b have high input impedance and output a voltage value equal to the input voltage value expressed by equations (1) and (2).

[0021] The switches 302a and 302b are switches that determine whether or not the outputs of the voltage followers 301a and 301b are connected to the subsequent stages. The switches 302a and 302b are controlled to be turned on or off at any timing by a pulse signal from a timing generator (not shown).

[0022] The output sections of the voltage followers 301a and 301b are connected to the comparators 303a and 303b via the switches 302a and 302b. The comparators 303a and 303b and the storage sections 304a and 304b have the same configuration as the comparator 105 and the storage section 108 described in FIG. 1. The analog values ​​output from the voltage followers 301a and 302b are stored as digital data in the storage sections 304a and 304b. That is, the comparator 303a, the reference signal generating circuit 106, the counter circuit 107, and the storage section 304a form a first AD converter. The comparator 303b, the reference signal generating circuit 106, the counter circuit 107, and the storage section 304b form a second AD converter. The first AD converter converts a first analog value (Vvola) based on a first voltage into a first digital value. The second AD converter converts a second analog value (Vvolb) based on the second voltage into a second digital value.

[0023] As shown in FIG. 3, the data stored in the storage unit 304a is Vsiga, and the data stored in the storage unit 304b is Vsigb. As described above, the comparator 105 inverts its own output potential when the magnitude relationship between the voltage of the input signal to the comparator and the reference signal of the ramp waveform generated by the reference signal generating circuit 106 is inverted. The storage unit 108 stores the count value at the time of inversion of the output potential of the comparator 105 as digital data. Therefore, if the voltage change amount per unit time of the ramp waveform is not constant, the stored digital value may vary with respect to the input analog value. In particular, the ramp waveform generated by the reference signal generating circuit 106 may have individual differences in the slope of the waveform due to manufacturing variations. As a result, differences occur in the digital values ​​stored for each individual with respect to the input analog value. This difference is called AD gain error.

[0024] The correction value output circuit 111 is configured to be capable of outputting a correction value for correcting an AD gain error for each individual with high accuracy. A method for calculating the correction value for correcting an AD gain error will be described below.

[0025] Vsiga stored in the storage unit 304a is expressed by equation (3) using Vvola of equation (1) and an AD gain error a that occurs when Vvola is AD converted. Vsiga = Vvola × (AD gain error a) (3)

[0026] On the other hand, Vsigb stored in the storage unit 304b is expressed by equation (4) using Vvolb of equation (2) and an AD gain error b that occurs when Vvolb is AD converted. Vsigb = Vvolb × (AD gain error b) (4)

[0027] Here, Vvola and Vvolb are known values ​​determined by the ratio of the resistance elements in the voltage generating unit 112 and the power supply voltage. Therefore, from equations (3) and (4), two digital values ​​Vsiga and Vsigb including the AD gain error for two known analog input values ​​can be obtained. The slope of the ramp waveform can be calculated from Vsiga and Vsigb, and the AD gain error for each individual can be corrected using the value of the slope.

[0028] In reality, in addition to the AD gain error described above, the fluctuation of the digital value due to the voltage fluctuation during AD conversion may also cause an error in the digital value output by the AD converter. Even in the same individual, when the comparator 105, the reference signal generating circuit 106, the counter circuit 107, and the memory unit 108 are subjected to fluctuations in the power supply voltage, the inversion potential, the reference signal, the count value, and the digital data output by these may fluctuate. The fluctuation of the digital data is called an AD conversion error. The AD conversion error varies depending on the time when the analog value is converted into a digital value. In other words, the same AD conversion error is superimposed on the digital values ​​that are AD converted at the same time. In order to cancel or reduce the influence of the AD conversion error superimposed on Vsiga and Vsigb, the correction value output circuit 111 operates the first AD converter and the second AD converter at the same time and performs AD conversion at the same timing. When the influence of the AD conversion error is taken into account, the above-mentioned formulas (3) and (4) are expressed as follows. Vsiga = Vvola × (AD gain error a) × (AD conversion error) (5) Vsigb = Vvolb × (AD gain error b) × (AD conversion error) (6)

[0029] Furthermore, by taking the ratio of equation (5) to equation (6), the (AD conversion error) term is cancelled out, and equation (7) is obtained. Vsiga / Vsigb= (Vvola × (AD gain error a)) / (Vvolb × (AD gain error b)) (7)

[0030] The semiconductor device 100 outputs a digital value (third digital value) obtained by AD converting an analog value output from a pixel, and a ratio between Vsiga (first digital value) and Vsigb (second digital value). Acquisition and output of Vsiga and Vsigb may be performed at any timing. For example, acquisition of Vsiga and Vsigb may be performed each time the signal generating unit 102 reads out pixel signals for one line, each time the signal generating unit 102 reads out pixel signals for all lines, or when the power is turned on or when an instruction is received from the user.

[0031] By outputting the ratio of Vsiga to Vsigb in this way, the downstream circuit can correct the digital pixel signal based on the ratio of Vsiga to Vsigb. Specifically, the AD gain error can be corrected from the ratio of Vsiga to Vsigb (actual measurement value) and its set value (ratio of Vvola to Vvolb). According to this embodiment, it is possible to cancel out or reduce the influence of the AD conversion error and accurately correct the AD gain error for each individual.

[0032] Instead of outputting the ratio between Vsiga and Vsigb, the semiconductor device 100 may output Vsiga and Vsigb, respectively, or may output a signal of another value calculated based on Vsiga and Vsigb. Also, the AD gain error may be corrected by the signal processing circuit 110 in the semiconductor device 100.

[0033] The above configuration described with reference to FIG. 1 and the like is merely one example of the embodiment of the present invention, and the technical scope should not be interpreted as being limited by the above specific example. For example, the semiconductor device 100 may be configured to include a laminated substrate including a first substrate and a second substrate. A signal generating section 102 consisting of unit pixels 101 is disposed on the first substrate. The second substrate may include a comparator 105, a reference signal generating circuit 106, a counter circuit 107, a memory section 108, a horizontal scanning circuit 109, a signal processing circuit 110, a correction value output circuit 111, and a vertical output line 104 for connecting the first substrate and the second substrate. By forming the first substrate and the second substrate into a laminated structure, it is possible to obtain effects such as speeding up the processing of signals output by the unit pixels 101 and saving space.

[0034] <Modification of the first embodiment> A modified example of the semiconductor device 100 will be described with reference to Fig. 4. In the following, the semiconductor device 400 according to this modified example will be mainly described with respect to differences from the semiconductor device 100 according to the first embodiment, and a description of common parts will be omitted.

[0035] The correction value output circuit 401 of the semiconductor device 400 is similar to that of the first embodiment in that it has the voltage generating unit 112, but has only one comparator 405a and one storage unit 408a. A pair of a comparator 405b and a storage unit 408b used for AD conversion and storage of a pixel signal (pixel value) is also used for outputting a correction value. The comparators 405a and 405b have the same configuration as the comparator 105, and the storage units 408a and 408b have the same configuration as the storage unit 108. The semiconductor device 400 includes a switch 402 for selectively connecting the voltage generating unit 112 or the signal generating unit 102 to the comparator 405b. The voltage Vola may be input to the comparator 405a, and the voltage Vvolb may be input to the comparator 405b, or vice versa.

[0036] In this manner, in this modification, Vvola or Vvolb output from the voltage generating unit 112 is input via the switch 402 to the comparator and storage unit that are normally used for AD conversion of the pixel signal from the signal generating unit 102. The method of correcting the AD gain error for each individual is the same as the method described in the first embodiment. This makes it possible to reduce the space required for the semiconductor device.

[0037] The comparator 405b, the reference signal generating circuit 106, the counter circuit 107, and the memory unit 405b can be regarded as an AD converter (third AD converter) that converts the pixel signal, or as an AD converter (first AD converter or second AD converter) that converts the output signal of the voltage generating unit 112.

[0038] Here, a modified example has been described in which one of the output signals from the voltage generating unit 112 is input to the comparator 105 and the storage unit 108 used for AD conversion of the pixel signal from the signal generating unit 102. That is, an example has been described in which only one of the first converter and the second converter also operates as the third converter. However, both the first converter and the second converter may also operate as the third converter. In this case, the semiconductor device 100 is configured to have a first switch that selectively connects either the voltage Vvola or the pixel output Vout to the first converter, and a second switch that selectively connects either the voltage Vvolb or the pixel output Vout to the second converter. Specifically, compared to the configuration of FIG. 4, the semiconductor device 400 further includes one more switch, and the two output signals from the voltage generating unit 112 are input to the comparator 105 and the storage unit 108 used for AD conversion of the pixel signal from the signal generating unit 102.

[0039] Second Embodiment The semiconductor device of this embodiment will be described focusing on the differences from the first embodiment.

[0040] 5 is a circuit diagram of a semiconductor device 500 according to this embodiment. In the semiconductor device 500, a column amplifier 501 (third amplifier) ​​is connected to the vertical output line 104 of each column. The gain of the column amplifier 501 is variable, and the semiconductor device 500 switches the gain of the column amplifier 501 depending on the level of the pixel output Vout output to the vertical output line 104.

[0041] For example, when the level of the pixel output Vout is low, the column amplifier 501 applies a gain of 8 times to amplify the signal and perform AD conversion with high resolution. On the other hand, when the level of the pixel output Vout is high, the column amplifier 501 does not apply a gain and performs AD conversion with low resolution. Note that since the column amplifier 501 does not apply a gain to the high-level pixel output Vout, the obtained AD conversion value is 1 / 8 of the AD conversion value of the low-level pixel output. Therefore, after AD conversion, the signal processing circuit 110 applies a digital gain of 8 times to the high-level pixel output Vout. In this way, the semiconductor device 500 can acquire pixel output values ​​from low levels to high levels in a wide dynamic range.

[0042] The comparator 105 compares the pixel output Vout input via the column amplifier 501 with a predetermined threshold voltage Vsh, and sets the gain of the column amplifier 501 based on the comparison result. Thereafter, the comparator 105 compares the output Vamp of the column amplifier 501 with a reference signal from a reference signal generating circuit 106, and stores the digital data in the storage unit 108, which is the same as the first embodiment. However, in this embodiment, the comparator 105 compares the pixel output Vout with a predetermined threshold voltage Vsh, and also stores gain information of the column amplifier 501 set based on the comparison result in the storage unit 108. The signal processing circuit 110 performs digital gain processing on the AD converted signal based on the gain information.

[0043] As described above, the semiconductor device 500 of this embodiment obtains a wide dynamic range by combining the analog gain of the column amplifier 501 and the digital gain in the signal processing circuit 110. In the above example, depending on the level of the pixel output Vout, an 8x analog gain is applied in the column amplifier, and an 8x digital gain is applied in the signal processing circuit.

[0044] In this way, when the column amplifier 501 does not apply a gain, the signal processing circuit 110 applies a digital gain equivalent to the analog gain value of the column amplifier 501. The digital gain value of the signal processing circuit 110 is set to the same value as the set value of the analog gain value of the column amplifier 501, but the actual gain value of the column amplifier 501 may deviate from the set value. This is because the analog gain value of the column amplifier may vary from one to another due to manufacturing variations, and may also vary depending on the temperature during operation. Unless the digital gain is processed based on an accurate analog gain value, the linearity of the output value output from the semiconductor device 500 cannot be maintained. Therefore, when applying a digital gain in the signal processing circuit 110, it is necessary to obtain an accurate analog gain value of the column amplifier 501 for each individual and each temperature and use it for signal processing.

[0045] In this embodiment, a correction value output circuit 502 is used to determine an accurate analog gain value of the column amplifier for each individual device and for each temperature.

[0046] First, the configuration of the correction value output circuit 502 will be described with reference to Fig. 6. The correction value output circuit 502 includes a voltage generating section 503, a voltage follower 603, an amplifier 604, comparators 605a and 605b, and storage sections 606a and 606b.

[0047] The voltage generating unit 503 is configured to generate a reference voltage using only passive elements, i.e., without using any active elements. The voltage generating unit 503 generates and outputs a reference voltage Vvol of an analog value by dividing a power supply voltage using a resistive element. The voltage generating unit 503 includes, for example, resistive elements R4 and R5 having resistance values ​​r4 and r5, a voltage regulator having a gain of 1, and a resistor R4 having a resistance value r5. The power supply voltage Vdd is divided by resistors R4 and R5 in a ratio of r4:r5, and the voltage follower 601 is supplied with a voltage expressed by the formula (8). The voltage Vvol corresponds to the voltage generated by the voltage generating unit 503. Vvol = r5 / (r4 + r5) × Vdd (8)

[0048] That is, the voltage input to the voltage follower 601 is determined by the ratio of resistors R4 and R5. Generally, the amount of variation in resistance value due to manufacturing variations is equal between adjacent resistive elements, so even if the resistance value itself varies, the ratio of resistance values ​​r4 and r5 in the voltage generating unit 503 does not vary, and a substantially constant voltage value is always input to the voltage follower 601. The voltage follower 601 has a high input impedance and outputs a voltage value equal to the input voltage value expressed by equation (8).

[0049] The switch 602 is a switch that determines whether or not to connect the output of the voltage follower 601 to a subsequent stage. The switch 602 is controlled to be turned on or off at any timing by a pulse signal from a timing generator (not shown).

[0050] The output of the voltage follower 601 is connected to a voltage follower 603 (first amplifier) ​​and an amplifier 604 (second amplifier) ​​via a switch 602. The voltage follower 603 has a high input impedance like the voltage follower 601, and outputs a voltage equal to the input voltage. The voltage follower 603 can also be regarded as an amplifier with a fixed gain of 1. The amplifier 604 has the same configuration as the column amplifier 501 arranged in the semiconductor device 500, and is an amplifier with a variable gain. The amplifier 604 is configured to include, for example, a plurality of capacitors C1 to C3 and a plurality of switches SW1 to SW3, and the switches SW By operating SW1 through SW3, the amplifier can be reset to the initial state or the gain of the amplifier can be changed. Note that the number of capacitances and switches shown in Figure 6 is an example.

[0051] The outputs of the voltage follower 603 and the amplifier 604 are connected to the comparators 605a and 605b. The comparators 605a and 605b and the storage units 606a and 606b have the same configuration as the comparator 105 and the storage unit 108 described in FIG. 1. The analog values ​​output from the voltage follower 603 and the amplifier 604 are stored as digital data in the storage units 606a and 606b. That is, the comparator 605a, the reference signal generating circuit 106, the counter circuit 107, and the storage unit 606a form a first AD converter. The comparator 605b, the reference signal generating circuit 106, the counter circuit 107, and the storage unit 606b form a second AD converter.

[0052] The voltage follower 603 corresponds to a first amplifier that amplifies Vvol (first voltage) generated by the voltage generating unit 503 to a first analog value with a first gain. The column amplifier 604 corresponds to a second amplifier that amplifies Vvol (first voltage) generated by the voltage generating unit 503 to a second analog value with a second gain. The first AD converter converts the first analog value to a first digital value. The second AD converter converts the second analog value to a second digital value.

[0053] As shown in FIG. 6, the data stored in the memory unit 606a is Vref, and the data stored in the memory unit 606b is Vsig. Vref corresponds to a first digital value, and Vsig corresponds to a second digital value. As described above, the analog gain value of the column amplifier 501 may vary from one individual to another due to manufacturing variations, and also varies depending on the temperature during operation. The correction value output circuit 502 is configured to be able to output a correction value for correcting analog gain error for each individual and for each temperature with high accuracy. The correction of analog gain error will be described below. A method for calculating a correction value for is described below.

[0054] Vref stored in the storage unit 606a is expressed by the formula (9). Vref = Vvol × Gvf × (AD gain error) × (AD conversion error) (9) Here, Vvol is defined by equation (8), and Gvf is the gain setting value of the voltage follower 603. Also, the "AD gain error" is an AD gain error that occurs when the output value of the voltage follower 603 is AD converted, and the "AD conversion error" is a fluctuation in digital data due to a voltage fluctuation during AD conversion.

[0055] On the other hand, Vsig stored in the storage unit 606b is expressed by the equation (10). Vsig = Vvol × Gamp × (analog gain error) × (AD gain error) × (AD conversion error) (10) Here, Gamp is the gain setting value of the amplifier 604, and “analog gain error” is the analog gain error that the amplifier 604 has.

[0056] Vvol is a known value determined by the power supply voltage and the ratio of the resistance elements in the voltage generating unit 503. In addition, since the gain of the voltage follower 603 is fixed to 1, the gain setting value Gvf of the voltage follower 603 is 1.

[0057] By taking the ratio of equation (9) to equation (10), the (AD gain error) term and the (AD conversion error) term are cancelled out, and equation (11) is obtained. Vsig / Vref=Gamp × (analog gain error) (11)

[0058] The semiconductor device 500 outputs a digital value (third digital value) obtained by AD converting an analog value output from a pixel, and a ratio between Vsig (first digital value) and Vref (second digital value). The correction value output circuit 502 obtains and outputs the ratio between Vsig and Vref for each gain setting value of the amplifier 604.

[0059] By outputting the ratio between Vsig and Vref in this way, the downstream circuit can correct the digital pixel signal based on the ratio between Vref and Vsig. Specifically, the analog gain error can be corrected from the ratio of Vsig / Vref (actual measurement value) and its set value (Gamp). At this time, the AD gain error is also corrected. In this way, it is possible to obtain an analog gain error for correcting the analog gain after offsetting or reducing the influence of the AD gain error and the AD conversion error. Therefore, according to this embodiment, it is possible to correct the analog gain error for each individual and for each temperature using the value of the analog gain error.

[0060] Instead of outputting the ratio between Vref and Vsig, the semiconductor device 500 may output Vref and Vsig, respectively, or may output a signal of another value calculated based on Vref and Vsig. Correction of analog gain error may be performed by the signal processing circuit 110 in the semiconductor device 500.

[0061] 6, like FIG. 1, merely shows an example of a specific embodiment for carrying out the present invention, and the technical scope should not be interpreted as being limited by FIG.

[0062] <Modification of the second embodiment> A modified example of the semiconductor device 500 will be described with reference to Fig. 7. In the following, the semiconductor device 700 according to this modified example will be mainly described with respect to differences from the semiconductor device 500 according to the second embodiment, and a description of common parts will be omitted.

[0063] The semiconductor device 700 includes a correction value output circuit 701 and a switch 702. The correction value output circuit 701 is the same as the correction value output circuit 502 in that it includes a voltage generating unit 503, a voltage follower 603, a comparator 605a, and a storage unit 606a, but does not include an amplifier 604, a comparator 605b, or a storage unit 606b. A set of an amplifier 704, a comparator 705, and a storage unit 708 used for amplifying, AD converting, and storing pixel signals is shared for outputting correction values. The amplifier 704, the comparator 705, and the storage unit 708 have the same configuration as the column amplifier 501, the comparator 105, and the storage unit 108, respectively. The switch 702 selectively connects the amplifier 704 to either the voltage generating unit 112 or the signal generating unit 102.

[0064] In this manner, in this modification, Vvol output from the voltage generating unit 503 is input via the switch 702 to the column amplifier 501, the comparator 105, and the storage unit 108, which are normally used for AD conversion of pixel signals from the signal generating unit 102. The method of correcting analog gain error for each individual is the same as the method described in the second embodiment. This makes it possible to reduce the space required for the semiconductor device.

[0065] <Third embodiment> Fig. 8 is a block diagram showing a configuration of an imaging system 800 according to this embodiment. The imaging system 800 of this embodiment includes a semiconductor device 801 (imaging device) to which any of the configurations of the semiconductor devices described in the above embodiments is applied. Specific examples of the imaging system 800 include a digital still camera, a digital camcorder, and a surveillance camera. Fig. 8 shows a configuration example of a digital still camera to which any of the semiconductor devices according to the above embodiments is applied.

[0066] 8 includes a semiconductor device 801, a lens 802 that forms an optical image of a subject on the semiconductor device 801, and an aperture 803 that varies the amount of light passing through the lens 802. The lens 802 and the aperture 803 form an optical system that focuses light on the semiconductor device 801.

[0067] The imaging system 800 also has a signal processing unit 804 that processes an output signal output from the semiconductor device 801. The signal processing unit 804 performs a signal processing operation such as performing various corrections and compression on an input signal as necessary and outputting the signal.

[0068] The imaging system 800 further includes a buffer memory unit 805 for temporarily storing image data, and an external interface unit (hereinafter referred to as an external I / F unit) 806 for communicating with an external computer or the like. The imaging system 800 further includes a recording medium 807 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (hereinafter referred to as a recording medium control I / F unit) 808 for recording or reading out data on the recording medium 807. The recording medium 807 may be built into the imaging system 800, or may be removable.

[0069] The imaging system 800 includes an overall control and calculation unit 809 that performs various calculations and controls the entire digital still camera, and a timing generation unit 810 that outputs various timing signals to the semiconductor device 801 and the signal processing unit 804. Here, the timing signals may be input from outside, and the imaging system 800 includes at least the semiconductor device 801 and the semiconductor device 804. and a signal processing unit 804 that processes an output signal output from the output terminal 806. The overall control / calculation unit 809 and the timing generation unit 810 may be configured to implement a part or all of the control functions of the semiconductor device 801.

[0070] The semiconductor device 801 outputs the image signal and AD gain error information or analog gain error information from a correction value output circuit provided inside the semiconductor device 801 to the signal processing unit 804. The signal processing unit 804 corrects the gain of the semiconductor device 801 based on the above-mentioned gain error information output from the semiconductor device 801, performs a predetermined signal processing on the image signal, and outputs image data. The imaging system 800 may have a driving device for driving (moving, displacing, deforming) an object, such as a motor or an actuator. The imaging system 800 may have a processing device that acquires information from a signal output from the semiconductor device 801, and a control device that controls a driving device such as a motor based on the information. The first driving device such as a motor can drive the lens 802 for a focusing (autofocus) operation based on the acquired information (distance measurement information) output from the semiconductor device 801. The second driving device such as a motor can drive the aperture 803 for an automatic exposure (autoexposure) operation based on the acquired information (photometric information) output from the semiconductor device 801. A third driving device such as a motor can drive the semiconductor device 801 for vibration reduction (shake correction) based on the acquired information output from the semiconductor device 801.

[0071] 3, for example, the signal processing unit 804 calculates AD gain error information based on the ratio of Vsiga to Vsigb, and corrects the AD gain error. Specifically, the slope of the ramp waveform is calculated from the ratio of Vsiga to Vsigb, and the amount of deviation of the AD gain from the set value is obtained.

[0072] 6, the signal processor 804 calculates analog gain error information based on the ratio of Vref to Vsig and corrects the analog gain error. Specifically, since the Vref value is a known value, the deviation amount from the amplifier gain setting value is calculated based on the ratio of Vref to Vsig after offsetting the AD conversion error. Note that the ratio of Vref to Vsig is calculated for each gain setting value of the amplifier 604 in the correction value output circuit 502, so the signal processor 804 performs gain correction using the ratio of Vref to Vsig according to the gain of the column amplifier 501.

[0073] Depending on the configuration of the semiconductor device, the AD gain error or the analog gain error may be calculated inside the semiconductor device 801 based on Vsiga, Vsigb, Vref, and Vsig. In such a case, the signal processing unit 804 corrects the AD gain error or the analog gain error using the AD gain error or the analog gain error information calculated inside the semiconductor device. In addition, the gain correction process itself may also be performed inside the semiconductor device 801.

[0074] By configuring an imaging system using the semiconductor device according to each of the above-mentioned embodiments, it is possible to realize an imaging system capable of acquiring images of higher quality.

[0075] <Fourth embodiment> A system (for example, an imaging system) and a device (for example, a transport device) according to a fourth embodiment of the present invention will be described with reference to Fig. 9A and Fig. 9B. Fig. 9A and Fig. 9B are diagrams showing the configurations of the imaging system and the transport device according to this embodiment.

[0076] FIG. 9A shows an example of an imaging system 2100 related to a vehicle-mounted camera. The imaging system 2100 includes a semiconductor device 2110. The semiconductor device 2110 is any one of the semiconductor devices (semiconductor device) described in the above-mentioned first and second embodiments. Imaging system 2100 The imaging system 2100 includes an image processing unit 2112 and a parallax acquisition unit 2114. The image processing unit 2112 is a processing device that performs image processing on a plurality of image data acquired by the semiconductor device 2110. The processing performed by the image processing unit 2112 includes a gain correction process based on a correction value output by the semiconductor device 2110. The parallax acquisition unit 2114 is a processing device that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the semiconductor device 2110. The imaging system 2100 also includes a distance acquisition unit 2116 that is a processing device that calculates a distance to an object based on the calculated parallax, and a collision determination unit 2118 that is a processing device that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 2114 and the distance acquisition unit 2116 are examples of information acquisition means that acquire information such as distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 2118 may determine the possibility of collision using any of these distance information. The above-mentioned processing device may be realized by dedicated hardware or by general-purpose hardware that performs calculations based on software modules. The processing device may also be realized by FPGA (Field Programmable Gate Array), ASIC, etc. (Application Specific Integrated Circuit), or This may be realized by a combination of the above.

[0077] The imaging system 2100 is connected to a vehicle information acquisition device 2120, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 2100 is also connected to a control ECU 2130, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 2118. That is, the control ECU 2130 is an example of a transportation equipment control means that controls transportation equipment based on distance information. The imaging system 2100 is also connected to an alarm device 2140 that issues an alarm to the driver based on the judgment result of the collision judgment unit 2118. For example, when the judgment result of the collision judgment unit 2118 indicates that there is a high possibility of a collision, the control ECU 2130 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 2140 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating a seat belt or steering wheel.

[0078] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 2100. Fig. 9B shows the imaging system 2100 when imaging the area in front of the vehicle (imaging range 2150). The vehicle information acquisition device 2120 sends an instruction to operate the imaging system 2100 to perform imaging. By using the semiconductor device of the above-mentioned embodiments 1 and 2 as the semiconductor device 2110, the imaging system 2100 of this embodiment can further improve the accuracy of distance measurement.

[0079] In the above description, an example of control to avoid collision with other vehicles has been described, but the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to avoid going out of lanes, etc. Furthermore, the imaging system is not limited to vehicles such as automobiles, but can be applied to transportation equipment (moving bodies) such as ships, aircraft, and industrial robots. The driving devices in transportation equipment (transport equipment) are various power sources such as engines, motors, wheels, and propellers. In addition, the present invention can be applied not only to transportation equipment, but also to a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS). [Explanation of symbols]

[0080] 100, 400, 500, 700... Semiconductor device 112,503 Voltage generation unit 303a,303b,605a,605b...Comparator

Claims

1. A voltage generating unit that generates a voltage; a first AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a first digital value; a second AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a second digital value; A signal generating unit that generates a signal in response to an external input; a third AD converter that converts an analog value based on the signal into a third digital value; a signal processing circuit that corrects the third digital value in accordance with a ratio between the first digital value and the second digital value; having A semiconductor device comprising:

2. A plurality of resistance elements are connected in series between a power supply voltage node and a ground voltage node; the voltage generating unit generates a voltage by dividing a power supply voltage by the plurality of resistance elements.

2. The semiconductor device according to claim 1,

3. a first amplifier that amplifies the voltage generated by the voltage generating unit to a first analog value with a first gain; a second amplifier that amplifies the voltage generated by the voltage generating unit to a second analog value with a second gain; having the first AD converter converts the first analog value into the first digital value; the second AD converter converts the second analog value into the second digital value; 3. The semiconductor device according to claim 2.

4. an input node of the first amplifier is electrically connected between a power supply voltage node and one of the plurality of resistance elements; an input node of the second amplifier is electrically connected between the ground voltage node and the one resistance element; 4. The semiconductor device according to claim 3.

5. The voltage source of the voltage generating unit is separate from the voltage source of the signal generating unit. The semiconductor device according to claim 1 .

6. the third digital value, the first digital value and the second digital value, or outputting the third digital value and a value based on the first digital value and the second digital value; The semiconductor device according to claim 1 .

7. the voltage generating unit generates a first voltage and a second voltage by dividing the power supply voltage by the plurality of resistance elements; the first AD converter converts a first analog value based on the first voltage into the first digital value; the second AD converter converts a second analog value based on the second voltage into the second digital value; The semiconductor device according to claim 2 .

8. at least one of a switch for selectively connecting either the voltage generating unit or the signal generating unit to the first AD converter, and a switch for selectively connecting either the voltage generating unit or the signal generating unit to the second AD converter; The semiconductor device according to claim 7.

9. A voltage generating unit that generates a voltage; a first AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a first digital value; a second AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a second digital value; a first amplifier that amplifies the voltage generated by the voltage generating unit to a first analog value with a first gain; a second amplifier that amplifies the voltage generated by the voltage generating unit to a second analog value with a second gain; having the first AD converter converts the first analog value amplified by the first amplifier into the first digital value; the second AD converter converts the second analog value amplified by the second amplifier into the second digital value; A plurality of resistance elements are connected in series between a power supply voltage node and a ground voltage node; the voltage generation unit generates a voltage by dividing a power supply voltage by the plurality of resistance elements; an input node of the first amplifier is electrically connected between a power supply voltage node and one of the plurality of resistance elements; an input node of the second amplifier is electrically connected between the ground voltage node and the one resistance element; A semiconductor device comprising:

10. the first AD converter and the second AD converter simultaneously perform AD conversion to convert the signal into the first digital value and AD conversion to convert the signal into the second digital value; The semiconductor device according to claim 1 .

11. the first gain is 1x; The semiconductor device according to claim 3 .

12. a third amplifier that amplifies the voltage generated by the signal generating unit to a third analog value with a third gain; the third AD converter converts the third analog value into a third digital value; The semiconductor device according to claim 3 or 11.

13. a switch for selectively connecting either the voltage generating unit or the signal generating unit to the second AD converter; The semiconductor device according to claim 12.

14. The gain of the third amplifier is variable. The semiconductor device according to claim 12 or 13.

15. The gain of the first amplifier is fixed, and the gain of the second amplifier is variable. The semiconductor device according to claim 11 .

16. The signal generating unit is a pixel array. The semiconductor device according to claim 1 .

17. The voltage generating unit is composed of only passive elements. The semiconductor device according to claim 1 .

18. the first AD converter converts the analog value to the first digital value by comparing it with a ramp waveform reference signal; the second AD converter converts the analog value to the second digital value by comparing it with a ramp waveform reference signal; The semiconductor device according to claim 1 .

19. A signal generating unit that generates a signal in response to an external input; A voltage generating unit that generates a voltage; a first AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a first digital value; a second AD converter that converts an analog value based on the voltage generated by the voltage generating unit into a second digital value; a third AD converter that converts an analog value based on the signal generated by the signal generating unit into a third digital value; having the third digital value is corrected according to a ratio between the first digital value and the second digital value. system.

20. A semiconductor device according to any one of claims 1 to 17, a signal processing unit for processing a signal output from the semiconductor device; A system comprising:

21. A semiconductor device according to any one of claims 1 to 17, A drive device for driving the object; a processing device for acquiring distance measurement information or photometric information from a signal output from the semiconductor device; a control device that controls the drive device based on the distance measurement information or the photometric information; having The driving device drives the object based on the distance measurement information or the photometric information. The device characterized by:

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