Ion irradiation method and wafer mask device

Abstract

To control ion irradiation in the vicinity of an opening end of a wafer mask.SOLUTION: An ion irradiation method includes: preparing a wafer mask device 12 which includes a first opening 50 and a second opening 52 communicating with the first opening 50 and in which an opening size of the second opening 52 is smaller than an opening size of the first opening 50; disposing the wafer mask device 12 on a semiconductor substrate 10 in such a manner that the second opening 52 is positioned farther from the semiconductor substrate 10 than the first opening 50; irradiating the semiconductor device 10 with ions from above the wafer mask device 12 to form a high resistance region 34 of higher resistivity than that before the ion irradiation in a region corresponding to the first opening 50 inside the semiconductor substrate 10.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an ion irradiation method and a wafer mask apparatus. [Background technology]

[0002] In recent years, CMOS technology has improved, and semiconductor devices incorporating analog and digital circuits are being used for various purposes. To improve the characteristics of an inductor element included in an analog circuit, a high-resistance region may be formed in a semiconductor substrate. For example, a high-resistance region is formed directly below the inductor element by irradiating the inductor formation region with light ions such as hydrogen (H) or helium (He). To prevent semiconductor elements such as transistors from being irradiated with ions, a wafer mask having an opening in the inductor formation region is used (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-043108 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to further improve the performance of semiconductor devices, there is a need to place a semiconductor element closer to an inductor element. However, if the inductor element and the semiconductor element are placed closer to each other, ions that pass through the opening edge of the wafer mask may be scattered in the semiconductor substrate, and may affect the semiconductor element located near the opening edge of the wafer mask. If the opening size of the wafer mask is made smaller, the effect on the semiconductor element can be prevented, but it may become impossible to form a sufficiently high resistance region over the entire inductor formation region, and the characteristic improvement of the inductor element may be insufficient.

[0005] It is an exemplary object of an embodiment of the present invention to provide a technique for controlling ion irradiation near an open edge of a wafer mask. [Means for solving the problem]

[0006] An ion irradiation method according to one embodiment of the present invention includes preparing a wafer mask device having a first opening and a second opening communicating with the first opening, the second opening being smaller in size than the first opening; positioning the wafer mask device over a semiconductor substrate so that the second opening is located farther from the semiconductor substrate than the first opening; and irradiating ions toward the semiconductor substrate from above the wafer mask device to form a high-resistance region in a region in the semiconductor substrate corresponding to the first opening, the high-resistance region having a higher resistivity than before the ion irradiation.

[0007] Another aspect of the present invention is a wafer mask apparatus comprising: a first mask plate having a first opening and a second opening communicating with the first opening, the second opening having a smaller opening size than the first opening, a second mask plate having a third opening communicating with the second opening, the third opening having a size corresponding to the opening size of the first opening, and a spacer provided between the first mask plate and the second mask plate for positioning the first mask plate and the second mask plate such that the first opening and the second opening communicate with each other.

[0008] Any combination of the above components or mutual substitution of the components or expressions of the present invention between methods, devices, systems, etc. are also valid as aspects of the present invention. Effect of the Invention

[0009] According to the present invention, it is possible to control ion irradiation in the vicinity of the opening edge of the wafer mask. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating a schematic configuration of an ion irradiation apparatus according to an embodiment. [Diagram 2]5A to 5C are cross-sectional views each showing a schematic ion irradiation step according to the embodiment. [Diagram 3] 3(a) and (b) are plan views each showing a schematic configuration of a mask plate. [Figure 4] 10A to 10C are cross-sectional views each showing a schematic ion irradiation step according to a comparative example. [Diagram 5] 4A to 4C are cross-sectional views each showing a schematic diagram of an ion irradiation step according to an embodiment of the present invention. [Figure 6] 4A to 4C are cross-sectional views each showing a schematic diagram of an ion irradiation step according to an embodiment of the present invention. [Figure 7] 10A to 10C are cross-sectional views each showing a schematic ion irradiation step according to another embodiment. [Figure 8] 10A to 10C are cross-sectional views each showing a schematic ion irradiation step according to a modified example. [Figure 9] 10A to 10C are cross-sectional views each showing a schematic ion irradiation step according to another modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiment of the present invention will be described in detail. Note that the configuration described below is an example and does not limit the scope of the present invention in any way. In addition, in the description of the drawings, the same elements are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, in the drawings referred to in the following description, the size and thickness of each component are for convenience of explanation, and do not necessarily indicate the actual dimensions or ratios.

[0012] 1 is a diagram showing a schematic configuration of an ion irradiation apparatus 70 according to an embodiment. The ion irradiation apparatus 70 includes a beam generator 72, a beam transport device 74, and an irradiation processing chamber 76. The beam generator 72 includes a cyclotron-type or Van de Graaff-type accelerator, and generates an ion beam B having an acceleration energy of, for example, about 1 MeV to 100 MeV. The beam generator 72 generates the ion beam B composed of light ions such as hydrogen (H) and helium (He). The beam transport device 74 transports the ion beam B generated by the beam generator 72 to the irradiation processing chamber 76.

[0013] The beam transport device 74 is provided with a deflection device 80, a beam slit 82, and an absorber 84. The deflection device 80 scans the ion beam B from the beam generation device 72 in an electric field or magnetic field so that the entire semiconductor substrate 10 is sequentially scanned by the ion beam B. The deflection device 80 performs two-dimensional scanning of the ion beam B, for example, in the horizontal and vertical directions.

[0014] The scanned ion beam B passes through a beam slit 82 and an absorber 84. By setting the distance from the deflection device 80 to the beam slit 82 to about 5 m to 10 m, the substantially parallel ion beam B passes through the beam slit 82. The parallelism of the ion beam B after passing through the beam slit 82 is, for example, within 1 degree.

[0015] The absorber 84 is an energy deceleration plate made of a material such as aluminum (Al), and decelerates the ion beam B passing through the absorber 84 to adjust it to have a desired energy. The ion beam B that has passed through the absorber 84 is scattered by the absorber 84, and the parallelism of the ion beam B that has passed through the absorber 84 decreases. The parallelism of the ion beam B that has passed through the absorber 84 depends on the thickness of the absorber 84, but is about 2 degrees to 5 degrees.

[0016] The semiconductor substrate 10 to be irradiated with the ion beam B includes circuit elements formed on the semiconductor substrate 10. The semiconductor substrate 10 includes, for example, semiconductor elements such as transistors formed in a semiconductor layer, and inductor elements formed in a wiring layer on the semiconductor layer. A wafer mask device 12 is provided on the surface of the semiconductor substrate 10. The semiconductor substrate 10 and the wafer mask device 12 are positioned relative to each other by a fixing device 14. The semiconductor substrate 10 and the wafer mask device 12 are attached to a transport plate 86 via the fixing device 14, and transported to the irradiation processing chamber 76.

[0017] The wafer mask device 12 is disposed in front of the semiconductor substrate 10 in the traveling direction of the ion beam B. Therefore, the scanned beam B is incident on the semiconductor substrate 10 through the wafer mask device 12. The wafer mask device 12 has an aperture pattern, and blocks a portion of the incident ion beam B and allows the remaining portion to pass. By irradiating the ion beam B, defects are formed inside the semiconductor substrate 10 at positions according to the aperture pattern of the wafer mask device 12, and a high-resistance region having a higher resistivity than before the ion irradiation is formed.

[0018] FIG. 2 is a cross-sectional view showing a schematic diagram of an ion irradiation process according to an embodiment. FIG. 2 shows the structure and arrangement of the semiconductor substrate 10 and the wafer mask device 12 in more detail. The semiconductor substrate 10 constitutes an integrated circuit (IC) such as a system LSI or a system-on-chip. The wafer mask device 12 is disposed above the semiconductor substrate 10, and blocks a part of the ion beam B incident on the semiconductor substrate 10 and allows the rest to pass through.

[0019] The semiconductor substrate 10 includes a semiconductor layer 20 and a wiring layer 22. The semiconductor layer 20 is provided on the back surface 26 side of the semiconductor substrate 10. The wiring layer 22 is provided on the front surface 24 side of the semiconductor substrate 10. In this specification, a direction perpendicular to the front surface 24 or the back surface 26 of the semiconductor substrate 10 may be referred to as the up-down direction, the thickness direction, or the depth direction. Also, as viewed from the semiconductor substrate 10, the front surface 24 side may be referred to as the upper side, and the back surface 26 side may be referred to as the lower side. Also, a direction parallel to the front surface 24 or the back surface 26 of the semiconductor substrate 10 may be referred to as the lateral direction or horizontal direction.

[0020] The semiconductor layer 20 is a low-resistance wafer having a resistivity of 10 Ω·cm or less, and is a semiconductor wafer having a resistivity of about 1 to 10 Ω·cm. The semiconductor layer 20 is, for example, a p-type silicon (Si) wafer produced by the Czochralski (CZ) method, and has a p-type carrier concentration of 10 15 cm -3 ~10 16 cm -3Wafers produced by the CZ method have a lower resistivity and are less expensive than high-resistivity wafers produced by the floating zone (FZ) method or the like. In one embodiment, the resistivity of the semiconductor layer 20 is 4 Ω·cm, and the p-type carrier concentration is 3.4×10 15 cm -3 It is.

[0021] The wiring layer 22 has a multi-layer wiring structure, and includes, for example, a plurality of interlayer insulating layers and metal wiring formed in the interlayer insulating layers. The thickness of the wiring layer 22 is about 5 μm to 30 μm, for example, about 10 μm, 15 μm, or 20 μm. The wiring layer 22 includes, for example, horizontal wiring extending in the horizontal direction, and via wiring extending in the vertical direction to connect horizontal wiring formed in different layers.

[0022] The semiconductor substrate 10 has a transistor forming region 16 and an inductor forming region 18. The transistor forming region 16 and the inductor forming region 18 are provided at different lateral positions in the semiconductor substrate 10. In the illustrated example, the transistor forming region 16 and the inductor forming region 18 are adjacent to each other.

[0023] A transistor 30 is provided in the transistor formation region 16. The transistor 30 includes, for example, impurity diffusion regions such as a well region, a source / drain region, and a contact region provided in the semiconductor layer 20, and a gate structure provided in the wiring layer 22. The transistor formation region 16 may also be provided with semiconductor elements such as diodes, and circuit elements such as resistors and capacitors.

[0024] An inductor 32 is provided in the inductor-forming region 18. The inductor 32 is provided in the wiring layer 22 and is formed by metal wiring extending in a loop or spiral shape in the wiring layer 22. A high-resistance region 34 is provided in the semiconductor layer 20 in the inductor-forming region 18. The high-resistance region 34 is a region having a higher resistivity than a body portion of the semiconductor layer 20. The high-resistance region 34 is formed by irradiating the semiconductor layer 20 with an ion beam B. The resistivity of the high-resistance region 34 is 100 Ω·cm or more, and preferably 500 Ω·cm or more or 1 kΩ·cm or more.

[0025] The high resistance region 34 includes a first high resistance region 36 and a second high resistance region 38. The first high resistance region 36 is provided in the center of the inductor forming region 18. The first high resistance region 36 is formed by the ion beam B passing through the second opening 52 of the wafer mask device 12. The first high resistance region 36 is formed relatively thick. The first high resistance region 36 is formed, for example, in a range from the interface 28 between the semiconductor layer 20 and the wiring layer 22 to a first depth d1. The first depth d1 is, for example, 20 μm or more, and preferably 50 μm or more or 100 μm or more.

[0026] The second high resistance region 38 is provided along the outer periphery of the inductor forming region 18. The second high resistance region 38 is formed by the ion beam B that has passed through the flange 44 of the wafer mask device 12. The second high resistance region 38 is provided adjacent to the first high resistance region 36 on the outer side of the first high resistance region 36. The second high resistance region 38 can also be said to be a region provided adjacent to the transistor forming region 16. The second high resistance region 38 is formed relatively thin. The second high resistance region 38 is formed, for example, in a range from the interface 28 between the semiconductor layer 20 and the wiring layer 22 to the second depth d2. The second depth d2 is smaller than the first depth d1, and is about 30% to 70% of the first depth d1. This is because the ion beam B loses energy by passing through the flange 44, and the depth that the ion beam B can reach is smaller than the case where the ion beam B does not pass through the flange 44. The second depth d2 is, for example, 10 μm or more, and preferably 20 μm or more or 40 μm or more.

[0027] The depth range of the high-resistance region 34 can be increased by irradiating the ion beam B multiple times while changing the irradiation conditions. For example, the depth position reached by the ion beam B incident on the semiconductor layer 20 can be changed by changing at least one of the ion species, irradiation energy, and thickness of the absorber 84 of the ion beam B. By irradiating the ion beam B multiple times while changing the depth position reached by the ion beam B, a high-resistance region 34 with an increased depth range can be formed.

[0028] The wafer mask device 12 includes a mask plate 40. The mask plate 40 is made of metals including aluminum (Al), stainless steel (SUS), nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti) and alloys thereof, semiconductor materials such as silicon (Si), or resin materials. In one embodiment, the mask plate 40 is made of nickel or an alloy containing nickel, for example, an alloy of iron and nickel (42 alloy). The mask plate 40 can be formed, for example, by using an electroforming method.

[0029] The mask plate 40 has an opening end surface 42 that defines a first opening 50, and a flange 44 that protrudes from the opening end surface 42 to define a second opening 52. The first opening 50 has a first opening size w1 that corresponds to the inductor-forming region 18. The first opening size w1 is, for example, about 50 μm to 1000 μm. The second opening 52 has a second opening size w2 that is smaller than the first opening size w1. The second opening size w2 is smaller than the first opening size w1 by the protruding width w3 of the flange 44, and w2=w1-2×w3. The protruding width w3 of the flange 44 is about 5 μm to 50 μm. Therefore, the difference w1-w2 between the first opening size w1 and the second opening size w2 is about 10 μm to 100 μm.

[0030] The thickness t1 of the first opening 50 is set to be thick enough to completely block the ion beam B incident on the transistor formation region 16. The thickness t1 of the first opening 50 is, for example, 50 μm or more, and preferably 100 μm or more or 200 μm or more. The thickness t2 of the second opening 52 is set to be thin enough to allow the ion beam B incident on the flange 44 to pass through. The thickness t2 of the second opening 52 is 1 μm or more and 20 μm or less, for example, about 10 μm.

[0031] The wafer mask device 12 is disposed so that the second opening 52 is the incident side (i.e., the upper side) of the ion beam B, and the first opening 50 is the exit side (i.e., the lower side) of the ion beam B. In other words, the wafer mask device 12 is disposed so that the second opening 52 is located farther from the semiconductor substrate 10 than the first opening 50. By disposing the wafer mask device 12 in such a direction, the ion beam B incident on the inductor-forming region 18 is prevented from being scattered by the wiring layer 22 and being irradiated onto the transistor 30 adjacent to the inductor-forming region 18. This prevents damage to the transistor 30 caused by irradiation with the ion beam B. Details of such an effect will be described separately later with reference to FIGS. 4 to 6.

[0032] 3(a) and (b) are plan views showing a schematic configuration of the mask plate 40. Fig. 3(a) is a bottom view of the mask plate 40 seen from the first opening 50 side, and Fig. 3(b) is a top view of the mask plate 40 seen from the second opening 52 side. In the illustrated example, the first opening 50 and the second opening 52 are rectangular. The first opening 50 and the second opening 52 are not limited to being rectangular, and may have any shape.

[0033] The flange 44 is provided in a rectangular frame shape, and is formed so that a protruding width w3 from the opening end surface 42 that defines the first opening 50 is constant. The protruding width w3 of the flange 44 may vary depending on the location. For example, the protruding width w3 of the flange 44 may be relatively large at a location adjacent to the transistor formation region 16 and relatively small at a location not adjacent to the transistor formation region 16. The flange 44 may be provided on a part of the outer periphery of the first opening 50. For example, the flange 44 may be provided only at a location adjacent to the transistor formation region 16, and may not be provided at a location not adjacent to the transistor formation region 16.

[0034] Next, the effects of the present embodiment will be described with reference to a comparative example. FIG. 4 is a cross-sectional view showing a schematic ion irradiation process according to the comparative example. The wafer mask device 60 according to the comparative example does not have a flange 44. The wafer mask device 60 has only an opening 62 with a first opening size w1 corresponding to the inductor-forming region 18. The wafer mask device 60 has an opening end surface 64 that defines the opening 62. The ion beam B passing through the opening 62 of the wafer mask device 60 forms a high-resistance region 66 in the semiconductor layer 20 of the inductor-forming region 18. The high-resistance region 66 in the comparative example is formed in the range from the interface between the semiconductor layer 20 and the wiring layer 22 to a first depth d1 throughout the entire inductor-forming region 18.

[0035] FIG. 4 shows a schematic diagram of the behavior of an ion beam B0 passing near an opening end surface 64 of the wafer mask device 60. The ion beam B0 incident on the wiring layer 22 is scattered by the wiring layer 22 and diffuses laterally. A part of the ion beam B0 passing near the opening end surface 64 is scattered by the wiring layer 22 and heads toward the outside of the inductor-forming region 18. FIG. 4 shows a schematic diagram of a diffusion range 68 where the ions scattered outside the inductor-forming region 18 reach. In the example of FIG. 4, the transistor 30 is disposed near the inductor-forming region 18, so that a part of the transistor 30 is present within the diffusion range 68 where the scattered ions reach. When the transistor 30 is irradiated with scattered ions, damage occurs to the gate insulating film, etc., leading to a decrease in the performance of the transistor 30, such as an increase in leakage current (e.g., subthreshold leakage current).

[0036] 5 and 6 are cross-sectional views showing an ion irradiation process according to the embodiment. FIG. 5 shows the behavior of the ion beam B1 passing through the vicinity of the flange 44 in the second opening 52. The behavior of the ion beam B1 passing through the vicinity of the flange 44 is similar to the behavior of the ion beam B0 passing through the vicinity of the opening end surface 64 in the comparative example of FIG. 4. That is, the ion beam B1 passing through the vicinity of the flange 44 can be scattered by the wiring layer 22 and directed to the outside of the inductor forming region 18. However, in the embodiment of FIG. 5, since the second opening 52 is small, the first diffusion range 56 where the scattered ions reach is far from the transistor 30. That is, the transistor 30 does not exist within the first diffusion range 56. As a result, damage to the transistor 30 caused by the ion beam B1 passing through the second opening 52 can be prevented.

[0037] FIG. 6 shows a schematic diagram of the behavior of the ion beam B2 passing through the flange 44. The ion beam B2 incident on the flange 44 is scattered by the flange 44. A part of the ion beam B2a scattered by the flange 44 toward the outside of the first opening 50 is incident on the opening end surface 42 of the mask plate 40 and is blocked. Another part of the ion beam B2b that travels straight without being scattered by the flange 44 is scattered by the wiring layer 22 and changes its traveling direction. The ion beam B2b that travels straight through the flange 44 loses energy at the flange 44, so that the second diffusion range 58 where the scattered ions reach is narrower than the diffusion range 68 in the comparative example of FIG. 4. As a result, the distance from the transistor 30 to the second diffusion range 58 can be secured, and damage to the transistor 30 caused by the ion beam B2 incident on the flange 44 can be prevented.

[0038] According to this embodiment, by providing a flange 44 at the opening end of the wafer mask device 12, the range in which ions are laterally scattered near the opening end can be reduced. As a result, even if the transistor 30 is disposed close to the inductor-forming region 18, damage to the transistor 30 due to ion irradiation can be prevented. Furthermore, according to this embodiment, by providing a flange 44 at the opening end of the wafer mask device 12, the second high-resistance region 38 can be formed at a position directly below the flange 44. As a result, the high-resistance region 34 can be formed throughout the entire inductor-forming region 18, and the effect of improving the characteristics of the inductor 32 can be enhanced.

[0039] 7 is a cross-sectional view that illustrates an ion irradiation process according to another embodiment. In the embodiment of FIG. 7, the configuration of a wafer mask device 112 is different from that of the above-mentioned embodiment. The following describes this embodiment, focusing on the differences from the above-mentioned embodiment.

[0040] The wafer mask apparatus 112 includes a first mask plate 140 , a second mask plate 142 , and a spacer 144 .

[0041] The first mask plate 140 has a first opening 150 and a second opening 152 communicating with the first opening 150. The first mask plate 140 is configured similarly to the above-mentioned mask plate 40. The first mask plate 140 has an opening end surface 146 that defines the first opening 150, and a flange 148 that protrudes from the opening end surface 146 and defines the second opening 152. The first opening 150 has a first opening size w1 that corresponds to the inductor forming region 18. The second opening size w2 of the second opening 152 is smaller than the first opening size w1 of the first opening 150. The protruding width w3 of the flange 148 is about 5 μm to 50 μm. The thickness t3 of the first mask plate 140 is 50 μm or more, for example, about 100 μm. The thickness of the flange 148, that is, the thickness of the second opening 152, is 1 μm or more and 20 μm or less, for example, about 10 μm.

[0042] The second mask plate 142 has a third opening 154. The opening size of the third opening 154 is equal to or larger than the first opening size w1. In the illustrated example, the third opening 154 has substantially the same shape as the first opening 150, and the opening size of the third opening 154 corresponds to the first opening size w1. Here, the opening size "corresponds" means that the opening sizes are substantially the same, and the difference in the opening sizes is sufficiently smaller than the protruding width w3 of the flange 148. For example, the difference in the opening sizes is 20% or less, preferably 10% or less, of the protruding width w3 of the flange 148, for example, 20 μm or less or 10 μm or less. The thickness t4 of the second mask plate 142, i.e., the thickness t4 of the third opening 154, is 50 μm or more, for example, about 100 μm.

[0043] The spacer 144 is provided between the first mask plate 140 and the second mask plate 142. The thickness t5 of the spacer 144 is, for example, 1 mm or more, and preferably 5 mm or more. By making the spacer 144 thick, the first mask plate 140 and the second mask plate 142 can be mechanically reinforced. Furthermore, by making the spacer 144 thick, the obliquely incident component of the ion beam B incident on the wafer mask device 112 can be blocked. For example, the component that passes obliquely through the third opening 154 cannot pass through the first opening 150 and is blocked by the first mask plate 140.

[0044] The spacer 144 positions the first mask plate 140 and the second mask plate 142 so that the first opening 150, the second opening 152, and the third opening 154 communicate with each other. The spacer 144 has, for example, a first engagement portion (not shown) that engages with the first mask plate 140, and a second engagement portion (not shown) that engages with the second mask plate 142. Each of the first engagement portion and the second engagement portion is formed by, for example, a recess or a protrusion.

[0045] The first mask plate 140, the second mask plate 142, and the spacer 144 are made of metals including aluminum (Al), stainless steel (SUS), nickel (Ni), tungsten (W), molybdenum (Mo), titanium (Ti), and alloys thereof, semiconductor materials such as silicon (Si), or resin materials. In one embodiment, the first mask plate 140, the second mask plate 142, and the spacer 144 are made of nickel or an alloy containing nickel, for example, an alloy of iron and nickel (42 alloy). The first mask plate 140 and the second mask plate 142 can be formed, for example, by electroforming.

[0046] The wafer mask device 112 is disposed so that the second mask plate 142 is the incident side (i.e., the upper side) of the ion beam B, and the first mask plate 140 is the exit side (i.e., the lower side) of the ion beam B. The first mask plate 140 is disposed so that the second opening 152 is the incident side (i.e., the upper side) of the ion beam B, and the first opening 150 is the exit side (i.e., the lower side) of the ion beam B. Therefore, the wafer mask device 112 is disposed so that the second opening 152 is located farther from the semiconductor substrate 10 than the first opening 150, and the third opening 154 is located farther from the semiconductor substrate 10 than the second opening 152.

[0047] In this embodiment, similarly to the above-described embodiment, the high resistance region 34 can be formed over the entire inductor-forming region 18 while preventing damage to the transistor 30 adjacent to the inductor-forming region 18. Moreover, according to this embodiment, the spacer 144 is provided with a thickness, so that the ion beam B passing through the third opening 154 and proceeding obliquely can be blocked by the first mask plate 140. That is, the second mask plate 142 can be used as a collimating mask, and the ion beam B capable of passing through both the first opening 150 and the third opening 154 can be irradiated onto the semiconductor substrate 10. This prevents the ion beam B from being irradiated obliquely toward the transistor-forming region 16, and more suitably prevents damage to the transistor 30.

[0048] According to the present embodiment, the thermal capacity of the wafer mask device 112 can be increased by providing the spacer 144 with a certain thickness. The wafer mask device 112 receives energy from the ion beam B by partially shielding the irradiated ion beam B, thereby generating heat. By providing the thick spacer 144 to increase the thermal capacity, it is possible to prevent the temperature of the wafer mask device 112 from rising excessively. This makes it possible to reduce the effect of a decrease in irradiation accuracy due to the deformation of the first mask plate 140 and the second mask plate 142 caused by heat.

[0049] FIG. 8 is a cross-sectional view showing a schematic diagram of an ion irradiation process according to a modified example. In this modified example, the wafer mask device 112a is arranged upside down from the above-mentioned embodiment. That is, the first mask plate 140a is arranged on the incident side (i.e., the upper side) of the ion beam B, and the second mask plate 142a is arranged on the exit side (i.e., the lower side) of the ion beam B. In this modified example, the second mask plate 142a has a first opening 150a, and the first mask plate 140a has a second opening 152a and a third opening 154a. The first mask plate 140a has an opening end surface 146 that defines the third opening 154a, and a flange 148 that protrudes from the opening end surface 146 and defines the second opening 152a. Therefore, the wafer mask device 112a is disposed such that the second opening 152a is located farther from the semiconductor substrate 10 than the first opening 150a, and the third opening 154a is located farther from the semiconductor substrate 10 than the second opening 152a. In this modified example, the same effects as those of the above-described embodiment can be achieved.

[0050] FIG. 9 is a cross-sectional view showing an ion irradiation process according to another modified example. In this modified example, the configuration of the wafer mask device 112b is different from the above-mentioned embodiment and modified example. Specifically, the top and bottom of the first mask plate 140b are reversed from those in FIG. 8. That is, the second opening 152b of the first mask plate 140b is disposed on the incident side (i.e., the upper side) of the ion beam B, and the third opening 154b is disposed on the exit side (i.e., the lower side) of the ion beam B. Therefore, the wafer mask device 112b is disposed so that the second opening 152b is located farther from the semiconductor substrate 10 than the third opening 154b. In this modified example, the same effects as those of the above-mentioned embodiment can be achieved.

[0051] The present invention has been described above based on the embodiments. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, that various design changes are possible, that various modifications are possible, and that such modifications are also within the scope of the present invention.

[0052] In the above-described embodiment and modified example, the wafer mask devices 12, 112, 112a, 112b are disposed on the front surface 24 of the semiconductor substrate 10, and the ion beam B is irradiated onto the front surface 24 of the semiconductor substrate 10. In still another embodiment, the wafer mask devices 12, 112, 112a, 112b may be disposed on the rear surface 26 of the semiconductor substrate 10, and the ion beam B may be irradiated onto the rear surface 26 of the semiconductor substrate 10. Also, the thickness of the high resistance region 34 may be increased by combining ion irradiation from the front surface 24 and ion irradiation from the rear surface 26 of the semiconductor substrate 10. [Explanation of symbols]

[0053] 10...semiconductor substrate, 12...wafer mask device, 16...transistor forming region, 18...inductor forming region, 20...semiconductor layer, 22...wiring layer, 30...transistor, 32...inductor, 34...high resistance region, 40...mask plate, 42...opening end surface, 44...flange, 50...first opening, 52...second opening.

Claims

1. preparing a wafer mask device including a first opening and a second opening communicating with the first opening, the second opening having a smaller opening size than the first opening; disposing the wafer mask device over the semiconductor substrate such that the second opening is located farther from the semiconductor substrate than the first opening; irradiating the semiconductor substrate with ions from above the wafer mask device to form a high-resistance region having a resistivity higher than that before the ion irradiation in a region in the semiconductor substrate corresponding to the first opening; the wafer mask device includes a first mask plate having the first opening and the second opening, and a second mask plate having a third opening communicating with the second opening and having an opening size corresponding to an opening size of the first opening; The ion irradiation method, wherein the first mask plate has an opening end surface that defines the first opening, and a flange that protrudes from the opening end surface and defines the second opening.

2. preparing a wafer mask device including a first opening and a second opening communicating with the first opening, the second opening having a smaller opening size than the first opening; disposing the wafer mask device over the semiconductor substrate such that the second opening is located farther from the semiconductor substrate than the first opening; irradiating the semiconductor substrate with ions from above the wafer mask device to form a high-resistance region having a resistivity higher than that before the ion irradiation in a region in the semiconductor substrate corresponding to the first opening; the wafer mask apparatus includes a first mask plate having the first opening and a second mask plate having the second opening; the second mask plate further includes a third opening communicating with the second opening and having an opening size corresponding to an opening size of the first opening; the second mask plate has an opening end surface that defines the third opening, and a flange that protrudes from the opening end surface to define the second opening, The ion irradiation method, wherein the second mask plate is disposed on the semiconductor substrate so as to be located farther from the semiconductor substrate than the first mask plate.

3. 3. The ion irradiation method according to claim 1, wherein the first opening has a thickness of 50 μm or more, and the second opening has a thickness of 1 μm or more and 20 μm or less.

4. 4. The ion irradiation method according to claim 1, wherein a difference in size between the first opening and the second opening is 10 μm or more and 100 μm or less.

5. 5. The ion irradiation method according to claim 1, wherein the wafer mask device further comprises a spacer provided between the first mask plate and the second mask plate.

6. 6. The ion irradiation method according to claim 5, wherein the spacer has a thickness of 1 mm or more.

7. preparing a wafer mask device including a first opening and a second opening communicating with the first opening, the second opening having a smaller opening size than the first opening; disposing the wafer mask device over the semiconductor substrate such that the second opening is located farther from the semiconductor substrate than the first opening; irradiating the semiconductor substrate with ions from above the wafer mask device to form a high-resistance region having a resistivity higher than that before the ion irradiation in a region in the semiconductor substrate corresponding to the first opening; the wafer mask apparatus includes a mask plate having the first opening and the second opening; The thickness of the first opening is 50 μm or more, and the thickness of the second opening is 1 μm or more and 20 μm or less, 2. An ion irradiation method, comprising: the high resistance region including a first high resistance region and a second high resistance region provided outside the first high resistance region and adjacent to the first high resistance region.

8. a first mask plate having a first opening and a second opening communicating with the first opening, the second opening being smaller in size than the first opening; a second mask plate having a third opening communicating with the second opening, the third opening having a size corresponding to the size of the first opening; a spacer provided between the first mask plate and the second mask plate, the spacer positioning the first mask plate and the second mask plate so that the second opening and the third opening are in communication.

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