Method for manufacturing silicon carbide semiconductor device

Abstract

To provide a method for manufacturing a SiC semiconductor device capable of reducing a manufacturing process.SOLUTION: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming an electrode 22 electrically connected to a base layer 13 and an impurity region 14 through a first contact hole 21a; forming a gate wiring 23 electrically connected to a connection wiring 19 through a second contact hole 21b and composed of a material which can reduce oxygen of an oxide film 30; and removing the oxide film 30 formed on a connection wiring 19 by reducing oxygen of the oxide film 30 into the gate wiring 23 by performing heat treatment on the gate wiring 23 during or after forming of the gate wiring 23.SELECTED DRAWING: Figure 2H

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon carbide (hereinafter also simply referred to as SiC) semiconductor device. [Background technology]

[0002] Conventionally, a SiC semiconductor device has been proposed in which a MOSFET (short for metal oxide semiconductor field effect transistor) having a base layer, a source region, etc. is formed on a semiconductor substrate made of SiC (see, for example, Patent Document 1). Specifically, this SiC semiconductor device has a drift layer, and the base layer, the source region, etc. are formed on the drift layer. In addition, in this SiC semiconductor device, a gate structure is formed in which a gate electrode is disposed on a gate insulating film, and a connection wiring connected to the gate electrode is formed on one surface side of the semiconductor substrate. The gate electrode and the connection wiring are made of polysilicon.

[0003] An interlayer insulating film is formed on one surface of the semiconductor substrate so as to cover the gate electrode and the connection wiring, and a first contact hole exposing the source region and the like and a second contact hole exposing the connection wiring are formed in the interlayer insulating film.

[0004] A source electrode connected to the source region etc. through the first contact hole and a gate wiring connected to the connection wiring through the second contact hole are formed on the interlayer insulating film, and a metal silicide film is disposed between the source electrode and the source region etc.

[0005] Such a SiC semiconductor device is manufactured as follows. Specifically, an interlayer insulating film is formed on one side of a semiconductor substrate on which a base layer, a source region, etc. are formed, and then a first contact hole and a second contact hole are simultaneously formed. Next, thermal oxidation is performed to form an oxide film on the portion of the semiconductor substrate exposed from the first contact hole, and an oxide film is also formed on the connection wiring exposed from the second contact hole. At this time, since the semiconductor substrate is made of SiC and the connection wiring is made of polysilicon, the oxide film on the connection wiring is formed thicker than the oxide film on the semiconductor substrate. Note that this oxide film is intended to suppress the diffusion of atoms constituting the metal layer into the connection wiring, etc., when a metal silicide film is formed using a metal layer described later.

[0006] Next, the oxide film formed on the portion of the semiconductor substrate exposed from the first contact hole is removed while leaving the oxide film on the connection wiring. After that, a metal layer made of nickel or the like is formed so as to be disposed in the first contact hole, and a heat treatment is performed to form a metal silicide film on the portion of the semiconductor substrate exposed from the first contact hole. At this time, since the oxide film is formed on the connection wiring, the atoms constituting the metal layer are prevented from diffusing into the connection wiring, etc., and the characteristics of the SiC semiconductor device are prevented from changing.

[0007] Next, the oxide film formed on the connection wiring is removed, and then an upper electrode that is connected to the source region and the like through the first contact hole is formed, and a gate wiring that is electrically connected to the connection wiring through the second contact hole is formed. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2010-62402 A Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the above-described SiC semiconductor device, it is necessary to carry out only a step for removing the oxide film on the connection wiring, which tends to increase the number of manufacturing steps.

[0010] In view of the above, an object of the present invention is to provide a method for manufacturing a SiC semiconductor device that can reduce the number of manufacturing steps. [Means for solving the problem]

[0011] In claim 1 for achieving the above object, there is provided a method for manufacturing a SiC semiconductor device having a connection wiring (19) connected to a gate electrode (18), the method comprising the steps of: preparing a semiconductor substrate (10) made of SiC, the semiconductor substrate (10) having a first or second conductivity type, a drift layer (12) of the first conductivity type formed on the substrate, a base layer (13) of the second conductivity type formed on the drift layer, and an impurity region (14) of the first conductivity type formed in a surface layer portion of the base layer, a gate insulating film (17) being formed between the drift layer and the impurity region in the base layer, a gate electrode being formed on the gate insulating film, and a connection wiring connected to the gate electrode and made of polysilicon being formed on one surface (10a) facing the base layer; forming an interlayer insulating film (20) so as to cover the base layer, the impurity region, the gate electrode, and the connection wiring; and The method includes forming a first contact hole (21a) exposing the base layer and the impurity region and forming a second contact hole (21b) exposing the connection wiring, performing thermal oxidation to form an oxide film (30) on the portion of the connection wiring exposed from the second contact hole, forming a metal layer (31) on the portion of the semiconductor substrate exposed from the first contact hole, performing a heat treatment to react the metal layer with the semiconductor substrate to form a metal silicide film (24), removing an unreacted metal layer (31a) in a portion of the metal layer other than the portion that has become the metal silicide film, forming an electrode (22) electrically connected to the base layer and the impurity region through the first contact hole, and forming a gate wiring (23) electrically connected to the connection wiring through the second contact hole and having a portion made of a material capable of reducing oxygen in the oxide film. Then, during or after the formation of the gate wiring, a heat treatment is performed on the gate wiring to reduce oxygen in the oxide film formed on the connection wiring into the gate wiring and remove the oxide film. In the step of preparing a semiconductor substrate, a gate electrode is formed, and then dangling bonds in the semiconductor substrate at the interface with the gate insulating film are terminated with nitrogen. In the step of forming an oxide film, an oxide film having a thickness of 10 nm or less is formed. .

[0012] According to this, when performing a heat treatment on the gate wiring, the oxide film is removed by reducing oxygen in the oxide film inside the gate wiring, which eliminates the need to perform only the process of removing the oxide film, thereby preventing an increase in the number of manufacturing processes.

[0013] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view of a SiC semiconductor device in a first embodiment. [Figure 2A] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. [Figure 2B] 2B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2A. [Figure 2C] 2C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2B. [Figure 2D] 2D is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2C. [Figure 2E] 2E is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2D. [Figure 2F] 2B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2E. [Figure 2G] 2C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2F. [Figure 2H] 2C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2G. [Figure 2I] 2C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 2H. [Diagram 3] 1 is a schematic diagram showing the composition of an interface between a semiconductor substrate and a gate insulating film; [Figure 4] FIG. 13 is a diagram showing the relationship between the thickness of an oxide film and the threshold voltage. [Diagram 5] FIG. 11 is a cross-sectional view of a SiC semiconductor device according to a second embodiment. [Figure 6A]6A to 6C are cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. [Figure 6B] 6B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 6A. [Figure 6C] 6C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 6B. [Figure 6D] 6D is a cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 6C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) A first embodiment will be described with reference to the drawings. In this embodiment, an inversion type MOSFET having a trench gate structure will be described as an example of a SiC semiconductor device. First, the configuration of the SiC semiconductor device will be described.

[0017] As shown in Fig. 1, the SiC semiconductor device is configured using a semiconductor substrate 10 made of SiC. + In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si surface and an n-type impurity concentration of nitrogen, phosphorus, etc. of 1.0×10 19 / cm 3 The substrate 11 has a thickness of about 50 to 300 μm. In this embodiment, the substrate 11 constitutes a drain region.

[0018] On the surface of the substrate 11, a n-type SiC substrate is formed. -A p-type drift layer 12 and a p-type base layer 13 are formed by epitaxial growth, etc. In the following description, the surface of semiconductor substrate 10 on the base layer 13 side is referred to as one surface 10a of semiconductor substrate 10, and the surface of semiconductor substrate 10 on the substrate 11 side is referred to as the other surface 10b of semiconductor substrate 10.

[0019] The drift layer 12 has an n-type impurity concentration of, for example, 1.0 to 50.0×10 15 / cm 3 The base layer 13 is formed on a part of the drift layer 12 and has a p-type impurity concentration of, for example, 2.0×10 17 / cm 3 The thickness is said to be about 0.5 to 2 μm.

[0020] The surface layer of the base layer 13 is + Source region 14 of type and p + The source region 14 is formed so as to contact the side of a trench 16, which will be described later, and the contact region 15 is formed on the opposite side of the trench 16 across the source region 14. The source region 14 has an n-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3 The contact region 15 has a p-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3 In this embodiment, the source region 14 corresponds to the impurity region. The contact region 15 can be regarded as a part of the base layer 13 having a high impurity concentration, and can also be said to be a part of the base layer 13.

[0021] In the semiconductor substrate 10, trenches 16 having a width of, for example, about 0.8 μm are formed so as to penetrate the base layer 13 and the source region 14 and reach the drift layer 12. Although only one trench 16 is shown in FIG. 1, the trenches 16 are actually formed in a stripe shape with a plurality of trenches arranged at equal intervals in the left-right direction of the page.

[0022] Each trench 16 is filled with a gate insulating film 17 formed to cover the wall surface of the trench 16, and a gate electrode 18 made of polysilicon or the like formed on the gate insulating film 17. This forms a trench gate structure. In this embodiment, the portion of the wall surface of the trench 16 that contacts the base layer 13 corresponds to the surface of the base layer sandwiched between the impurity region and the drift layer.

[0023] The gate insulating film 17 is also formed on surfaces other than the inner wall surface of the trench 16. Specifically, the gate insulating film 17 is formed from the inner wall surface of the trench 16 to one surface 10a of the semiconductor substrate 10. In addition, in the portion of the gate insulating film 17 formed on the one surface 10a of the semiconductor substrate 10, a contact hole 17a exposing the source region 14 and the contact region 15 is formed.

[0024] A connection wiring 19 connected to the gate electrode 18 is formed on a portion of the gate insulating film 17 formed on the first surface 10a of the semiconductor substrate 10. This connection wiring 19 is formed by patterning the polysilicon formed on the first surface 10a of the semiconductor substrate 10 when forming the gate electrode 18 by disposing polysilicon in the trench 16 as described later. Note that the connection wiring 19 is electrically connected to the gate electrode 18 in a cross section different from that in FIG.

[0025] Furthermore, when the polysilicon formed on the surface 10a of the semiconductor substrate 10 is patterned to form the connection wiring 19, the portion of the polysilicon embedded in the trench 16 located on the opening side of the trench 16 is removed. Therefore, the gate electrode 18 is not embedded on the opening side of the trench 16. In other words, the gate insulating film 17 located on the opening side of the trench 16 is exposed from the gate electrode 18. Although not particularly limited, for example, the gate electrode 18 is not disposed in a portion of the trench 16 about 50 to 150 nm from the opening side.

[0026] An interlayer insulating film 20 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 18, the gate insulating film 17, etc. The interlayer insulating film 20 covering the gate electrode 18 is disposed so as to fill the opening of the trench 16. The interlayer insulating film 20 in this embodiment is made of BPSG (abbreviation of borophosphosilicate glass) or the like.

[0027] A contact hole 20a is formed in the interlayer insulating film 20, communicating with the contact hole 17a to expose the source region 14 and the contact region 15. The contact hole 20a formed in the interlayer insulating film 20 functions as one contact hole together with the contact hole 17a formed in the gate insulating film 17. For this reason, hereinafter, the contact hole 17a and the contact hole 20a are collectively referred to as a first contact hole 21a.

[0028] Further, second contact holes 21b exposing the connection wiring 19 are formed in the interlayer insulating film 20. The patterns of the first contact holes 21a and the second contact holes 21b are arbitrary, and examples thereof include a pattern in which a plurality of squares are arranged, a pattern in which rectangular lines are arranged, or a pattern in which lines are lined up.

[0029] A source electrode 22 is formed on the interlayer insulating film 20, and is electrically connected to the source region 14 and the contact region 15 through the first contact hole 21a. In addition, a gate wiring 23 is formed on the interlayer insulating film 20, and is electrically connected to the connection wiring 19 through the second contact hole 21b.

[0030] The gate wiring 23 is made of a material capable of reducing oxygen in the oxide film, and in this embodiment, is made of aluminum or a material containing aluminum as a main component. The source electrode 22 is not particularly limited, but in this embodiment, it is formed in the same process as the gate wiring 23, as will be described later. Therefore, the source electrode 22 in this embodiment is made of aluminum or a material containing aluminum as a main component, like the gate wiring 23.

[0031] The source electrode 22 may be made of a material different from that of the gate line 23, and may not be made of a material capable of reducing oxygen in the oxide film. In this embodiment, the source electrode 22 corresponds to an electrode.

[0032] A metal silicide film 24 for reducing contact resistance between the source region 14 and the contact region 15 and the source electrode 22 is formed in a portion of the semiconductor substrate 10 exposed from the first contact hole 21a. The source electrode 22 is electrically connected to the source region 14 and the contact region 15 via the metal silicide film 24. The metal silicide film 24 in this embodiment is made of nickel silicon (NiSi) or the like.

[0033] A drain electrode 25 electrically connected to the substrate 11 is formed on the other surface 10b side of the semiconductor substrate 10. In the SiC semiconductor device of the present embodiment, such a structure constitutes an n-channel type inversion type trench gate structure MOSFET.

[0034] In such a SiC semiconductor device, when a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 18 while a voltage lower than that of the drain electrode 25 is applied to the source electrode 22, an n-type inversion layer (i.e., a channel) is formed in the portion of the base layer 13 that contacts the trench 16. Then, electrons are supplied from the source region 14 to the drift layer 12 through the inversion layer, thereby turning the device on.

[0035] Next, a method for manufacturing the above-mentioned SiC semiconductor device will be described with reference to FIGS. 2A to 2I.

[0036] 2A, a semiconductor substrate 10 made of SiC is prepared, on which a base layer 13, a source region 14, a contact region 15, a trench 16, a gate insulating film 17, a gate electrode 18, and a connection wiring 19 are formed. In this process, the gate insulating film 17 formed on the wall surface of the trench 16 and the gate insulating film 17 formed on one surface 10a of the semiconductor substrate 10 are connected to each other.

[0037] In this embodiment, after the trench 16 is formed, polysilicon is deposited by a CVD method or the like to form a gate electrode 18 filling the trench 16 and to deposit the polysilicon on the first surface 10a of the semiconductor substrate 10. CVD is an abbreviation for Chemical Vapor Deposition. Thereafter, the polysilicon formed on the first surface 10a of the semiconductor substrate 10 is patterned to form a connection wiring 19 connected to the gate electrode 18. At this time, the portion of the polysilicon filling the trench 16 that is located on the opening side of the trench 16 is removed. Therefore, the opening side of the trench 16 is in a state where the gate electrode 18 is not filled.

[0038] Thereafter, although not shown, in this embodiment, a nitrogen termination process is performed in which dangling bonds in the interface between the semiconductor substrate 10 and the gate insulating film 17 are terminated with nitrogen by performing a heat treatment in an oxygen-nitrogen atmosphere (i.e., an NO atmosphere). That is, dangling bonds in the interface between the base layer 13 and the gate insulating film 17 are terminated with nitrogen. This lowers the interface state, thereby enabling the threshold voltage to be reduced.

[0039] 2B, an interlayer insulating film 20 is formed by a CVD method or the like so as to cover the gate electrode 18, the connection wiring 19, etc. The interlayer insulating film 20 is disposed so as to fill the opening side of the trench 16 as well.

[0040] Next, as shown in FIG. 2C, etching or the like is performed using a mask not shown to simultaneously form a first contact hole 21a that exposes the source region 14 and the contact region 15, and a second contact hole 21b that exposes the connection wiring 19.

[0041] 2D, thermal oxidation is performed to form an oxide film 30 having a thickness of about 1 to 10 nm on the portion of the connection wiring 19 exposed from the second contact hole 21b. Note that such an oxide film 30 is formed, for example, by performing dry oxidation at 700° C. for 40 minutes or pyro-oxidation at 700° C. for 5 minutes.

[0042] Here, in the formation of the oxide film 30 in this process, oxygen may enter the semiconductor substrate 10 through the gate insulating film 17 from the opening side of the trench 16 where the gate electrode 18 is not arranged. In this case, the thicker the oxide film 30 is formed, the easier it is for oxygen to enter the semiconductor substrate 10. Then, as shown in FIG. 3, when oxygen enters the semiconductor substrate 10, the nitrogen terminated at the interface between the semiconductor substrate 10 and the gate insulating film 17 is replaced by oxygen, and the interface state becomes high and the threshold voltage becomes high. According to the study by the present inventors, as shown in FIG. 4, it was confirmed that when the oxide film 30 becomes larger than 10 nm, the threshold voltage becomes 10% or more higher than the reference value. Note that the reference value here is the threshold voltage when the thickness of the oxide film 30 is 0 nm (i.e., the threshold voltage is 1). At present, it is desired that the threshold voltage has an error of about 10% from the reference value. For this reason, in this embodiment, the oxide film 30 is formed to be 10 nm or less.

[0043] As described above, the semiconductor substrate 10 of this embodiment is made of SiC, which is a material that is less susceptible to oxidation than silicon. Therefore, when the oxide film 30 is formed as a thin film of 10 nm or less, almost no oxide film is formed on the portion of the surface 10a of the semiconductor substrate 10 exposed from the first contact hole 21a.

[0044] 2E, a metal layer 31 of nickel or the like is formed on the portion including the portion exposed from the first contact hole 21a by a sputtering method or the like. Note that, before carrying out this step, wet etching or the like may be carried out as necessary to remove an oxide film that may be formed on the portion of the surface 10a of the semiconductor substrate 10 exposed from the first contact hole 21a.

[0045] 2F, a heat treatment is performed at about 700 to 800° C. in a nitrogen atmosphere to react the semiconductor substrate 10 exposed from the first contact hole 21a with the metal layer 31 to form a metal silicide film 24. At this time, since the oxide film 30 is formed on the connection wiring 19 exposed from the second contact hole 21b, the atoms constituting the metal layer 31 are prevented from diffusing into the connection wiring 19 and the like.

[0046] In this embodiment, since a nickel film is formed as the metal layer 31, the metal silicide film 24 made of nickel silicon is formed. The portion of the metal layer 31 that does not react with the semiconductor substrate 10 (i.e., SiC) remains as an unreacted metal layer 31a.

[0047] 2G, the unreacted metal layer 31a is removed by wet etching or the like. After that, although not shown, a heat treatment is performed at about 950 to 1050° C. in a nitrogen atmosphere to further reduce the contact resistance between the metal silicide film 24 and the semiconductor substrate 10 (i.e., the source region 14 and the contact region 15).

[0048] 2H, a metal layer is formed on the interlayer insulating film 20 by a CVD method or the like, and then etching or the like is performed using a mask (not shown) to pattern the metal layer to form the source electrode 22 and the gate wiring 23. As described above, the gate wiring 23 is made of a material capable of reducing oxygen in the oxide film 30. In this embodiment, the source electrode 22 and the gate wiring 23 are formed by patterning a common metal layer, so the source electrode 22 is made of the same material as the gate wiring 23.

[0049] Thereafter, as shown in FIG. 2I, the gate wiring 23 is heated to a temperature equal to or lower than the melting point thereof and equal to or higher than the temperature of a subsequent process such as soldering, thereby stabilizing the film quality of the source electrode 22 and the gate wiring 23. At this time, the oxide film 30 formed on the connection wiring 19 is removed by reducing oxygen to the gate wiring 23, since the gate wiring 23 is made of a material capable of reducing oxygen in the oxide film 30. That is, in this embodiment, stabilizing the film quality of the gate wiring 23 and removing the oxide film 30 are performed in the same process. Note that, in this embodiment, this process corresponds to the heat treatment for the gate wiring 23. In this manner, the SiC semiconductor device of this embodiment is manufactured.

[0050] According to the present embodiment described above, the gate wiring 23 is made of a material capable of reducing oxygen in the oxide film 30. When a heat treatment is performed to stabilize the film quality of the gate wiring 23, the oxide film 30 is removed by causing the gate wiring 23 to reduce oxygen in the oxide film 30. Therefore, it is not necessary to perform only the step of removing the oxide film 30, and an increase in the number of manufacturing steps can be suppressed.

[0051] (1) In this embodiment, after the gate electrode 18 is formed, nitrogen termination is performed, and when the oxide film 30 is formed, the thickness of the oxide film 30 is set to 10 nm or less. This makes it possible to suppress the nitrogen substituted at the interface with the gate insulating film 17 of the base layer 13 from being replaced with oxygen, and suppresses an increase in the on-resistance due to an increase in the interface state.

[0052] Second embodiment A second embodiment will be described. In this embodiment, a barrier metal film is formed in comparison with the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0053] In the semiconductor device of this embodiment, as shown in FIG. 5, the source electrode 22 and the gate wiring 23 are configured to have barrier metal films 22a and 23a, respectively, and main wiring parts 22b and 23b laminated on the barrier metal films 22a and 23a. The main wiring part 23b is made of, for example, aluminum or a material mainly composed of aluminum. The barrier metal films 22a and 23a are made of a material that suppresses the diffusion of aluminum contained in the main wiring parts 22b and 23b to the connection wiring 19 and the like. In addition, the barrier metal films 22a and 23a are made of a material that can reduce oxygen in the oxide film 30 and is more difficult to diffuse than the main wiring parts 22b and 23b. The barrier metal films 22a and 23a of this embodiment are made of, for example, titanium or the like.

[0054] In addition, a metal silicide film 26 for reducing the contact resistance between the barrier metal film 23a and the connection wiring 19 is formed between the barrier metal film 23a in the gate wiring 23 and the connection wiring 19. The metal silicide film 26 in this embodiment is made of titanium silicon.

[0055] The above is the configuration of the SiC semiconductor device in this embodiment. Next, a method for manufacturing the SiC semiconductor device in this embodiment will be described with reference to Figures 6A to 6D.

[0056] In this embodiment, after removing the unreacted metal layer 31a by carrying out the step of Fig. 2G, a barrier metal layer 40 made of a material that is less likely to diffuse than the main wiring portion 23b is formed by a CVD method or the like as shown in Fig. 6A. In this embodiment, a titanium layer is formed as the barrier metal layer 40.

[0057] Thereafter, as shown in FIG. 6B, a heat treatment is performed at about 700 to 800° C. in a nitrogen atmosphere. As a result, oxygen in the oxide film 30 is reduced to the barrier metal layer 40 and removed. In addition, since the heat treatment is performed at 700 to 800° C., the connection wiring 19 and the barrier metal layer 40 react with each other to form the metal silicide film 26. Since the barrier metal layer 40 is made of a material that is difficult to diffuse, the atoms that form the barrier metal layer 40 are prevented from diffusing to the connection wiring 19 and the like in this process. That is, the barrier metal layer 40 is made of a material that can reduce oxygen in the oxide film 30 when the metal silicide film 26 is formed, and is difficult to diffuse to the connection wiring 19 and the like. In this embodiment, this process corresponds to the heat treatment for the gate wiring 23.

[0058] 6C, a main wiring layer 41 constituting the main wiring portions 22b and 23b is formed. Then, as shown in FIG. 6D, the barrier metal layer 40 and the main wiring layer 41 are patterned by etching or the like using a mask (not shown) to form the source electrode 22 and the gate wiring 23.

[0059] Thereafter, although not shown, the SiC semiconductor device of this embodiment is manufactured by carrying out a process similar to that of Fig. 2I to stabilize the film quality of the source electrode 22 and the gate wiring 23. Note that in this embodiment, since the oxide film 30 has already been removed, the oxide film 30 is not removed in this process.

[0060] According to the present embodiment described above, the barrier metal layer 40 (i.e., the barrier metal film 23a) constituting the gate wiring 23 is made of a material capable of reducing oxygen in the oxide film 30. When performing a heat treatment to form the metal silicide film 26, the oxide film 30 is removed by causing the barrier metal layer 40 to reduce oxygen in the oxide film 30. Therefore, it is not necessary to perform only the step of removing the oxide film 30, and the same effect as in the first embodiment can be obtained.

[0061] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0062] For example, in each of the above embodiments, a semiconductor device has been described in which a MOSFET of an n-channel type trench gate structure in which the first conductivity type is n-type and the second conductivity type is p-type has been formed. However, the semiconductor device may be configured, for example, by forming a MOSFET of a p-channel type trench gate structure in which the conductivity types of each component are inverted with respect to the n-channel type. Furthermore, the semiconductor device may be configured to include an IGBT of a similar structure in addition to the MOSFET. In the case of an IGBT, the n-channel type MOSFET in each of the above embodiments may be formed in a p-channel type trench gate structure in which the conductivity types of each component are inverted with respect to the n-channel type. + The substrate 11 is + Except for the change to a collector layer of the N-type, this MOSFET is similar to the MOSFET described in the first embodiment.

[0063] Furthermore, in each of the above embodiments, the semiconductor device has been described as having a trench gate structure, but the semiconductor device may have a planar gate structure.

[0064] In each of the above embodiments, the oxide film 30 formed during the manufacture of the semiconductor device may have a thickness of 10 nm or more. Even if such an oxide film 30 is formed, in the first and second embodiments, it is not necessary to perform only the step of removing the oxide film 30, and therefore an increase in the number of manufacturing steps can be suppressed. [Explanation of symbols]

[0065] 10. Semiconductor Substrate 10a one side 11 Substrate 12 Drift Layer 13 Base Layer 14 Source region (impurity region) 15 Gate insulating film 18 Gate electrode 19 Connection Wiring 20 Interlayer insulating film 22 Source electrode 23 Gate wiring 24 Metal silicide film 31 Metal layer 31a Unreacted metal layer

Claims

1. A method for manufacturing a silicon carbide semiconductor device including a gate electrode (18) and a connection wiring (19) connected thereto, comprising: a semiconductor substrate (10) made of silicon carbide, the semiconductor substrate (10) having a first conductivity type or a second conductivity type substrate (11), a drift layer (12) of the first conductivity type formed on the substrate, a base layer (13) of a second conductivity type formed on the drift layer, and an impurity region (14) of the first conductivity type formed in a surface layer portion of the base layer, the semiconductor substrate (10) having a gate insulating film (17) formed between the drift layer and the impurity region of the base layer, the gate electrode being formed on the gate insulating film, the base layer side being defined as one surface (10a) on which the connection wiring connected to the gate electrode and made of polysilicon is formed; forming an interlayer insulating film (20) so as to cover the base layer, the impurity region, the gate electrode, and the connection wiring; forming a first contact hole (21a) exposing the base layer and the impurity region in a portion including the interlayer insulating film, and forming a second contact hole (21b) exposing the connection wiring; performing thermal oxidation to form an oxide film (30) on a portion of the connection wiring exposed through the second contact hole; forming a metal layer (31) on a portion of the semiconductor substrate exposed through the first contact hole; performing a heat treatment to react the metal layer with the semiconductor substrate to form a metal silicide film (24); removing an unreacted metal layer (31 a) from a portion of the metal layer other than the portion that has become the metal silicide film; forming an electrode (22) electrically connected to the base layer and the impurity region through the first contact hole, and forming a gate wiring (23) electrically connected to the connection wiring through the second contact hole and having a portion made of a material capable of reducing oxygen in the oxide film; During or after the gate wiring is formed, a heat treatment is performed on the gate wiring to reduce oxygen in the oxide film formed on the connection wiring into the gate wiring, thereby removing the oxide film; In preparing the semiconductor substrate, after forming the gate electrode, dangling bonds in the semiconductor substrate at an interface with the gate insulating film are terminated with nitrogen; The method for manufacturing a silicon carbide semiconductor device, wherein the oxide film is formed to a thickness of 10 nm or less.

2. After forming the gate wiring, a heat treatment is performed on the gate wiring to stabilize the film quality of the gate wiring; 2. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film is removed during a heat treatment for stabilizing a film quality of the gate wiring.

3. The formation of the gate wiring includes forming a main wiring layer (41), forming a barrier metal layer (40) which is a material capable of reducing oxygen in the oxide film and is less likely to diffuse than the main wiring layer before forming the main wiring layer, and patterning the barrier metal layer and the main wiring layer to form the gate wiring; After forming the barrier metal layer and before forming the main wiring layer, a heat treatment is performed on the gate wiring to react the barrier metal layer with the connection wiring to form a metal silicide film (26); 2. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film is removed during a heat treatment for forming the metal silicide film.

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