Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device in which the variation in on-resistance can be suppressed without increasing the variation in threshold voltage, and a manufacturing method for a silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device includes a first semiconductor layer 2 of a first conductivity type provided on a front surface of a silicon carbide semiconductor substrate 1 of the first conductivity type, a second semiconductor layer 6 of a second conductivity type, a third semiconductor layer 7 of the first conductivity type, a first semiconductor region 8 of the first conductivity type provided selectively on a surface layer of the third semiconductor layer 7 on the opposite side of the silicon carbide semiconductor substrate 1, a second semiconductor region 9 of the second conductivity with higher impurity concentration than the second semiconductor layer, a trench 10, a gate electrode 12 provided through a gate insulating film 11, an interlayer insulating film 13, a first electrode 16, and a second electrode 15. The first semiconductor region 8 is thinner than a part of the third semiconductor layer 7 that is held between the first semiconductor region 8 and the second semiconductor layer 6.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, there is a silicon carbide semiconductor device having a trench gate structure as a structure with a high channel density to allow a large current to flow. The structure of a conventional silicon carbide semiconductor device will be described using a trench MOSFET as an example. FIG. 13 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. FIG. 13 shows the structure of an active region through which current flows when the device is on. As shown in FIG. 13, a trench MOSFET 170 has n + A first n-type drift layer is formed on the front surface of the silicon carbide substrate 101. - A silicon carbide epitaxial layer 102 is deposited.

[0003] 1st n - A p-type base layer 106 and an n-type silicon carbide epitaxial layer 102 are formed on the p-type silicon carbide epitaxial layer 102. + A n-type source region 108 is formed in sequence. + A first n-type source region 108 is formed through the p-type base region 106. - The structure has a trench gate including a trench 110, a gate insulating film 111, and a gate electrode 112 formed so as to reach the 1n-th silicon carbide epitaxial layer 102. - After epitaxially growing a p-type base region 106 on the silicon carbide epitaxial layer 102, a part of the p-type base region 106 is inverted to n-type by ion implantation of n-type impurities into the p-type base region 106, and + A type source region 108 is formed.

[0004] In FIG. 13, the reference numerals 103, 109, 113, 114, and 115 respectively denote the first p + type region, p ++ These are a type contact region, an interlayer insulating film, a source electrode pad, and a drain electrode.

[0005] Here, the ion implantation depth varies by less than 5%, while the thickness of the epitaxially grown layer varies by more than 10%. In the above configuration, since the epitaxial growth is performed up to the surface, the thickness of the p-type epitaxial layer is thick, and the thickness of the p-type base region 106 varies. This variation directly leads to variation in the channel length (thickness of the p-type base region 106), resulting in a problem of variation in the threshold voltage.

[0006] To solve this problem, a silicon carbide semiconductor device has been proposed. Fig. 14 is a cross-sectional view showing another structure of a conventional silicon carbide semiconductor device. In a trench-type MOSFET 171 shown in Fig. 14, a p-type base region 106 is formed by thin p-type epitaxial growth, and an n-type source region 107 thereon is formed with a low impurity concentration (1 × 10 17 / cm 3 The n-type epitaxial growth is performed on the n-type source region 107. + The source region 108 is formed with a high impurity concentration (5×10 18 / cm 3 (more than or equal to n) + The p-type base region 106 is formed by p-type epitaxial growth (see, for example, Patent Document 1). With this method, the p-type base region 106 is formed by thin p-type epitaxial growth, so the variation in thickness of the p-type base region 106 is small. Since the channel length is determined by the thin (about 0.4 μm) p-type epitaxial growth layer, the variation in channel length can be reduced compared to the configuration of FIG. 13, and the variation in threshold voltage can be suppressed.

[0007] In FIG. 14, reference numerals 104, 105, and 109a respectively denote the 2nth - Silicon carbide epitaxial layer, second p + Type region and p + The contact area is a mold contact area. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2019-46909 A Summary of the Invention [Problem to be solved by the invention]

[0009] However, in the conventional structure shown in FIG. + Since the n-type source region 108 is formed by epitaxial growth, the variation in n-type impurity concentration is large, at about 50%, and the n-type source region 107 and the n + This increases the variation in the contact resistance of the source region 108, and therefore the variation in the on-resistance. 18 / cm 3 There is a problem that there is no method to evaluate epitaxially grown layers with such high impurity concentrations. Furthermore, there is a problem that the history of epitaxial growth with high impurity concentrations may result in the incorporation of more dopants than expected into the next batch.

[0010] In order to solve the problems associated with the conventional techniques described above, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that are capable of suppressing variations in on-resistance without increasing variations in threshold voltage. [Means for solving the problem]

[0011] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A third semiconductor layer of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer is selectively provided in a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate, the second semiconductor region penetrating the third semiconductor layer. A trench is provided penetrating the first semiconductor region, the second semiconductor layer and the third semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. An interlayer insulating film is provided on the gate electrode. A first electrode is provided on surfaces of the second semiconductor layer and the first semiconductor region. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. The first semiconductor region is thinner than a portion of the third semiconductor layer sandwiched between the first semiconductor region and the second semiconductor layer. The impurity concentration gradually decreases toward the third semiconductor layer. .

[0012] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A third semiconductor layer of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer is selectively provided in a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate, the second semiconductor region penetrating the third semiconductor layer. A trench is provided penetrating the first semiconductor region, the second semiconductor layer and the third semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. An interlayer insulating film is provided on the gate electrode. A first electrode is provided on surfaces of the second semiconductor layer and the first semiconductor region. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. The first semiconductor region is thinner than the third semiconductor layer in a portion sandwiched between the first semiconductor region and the second semiconductor layer, and is composed of a high concentration portion on the front surface side and a low concentration portion on the third semiconductor layer side.

[0013] In the silicon carbide semiconductor device according to the present invention, a maximum impurity concentration of the first semiconductor region is 1.0×10 18 / cm 3 Above 5.0×10 19 / cm 3 The present invention is characterized in that:

[0014] In the silicon carbide semiconductor device according to the present invention, the third semiconductor layer has an impurity concentration of 1.0×10 16 / cm 3 Above 1.0×1018 / cm 3 Characterized in that 。

[0015] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step is performed in which a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is formed on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. Next, a second step is performed in which a second semiconductor layer of a second conductivity type is formed on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a third step is performed in which a third semiconductor layer of a first conductivity type is formed by epitaxial growth on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a fourth step is performed in which a first semiconductor region of a first conductivity type is selectively formed by injecting an impurity of a first conductivity type into a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a fifth step is performed in which a second semiconductor region of the second conductivity type having a higher impurity concentration than the second semiconductor layer is selectively formed, penetrating the third semiconductor layer, by injecting a second conductivity type impurity into a surface layer of the third semiconductor layer on the side opposite to the silicon carbide semiconductor substrate side. Next, a sixth step is performed in which a trench is formed penetrating the first semiconductor region, the second semiconductor layer, and the third semiconductor layer to reach the first semiconductor layer. Next, a seventh step is performed in which a gate electrode is formed inside the trench via a gate insulating film. Next, an eighth step is performed in which an interlayer insulating film is formed on the gate electrode. Next, a ninth step is performed in which a first electrode is formed on the surfaces of the second semiconductor layer and the first semiconductor region. Next, a tenth step is performed in which a second electrode is formed on the back surface of the silicon carbide semiconductor substrate. The first semiconductor region is thinner than the third semiconductor layer in a portion sandwiched between the first semiconductor region and the second semiconductor layer. The impurity concentration gradually decreases toward the third semiconductor layer. It is formed as follows. In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step is performed in which a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is formed on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. Next, a second step is performed in which a second semiconductor layer of a second conductivity type is formed on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a third step is performed in which a third semiconductor layer of a first conductivity type is formed by epitaxial growth on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a fourth step is performed in which a first semiconductor region of a first conductivity type is selectively formed by injecting an impurity of a first conductivity type into a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a fifth step is performed in which a second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer is selectively formed, penetrating the third semiconductor layer, by injecting a second conductivity type impurity into a surface layer of the third semiconductor layer on the opposite side to the silicon carbide semiconductor substrate side. Next, a sixth step is performed in which a trench is formed penetrating the first semiconductor region, the second semiconductor layer, and the third semiconductor layer and reaching the first semiconductor layer. Next, a seventh step is performed in which a gate electrode is formed inside the trench via a gate insulating film. Next, an eighth step is performed in which an interlayer insulating film is formed on the gate electrode. Next, a ninth step is performed in which a first electrode is formed on the surfaces of the second semiconductor layer and the first semiconductor region. Next, a tenth step is performed in which a second electrode is formed on the back surface of the silicon carbide semiconductor substrate. The first semiconductor region is formed to be thinner than the third semiconductor layer in a portion sandwiched between the first semiconductor region and the second semiconductor layer, and in the fourth step, the first semiconductor region is formed to have a two-layer structure of a high concentration portion on the front surface side and a low concentration portion on the third semiconductor layer side.

[0016] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the fourth step, phosphorus or nitrogen is implanted as the impurity of the first conductivity type.

[0017] In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the fourth step, a maximum impurity concentration of the first semiconductor region is 1.0×10 18 / cm 3 Above 5.0×10 19 / cm 3 The present invention is characterized in that the following is formed:

[0018] In the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the third step, the impurity concentration of the third semiconductor layer is 1.0×10 16 / cm 3 Above 1.0×10 18 / cm 3 The present invention is characterized in that the following is formed: 。

[0019] According to the above-mentioned invention, the n-type source region (third semiconductor layer) is formed by epitaxial growth, + The n-type source region (first semiconductor region) is formed by ion implantation. + The p-type source region has a profile in which the n-type impurity concentration gradually decreases toward the n-type source region. The channel layer is determined by a p-type base layer (second semiconductor layer) formed by epitaxial growth with a thin film thickness, so the channel length variation is low, and + The n-type source region is formed by ion implantation. + This makes it possible to reduce the variation in the impurity concentration of the type source region, and thus to suppress the variation in the contact resistance. Effect of the Invention

[0020] Advantageous Effects of Invention According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, an effect is exhibited in that it is possible to suppress variations in on-resistance without increasing variations in threshold voltage. [Brief description of the drawings]

[0021] [Figure 1] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment. [Diagram 2] 1 is a graph showing an impurity concentration profile along line AA' of a conventional silicon carbide semiconductor device (part 1). [Diagram 3] 13 is a graph showing an impurity concentration profile along the line A-A' of a conventional silicon carbide semiconductor device (part 2). [Figure 4] 4 is a graph showing an impurity concentration profile along line AA' of the silicon carbide semiconductor device according to the embodiment. [Diagram 5] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 1). [Figure 6] 5A to 5C are cross-sectional views (part 2) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. [Figure 7] 6A to 6C are cross-sectional views (part 3) illustrating a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 8] 4 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 4). FIG. [Figure 9] 5 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 5). FIG. [Figure 10] 4 is a graph showing measurement results of impurity concentrations in a portion along line AA' of the silicon carbide semiconductor device according to the embodiment. [Figure 11] 4 is a graph showing measurement results of impurity concentrations in a portion along line AA' of the silicon carbide semiconductor device according to the embodiment. [Figure 12] 1 is a graph showing results of measuring contact resistance in a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. [Figure 13] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. [Figure 14] FIG. 11 is a cross-sectional view showing another structure of the conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] A preferred embodiment of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before the index represents a negative index. In addition, the description of "same" or "equivalent" should include up to 5% in consideration of variations in manufacturing.

[0023] (Embodiment) The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a trench-type MOSFET 70 will be taken as an example of a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC) as a wide band gap semiconductor. Fig. 1 is a cross-sectional view showing a structure of the silicon carbide semiconductor device according to the embodiment.

[0024] 1, the trench MOSFET 70 includes a MOS gate having a trench gate structure on the front surface (the surface on the side of a p-type base layer 6 described later) of a semiconductor substrate. + A first n-type silicon carbide substrate (a silicon carbide semiconductor substrate of a first conductivity type) 1 is provided on the -The n-type silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 2 is epitaxially grown in sequence. - The silicon carbide epitaxial layer 4 is - Alternatively, the n-type silicon carbide epitaxial layer 2 may be epitaxially grown on the n-type silicon carbide epitaxial layer 2. + A silicon carbide substrate 1, a p-type base layer 6, and a first n - A silicon carbide epitaxial layer 2 and a 2n - The silicon carbide epitaxial layer 4 and the silicon carbide epitaxial layer 5 form a silicon carbide semiconductor base (a semiconductor substrate made of silicon carbide).

[0025] The MOS gate of the trench gate structure includes a p-type base layer (a second semiconductor layer of a second conductivity type) 6, an n-type source region (a third semiconductor layer of a first conductivity type) 7, and a + A first conductive type source region (a first semiconductor region of a first conductive type) 8, p ++ The p-type contact region (second semiconductor region of a second conductivity type) 9, a trench 10, a gate insulating film 11, and a gate electrode 12. The p-type base layer 6 has a thickness of, for example, 0.4 μm or more and 0.6 μm or less, and an impurity concentration of 5.0×10 16 / cm 3 Above 2.0×10 18 / cm 3 Preferably, the p-type base layer 6 has a dopant concentration of 1×10 17 / cm 3 5×10 or more 17 / cm 3 The impurity concentrations are as follows:

[0026] Specifically, the trench 10 penetrates the p-type base layer 6 in the depth direction y from the front surface of the semiconductor substrate, and - The silicon carbide epitaxial layer 4 (the second n - When the silicon carbide epitaxial layer 4 is not provided, the first n - The trenches 10 reach the silicon carbide epitaxial layer 2 (hereinafter referred to as (2)). The depth direction y is the direction from the front surface to the back surface of the semiconductor substrate. The trenches 10 are arranged, for example, in a stripe shape.

[0027] Inside the trench 10, a gate insulating film 11 is provided along the inner wall of the trench 10, and a gate electrode 12 is provided on the gate insulating film 11 so as to be embedded inside the trench 10. One unit cell of the main semiconductor element is composed of the gate electrode 12 in one trench 10 and adjacent mesa regions (regions between adjacent trenches 10) sandwiching the gate electrode 12. Although only one trench MOS structure is shown in FIG. 1, more trench-structured MOS gate (insulated gate made of metal-oxide film-semiconductor) structures may be arranged in parallel.

[0028] 1st n - An n-type region (hereinafter, referred to as a second n-type region) is formed in the surface layer of the source side (the source electrode 16 side described later) of the silicon carbide epitaxial layer 2 so as to contact the p-type base layer 6. - A second silicon carbide epitaxial layer (hereinafter referred to as a 2n-type silicon carbide epitaxial layer) 4 may be provided. - The 2n-type silicon carbide epitaxial layer 4 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. - The silicon carbide epitaxial layer 4 is formed uniformly in a direction parallel to the front surface of the substrate (front surface of the semiconductor substrate) so as to cover the inner wall of the trench 10, for example. - The silicon carbide epitaxial layer 4 is provided from the interface with the p-type base layer 6 to a position on the drain side (the side of a drain electrode 15 described later) from the bottom surface of the trench 10.

[0029] 1st n - The surface layer of the silicon carbide epitaxial layer 2 is formed of a first p + The mold region 3 may be selectively provided. + The mold region 3 is disposed between adjacent trenches 10. - The second p type silicon carbide epitaxial layer 4 includes + The mold region 5 may be selectively provided. + The mold region 5 is a first p + At a position facing the mold region 3 in the depth direction, a 2n -The bottom surface of the first p-type silicon carbide epitaxial layer 4 is + The second p-type region 3 is in contact with the p-type base layer 6 at its top surface. + Through the p-type region 5, the p-type base layer 6 and the first p + The mold region 3 is electrically connected to the mold region 3 .

[0030] 2nd n - The silicon carbide epitaxial layer 4 and the second p + A p-type base region 6 is provided on the surface of the base layer 5. The p-type base region 6 is a p-type epitaxial layer that has not been ion-implanted. The p-type base region 6 may be configured by ion-implanting p-type impurities into an n-type epitaxial layer. An n-type source region 7 is provided on the surface of the p-type base layer 6. The n-type source region 7 is an n-type epitaxial layer that has not been ion-implanted. Inside the n-type source region 7, an n-type source region 7 is provided. + Type source region 8 and p ++ A contact region 9 is optionally provided. + The n-type source region 8 is an n-type source region 7 + The n-type source region 7 and the n-type silicon carbide substrate 1 are disposed on the surface layer opposite to the n-type source region 7. + The n-type source region 8 is in contact with the gate insulating film 11 on the side wall of the trench 10, and faces the gate electrode 10 via the gate insulating film 11 on the side wall of the trench 10. ++ A contact region 9 is provided. ++ The n-type contact region 9 is connected to the n-type source region 7 and + The source region 8 is in contact with the p ++ The impurity concentration of the p-type contact region 9 is higher than the impurity concentration of the p-type base region 6 .

[0031] The n-type source region 7 is + The n-type source region 7 and the n-type + The n-type source regions 7 and 8 are in contact with each other. + The width of the source region 8 is approximately the same. +In a portion of the n-type source region 8, + The thickness of the n-type source region 8 is + The thickness of the n-type source region 7 is thinner than the thickness of the n-type source region 7 located between the p-type base region 6 and the n-type source region 8 .

[0032] Figures 2 and 3 are graphs showing impurity concentration profiles of the A-A' portion of a conventional silicon carbide semiconductor device. Figure 2 shows the case of the conventional silicon carbide semiconductor device shown in Figure 13, and Figure 3 shows the case of the conventional silicon carbide semiconductor device shown in Figure 14. In Figures 2 and 3, the horizontal axis shows the depth from the surface of the silicon carbide semiconductor substrate, and the vertical axis shows the n-type or p-type impurity concentration, with the n-type impurity concentration shown by a solid line and the p-type impurity concentration shown by a dashed line.

[0033] In FIG. 2, up to depth A2 is n + The n-type source region 108 extends to a depth A3, and the p-type base layer 106 extends to a depth A4. In the conventional silicon carbide semiconductor device shown in FIG. + Since the n-type source region 108 is formed by multiple ion implantations, the n-type impurity concentration is almost constant up to depth A1, and the n-type impurity concentration decreases rapidly from depth A1 to depth A2. The p-type base layer 106 is formed by epitaxial growth up to the surface, and the p-type impurity concentration is almost constant.

[0034] In FIG. 3, up to depth B1 is n + The region between depths B2 and B3 is a non-doped layer, and the region between depths B3 and B4 is a p-type base layer 106. In the conventional silicon carbide semiconductor device shown in FIG. + Since the n-type source region 108 and the n-type source region 109 are formed by epitaxial growth, the n-type impurity concentration is approximately constant. Also, since the p-type base layer 106 is formed by epitaxial growth, the p-type impurity concentration is approximately constant.

[0035] 4 is a graph showing an impurity concentration profile of a portion A-A' of a silicon carbide semiconductor device according to an embodiment. In Fig. 4, the horizontal axis indicates the depth from the surface of a silicon carbide semiconductor substrate, and the vertical axis indicates the n-type or p-type impurity concentration, with the n-type impurity concentration indicated by a solid line and the p-type impurity concentration indicated by a dashed line.

[0036] 4, the depth C0 is the point where the n-type impurity concentration is maximum, and C1 is the point where the n-type impurity concentration is half of C0. C2 is the boundary between the n-type source region 7 and the p-type base layer 6, and C3 is the boundary between the p-type base layer 6 and the second n - The boundary between the n-type silicon carbide epitaxial layer 4 and the n-type silicon carbide epitaxial layer 4 is a boundary between the n-type silicon carbide epitaxial layer 4 and the n-type silicon carbide epitaxial layer 4. + The n-type source region 7 is formed by epitaxial growth in the silicon carbide semiconductor device according to the embodiment, as described later. + The n-type source region 8 is formed by ion-implanting n-type impurities into a layer formed by epitaxial growth. + The n-type source region 8 has a profile in which the n-type impurity concentration gradually decreases in the form of a Gaussian distribution from the depth C0 toward the n-type source region 7. The n-type source region 7 has a substantially constant n-type impurity concentration, and the p-type base layer 6 has a substantially constant p-type impurity concentration.

[0037] Also, n + It is preferable that the thickness w1 of the n-type source region 8 is equal to or smaller than the thickness w2 of the n-type source region 7 (w1≦w2). + The damage caused by ion implantation when forming the n-type source region 8 is + Since the n-type source region 7 reaches a depth of about the thickness w1 of the n-type source region 8, by making w1≦w2, the n-type source region 7 can absorb the damage and prevent the damage from reaching the p-type base layer 6. +The p-type base layer 6 facing the n-type source region 8 in the depth direction is not damaged by ion implantation. As a result, damage caused by ion implantation does not affect the channel, and the characteristics are not deteriorated. This makes it possible to suppress variations in threshold voltage in silicon carbide semiconductor devices. For example, + The combined thickness (w1+w2) of the n-type source region 8 and the n-type source region 7 is 0.4 μm or more and 0.6 μm or less, + The thickness w1 of the type source region 8 satisfies w1≦w2 and is not less than 0.05 μm and not more than 0.3 μm.

[0038] Also, n + The maximum impurity concentration of the source region 8 is 1.0×10 18 / cm 3 Above 5.0×10 19 / cm 3 More preferably, it is 1.0×10 18 / cm 3 Above 3.0×10 19 / cm 3 The impurity concentration of the n-type source region 7, which is an epitaxial layer, is 1.0×10 16 / cm 3 Above 1.0×10 18 / cm 3 More preferably, it is 0.5×10 or less. 17 / cm 3 More than 1.5 x 10 17 / cm 3 The n-type source region 7 and the n + By setting the impurity concentration of the type source region 8 in this range, the variation can be suppressed without increasing the on-resistance.

[0039] In addition, in the embodiment, p ++ The impurity concentration of the p-type contact region 9 is higher than the impurity concentration of the p-type base region 6, and is 1.0×10 19 / cm 3 Above 5.0×10 20 / cm 3 It is preferable that p ++ It is preferable to provide the p-type contact region 9 in a single stage.++ The impurity concentration is high up to the drain side of the p-type contact region 9, and the avalanche resistance can be improved. ++ It is also possible to form the type contact region 9 in two stages by forming the surface with a high impurity concentration, similar to the source region. In this case, it is only necessary to make the surface have a high impurity concentration, which makes the formation easier and improves the manufacturing throughput.

[0040] The interlayer insulating film 13 is provided on the entire front surface of the semiconductor substrate so as to cover the gate electrode 12. The interlayer insulating film 13 has a contact hole that penetrates the interlayer insulating film 13 in the depth direction y and reaches the front surface of the substrate.

[0041] The source electrode (first electrode) 16 is connected to the semiconductor substrate (n + The source electrode 16 is in ohmic contact with the n-type source region 8 and is electrically insulated from the gate electrode 12 by an interlayer insulating film 13. + Type source region 8 and p ++ The source electrode 16 is in ohmic contact with the contact region 9. A barrier metal (not shown) for preventing diffusion of metal atoms from the source electrode 16 toward the gate electrode 12 may be provided between the source electrode 16 and the interlayer insulating film 13. A source electrode pad 14 is provided on the source electrode 16. A drain electrode (second electrode) 15 serving as a drain electrode is provided on the rear surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the drain electrode 15. A barrier metal (not shown) may also be provided between the source electrode 16 and the interlayer insulating film 13 and the source electrode pad 14.

[0042] (Method of Manufacturing Silicon Carbide Semiconductor Device According to an Embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Figures 5 to 9 are cross-sectional views showing states during the manufacturing process of a silicon carbide semiconductor device according to an embodiment.

[0043] First, n-type silicon carbide +A type silicon carbide substrate 1 is prepared. + A first n-type silicon carbide layer is formed on a first main surface (front surface) of the silicon carbide substrate 1 while doping it with n-type impurities, for example, nitrogen (N) atoms. - A silicon carbide epitaxial layer 2 is epitaxially grown.

[0044] Next, the 1nth - On the surface of the silicon carbide epitaxial layer 2, a mask for ion implantation (not shown) having a predetermined opening is formed by photolithography, for example, of an oxide film. Then, using this oxide film as a mask, p-type impurities, for example, aluminum (Al) atoms are ion-implanted by an ion implantation method to form a first n-type silicon carbide epitaxial layer. - A first p-type epitaxial layer having a depth of 0.3 μm to 1.0 μm is formed on the surface of the silicon carbide epitaxial layer 2. + For example, mold region 3 is 2.0×10 17 / cm 3 Above 2.0×10 18 / cm 3 The impurity concentrations are as follows: The state up to this point is shown in FIG.

[0045] Next, the 1nth - A second n-type silicon carbide epitaxial layer having a thickness of 0.3 μm to 1.0 μm and doped with n-type impurities such as nitrogen is formed on the surface of the n-type silicon carbide epitaxial layer 2. - The silicon carbide epitaxial layer 4 is formed at a thickness of, for example, 1.0×10 16 / cm 3 Above 5.0×10 17 / cm 3 The impurity concentration is as follows:

[0046] Next, the 2nd - On the surface of the silicon carbide epitaxial layer 4, a mask for ion implantation (not shown) having a predetermined opening is formed by photolithography, for example, of an oxide film. Then, using this oxide film as a mask, p-type impurities, for example, aluminum atoms, are ion-implanted by an ion implantation method to form a 2n-type silicon carbide epitaxial layer. - The surface layer of the silicon carbide epitaxial layer 4 is provided with a 2n-type -The second p-type silicon carbide epitaxial layer 4 is + The mold area 5 is, for example, 2.0 × 10 17 / cm 3 Above 2.0×10 18 / cm 3 The following impurity concentrations are used: The state up to this point is shown in FIG.

[0047] Next, the 2nd - On the surface of the silicon carbide epitaxial layer 4, a p-type base layer 6 is formed, for example, at a thickness of 5.0×10 16 / cm 3 Above 2.0×10 18 / cm 3 The p-type base layer 6 is formed by epitaxial growth at the following impurity concentration. After the p-type base layer 6 is formed by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the channel region of the p-type base layer 6. The p-type base layer 6 is also formed by epitaxial growth at the following impurity concentration. - Alternatively, the n-type silicon carbide epitaxial layer 4 may be epitaxially grown and then ion-implanted with a p-type impurity such as aluminum.

[0048] Next, an n-type source region 7 having a thickness of about 0.5 μm is formed on the surface of the p-type base layer 6 by, for example, 1.0×10 17 / cm 3 After the n-type source region 7 is formed by epitaxial growth, n-type impurities such as phosphorus (P) or nitrogen are further ion-implanted into the surface of the n-type source region 7, so that the surface layer of the n-type source region 7 is doped with n. + The source region 8 is, for example, 3.0×10 19 / cm 3 At this time, n + The thickness of the n-type source region 8 is + The thickness of the n-type source region 7 is formed so as to be thinner than the thickness of the portion sandwiched between the n-type source region 8 and the p-type base region 6. This prevents damage caused by ion implantation from remaining in the p-type base layer 6. +The n-type source region 8 can also be selectively formed by forming an ion implantation mask having a predetermined opening on the n-type source region 7 out of, for example, an oxide film, and using this oxide film as a mask by ion implantation.

[0049] Next, an ion implantation mask (not shown) having a predetermined opening is formed of, for example, an oxide film. Then, using this oxide film as a mask, p-type impurities, for example, aluminum atoms, are ion-implanted by an ion implantation method to form n-type source regions 7 and n + A part of the source region 8 is p ++ The contact area 9 is, for example, 1.0×10 20 / cm 3 The impurity concentration is formed as p ++ The impurity concentration of the p-type contact region 9 is higher than the impurity concentration of the p-type base region 6, and is 1.0×10 19 / cm 3 Above 5.0×10 20 / cm 3 It is preferable to form it so that: ++ The contact region 9 is formed so that its bottom surface reaches the p-type base layer 6. The state up to this point is shown in FIG.

[0050] Thus, in the embodiment, n + Since damage caused by ion implantation of the n-type source region 8 does not remain in the p-type base layer 6, the variation in threshold voltage can be reduced. In addition, since the channel layer is determined by the p-type base layer 6 formed by epitaxial growth with a thin film thickness, the variation in channel length remains low. In addition, the variation in impurity concentration due to ion implantation is small at about 3%, so that the n + This reduces the variation in the impurity concentration of the type source region 8, suppresses the variation in the contact resistance, and eliminates the need for evaluation of the quality of the result. In addition, since there is no epitaxial growth with a high impurity concentration, there is no effect on the epitaxial growth apparatus.

[0051] Next, n +A trench forming mask having a predetermined opening is formed on the surface of the source region 8 by photolithography, for example, an oxide film. Next, an n + A second n-type source region 8, an n-type source region 7, and a p-type base layer 6 are formed. - A trench 10 is formed so as to reach the silicon carbide epitaxial layer 4. Next, the trench forming mask is removed.

[0052] Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1750° C. to form the first p + Type area 3, 2nd p + type area 5, n + Type source region 8 and p ++ An activation process is then carried out on the mold contact region 9. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or each ion implantation may be activated by a heat treatment. The state up to this point is shown in FIG.

[0053] Next, n + Type source region 8 and p ++ A gate insulating film 11 is formed along the surface of the contact region 9 and the bottom and sidewalls of the trench 10. This gate insulating film 11 may be formed by thermal oxidation at a temperature of about 1300° C. in an oxygen atmosphere. Alternatively, this gate insulating film 11 may be formed by a method of deposition by a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO).

[0054] Next, a polycrystalline silicon film doped with, for example, phosphorus atoms is provided on the gate insulating film 11. This polycrystalline silicon film may be formed so as to fill the inside of the trench 10. This polycrystalline silicon film is patterned by photolithography and left inside the trench 10 to form the gate electrode 12. For the gate electrode 12, a p-type polycrystalline silicon film may be used.

[0055] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 11 and the gate electrode 12, forming an interlayer insulating film 13. The interlayer insulating film 13 and the gate insulating film 11 are patterned by photolithography. + Type source region 8 and p ++ A contact hole is formed exposing the mold contact region 9. The state up to this point is shown in FIG.

[0056] Next, a conductive film that will become the source electrode 16 is formed in the contact hole provided in the interlayer insulating film 13 and on the interlayer insulating film 13. The conductive film is, for example, a nickel (Ni) film. After that, a heat treatment is performed at a temperature of, for example, about 700° C. to selectively react the conductive film with silicon carbide, and then the unreacted conductive film is selectively removed to leave the source electrode 16 only in the contact hole, and n + Type source region 8 and p ++ The contact region 9 is brought into contact with a source electrode 16 .

[0057] Next, a metal layer to become the source electrode pad 14 is formed on the source electrode 16 on the front surface of the silicon carbide semiconductor substrate and on the interlayer insulating film 13 by, for example, a sputtering method. At this time, a barrier metal (not shown) made of titanium or titanium nitride may be formed first. The thickness of the metal layer on the interlayer insulating film 13 may be, for example, 5.5 μm. The metal layer may be made of, for example, aluminum containing silicon at a rate of 1% (Al-Si). Next, the metal film is selectively removed to form the source electrode pad 14.

[0058] Next, n + On the second main surface (rear surface) of the silicon carbide substrate 1, a conductive film serving as the drain electrode 15, for example, a molybdenum film and a nickel film, are successively formed by, for example, a sputtering method. Then, a heat treatment such as laser annealing is performed to form an n + The drain electrode is formed by reacting the silicon carbide substrate 1 with a conductive film to form an ohmic junction.

[0059] Next, a film of titanium, nickel and gold is formed in this order as a drain electrode pad (not shown) on the surface of the drain electrode 15. In this manner, the trench MOSFET 70 shown in FIG.

[0060] Here, Fig. 10 is a graph showing the measurement results of the impurity concentration in the A-A' portion of the silicon carbide semiconductor device according to the embodiment shown in Fig. 1. In Fig. 10, the horizontal axis shows the depth from the surface of the silicon carbide semiconductor substrate in µm, and the vertical axis shows the n-type or p-type impurity concentration in cm. -3 It is.

[0061] 10, the depth D1 is the point where the n-type impurity concentration is maximum, and D2 is the point where the n-type impurity concentration is half of D1. D3 is the boundary between the n-type source region 7 and the p-type base layer 6. The n-type impurity concentration is from the surface of the silicon carbide semiconductor substrate to a depth D2 (approximately 0.2 μm). + 10, the n-type source region 8 is located at a depth D3 (approximately 0.5 μm) and the n-type source region 7 is located at a depth D3 or greater and the p-type base layer 6 is located at a depth greater than the depth D3. + The n-type source region 8 has a profile in which the n-type impurity concentration gradually decreases from a depth D1 (approximately 0.17 μm) toward the n-type source region 7. For example, the impurity concentration is 1.0×10 19 / cm 3 to 1.0×10 17 / cm 3 The n-type source region 7 has a substantially constant n-type impurity concentration, and the p-type base layer 6 has a substantially constant p-type impurity concentration.

[0062] Figure 11 shows the +In this example, the n-type source region 8 is formed of two layers, a high concentration portion 8a on the surface side and a low concentration portion 8b on the n-type source region 7 side. Depth E1 is the point where the n-type impurity concentration is maximum in the high concentration portion 8a, and E2 is the point where the n-type impurity concentration is 1 / 2 of E1. Depth E3 is the point where the n-type impurity concentration is maximum in the low concentration portion 8b, and E4 is the point where the n-type impurity concentration is 1 / 2 of E3. E5 is the boundary between the n-type source region 7 and the p-type base layer 6. The high concentration portion 8a is from the surface of the silicon carbide semiconductor substrate to the depth E2, and the low concentration portion 8b is from the depth E2 to the depth E4. The n-type source region 7 is from the depth E4 to the depth E5 (about 0.5 μm), and the p-type base layer 6 is from the depth E5 onwards. As shown in FIG. 11, the depth E2 of the high concentration portion 8a is 0.1 μm or less. The depth E4 of the low concentration portion 8b is about 0.21 μm, which is thicker than the high concentration portion. The impurity concentration E1 in the high concentration portion 8a is 5.0×10 18 / cm 3 Above 5.0×10 19 / cm 3 or less, and the impurity concentration of E3 in the low-concentration portion 8b is 1.0×10 18 / cm 3 Above 5.0×10 18 / cm 3 Also, n + The n-type source region 8 has a profile in which the n-type impurity concentration gradually decreases from a depth E3 (approximately 0.16 μm) toward the n-type source region 7. For example, the impurity concentration is 1.0×10 18 / cm 3 to 1.0×10 17 / cm 3 The n-type source region 7 has a substantially constant n-type impurity concentration, and the p-type base layer 6 has a substantially constant p-type impurity concentration. + By forming the p-type source region 8 into two layers and making the n-type source region 7 side a low concentration portion, damage to the p-type base layer 6 during ion implantation can be minimized while keeping the contact resistance low.

[0063] 12 is a graph showing the results of measuring the contact resistance in the silicon carbide semiconductor device according to the embodiment and the conventional silicon carbide semiconductor device. In FIG. 12, the vertical axis represents n + The contact resistance of the n-type source region 8 is normalized by the average value, and the standard deviation is indicated by the error bar. + 15. This is a silicon carbide semiconductor device having the structure of FIG. 14 in which a type source region 8 is formed by epitaxial growth.

[0064] As shown in FIG. 12, in the silicon carbide semiconductor device according to the embodiment, n + By forming the type source region 8 by ion implantation, the variation (standard deviation) of the contact resistance can be reduced from 11.4% to 3.2%.

[0065] As described above, according to the embodiment, the n-type source region is formed by epitaxial growth. + The n-type source region is formed on the surface of the n-type source region by ion implantation. + The p-type source region has a profile in which the n-type impurity concentration gradually decreases toward the n-type source region. The n-type source region is designed to prevent damage caused by ion implantation from remaining in the p-type base layer. + Since ion implantation is performed on the p-type source region, the variation in threshold voltage can be reduced. The channel layer is determined by a p-type base layer formed by epitaxial growth with a thin film thickness, so the variation in channel length is low, and the n + The n-type source region is formed by ion implantation. + This makes it possible to reduce the variation in the impurity concentration of the type source region, and thus to suppress the variation in the contact resistance.

[0066] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions of each part and the impurity concentration are set in various ways according to the required specifications. In addition, in each of the above-mentioned embodiments, the case where silicon carbide is used as the wide band gap semiconductor is described as an example, but the present invention can also be applied to wide band gap semiconductors other than silicon carbide, such as gallium nitride (GaN). In addition, the present invention can also be applied to semiconductors other than wide band gap semiconductors, such as silicon (Si) and germanium (Ge). In addition, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention can be applied similarly even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0067] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and automobile igniters. [Explanation of symbols]

[0068] 1, 101 n + Silicon carbide substrate 2, 102 1st n - Silicon carbide epitaxial layer 3, 103 1st p. + type area 4, 104 2nd n - Silicon carbide epitaxial layer 5, 105 2nd p. + type area 6, 106 p-type base layer 7, 107 n-type source region 8, 108 n + Type Source Area 9, 109 p. ++ Mold Contact Area 10, 110 Trench 11, 111 Gate insulating film 12, 112 Gate electrode 13, 113 Interlayer insulating film 14, 114 Source electrode pad 15, 115 Drain electrode 16 Source electrode 70, 170, 171 Trench MOSFET 109a p + Mold Contact Area

Claims

1. a first conductivity type silicon carbide semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third semiconductor layer of a first conductivity type selectively provided on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the third semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer, the second semiconductor region being selectively provided in a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate side and penetrating the third semiconductor layer; a trench passing through the first semiconductor region, the second semiconductor layer, and the third semiconductor layer and reaching the first semiconductor layer; a gate electrode provided inside the trench via a gate insulating film; an interlayer insulating film provided on the gate electrode; a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; A second electrode provided on a back surface of the silicon carbide semiconductor substrate; Equipped with a first semiconductor region that is thinner than a portion of the third semiconductor layer that is sandwiched between the first semiconductor region and the second semiconductor layer, and an impurity concentration gradually decreases toward the third semiconductor layer.

2. A first conductivity type silicon carbide semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third semiconductor layer of a first conductivity type selectively provided on a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the third semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer, the second semiconductor region being selectively provided in a surface layer of the third semiconductor layer opposite to the silicon carbide semiconductor substrate side and penetrating the third semiconductor layer; a trench passing through the first semiconductor region, the second semiconductor layer, and the third semiconductor layer and reaching the first semiconductor layer; a gate electrode provided inside the trench via a gate insulating film; an interlayer insulating film provided on the gate electrode; a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region; A second electrode provided on a back surface of the silicon carbide semiconductor substrate; Equipped with the first semiconductor region is thinner than the third semiconductor layer in a portion sandwiched between the first semiconductor region and the second semiconductor layer, and comprises a high concentration portion on a front surface side and a low concentration portion on the third semiconductor layer side.

3. The maximum impurity concentration of the first semiconductor region is 1.0×10 18 / cm 3 Above 5.0 x 10 19 / cm 3 3. The silicon carbide semiconductor device according to claim 1, wherein:

4. The impurity concentration of the third semiconductor layer is 1.0×10 16 / cm 3 Above 1.0 x 10 18 / cm 3 4. The silicon carbide semiconductor device according to claim 1, wherein:

5. A first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than a silicon carbide semiconductor substrate on a front surface of the silicon carbide semiconductor substrate; a second step of forming a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third step of forming a third semiconductor layer of a first conductivity type by epitaxial growth on a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a fourth step of selectively forming a first semiconductor region of the first conductivity type by injecting a first conductivity type impurity into a surface layer of the third semiconductor layer on an opposite side to the silicon carbide semiconductor substrate; a fifth step of selectively forming a second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer, penetrating the third semiconductor layer, by injecting a second conductivity type impurity into a surface layer of the third semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a sixth step of forming a trench penetrating the first semiconductor region, the second semiconductor layer, and the third semiconductor layer and reaching the first semiconductor layer; a seventh step of forming a gate electrode inside the trench via a gate insulating film; an eighth step of forming an interlayer insulating film on the gate electrode; a ninth step of forming a first electrode on a surface of the second semiconductor layer and the first semiconductor region; A tenth step of forming a second electrode on a back surface of the silicon carbide semiconductor substrate; Including, a first semiconductor region formed on the first semiconductor layer and a second semiconductor layer formed on the second semiconductor layer, the first semiconductor region being thinner than a portion of the third semiconductor layer sandwiched between the first semiconductor region and the second semiconductor layer, and an impurity concentration gradually decreasing toward the third semiconductor layer.

6. a first step of forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, the first semiconductor layer having a lower impurity concentration than the silicon carbide semiconductor substrate; a second step of forming a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third step of forming a third semiconductor layer of a first conductivity type by epitaxial growth on a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a fourth step of selectively forming a first semiconductor region of the first conductivity type by injecting a first conductivity type impurity into a surface layer of the third semiconductor layer on an opposite side to the silicon carbide semiconductor substrate; a fifth step of selectively forming a second semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer, penetrating the third semiconductor layer, by injecting a second conductivity type impurity into a surface layer of the third semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a sixth step of forming a trench penetrating the first semiconductor region, the second semiconductor layer, and the third semiconductor layer and reaching the first semiconductor layer; a seventh step of forming a gate electrode inside the trench via a gate insulating film; an eighth step of forming an interlayer insulating film on the gate electrode; a ninth step of forming a first electrode on a surface of the second semiconductor layer and the first semiconductor region; A tenth step of forming a second electrode on a back surface of the silicon carbide semiconductor substrate; Including, the first semiconductor region is formed so as to be thinner than a portion of the third semiconductor layer sandwiched between the first semiconductor region and the second semiconductor layer; a second semiconductor layer formed on the first semiconductor layer and having a first impurity region on the first semiconductor layer side, the second semiconductor layer being electrically connected to the first impurity region and the first semiconductor layer being electrically connected to the first impurity region, the second semiconductor layer being electrically connected to the first impurity region and the first semiconductor layer being electrically connected to the first impurity region.

7. 7. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein in the fourth step, phosphorus or nitrogen is implanted as the impurity of the first conductivity type.

8. In the fourth step, the maximum impurity concentration of the first semiconductor region is 1.0×10 18 / cm 3 Above 5.0 x 10 19 / cm 3 7. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the following is formed:

9. In the third step, the impurity concentration of the third semiconductor layer is 1.0×10 16 / cm 3 Above 1.0 x 10 18 / cm 3 7. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the following is formed:

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