ICs with Trench-Based Metal-Insulator-Metal Capacitors

Abstract

An integrated circuit (IC) (200) includes a semiconductor surface layer (209) of a substrate (208) including a circuit (180) formed in the semiconductor surface layer configured with a metal-insulator-metal (MIM) capacitor (220). A multilevel metal stack on the semiconductor surface layer includes a bottom plate contact metal layer (240) including a bottom capacitor plate contact (240a). A first interlevel dielectric (ILD) layer (218) overlies the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, the trench being lined with a bottom capacitor plate (221a) having a capacitor dielectric layer (222a) thereover and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench (225). A second ILD layer (219) overlies the filled trench. A filled via (245a) through the second ILD layer provides contact to the top plate contact (224a) on the top capacitor plate.

Description

[Technical field]

[0001] This disclosure relates to integrated circuit (IC) devices having nonplanar metal-insulator-metal capacitors. [Background technology]

[0002] Metal-insulator-metal (MIM) capacitors are generally considered to be important passive components in IC devices, including radio frequency (RF) and analog ICs. MIM capacitors are gaining attention because of their high capacitance density and the relatively small chip area they offer, which increases circuit density and further reduces IC manufacturing costs.

[0003] For example, advanced analog circuit applications require voltage linearity of less than ±1 parts per million (ppm) and 1 fF / μm 2 Precision capacitors with capacitance densities exceeding 10 ... Summary of the Invention

[0004] This Summary explains in a simplified form concepts that are further described below in the Detailed Description, including the drawings provided. This Summary does not limit the scope of the claimed subject matter.

[0005] In some examples, an IC includes a semiconductor surface layer of a substrate including circuit elements formed in the semiconductor surface layer configured with a metal-insulator-metal (MIM) capacitor. A multilevel metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer overlies the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, the trench lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer overlies including the filled trench. A filled via through the second ILD layer provides contact to the top capacitor plate. [Brief description of the drawings]

[0006] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale.

[0007] [Figure 1] 1 is a flow chart illustrating steps in an example method of manufacturing an IC including at least one trench-based MIM capacitor, according to an example embodiment.

[0008] [Figure 2A] 2A-2G show successive cross-sectional views, with FIG. 2A showing a cross-sectional view of a first flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a metal fill for the fill material. [Figure 2B] 1A-1C show cross-sectional views of a first flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a metal fill for the filling material. [Figure 2C] 1A-1C show cross-sectional views of a first flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a metal fill for the filling material. [Figure 2D]1A-1C show cross-sectional views of a first flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a metal fill for the filling material. [Figure 2E] 1A-1C show cross-sectional views of a first flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a metal fill for the filling material. [Figure 2F] 1A-1C show cross-sectional views of a first flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a metal fill for the filling material. [Figure 2G] 1 illustrates a cross-sectional view of a first flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a metal fill for the filling material, showing the completed trench-based MIM capacitor.

[0009] [Figure 3A] 3A-3E show successive cross-sectional views, with FIG. 3A showing cross-sectional views for a second flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a dielectric fill for the fill material, in accordance with an exemplary embodiment. [Figure 3B] 1 illustrates a cross-sectional view for a second flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a dielectric fill for the fill material, according to an exemplary embodiment. [Figure 3C] 1 illustrates a cross-sectional view for a second flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a dielectric fill for the fill material, according to an exemplary embodiment. [Figure 3D] 1 illustrates a cross-sectional view for a second flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a dielectric fill for the fill material, according to an exemplary embodiment. [Figure 3E] 1 illustrates a cross-sectional view for a second flow option for forming an exemplary trench-based MIM capacitor on an IC utilizing a dielectric fill for the fill material, according to an exemplary embodiment.

[0010] [Figure 4] 1 illustrates an example IC including a trench-based MIM capacitor having a two-dimensional (2D) array of trenches. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Example embodiments are described with reference to the drawings, in which like reference numerals are used to indicate similar or equivalent elements. The illustrated order of acts or events is not limiting, as some acts or events may occur in different orders and / or contemporaneously with other acts or events. Also, some illustrated acts or events may not be required to implement the methodologies in accordance with the present description.

[0012] Additionally, the terms "coupled to" or "coupled with" (and the like) describe either an indirect or direct electrical connection. Thus, when a first device "couples" to a second device, the connection may be made through a direct electrical connection, where only parasitics are present in the path, or through an indirect electrical connection through intermediaries, including other devices and connections. In the case of an indirect coupling, the intermediaries generally do not alter the information in the signal, but may adjust its current levels, voltage levels, and / or power levels.

[0013] To conserve chip area, it may be desirable to provide an IC with an array of non-planar MIM capacitors that, unlike planar capacitors, include additional sidewall capacitance from the four walls to provide a higher capacitance (C) per unit area (C / A) beyond the C / A provided by conventional planar MIM capacitor structures. C / A values ​​for trench-based MIM capacitors are generally in the range of 2 to 10 fF / μm. 2 The trench-based MIM capacitor structure can optionally be formed on a field oxide, such as on a shallow trench isolation (STI) or on a local oxidation of silicon (LOCOS).

[0014] FIG. 1 is a flow chart showing steps in an exemplary method 100 of manufacturing an IC generally on a wafer, including a plurality of IC dies each including at least one trench-based MIM capacitor including a filled trench. FIG. 2G described below shows an IC (designated as IC 200) having a completed trench-based MIM capacitor, the features of which are shown with reference numbers used below to describe the method 100. More generally, a trench-based MIM includes a plurality of electrically interconnected filled trenches (see FIG. 4 described below). In addition to including a metal or metal alloy, the top and bottom metal plates of a trench-based MIM capacitor may include non-metallic atoms such as N (TaN or TiN) or Si. For example, the bottom plate may include TaN, Ti / TiN, TiN, Ni, Pt, Co, CoSi, or Ir, tungsten nitride (WN), or WCN (where WN or WCN may also act as a Cu diffusion barrier), and the top plate may also include TaN, TiN, Ni, Pt, Co, CoSi, or Ir.

[0015] Step 101 generally includes providing a semiconductor surface layer 209 (e.g., including an epitaxial layer) on a substrate 208 in the form of a wafer including a plurality of IC dies each including circuit elements 180 including circuit elements formed in the semiconductor surface layer 209 that may be configured on an IC 200 with a MIM capacitor 220 to realize at least one circuit function. The functional circuit elements 180 include circuit elements (including transistors, and generally diodes, resistors, capacitors, etc.) formed in the semiconductor surface layer 209 that are configured with a trench-based MIM capacitor 220 to realize at least one circuit function. Exemplary circuit functions include analog (e.g., amplifiers or power converters), radio frequency (RF), digital, or non-volatile memory functions.

[0016] A bottom plate contact metal layer includes a bottom plate contact 240a, shown by way of example only as a metal 1 (M1) layer 240, with a first interlevel dielectric (ILD) layer 218, and a second ILD layer 219 above M1 240. Although described as being an M1 layer 240, the bottom plate metal contact layer can be any metal interconnect level except for the top metal level. Some example metal levels can include copper, but are not limited to copper metal levels.

[0017] 2A-2G show a pre-metal dielectric (PMD) layer 211 on top of a semiconductor surface layer 209, shown as a p-epi layer, with an etch stop layer 212 on top of the PMD layer 211. On top of the etch stop layer 212 is a PMD cap dielectric layer 214, and a bottom plate contact metal layer, shown as M1 layer 240, is damascened into the PMD cap dielectric layer 214. Also shown is an etch stop layer 215 on top of the PMD cap dielectric layer 214 and the M1 layer.

[0018] The plates of the trench-based MIM capacitor may be coupled to a node within the circuit element 180. However, it is also possible to provide the plates of the trench-based MIM capacitor as separate pins of the IC. Exemplary circuit functions include analog (e.g., an amplifier or power converter), radio frequency (RF), digital, or non-volatile memory functions. The substrate 208 and / or the semiconductor surface layer 209 may include silicon, silicon germanium, or another semiconductor material.

[0019] The capabilities of the circuit elements 180 provided on the IC can vary, for example, from simple apparatus to complex devices. The particular functionality contained within the circuit elements 180 is not important. The circuit elements are generally formed within a semiconductor surface layer 209 of a substrate 208 prior to forming the trench-based MIM capacitor.

[0020] In steps 102-108, described below, a trench-based MIM capacitor is formed on the bottom plate contact. Figure 2A is a cross-sectional view of an in-process IC after step 102, which includes etching through first ILD layer 218 to form at least one trench 237 that exposes a top surface of bottom plate contact 240a. First ILD layer 218 may be 2kA to 7kA thick, such as about 3kA thick. The etch of step 102 generally includes a masked etch. This mask level represents the only additional mask level required to add a trench-based MIM capacitor to an IC process that already has a multilevel metal stack.

[0021] The bottom plate contact 240a includes an optional surrounding shielding that is connected to a circuit node in the IC to avoid strays that may cause additional noise, where the shielding may include a metal portion 240b that is coupled by a metal filled contact 207 (e.g., including W) shown with a liner 207a (e.g., a refractory metal containing liner) that is coupled to a p+ contact 206 in the semiconductor surface layer 209 if the semiconductor surface layer 209 is p-type. Also shown below the bottom plate contact 240a is an optional field dielectric shown as a shallow trench isolation (STI) 203. The field dielectric may be a localized oxidation of silicon (LOCOS).

[0022] Step 103 includes deposition in trench 237 including bottom capacitor plate layer 221, then at least one capacitor dielectric layer 222, then top capacitor plate layer 223, with the IC result in process shown in Figure 2B. As mentioned above, bottom capacitor plate layer 221 and top capacitor plate layer 223 may each be selected from a variety of conductive materials such as Ta, Ti, TaN, TiN, Ni, W, WN, Pt, Co, CoSi, or Ir, and each of these layers is generally between 50 Å and 500 Å thick.

[0023] The capacitor dielectric layer 222 is generally formed by a deposition process such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD), and may include a single layer or a dielectric stack having two or more dielectric layers. The capacitor dielectric layer 222 may include a high-k dielectric layer, as defined herein, having a k-value (k>7) of at least silicon nitride, such that its k-value exceeds the k-value of silicon dioxide (k-value of 3.9), silicon dioxide-nitride-silicon dioxide (ONO), NON, oxide, nitride, referred to herein as silicon nitride or SiON, or a multi-layer dielectric stack (e.g., ONON or ONO). One capacitor dielectric stack includes ONO. The total thickness of the capacitor dielectric layer 222 is generally in the range of 20 Å to 2,000 Å.

[0024] The nitride layer (e.g., silicon nitride or silicon oxynitride) of the capacitor dielectric stack may have a hydrogen concentration of ≦18 atomic %. This hydrogen concentration in the nitride layer is low compared to the hydrogen concentration in conventional silicon nitride or silicon oxynitride layers, which is generally 20-30 atomic %. It is recognized herein that a relatively low hydrogen content in the nitride layer in the capacitor dielectric stack provides improved voltage linearity for the MIM capacitor, including a low |β| value and a low |(α)| value.

[0025] The deposition process for obtaining the low hydrogen concentration nitride layer may involve CVD such as LPCVD or PECVD, the gas used being N 2 At least one nitrogen compound other than N 2 A nitrogen source containing N 2 The mass flow rate of the nitrogen source is at least 51% of the mass flow rate of the nitrogen source. As a specific example, PECVD silicon nitride can be deposited at a deposition temperature range of 300° C. to 500° C. with a N 2 Mass flow rate: 200sccm to 1,000sccm NH 3 Mass flow rate: 20sccm to 200sccm of SiH 4Deposition may be performed at a mass flow rate, at a pressure of 2-6 Torr, while applying RF low frequency (LF) power and RF high frequency (HF) power. The RF-LF power may be in the frequency range of 50 kHz to about 500 kHz, e.g., 400 kHz with a power range of 10 W to 200 W, and the RF-HF power may be in the frequency range of 10 MHz or higher, e.g., 13.65 MHz with a power range of 50 W to 400 W.

[0026] Step 104 includes filling the trench with at least one fill material to form a filled trench 225. FIG. 2C shows the in-process IC after step 104, where the fill material is shown as a metal layer 224, such as including W, Cu, Al, Ni, or Ta. For a metal fill material, an example thickness range is 2kA to 3kA. Step 105 includes removing the fill material 224 laterally of the filled trench 225, and then a portion of the first ILD layer 218, with the in-process result shown in FIG. 2D, defining a top capacitor plate 223 to form a top capacitor plate 223a, defining a capacitor dielectric layer 222 to form a patterned capacitor dielectric layer 222a, and defining a bottom capacitor plate layer 221 to form a bottom capacitor plate 221a and expose a contact to the top capacitor plate, shown as top capacitor plate 224a. The removing may include a chemical mechanical polishing (CMP) or etching process. The removing may be a single pass or multi-pass CMP or may be an etching process. The target range for the thickness of the filled trench 225 / first ILD layer 218 after etchback or CMP that defines the height of the trench-based MIM capacitor may be nominally about 1.7 kA, varying in height to have a height generally between 1.5 kA and 3.0 kA depending on the initial thickness of the first ILD layer 218 and the etching or CMP process.

[0027] Step 106 includes forming a second ILD layer 219, including over the filled trench 225, the result of which is shown in FIG. 2E. A CVD-based deposition process may be used to form the second ILD layer 219, such as using a TEOS-based deposition process. Step 107 includes etching vias, including a via 231 through the second ILD layer 219 to reach the top plate contact 224a, and another via 232 through both the second ILD layer 219 and the first ILD layer 218, and optionally to reach the metal shield portion 240b of the metal shield, the in-process IC result being shown in FIG. 2F. The vias 231, 232 shown have relatively wide tops relative to their narrow bottoms. This shape is similar to that of the C 5 F 8 / O 2 This can be achieved using a baseline etch chemistry such as utilizing .OMEGA. / Ar, which can provide a tapered via profile.

[0028] Step 108 involves filling the vias 231, 232 with a metal 2 (M2) layer 245 including via plug 245a contacting the top plate contact 224a and via plug 245b contacting the metal shield portion 240b, with the in-process IC result shown in Figure 2F. Although not shown, contact to the bottom plate contact 240a is generally provided by a metal-to-via connection to a bottom plate contact metal layer shown as M1 layer 240 similar to the contact made to the metal shield portion 240b.

[0029] Wafer processing may then be completed by conventional back-end-of-the-line (BEOL) processing, which generally includes forming one or more additional metal levels (e.g., M3, M4, ...), including a top metal level that provides bond pads. The top metal layer may include aluminum (or an aluminum alloy) or copper. A protective overcoat (PO) generally follows, and then the PO layer is patterned to expose the bond pads. The PO layer may include silicon oxide, silicon nitride, or SiON.

[0030] 3A-3E show sequential cross-sectional views of a second flow option for forming an example trench-based MIM capacitor on an IC that utilizes a dielectric fill material 324 (instead of the metal fill material described above for FIGS. 2A-2G) to form a filled trench, according to an example embodiment. FIG. 3A shows the IC in process after depositing an etch stop layer 312, and then the dielectric fill material 324 over the in-process IC structure shown in FIG. 2B described above. The dielectric fill material 324 can be deposited by a TEOS-based process. The thickness range of the dielectric fill material 324 can be 5 kA to 8 kA, such as 7 kA to 7.5 kA (before CMP or etching).

[0031] As discussed above, step 105 includes removing the fill material, which in this embodiment is a dielectric fill material 324, which is lateral to the filled trench and is part of the first ILD 218. This step also includes defining a top capacitor plate layer 223 to form a top capacitor plate layer 223, defining a capacitor dielectric layer 222 to form a patterned capacitor dielectric layer 222, defining a bottom capacitor plate layer 221 to form a bottom capacitor plate layer 221, and exposing a contact to the top capacitor plate, shown as top capacitor plate contact 324a, with the result in the process shown in Figure 3B including the filled trench 325. The removing may include a chemical mechanical polishing (CMP) or etching process.

[0032] Similar to the metal fill process described above, step 106 includes forming a second ILD layer, now shown as 319, including over the filled trench with the result shown in Figure 3C. Step 107 includes etching a via 331 through second ILD layer 219 and etch stop layer 312 to form a patterned etch stop layer 312a to reach top capacitor plate 223a to provide contact, and another via 332 through second ILD layer 219 and first ILD layer 218 to reach metal portion 240b of the metal shield, with the in-process IC result after step 107 being shown in Figure 3D. Step 108 involves filling the vias 331, 332 with a metal layer with via plug 245a directly contacting the top capacitor plate 223a and via plug 245b also contacting metal layer 240b, and the in-process IC result is shown in Figure 3E as IC 300 having MIM capacitor 320 shown as a MIM capacitor. As with IC 200 described above, although not shown, contact to the bottom plate contact 240a is generally provided by a metal-to-via connection to M1 layer 240, similar to the contact made to metal shield portion 240b.

[0033] Although a trench-based MIM capacitor may be composed of a single trench, a trench-based MIM capacitor may include a 2D array of filled trenches to maximize capacitance with contributions from each filled trench from both their sidewalls and bottom. Figure 4 shows an example IC 400 that includes a trench-based MIM capacitor 420 having an interconnected 2D array of filled trenches in one of its dimensions shown as 425a, 425b, 425c, and 425d.

[0034] The 3D topography enabled by the trench-based MIM capacitor integration scheme described herein can achieve C / A ratios up to 20 times greater than can be achieved by conventional planar MIM capacitors. The higher the aspect ratio (AR) of the trench, the greater the capacitance provided. Trench-based MIM capacitors typically achieve >1.5 fF / μm 2 The capacitance / area (C / A) value is, for example, 2 fF / μm 2 ~10fF / μm 2 C / A values ​​in the range of 3 to 5 fF / μm in some cases 2 to provide.

[0035] In conventional ICs with multi-level metal stacks, the via trench and CMP process already available as part of the copper BEOL process can be utilized to realize the trench-based MIM capacitor with only one additional mask, which is for the trench etch. Conventional barrier layer materials for copper (e.g., Ta / TaN) can be used as the top plate 223a and bottom capacitor plate 221a for the trench-based MIM capacitor. Due to the additional thickness of the trench-based MIM capacitor due to the thickness of the bottom capacitor plate 221a, the thickness of the patterned capacitor dielectric layer 222a, and the thickness of the top plate 223a, the height to contact the top plate 223 is reduced, which is smaller than the total height (M2 245 to M1 240) of the via trench used by the shielding including the metal portion 240b. In the case of IC 200, the height of the via trench to contact the top plate 223a is even smaller than that of IC 300 due to the added thickness of the top plate contact 224a on top of the top plate 223a. Thus, for either IC 200 or 300, a more robust capacitor is created by reducing the chance of a short between the top plate 223a and the bottom capacitor plate 221a of the trench-based MIM capacitor, rather than the entirety of a conventional via trench (M2 245-M1 240). The reduced trench depth also allows for a more uniform deposition of the capacitor dielectric layer 222, forming a more uniform patterned capacitor dielectric layer 222a and plates 221a, 223a on the trench sidewalls, thereby reducing capacitance variation for the trench-based MIM capacitor.

[0036] As mentioned above, after top electrode deposition, the trench can be filled with a dielectric material or filled with a metal. This flexibility in fill material allows for easier process integration while reducing contamination concerns, and reduces issues with etch topography and alignment. As mentioned above, alternative materials such as Ti / TiN can be used as the top electrode to allow the trench to be filled with W, reducing alignment issues and equivalent series resistance (ESR). Using TiN over TaN for the bottom plate can also improve the symmetry of the capacitor characteristics over the voltage range, since the top and bottom interfaces are the same.

[0037] Aspects of the present disclosure may be used to form semiconductor dies that may be integrated into various assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and / or layers thereon, including barrier layers, dielectric layers, device structures, active elements, and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Additionally, the semiconductor die may be formed from a variety of processes including bipolar, insulated gate bipolar transistor (IGBT), CMOS, BiCMOS, and MEMS.

[0038] Those skilled in the art having reference to this description will appreciate that many other embodiments are possible within the scope of the claimed invention, and that further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this description.

Claims

1. 1. A method for manufacturing an integrated circuit (IC) including a metal-insulator-metal (MIM) capacitor, comprising: providing a semiconductor surface layer on a substrate including circuit elements formed in the semiconductor surface layer, the bottom plate contact metal layer including a bottom plate contact having a first interlevel dielectric (ILD) layer over the bottom plate contact metal layer; Forming a MIM capacitor, comprising: etching through the first ILD layer to form a trench exposing a top surface of the bottom plate contact; depositing a bottom capacitor plate layer, then a capacitor dielectric layer, and then a top capacitor plate layer in the trench; filling the trench with at least one fill material to form a filled trench; removing the fill material laterally of the filled trench and then removing a portion of the first ILD layer, the removing including defining the top capacitor plate layer to form a top capacitor plate and defining the bottom capacitor plate layer to form a bottom capacitor plate; forming the MIM capacitor, forming a second ILD layer including over the filled trench; forming a filled via through the second ILD layer to allow contact to the top capacitor plate; A method comprising:

2. 2. The method of claim 1 , the capacitor dielectric layer comprises a dielectric stack including a first silicon dioxide layer, a nitride layer, and a second silicon dioxide layer; The method, wherein depositing the nitride layer comprises low pressure chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD), or atomic layer deposition (ALD).

3. 2. The method of claim 1 , The method wherein the capacitor dielectric layer has a thickness of between 20 Å and 2,000 Å.

4. 2. The method of claim 1 , The method, wherein the fill material comprises tungsten.

5. 2. The method of claim 1 , The method, wherein the fill material comprises a dielectric material.

6. 2. The method of claim 1 , the bottom capacitor plate layer and the top capacitor plate layer both comprise a refractory metal selected from the group consisting of Ta, Ti, TaN, TiN, Ni, W, WN, Pt, Co, CoSi, and Ir, and the bottom capacitor plate layer and the top capacitor plate layer both have a thickness between 50 Å and 500 Å.

7. 2. The method of claim 1 , The method, wherein the bottom plate contact metal layer is in a metal 1 layer and the filled via is in a metal 2 layer.

8. 2. The method of claim 1 , The MIM capacitor has a capacitance of 2 to 10 fF / μm ２ and providing a capacitance / area (C / A) value where C / A is a

9. 2. The method of claim 1 , The method, wherein the semiconductor surface layer beneath the MIM capacitor comprises shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

10. 1. An integrated circuit (IC), comprising: a semiconductor substrate including a semiconductor surface layer and circuit elements including circuit elements formed in the semiconductor surface layer configured with a metal-insulator-metal (MIM) capacitor; a multilevel metal stack on the semiconductor surface layer, the multilevel metal stack including a bottom plate contact metal layer including a bottom capacitor plate contact and a first interlevel dielectric (ILD) layer on the bottom plate contact metal layer; Including, The MIM capacitor is a trench in the first ILD layer above the bottom capacitor plate contact, the trench being lined with a bottom capacitor plate having a capacitor dielectric layer thereover and a top capacitor plate on the capacitor dielectric layer; a fill material filling the trench to form a filled trench; a second ILD layer including over the filled trench; a filled via through the second ILD layer providing contact to the top capacitor plate; Including, The MIM capacitor is located on a bottom plate contact on a pre-metal dielectric layer formed over the semiconductor substrate.

11. 11. The IC of claim 10, the fill material comprises tungsten, and the filled via extends to the tungsten to provide contact to the top capacitor plate.

12. 11. The IC of claim 10, The IC, wherein the fill material comprises a dielectric material and the filled via extends through the fill material.

13. 11. The IC of claim 10, an IC, wherein said bottom capacitor plate and said top capacitor plate both comprise a refractory metal selected from the group consisting of Ta, Ti, TaN, TiN, Ni, W, WN, Pt, Co, CoSi, and Ir.

14. 11. The IC of claim 10, The MIM capacitor has a capacitance of 2 to 10 fF / μm ２ The IC provides a capacitance / area (C / A) value of

15. 11. The IC of claim 10, The capacitor dielectric layer comprises a dielectric stack including a first silicon dioxide layer, a nitride layer, and a second silicon dioxide layer.

16. 11. The IC of claim 10, The thickness of the capacitor dielectric layer is between 20 Å and 2,000 Å.

17. 11. The IC of claim 10, the bottom plate contact metal layer is in a metal 1 layer and the filled via is in a metal 2 layer.

18. 11. The IC of claim 10, the bottom capacitor plate and the top capacitor plate both comprise a refractory metal selected from the group consisting of Ta, Ti, TaN, TiN, Ni, W, WN, Pt, Co, CoSi, and Ir; the bottom capacitor plate and the top capacitor plate each have a thickness between 50 Å and 500 Å.

19. 11. The IC of claim 10, The IC, wherein the bottom plate contact metal layer comprises copper.

20. 11. The IC of claim 10, The MIM capacitor comprises a two-dimensional array of the filled trenches.

21. 11. The IC of claim 10, The capacitor dielectric layer comprises a dielectric stack, and further comprises an etch stop layer within the dielectric stack.

22. The IC of claim 10, the bottom plate contact overlies a field dielectric layer formed on the semiconductor surface layer.

23. 23. The IC of claim 22, The IC, wherein the field dielectric layer is shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

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