Field effect transistor and its manufacturing method

Abstract

To provide a field effect transistor in which electric field concentration at the lower end of a trench can be suppressed and the on-state voltage can be reduced.SOLUTION: There is provided a field effect transistor that has a semiconductor substrate (12) provided with a plurality of trenches (20) in an upper surface, and gate electrodes (24) arranged in the trenches. A plurality of breakdown voltage areas (48) are provided in each inter-trench range (28). The plurality of breakdown voltage areas are arranged so as to form a plurality of rows (49) extending in a first direction that intersects the plurality of trenches. The plurality of rows are arranged spaced apart in a second direction that is parallel to the trenches. The breakdown voltage areas extend from above the lower ends of the trenches to below the lower ends of the trenches, and are arranged spaced apart from gate insulating films (22). The drift areas are in contact with the gate insulating films at positions between the breakdown voltage areas and the gate insulating films.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a field effect transistor.

[0002] The field effect transistor disclosed in Patent Document 1 has multiple p-type deep layers protruding downward from the body region. Each deep layer extends in a direction intersecting each trench. Each deep layer is arranged at intervals in a direction parallel to each trench. Each deep layer extends from above the bottom end of each trench to below the bottom end of each trench. With this configuration, a depletion layer extends from each deep layer to the drift region, suppressing electric field concentration at the bottom end of each trench. This makes it possible to protect the gate insulating film from the electric field at the bottom end of each trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-194065 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the field effect transistor of Patent Document 1, each deep layer is in contact with the side surface of the trench (i.e., the gate insulating film) below the body region. Therefore, electrons that have passed through a channel formed in the body region cannot flow from the body region to the deep layer below it. In other words, the electrons flow to the drift region, bypassing the deep layer. For this reason, the field effect transistor of Patent Document 1 has a problem of high on-voltage. This specification proposes a field effect transistor that can suppress electric field concentration at the bottom end of the trench and reduce the on-voltage. [Means for solving the problem]

[0005] The field effect transistor disclosed in this specification includes a semiconductor substrate (12) having a plurality of trenches (20) on an upper surface thereof, a gate insulating film (22) covering the inner surface of the trench, and a gate electrode (24) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes a plurality of n-type source regions (40), a p-type body region (42), an n-type drift region (44), and a plurality of p-type breakdown voltage regions (48). Each of the ranges of the semiconductor substrate located between the plurality of trenches is an inter-trench range (28). Each of the plurality of source regions is provided within the corresponding inter-trench range and contacts the corresponding gate insulating film. The body region extends across each of the inter-trench ranges and contacts each of the gate insulating films below the source region within each of the inter-trench ranges. The drift region is distributed across a range from within the inter-trench area to below the trenches, and contacts the gate insulating films below the body region. A plurality of the voltage withstanding regions are provided within the inter-trench area. The voltage withstanding regions are arranged to form a plurality of rows (49) extending along a first direction intersecting the trenches. In each row, the voltage withstanding regions are arranged at intervals in the first direction. The rows are arranged at intervals in a second direction parallel to the trenches. The voltage withstanding regions have a higher p-type impurity concentration than the body region, extend from above the bottom end of each trench to below the bottom end of each trench, and are arranged at intervals from the gate insulating films. The drift region contacts the gate insulating film at a position between each of the voltage withstanding regions and each of the gate insulating films.

[0006] In this field effect transistor, the p-type voltage-resistant regions extend from above the lower end of each trench to below the lower end of each trench at a position spaced apart from each gate insulating film. When this field effect transistor is turned off, a depletion layer extends from each voltage-resistant region into the drift region. Although each voltage-resistant region is disposed at a position spaced apart from each gate insulating film, the depletion layer can extend from each voltage-resistant region to the periphery of the lower end of the trench because the p-type impurity concentration of each voltage-resistant region is high. Therefore, electric field concentration at the lower end of each trench is suppressed, and the gate insulating film is protected from the electric field. Also, in this field effect transistor, the drift region is in contact with the gate insulating film at a position between each voltage-resistant region and each gate insulating film. Therefore, when this field effect transistor is turned on, electrons that have passed through the channel formed in the body region can flow to the drift region without being hindered by the voltage-resistant region. Therefore, this field effect transistor has a low on-resistance. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view of a MOSFET according to an embodiment, seen from above (a source electrode and an interlayer insulating film are omitted); [Diagram 2] Cross-sectional view taken along line II-II in Figures 1, 4, and 5. [Diagram 3] Cross-sectional view taken along line III-III in Figures 1, 4 and 5. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIGS. [Diagram 5] 4 is a cross-sectional view taken along line VV in FIGS. 1 to 3. FIG. [Figure 6] FIG. 3 is a diagram showing the distribution of equipotential lines in the cross section of FIG. 2. [Figure 7] FIG. 1 is an explanatory diagram of a MOSFET manufacturing method (a plan view of a semiconductor substrate). [Figure 8] FIG. 3 is an explanatory diagram of a method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 9] FIG. 3 is an explanatory diagram of a method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 10]FIG. 3 is an explanatory diagram of a method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 11] FIG. 3 is an explanatory diagram of a method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 12] FIG. 3 is an explanatory diagram of a method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 13] 10 is an explanatory diagram of a modified example of the method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 14] 10 is an explanatory diagram of a modified example of the method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 15] 10 is an explanatory diagram of a modified example of the method for manufacturing a MOSFET (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 16] 3 is a cross-sectional view of a MOSFET according to a first modification, corresponding to FIG. 2 (a cross-sectional view of a portion corresponding to FIG. 2). [Figure 17] 2 (a cross-sectional view of a portion corresponding to FIG. 2 ) of a MOSFET according to a second modification. [Figure 18] 2 (a cross-sectional view of a portion corresponding to FIG. 2) of a MOSFET according to a third modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The field effect transistor of the example disclosed herein may further include a plurality of p-type bottom regions (50). Each of the bottom regions may have a lower p-type impurity concentration than each of the voltage withstanding regions. Each of the bottom regions may contact the gate insulating film at the lower end of the corresponding trench and be spaced apart from each of the voltage withstanding regions.

[0009] According to this configuration, the bottom region can more effectively suppress the electric field concentration at the lower end of the trench.

[0010] In the field effect transistor disclosed in the present specification, the drift region may have a low concentration region (44b) and a high concentration region (44a) having a higher n-type impurity concentration than the low concentration region. The high concentration region may be distributed from a position contacting the body region to a position below the lower end of each trench, and contact each gate insulating film at a position between each voltage-resistant region and each gate insulating film. The low concentration region may contact the high concentration region from below.

[0011] This specification proposes a method for manufacturing any of the above field effect transistors, which may include the steps of forming a mask (80) extending in a lattice pattern on an upper surface of the semiconductor substrate, and forming a plurality of the voltage-withstanding regions in the semiconductor substrate by injecting a p-type impurity into the semiconductor substrate through the mask.

[0012] According to this configuration, since the mask is formed in a lattice pattern, the mask can be stably formed, that is, the mask can be prevented from partially collapsing, and therefore, a field effect transistor can be suitably manufactured.

[0013] The manufacturing method disclosed herein may further include a step of forming a trench in the top surface of the semiconductor substrate, and forming the body region and the bottom region by injecting p-type impurities into the top surface of the semiconductor substrate and a bottom surface of the trench.

[0014] According to this manufacturing method, the body region and the bottom region can be formed simultaneously. EXAMPLES

[0015] 1 to 5 show a metal oxide semiconductor field effect transistor (MOSFET) 10 according to the embodiment. The MOSFET 10 has a semiconductor substrate 12. In the following description, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, a direction perpendicular to the z direction is referred to as the x direction, and a direction perpendicular to the z direction and the x direction is referred to as the y direction. The x direction and the y direction are parallel to an upper surface 12a and a lower surface 12b of the semiconductor substrate 12.

[0016] As shown in Figures 1 to 3, a plurality of trenches 20 are provided in an upper surface 12a of a semiconductor substrate 12. As shown in Figure 1, each trench 20 extends linearly in the y direction. The plurality of trenches 20 are arranged at intervals in the x direction. Hereinafter, within the semiconductor substrate 12, a range sandwiched between the plurality of trenches 20 is referred to as an inter-trench range 28.

[0017] The inner surface of each trench 20 is covered with a gate insulating film 22. A gate electrode 24 is disposed in each trench 20. Each gate electrode 24 is insulated from the semiconductor substrate 12 by the gate insulating film 22. The upper surface of each gate electrode 24 is covered with an interlayer insulating film 26.

[0018] 2 to 5, a source electrode 30 is disposed on the upper surface 12a of the semiconductor substrate 12. The source electrode 30 covers the interlayer insulating film 26 and the upper surface 12a of the semiconductor substrate 12. The source electrode 30 is in contact with the upper surface 12a of the semiconductor substrate 12 in an area where the interlayer insulating film 26 is not present. The source electrode 30 is insulated from the gate electrode 24 by the interlayer insulating film 26.

[0019] The drain electrode 32 is disposed on the lower surface 12b of the semiconductor substrate 12. The drain electrode 32 contacts substantially the entire area of ​​the lower surface 12b of the semiconductor substrate 12.

[0020] As shown in FIGS. 1 to 5, the semiconductor substrate 12 has a plurality of source regions 40, a body region 42, a drift region 44, a drain region 46, a plurality of voltage-withstanding regions 48, and a plurality of bottom regions 50.

[0021] As shown in FIGS. 1 to 3, each source region 40 is an n-type region and has a relatively high n-type impurity concentration. Each source region 40 is disposed within a corresponding inter-trench area 28. Two source regions 40 are provided within each inter-trench area 28. Each source region 40 is disposed at a position adjacent to the corresponding trench 20. As shown in FIG. 1, each source region 40 extends long in the y direction along the trench 20. As shown in FIGS. 2 and 3, each source region 40 contacts the gate insulating film 22 at the upper end of the corresponding trench 20. Each source region 40 is in ohmic contact with the source electrode 30.

[0022] The body region 42 is a p-type region. As shown in FIGS. 2 and 3, the body region 42 extends across a plurality of inter-trench ranges 28. The body region 42 has a plurality of contact regions 42a and low-concentration regions 42b. Each contact region 42a has a higher p-type impurity concentration than the low-concentration region 42b. Each contact region 42a is disposed between two source regions 40 in the corresponding inter-trench range 28. Each contact region 42a is in ohmic contact with the source electrode 30. As shown in FIG. 1, each contact region 42a extends long in the y direction along the trench 20. As shown in FIGS. 2 and 3, the low-concentration region 42b is distributed across a plurality of inter-trench ranges 28. In each inter-trench range 28, the low-concentration region 42b contacts the contact region 42a and the source region 40 from below. The low-concentration region 42b contacts the gate insulating film 22 below each source region 40.

[0023] The drift region 44 is an n-type region having a lower n-type impurity concentration than the source region 40. As shown in FIGS. 2 and 3, the drift region 44 contacts the body region 42 (more specifically, the low concentration region 42b) from below. The drift region 44 contacts the gate insulating film 22 below the body region 42. The drift region 44 is separated from the source region 40 by the body region 42. The drift region 44 is distributed from within each inter-trench range 28 to a range below each trench 20. In the range below each trench 20, the drift region 44 is widely distributed in the lateral direction. The drift region 44 has a high concentration region 44a and a low concentration region 44b. The high concentration region 44a has a higher n-type impurity concentration than the low concentration region 44b. The high concentration region 44a contacts the body region 42 (more specifically, the low concentration region 42b) from below. The high concentration region 44a is distributed from a position contacting the body region 42 to below the lower end of each trench 20. The low concentration region 44b is disposed below the lower end of each trench 20. The low concentration region 44b is in contact with the high concentration region 44a from below. The low concentration region 44b is distributed widely in the lateral direction across each area below each inter-trench area 28.

[0024] The drain region 46 is an n-type region having a higher n-type impurity concentration than the drift region 44. The drain region 46 contacts the drift region 44 (more specifically, the low concentration region 44b) from below. The drain region 46 is disposed in a range including the lower surface 12b of the semiconductor substrate 12. The drain region 46 is in ohmic contact with the drain electrode 32.

[0025] The multiple voltage-withstanding regions 48 are p-type regions having a higher p-type impurity concentration than the body region 42. As shown in FIG. 2, each voltage-withstanding region 48 is disposed within a corresponding inter-trench region 28. Each voltage-withstanding region 48 is disposed within a range surrounded by the drift region 44 (more specifically, the high-concentration region 44a). As shown in FIG. 1, multiple voltage-withstanding regions 48 are provided within each inter-trench region 28. Within each inter-trench region 28, the voltage-withstanding regions 48 are arranged at intervals in the y direction (i.e., a direction parallel to the trenches 20). A row 49 is formed by linearly arranging the multiple voltage-withstanding regions 48 arranged within different inter-trench regions 28 along the x direction (a direction intersecting the multiple trenches 20). Within each row 49, the multiple voltage-withstanding regions 48 are arranged at intervals in the x direction. A multiple number of rows 49 (i.e., rows extending in the x direction) of the voltage-withstanding regions 48 are formed in the semiconductor substrate 12. Each row 49 is arranged at intervals in the y direction. As shown in FIG. 2, each of the voltage-resistant regions 48 extends from a position above the lower end of each of the trenches 20 to a position below the lower end of each of the trenches 20. A space C1 is provided between each of the voltage-resistant regions 48 and the gate insulating film 22. Therefore, each of the voltage-resistant regions 48 does not contact the gate insulating film 22. The drift region 44 (more specifically, the high-concentration region 44a) is disposed in the space C1. In the space C1, the drift region 44 (more specifically, the high-concentration region 44a) contacts the gate insulating film 22. Each of the voltage-resistant regions 48 is separated from the body region 42. Each of the voltage-resistant regions 48 is floating in the drift region 44. Also, as shown in FIG. 3, in a position where the voltage-resistant region 48 is not provided, the drift region 44 (more specifically, the high-concentration region 44a) contacts the gate insulating film 22 below the body region 42.

[0026] The bottom regions 50 are p-type regions having a p-type impurity concentration lower than the breakdown voltage region 48. The p-type impurity concentration of each bottom region 50 is substantially equal to the p-type impurity concentration of the body region 42. As shown in FIGS. 2 and 3, each bottom region 50 is disposed at the bottom of the corresponding trench 20. Each bottom region 50 contacts the gate insulating film 22 at the bottom surface of the corresponding trench 20. The drift region 44 contacts the side and bottom surfaces of each bottom region 50. Each bottom region 50 is floating in the drift region 44. Each bottom region 50 extends from the lower end of each trench 20 to a depth reaching the low concentration region 44b. As shown in FIG. 5, each bottom region 50 extends continuously in the y direction along the trench 20. Each bottom region 50 contacts the gate insulating film 22 over substantially the entire area of ​​the bottom surface of the corresponding trench 20. As shown in FIG. 2, a gap is provided between each bottom region 50 and the breakdown voltage region 48. Therefore, each bottom region 50 does not contact the voltage-withstanding region 48 .

[0027] Next, the operation of the MOSFET 10 will be described. When a potential equal to or higher than the threshold is applied to the gate electrode 24, a channel is formed in the body region 42 near the gate insulating film 22. When a potential higher than that of the source electrode 30 is applied to the drain electrode 32 while the channel is formed, electrons flow from the source region 40 to the drain region 46 through the channel and the drift region 44. That is, the MOSFET 10 is turned on. In the cross section shown in FIG. 3 where the withstand voltage region 48 does not exist, the electrons that have passed through the channel flow downward in the drift region 44 as shown by the arrow 102. In the cross section shown in FIG. 2 where the withstand voltage region 48 exists, the withstand voltage region 48 does not contact the gate insulating film 22 at the bottom of the body region 42, so that the electrons that have passed through the channel flow downward through the drift region 44 in the interval C1 as shown by the arrow 100 in FIG. 2. In this way, in the MOSFET 10 of the embodiment, the p-type withstand voltage region 48 does not contact the gate insulating film 22, so that the electrons that have passed through the channel can flow downward along the side of the trench 20. For this reason, the on-resistance of the MOSFET 10 is low.

[0028] Moreover, when the MOSFET 10 is in an on state, a depletion layer with a minute width extends from the withstand voltage region 48 and the bottom region 50 (i.e., the p-type region) into the drift region 44. As described above, since the withstand voltage region 48 is disposed at a position away from the gate insulating film 22, the depletion layer extending from the withstand voltage region 48 into the drift region 44 does not reach the gate insulating film 22. Therefore, the depletion layer extending from the withstand voltage region 48 into the drift region 44 is prevented from blocking the flow of electrons. Furthermore, since the p-type impurity concentration of the bottom region 50 is low, the width of the depletion layer extending from the bottom region 50 into the drift region 44 is extremely small. Therefore, the depletion layer extending from the bottom region 50 into the drift region 44 is prevented from blocking the flow of electrons. In this way, the depletion layers extending from the withstand voltage region 48 and the bottom region 50 are less likely to block the flow of electrons, and the on-resistance of the MOSFET 10 is further reduced.

[0029] In the MOSFET 10 of the embodiment, the drift region 44 around the voltage-resistant region 48 is composed of the high-concentration region 44a. Since the n-type impurity concentration of the high-concentration region 44a is high, the resistivity of the high-concentration region 44a is low. Therefore, electrons that have passed through the channel can flow through the high-concentration region 44a with low loss. In particular, since the drift region 44 in the narrow gap C1 is composed of the high-concentration region 44a, electrons can pass through the gap C1 with low loss. This further reduces the on-resistance of the MOSFET 10.

[0030] When the potential of the gate electrode 24 is reduced to a value less than 100 V, the channel disappears and the flow of electrons stops. That is, the MOSFET 10 is turned off. When the MOSFET 10 is turned off, the depletion layer spreads from the body region 42 to the drift region 44, and the drift region 44 is depleted over a wide range. At this time, the depletion layer also extends widely from the voltage-resistant region 48 and the bottom region 50 to the drift region 44. The voltage-resistant region 48 is disposed at a position away from the lower end of the trench 20. However, since the p-type impurity concentration of the voltage-resistant region 48 is high, the depletion layer extending from the voltage-resistant region 48 extends to the periphery of the lower end of the trench 20. In this way, the depletion layer extending from the voltage-resistant region 48 depletes the drift region 44 around the lower end of the trench 20, thereby suppressing the electric field concentration at the lower end of the trench 20. In addition, the depletion layer extending from the bottom region 50 also depletes the drift region 44 around the lower end of the trench 20. This also suppresses electric field concentration at the bottom end of trench 20. In this manner, the depletion layer spreads from voltage-resistant region 48 and bottom region 50 to the periphery of the bottom end of trench 20, thereby suppressing electric field concentration at the bottom end of trench 20.

[0031] In addition, the withstand voltage region 48 having a high p-type impurity concentration is unlikely to be depleted when the MOSFET 10 is off. Since the withstand voltage region 48, which is unlikely to be depleted, extends from the upper side to the lower side of the lower end of the trench 20, an electric field is unlikely to be generated in the drift region 44 above the lower end of the withstand voltage region 48 when the MOSFET 10 is off. That is, as shown by the dashed lines 200 in Figures 4 and 6, the presence of the withstand voltage region 48 makes it unlikely for equipotential lines to enter the drift region 44 above the lower end of the withstand voltage region 48. This also suppresses electric field concentration at the lower end of the trench 20.

[0032] As described above, the MOSFET 10 of the embodiment suppresses electric field concentration at the bottom end of the trench 20. This suppresses application of a high electric field to the gate insulating film 22 at the bottom end of the trench 20. This allows the MOSFET 10 to have a high breakdown voltage.

[0033] In the MOSFET 10 of the embodiment, the withstand voltage region 48 does not exist around the trench 20. Therefore, the volume of the withstand voltage region 48 is smaller than that of a conventional MOSFET in which the withstand voltage region extends continuously in the direction intersecting with the trench. However, even in the conventional MOSFET, the volume of the withstand voltage region at the intersection between the trench and the withstand voltage region is relatively small because the volume of the trench is large at the intersection. Therefore, even if the withstand voltage region 48 is eliminated at the intersection as in the MOSFET 10 of the embodiment, the reduction in the volume of the withstand voltage region 48 is small. Therefore, in the MOSFET 10 of the embodiment, the volume of the withstand voltage region 48 can be sufficiently secured, and the depletion layer can be widely extended from the withstand voltage region 48 into the drift region 44 when the MOSFET 10 is turned off.

[0034] As described above, in the MOSFET 10 of the embodiment, the on-resistance can be reduced while maintaining a high breakdown voltage.

[0035] Next, a method for manufacturing the MOSFET 10 will be described. The entire semiconductor substrate 12 before processing is composed of the low concentration region 44b of the drift region 44. First, as shown in FIGS. 7 and 8, a mask 80 is formed on the upper surface 12a of the semiconductor substrate 12. Here, the mask 80 is formed so that an opening 80a is located above the area where the withstand voltage region 48 is to be formed. In other words, a lattice-shaped mask 80 is formed so as to avoid the area where the withstand voltage region 48 is to be formed. Therefore, the beam portion of the mask 80 extending in the y direction extends along the area 20x where the trench 20 is to be formed, and the beam portion of the mask 80 extending in the x direction extends in a direction perpendicular to the area 20x where the trench 20 is to be formed.

[0036] 9, p-type impurities are implanted into the semiconductor substrate 12 through a mask 80. Here, the implantation energy is increased to implant the p-type impurities to a deep position from the upper surface 12a. This forms a plurality of voltage-resistant regions 48. After the voltage-resistant regions 48 are formed, the mask 80 is removed.

[0037] In the ion implantation process for the voltage-resistant region 48, a high implantation energy is used as described above, so the mask 80 needs to be thick. This results in a high aspect ratio in the cross-sectional shape of the mask 80 as shown in FIGS. 8 and 9. Generally, when a mask is formed with such a high aspect ratio, a part of the mask may collapse. However, in this embodiment, the mask 80 is formed in a lattice shape as shown in FIG. 7, so that the collapse of the mask 80 is prevented.

[0038] Next, a mask (not shown) is formed to cover the outer periphery of the MOSFET 10, and n-type impurities are ion-implanted into the semiconductor substrate 12 through the mask, as shown in FIG.

[0039] Next, as shown in FIG. 11, the upper surface 12a of the semiconductor substrate 12 is selectively etched to form a trench 20.

[0040] 12, p-type impurities are implanted into the semiconductor substrate 12 from the upper surface 12a side. This forms a low concentration region 42b of the body region 42. At this time, the p-type impurities are also implanted into the bottom surface of the trench 20. As a result, a p-type bottom region 50 is formed in the area exposed at the bottom surface of the trench 20. In this manner, with this manufacturing method, the low concentration region 42b and the bottom region 50 can be formed simultaneously.

[0041] Next, the gate insulating film 22 and the gate electrode 24 are formed in the trench 20. Next, the contact region 42a, the source region 40, and the drain region 46 are formed by ion implantation. Thereafter, the interlayer insulating film 26, the source electrode 30, and the drain electrode 32 are formed, thereby completing the MOSFET 10 shown in FIGS.

[0042] In the above-mentioned manufacturing method, the low concentration region 42b of the body region 42 is formed by ion implantation, but the low concentration region 42b may be formed by epitaxial growth. In this case, before the epitaxial growth, as shown in FIG. 13, the breakdown voltage region 48 and the high concentration region 44a of the drift region 44 are formed by ion implantation in a shallow range near the upper surface 12a of the semiconductor substrate 12. Next, as shown in FIG. 14, the low concentration region 42b is epitaxially grown on the semiconductor substrate 12. Next, as shown in FIG. 15, the trench 20 and the bottom region 50 are formed. Next, in the same manner as in the above-mentioned manufacturing method, the gate insulating film 22, the gate electrode 24, the contact region 42a, the source region 40, the drain region 46, the interlayer insulating film 26, the source electrode 30, and the drain electrode 32 are formed. In this way, the MOSFET 10 is completed.

[0043] In another manufacturing method, the voltage-resistant region 48 may be formed by ion implantation after the trench 20 is formed.

[0044] In the MOSFET 10 according to the embodiment described above, the lower end of the withstand voltage region 48 is located above the lower end of the high-concentration region 44a. However, as shown in FIG. 16, the withstand voltage region 48 may reach the low-concentration region 44b.

[0045] In the above-described embodiment, the breakdown voltage region 48 is separated from the body region 42. However, the breakdown voltage region 48 may be connected to the body region 42 as shown in FIG.

[0046] In the above-described embodiment, the bottom region 50 is provided at the bottom of the trench 20. However, as shown in Fig. 18, the bottom region 50 does not have to be provided at the bottom of the trench 20. Even in this configuration, the depletion layer extending from the voltage-withstanding region 48 can suppress electric field concentration at the bottom end of the trench 20.

[0047] In the above-described embodiment, the drift region 44 has the high concentration region 44a and the low concentration region 44b. However, the n-type impurity concentration may be uniform throughout the drift region 44.

[0048] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0049] 10: MOSFET, 12: semiconductor substrate, 20: trench, 22: gate insulating film, 24: gate electrode, 28: trench region, 30: source electrode, 32: drain electrode, 40: source region, 42: body region, 44: drift region, 46: drain region, 48: voltage-resistant region, 50: bottom region

Claims

1. A field effect transistor, A semiconductor substrate (12) having a plurality of trenches (20) formed on an upper surface thereof; a gate insulating film (22) covering the inner surface of the trench; a gate electrode (24) disposed within the trench and insulated from the semiconductor substrate by the gate insulating film; having The semiconductor substrate is A plurality of n-type source regions (40); a p-type body region (42); an n-type drift region (44); A plurality of p-type breakdown voltage regions (48); having each area of ​​the semiconductor substrate located between a plurality of the trenches is an inter-trench area (28); Each of the plurality of source regions is provided within a corresponding one of the inter-trench ranges and is in contact with a corresponding one of the gate insulating films; the body region extends across the inter-trench ranges and contacts the gate insulating films below the source region within the inter-trench ranges; the drift region is distributed across a range from within the inter-trench area to below the trenches, and is in contact with the gate insulating films below the body region; A plurality of the voltage-resistant regions are provided within the respective inter-trench ranges, A plurality of the voltage-resistant regions are arranged within an area surrounded by the drift region, the plurality of breakdown voltage regions are separated from the body region by the drift region; The plurality of voltage-resistant regions are arranged to form a plurality of rows (49) extending along a first direction intersecting the plurality of trenches; In each of the rows, a plurality of the voltage-resistant regions are arranged at intervals in the first direction, A plurality of the rows are spaced apart in a second direction parallel to the trenches; each of the breakdown voltage regions has a p-type impurity concentration higher than that of the body region, extends from above a lower end of each of the trenches to below the lower end of each of the trenches, and is disposed at a distance from each of the gate insulating films; the drift region is in contact with the gate insulating film at a position between each of the voltage withstanding regions and each of the gate insulating films; Field effect transistor.

2. a plurality of p-type bottom regions (50); each of the bottom regions has a lower p-type impurity concentration than each of the voltage withstanding regions; each of the bottom regions contacts the gate insulating film at the lower end of the corresponding trench and is spaced apart from each of the voltage-withstanding regions; 2. The field effect transistor of claim 1.

3. The drift region has a low concentration region (44b) and a high concentration region (44a) having an n-type impurity concentration higher than that of the low concentration region, the high concentration regions are distributed from a position in contact with the body region to a position below the lower end of each of the trenches, and are in contact with each of the gate insulating films at positions between each of the voltage withstanding regions and each of the gate insulating films; The low concentration region is in contact with the high concentration region from below.

3. A field effect transistor according to claim 1 or 2.

4. A method for producing a field effect transistor according to any one of claims 1 to 3, comprising the steps of: forming a mask (80) extending in a lattice pattern on the upper surface of the semiconductor substrate; forming a plurality of said voltage withstanding regions in said semiconductor substrate by implanting p-type impurities into said semiconductor substrate through said mask; The manufacturing method according to claim 1, 5. A method for producing a field effect transistor according to claim 2, comprising the steps of: forming a mask (80) extending in a lattice pattern on the upper surface of the semiconductor substrate; forming a plurality of the voltage withstanding regions in the semiconductor substrate by implanting a p-type impurity into the semiconductor substrate through the mask; forming the trench in the top surface of the semiconductor substrate; forming the body region and the bottom region by implanting p-type impurities into the top surface of the semiconductor substrate and into a bottom surface of the trench; The manufacturing method according to claim 1,

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