Semiconductor device manufacturing method

Abstract

To provide a semiconductor device with a low on-resistance.SOLUTION: A semiconductor device 1 comprises: a semiconductor layer 10 having a first main surface 10a and a second main surface 10b; and a trench gate 30. The semiconductor layer includes: an n-type drift region 12; and a p-type body region 14 that is provided on a side closer to the first main surface than the drift region. The trench gate is provided in a trench TR1 reached to a drift region in a manner to penetrate the body region from the first main surface of the semiconductor layer. A side surface of the trench gate is in contact with the body region and the drift region. In a part in contact with the side surface of the trench gate, only the body region of the body region and the drift region includes a channel region 14b lower in impurity density than a side farther from the side surface of the trench gate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which the impurity concentration in the portion in contact with the side surface of the trench gate is reduced. In the semiconductor device disclosed in Patent Document 1, the impurity concentration in the portion of the p-type body layer in contact with the side surface of the trench gate is particularly reduced, which is said to reduce channel resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-101706 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in Patent Document 1, the impurity concentration in the portion of the n-type drift layer that contacts the side surface of the trench gate is also reduced, which raises concerns about an increase in drift resistance. [Means for solving the problem]

[0005] The semiconductor device disclosed in this specification may include a semiconductor layer (10) having a first main surface (10a) and a second main surface (10b), and a trench gate (30). The semiconductor layer may include a drift region (12) of a first conductivity type, and a body region (14) of a second conductivity type provided on the first main surface side of the drift region. The trench gate is provided in a trench (TR1) that extends from the first main surface of the semiconductor layer through the body region to the drift region. A side surface of the trench gate is in contact with the body region and the drift region. In a portion that is in contact with the side surface of the trench gate, only the body region of the body region and the drift region has a channel region (14b) having a lower impurity concentration than the side farther from the side surface of the trench gate. In this semiconductor device, a channel region having a low impurity concentration is selectively formed only in the body region, so that it is possible to reduce only the channel resistance while suppressing an increase in drift resistance.

[0006] The manufacturing method of the semiconductor device (1) disclosed in this specification can include a trench forming step of forming a trench (TR1) extending from a first main surface (10a) to a deep portion of a first conductivity type semiconductor layer (10) having the first main surface (10a) and a second main surface (10b), and an ion implantation step of forming a body region (14) by implanting impurity ions of a second conductivity type into a surface layer portion of the semiconductor layer, the impurity ions being implanted in a range shallower than the trench. The ion implantation step is performed so that the impurity ions irradiated toward the inside of the trench are not present in at least a part of the depth range implanted into the semiconductor layer. According to this manufacturing method, when the body region is formed in the ion implantation step, the impurity concentration of the portion of the body region facing the trench can be reduced. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view of a main portion of a semiconductor device. [Diagram 2]2 is a schematic cross-sectional view of a main part of a semiconductor layer in a process for manufacturing the semiconductor device of FIG. 1. [Diagram 3] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in a process for manufacturing the semiconductor device of FIG. 1. [Figure 4] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in a process for manufacturing the semiconductor device of FIG. 1. [Diagram 5] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in a process for manufacturing the semiconductor device of FIG. 1. [Figure 6] FIG. 1 is a diagram showing the relationship between the taper angle of the trench and the channel concentration percentage. [Figure 7] 2 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of manufacturing a modified example of the semiconductor device in FIG. 1. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] As shown in Fig. 1, the semiconductor device 1 is a type of semiconductor device known as an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10 having a first main surface 10a and a second main surface 10b, a drain electrode 22 covering the second main surface 10b of the semiconductor layer 10, a source electrode 24 covering the first main surface 10a of the semiconductor layer 10, and a trench gate 30 provided in a surface portion of the semiconductor layer 10. Here, the first main surface 10a and the second main surface 10b are a pair of surfaces extending in parallel on the surface of the semiconductor layer 10, and are surfaces perpendicular to the thickness direction of the semiconductor layer 10. The semiconductor layer 10 is an n + A drain region 11, an n-type drift region 12, a p-type electric field relaxation region 13, a p-type body region 14, and an n + A source region 15 of p + and a body contact region 16. The material of the semiconductor layer 10 is not particularly limited, but may be, for example, silicon carbide (SiC).

[0009] The drain region 11 is provided in the back layer portion of the semiconductor layer 10, and contains a high concentration of n-type impurities. The drain region 11 is provided at a position exposed to the second main surface 10b of the semiconductor layer 10, and is in ohmic contact with the drain electrode 22. The drain region 11 also serves as a base substrate for epitaxial growth of the drift region 12 described below.

[0010] The drift region 12 is provided on the surface of the drain region 11, is disposed between the drain region 11 and the body region 14, and is in contact with both the drain region 11 and the body region 14. The drift region 12 is formed by epitaxial growth from the surface of the drain region 11, and has a substantially constant n-type impurity concentration.

[0011] The electric field relaxation region 13 is provided on the drift region 12 so as to be in contact with the bottom surface of the trench gate 30. The electric field relaxation region 13 can relax the electric field concentration on the bottom surface of the trench gate 30.

[0012] The body region 14 is provided on the surface of the drift region 12, and is disposed between the drift region 12 and the source region 15 and between the drift region 12 and the body contact region 16. The body region 14 has a main body region 14a and a channel region 14b. The main body region 14a is separated from the side of the trench gate 30 by the channel region 14b, and is a region of the body region 14 farther from the side of the trench gate 30. The channel region 14b is in contact with the side of the trench gate 30, and is a region of the body region 14 closer to the side of the trench gate 30, and has a lower p-type impurity concentration than the main body region 14a. When measured on a plane parallel to the principal surface of the semiconductor layer 10, the p-type impurity concentration of the main body region 14a is approximately constant, and the p-type impurity concentration of the channel region 14b decreases as it approaches the side of the trench gate 30.

[0013] The source region 15 is provided in a surface layer portion of the semiconductor layer 10, on the surface of the body region 14, and contains a high concentration of n-type impurities. The source region 15 is provided at a position exposed to the first main surface 10a of the semiconductor layer 10, and is in ohmic contact with the source electrode 24.

[0014] The body contact region 16 is provided in a surface layer portion of the semiconductor layer 10, on the surface of the body region 14, and contains a high concentration of p-type impurities. The body contact region 16 is provided at a position exposed to the first main surface 10a of the semiconductor layer 10, and is in ohmic contact with the source electrode 24.

[0015] The trench gate 30 is provided in a trench TR1 that extends from the first main surface 10a of the semiconductor layer 10 through the source region 15 and the body region 14 to the drift region 12. The side surfaces of the trench gate 30 contact the source region 15, the channel region 14b of the body region 14, and the drift region 12, and the bottom surface of the trench gate 30 contacts the electric field relaxation region 13. The trench gate 30 has a gate insulating film 32 and a gate electrode 34. The side surfaces and bottom surface of the gate electrode 34 are covered with the gate insulating film 32. The gate electrode 34 is insulated from the source electrode 24 by an interlayer insulating film.

[0016] Next, the operation of the semiconductor device 1 will be described. When a positive voltage higher than that of the source electrode 24 is applied to the drain electrode 22 and a positive voltage higher than the threshold voltage is applied to the gate electrode 32, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the channel region 14b of the body region 14 that contacts the side surface of the trench gate 30. Electrons injected from the source region 15 move to the drift region 12 through the inversion layer of the channel region 14b, and the semiconductor device 1 turns on. Since the p-type impurity concentration of the channel region 14b is low, the channel resistance decreases. In this way, the semiconductor device 1 can have low on-resistance characteristics.

[0017] When the positive voltage applied to the gate electrode 32 falls below the threshold voltage, the inversion layer in the channel region 14b disappears, and the semiconductor device 1 turns off. When the semiconductor device 1 turns off, a depletion layer spreads from the junction between the drift region 12 and the body region 14 to each of the drift region 12 and the body region 14. Since the body region 14 has the main body region 14a with a high concentration of p-type impurities, the main body region 14a is prevented from being completely depleted and punching through when the semiconductor device 1 turns off. This allows the semiconductor device 1 to have high avalanche resistance characteristics.

[0018] Next, a method for manufacturing the semiconductor device 1 will be described. First, as shown in Fig. 2, a semiconductor layer 10 is prepared in which a drain region 11 and a drift region 12 are stacked. This semiconductor layer 10 is formed by crystal growth from the drain region 11 to the drift region 12 using an epitaxial growth technique.

[0019] 3, a trench TR1 is formed by using a dry etching technique to extend from the first main surface 10a of the semiconductor layer 10 to a predetermined depth (an example of a trench forming process). Here, the taper angle θ of the trench TR1 is defined as the angle between an extension line extending parallel to the bottom surface of the trench TR1 from the end of the bottom surface of the trench TR1 and the side surface of the trench TR1. As described later, the trench TR1 is formed so that the taper angle θ is 87° or more.

[0020] 4, p-type impurity ions (e.g., aluminum ions) are irradiated toward the first main surface 10a of the semiconductor layer 10 using an ion implantation technique (an example of an ion implantation step). The p-type impurity ions implanted into the surface layer portion of the semiconductor layer 10 form a body region 14, and the p-type impurity ions implanted into the bottom surface of the trench TR1 through the trench TR1 form an electric field relaxation region 13.

[0021] In this ion implantation process, the p-type impurity concentration of the portion of the body region 14 exposed to the trench TR1 is reduced, and the channel region 14b is formed. The p-type impurity ions irradiated toward the inside of the trench TR1 pass through the depth range of the semiconductor layer 10 and are implanted into the bottom surface of the trench TR1. For this reason, if the trench TR1 is not formed, the p-type impurity ions implanted into the region corresponding to the trench TR1 may diffuse into the channel region 14b. However, in this manufacturing method, such diffusion of the p-type impurity ions does not exist, and therefore the p-type impurity concentration of the channel region 14b is reduced. In addition, the p-type impurity ions of the channel region 14b are diffused outward into the trench TR1, and the p-type impurity concentration of the channel region 14b is reduced. For these reasons, the p-type impurity concentration of the portion of the body region 14 exposed to the trench TR1 is selectively reduced, and the channel region 14b is formed.

[0022] In the ion implantation process, the p-type impurity ions are uniformly irradiated in the plane of the semiconductor layer 10. Therefore, the p-type impurity concentration at a predetermined depth in the semiconductor layer 10, i.e., the p-type impurity concentration at a predetermined depth in the main body region 14a, is constant. Therefore, by identifying a region in the plane of the semiconductor layer 10 at a predetermined depth where the p-type impurity concentration is reduced, the position of the channel region 14b can be identified. The width 14W of the channel region 14b measured in a direction perpendicular to the side surface of the trench gate 30 may be 10 nm or more and 40 nm or less. If the width 14W of the channel region 14b is 10 nm or more, an inversion layer is formed in the channel region 14b, and the channel resistance is reduced. If the width 14W of the channel region 14b is 40 nm or less, the main body region 14a can be secured to be wide, and the deterioration of the avalanche resistance due to punch-through can be suppressed.

[0023] 5, n-type impurity ions (e.g., nitrogen ions) and p-type impurity ions (e.g., aluminum ions) are implanted into the surface layer of the semiconductor layer 10 using ion implantation technology to form a source region 15 and a body contact region 16. Next, a gate insulating film 32 and a gate electrode 34 are formed in the trench using CVD technology to form a trench gate 30 (see FIG. 1). Finally, a drain electrode 22 is coated on the second main surface 10b of the semiconductor layer 10, and a source electrode 24 is coated on the first main surface 10a of the semiconductor layer 10, completing the semiconductor device 1 (see FIG. 1).

[0024] FIG. 6 shows the relationship between the taper angle (θ) of the trench TR1 and the channel concentration percentage of the channel region 14b. The channel concentration percentage is the lowest p-type impurity concentration in the channel region 14b relative to the p-type impurity concentration in the main body region 14a, expressed as a percentage. As shown in FIG. 6, the channel concentration percentage depends on the taper angle (θ) of the trench TR1, and decreases as the taper angle (θ) of the trench TR1 increases. When the taper angle (θ) of the trench TR1 is 87° or more, the channel concentration percentage is 50% or less. That is, the p-type impurity concentration of at least a part of the channel region 14b can be half or less of the p-type impurity concentration of the main body region 14a.

[0025] FIG. 7 shows a modified example of the ion implantation process. In this example, p-type impurity ions are implanted in a state where the trench TR1 is filled with the shielding material 42. This makes it possible to prevent an electric field relaxation region from being formed at the bottom of the trench TR1. The shielding material 42 may be, for example, a resist, a silicon oxide film, or a metal-containing fluid material as long as it shields p-type impurity ions so that the p-type impurity ions are not implanted into the bottom of the trench TR1. When the shielding material 42 is a resist or a silicon oxide film, the shielding material 42 may be formed so as to protrude from the first main surface 10a of the semiconductor layer 10, as shown in FIG. 7. In this example, too, the p-type impurity ions implanted into the shielding material 42 are prevented from being present in at least a part of the depth range of the body region 14, so that a channel region 14b in which the p-type impurity concentration is selectively reduced can be formed.

[0026] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0027] The technology disclosed in this specification may include a semiconductor layer having a first main surface and a second main surface, and a trench gate. The semiconductor layer may have a drift region of a first conductivity type, and a body region of a second conductivity type provided closer to the first main surface than the drift region. The trench gate is provided in a trench that extends from the first main surface of the semiconductor layer through the body region to the drift region. A side surface of the trench gate is in contact with the body region and the drift region. In a portion that is in contact with the side surface of the trench gate, only the body region of the body region and the drift region has a channel region with a lower impurity concentration than the side farther from the side surface of the trench gate.

[0028] In the semiconductor device, a second conductivity type impurity concentration in at least a part of the channel region may be equal to or less than half of a second conductivity type impurity concentration in the body region on a side farther from a side surface of the trench gate. This semiconductor device can have low on-resistance characteristics.

[0029] In the semiconductor device, the semiconductor layer may further include an electric field relaxation region of a second conductivity type provided in contact with a bottom surface of the trench gate, thereby relaxing electric field concentration at the bottom surface of the trench gate.

[0030] In the semiconductor device, a taper angle of a side surface of the trench may be 87° or more.

[0031] In the semiconductor device, the width of the channel region as measured in a direction perpendicular to a side surface of the trench gate may be 40 nm or less. In the semiconductor device, the width of the low-impurity-concentration channel region is limited, thereby suppressing deterioration of avalanche resistance due to punch-through.

[0032] The method for manufacturing a semiconductor device disclosed in this specification can include a trench forming step of forming a trench extending from a first main surface of a first conductivity type semiconductor layer having a first main surface and a second main surface toward a deep portion, and an ion implantation step of forming a body region by implanting impurity ions of a second conductivity type into a surface layer portion of the semiconductor layer, the impurity ions being implanted in a range shallower than the trench. The ion implantation step is performed so that the impurity ions irradiated toward the inside of the trench are not present in at least a part of the depth range implanted into the semiconductor layer.

[0033] In the ion implantation step of the above manufacturing method, the side of the trench may be exposed in a depth range where the impurity ions are implanted into the semiconductor layer. According to this manufacturing method, the impurity concentration of the portion of the body region exposed on the side of the trench can be selectively reduced. Furthermore, in this ion implantation step, the impurity ions may also be implanted into the bottom of the trench to form an electric field relaxation region. According to this manufacturing method, the body region and the electric field relaxation region can be formed simultaneously.

[0034] In the above-described manufacturing method, the trench may be filled with a shielding material in the ion implantation step. According to this manufacturing method, only the body region can be formed in the ion implantation step.

[0035] In the above manufacturing method, a taper angle of the side surface of the trench may be 87° or more. According to this manufacturing method, the impurity concentration of the portion of the body region exposed on the side surface of the trench can be set to half or less of the impurity concentration of the body region on the side farther from the side surface of the trench.

[0036] Although the specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples exemplified above. In the above embodiment, a MOSFET is exemplified, but the technology disclosed in this specification is also applicable to other types of semiconductor devices equipped with a trench gate, such as an IGBT (Insulated Gate Bipolar Transistor). In the above embodiment, an n-channel type semiconductor device is described, but the technology disclosed in this specification is also applicable to a p-channel type semiconductor device. In addition, the technical elements described in this specification or the drawings exert technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve multiple objectives simultaneously, and achieving one of the objectives itself has technical usefulness. [Explanation of symbols]

[0037] 1: semiconductor device, 10: semiconductor layer, 10a: first main surface, 10b: second main surface, 11: drain region, 12: drift region, 13: electric field relaxation region, 14: body region, 14a: main body region, 14b: channel region, 15: source region, 16: body contact region, 22: drain electrode, 24: source electrode, 30: trench gate, 32: gate insulating film, 34: gate electrode

Claims

1. A method for manufacturing a semiconductor device (1), comprising the steps of: A trench forming step of forming a trench (TR1) extending from a first main surface (10a) to a depth of a first conductivity type semiconductor layer (10) having a first main surface (10a) and a second main surface (10b); an ion implantation step of forming a body region (14) by implanting impurity ions of a second conductivity type into a surface layer portion of the semiconductor layer, the impurity ions being implanted into a range shallower than the trench; the ion implantation step is performed such that the impurity ions irradiated into the trench are not present in at least a portion of a depth range of the impurity ions implanted into the semiconductor layer; In the ion implantation step, a shielding material (42) is filled in the trench.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a taper angle of the side surface of the trench is 87 degrees or more.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor layer is made of silicon carbide.

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