Method for forming a semiconductor layer

Abstract

The present invention includes preparing a Si substrate (101) having a Si oxide layer (102) composed of SiO2 formed on a main surface, affixing a crystal substrate on the Si substrate (101), making the affixed crystal substrate into a thin layer, thereby forming a first semiconductor layer (104) on the Si substrate (101), and then forming a first insulation layer (105), and using the first insulation layer (105) as a selective growth mask to epitaxially grow a group III-V compound semiconductor from the surface of the first semiconductor layer (104) exposed in an anticipated region from a first opening (125b), thereby forming a second semiconductor layer (108).

Description

[Technical field]

[0001] The present invention relates to a method for forming a semiconductor layer having a heterointerface perpendicular to a substrate. [Background technology]

[0002] III-V semiconductors can create new functions by forming heterojunctions, and are used in various devices such as transistors and light-emitting / receiving elements. Normally, heterojunctions are formed by growing crystals perpendicular to the III-V semiconductor substrate, forming a heterointerface parallel to the substrate. Devices made of III-V compounds that are widely used utilize such heterojunctions and heterointerfaces. In addition, the formation of heterojunction devices made of III-V semiconductors on Si substrates is expected to enable multi-functionalization through integration with Si devices, and various fabrication technologies have been implemented.

[0003] On the other hand, there have been no reports of technology for forming a heterointerface perpendicular to the substrate, or a high-quality heterojunction in a horizontal direction relative to the substrate, on a Si substrate, and further technology for fabricating a device using the same on a Si substrate, and these technologies have not been established. If such a technology for forming a heterojunction surface perpendicular to the substrate plane could be realized, various applications would be possible. For example, it would be possible to form a tunnel field effect transistor (TFET) consisting of a heterojunction as described in Non-Patent Document 1 on a Si substrate. As described in Non-Patent Document 1, this device requires the formation of a heterojunction perpendicular to the gate electrode and gate insulating layer.

[0004] Conventional techniques require the formation of a nanowire structure as described in Non-Patent Document 2 or a mesa structure with a very high aspect ratio as described in Non-Patent Document 3, and it is believed to be difficult to mass-produce practical devices.

[0005] To overcome this problem, a technique has been reported in which a {111} facet formed on a Si(100) substrate by anisotropic etching and selective growth technology are used to grow crystals horizontally to the substrate, forming a heterojunction perpendicular to the growth direction, as described in Non-Patent Document 4. However, in this case, stacking faults are likely to occur due to growth in the {111} direction, making it difficult to form high-quality crystals with high uniformity. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] P. Long et al., "A high-current InP-channel triple heterojunction tunnel transistor design", 2017 75th Annual Device Research Conference, 17082422, 2017. [Non-Patent Document 2] E. Memisevic et al., "Vertical InAs / GaAsSb / GaSb Tunneling Field-Effect Transistor on Si with S = 48 mV / decade and Ion=10μA / μm for Ioff=1nA / μm at VDS=0.3V", 2016 IEEE International Electron Devices Meeting, vol. 16651219, IEDM16-500-IEDM16-503, 2016. [Non-Patent Document 3] M. Fujimatsu et al., "71mV / dec of Sub-threshold Slope in Vertical Tunnel Field-effect Transistors with GaAsSb / InGaAs Heterostructure", 2012 International Conference on Indium Phosphide and Related Materials, 13235642, pp. 25-28, 2013. [Non-Patent Document 4] Y. Han et al., "Micrometer-scale InP selectively grown on SOI for fully integrated Si-photonics", Applied Physics Letters, vol. 117, 052102, 2020. Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, conventionally, there has been a problem in that it is not easy to form a heterojunction having a heterointerface perpendicular to the substrate made of III-V compound semiconductors on a Si substrate.

[0008] The present invention has been made to solve the above-mentioned problems, and has an object to easily form a heterojunction having a heterointerface perpendicular to the substrate made of III-V compound semiconductors on a Si substrate. [Means for solving the problem]

[0009] The method for forming a semiconductor layer according to the present invention includes a first step of attaching a crystal substrate made of a III-V compound semiconductor crystal having a (110) plane as a main surface onto a Si substrate, and thinning the attached crystal substrate to form a first semiconductor layer on the Si substrate; a second step of forming a first insulating layer on the first semiconductor layer, the first insulating layer having a first opening of a rectangular planar shape with its long sides in the

[0001] direction of the first semiconductor layer and its short sides in the [-110] direction; a third step of forming a sacrificial pattern made of amorphous Si on the first insulating layer, the sacrificial pattern having a rectangular planar shape with its long sides in the [-110] direction of the first semiconductor layer and its short sides in the

[0001] direction; a fourth step of forming a second insulating layer on the first insulating layer so as to cover the sacrificial pattern; and a fourth step of forming a through hole reaching the sacrificial pattern at a location of the second insulating layer that does not overlap with the first opening. The method includes a fifth step of forming a through hole, a sixth step of removing the sacrificial pattern through the through hole to expose a surface of the first semiconductor layer in the first opening, a seventh step of using the first insulating layer having the first opening as a selective growth mask to crystal-grow a III-V compound semiconductor from the surface of the first semiconductor layer exposed in the first opening, and forming a second semiconductor layer between the first insulating layer and the second insulating layer in a state in which a side surface consisting of a facet of the crystal-grown III-V compound semiconductor is disposed between the first insulating layer and the second insulating layer, and an eighth step of, following the formation of the second semiconductor layer, crystal-grow a III-V compound semiconductor having a different composition from the second semiconductor layer from the side surface of the second semiconductor layer between the first insulating layer and the second insulating layer to form a third semiconductor layer that forms a heterojunction with the side surface of the second semiconductor layer. Effect of the Invention

[0010] As described above, according to the present invention, a crystal substrate made of III-V compound semiconductor crystals having a (110) main surface is attached onto a Si substrate, thereby forming a first semiconductor layer on the Si substrate. This makes it possible to easily form a heterojunction made of III-V compound semiconductor with a heterointerface perpendicular to the substrate on the Si substrate. [Brief description of the drawings]

[0011] [Figure 1A]FIG. 1A is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method for forming a semiconductor layer according to an embodiment of the present invention. [Figure 1C] FIG. 1C is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method for forming a semiconductor layer according to an embodiment of the present invention. [Figure 1D] FIG. 1D is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method for forming a semiconductor layer according to an embodiment of the present invention. [Figure 1E] FIG. 1E is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method for forming a semiconductor layer according to an embodiment of the present invention. [Figure 1F] FIG. 1F is a plan view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1G] FIG. 1G is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1H] FIG. 1H is a plan view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1I] FIG. 1I is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method for forming a semiconductor layer according to an embodiment of the present invention. [Figure 1J] FIG. 1J is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1K] FIG. 1K is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method for forming a semiconductor layer according to an embodiment of the present invention. [Figure 1L] FIG. 1L is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1M]FIG. 1M is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1N] FIG. 1N is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1O] FIG. 1O is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. [Figure 1P] FIG. 1P is a cross-sectional view showing a state of a semiconductor layer in the middle of a process for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, a method for forming a semiconductor layer according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1P.

[0013] First, as shown in Fig. 1A, a Si substrate 101 is prepared, on whose main surface a Si oxide layer 102 made of SiO2 is formed. The main surface of the Si substrate 101 is a (001) surface. For example, the Si oxide layer 102 can be formed by depositing SiO2 by a well-known deposition method.

[0014] Next, as shown in FIG. 1B, the crystal substrate 103 is attached onto the Si substrate 101. In this example, the surface of the Si oxide layer 102 and the surface of the crystal substrate 103 are bonded by a known bonding technique. The crystal substrate 103 is made of a III-V compound semiconductor crystal with the main surface being the (110) plane. This III-V compound semiconductor can be, for example, InP.

[0015] Next, the attached crystal substrate 103 is thinned to form a first semiconductor layer 104 on the Si substrate 101 as shown in Fig. 1C (first step). For example, the crystal substrate 103 can be thinned by chemical etching or a chemical-mechanical-polishing (CMP) method. In this example, the first semiconductor layer 104 is formed on the Si substrate 101 via a Si oxide layer 102.

[0016] Here, the main surface of the first semiconductor layer 104 can be formed to be inclined from the (110) plane toward the {111}B plane by 3 to 6 degrees. For example, the above-mentioned state can be achieved by using a crystal substrate 103 whose main surface is inclined from the (110) plane toward the {111}B plane by 3 to 6 degrees. Furthermore, the crystal substrate 103 can be thinned by, for example, adjusting the polishing angle so that the main surface is inclined from the (110) plane toward the {111}B plane by 3 to 6 degrees.

[0017] As described above, by tilting the main surface of the first semiconductor layer 104 by 3 to 6 degrees from the (110) plane toward the {111}B plane, it is possible to suppress the formation of {112} or {111} facets and obtain a flat growth surface when crystal is regrown from the first semiconductor layer 104 as described below (References 1 and 2).

[0018] Next, as shown in Fig. 1D, the first insulating layer 105 is formed. The first insulating layer 105 can have a laminated structure of an Al oxide layer 105a made of Al2O3 and a Si oxide layer 105b (Reference 3). For example, the first insulating layer 105 can be configured from a laminated structure of an Al oxide layer 105a having a thickness of 3 nm and a Si oxide layer 105b having a thickness of 30 nm.

[0019] Next, as shown in FIG. 1E and FIG. 1F, a first opening 125b having a rectangular planar shape with a long side in the

[0001] direction of the first semiconductor layer 104 and a short side in the [-110] direction is formed in the Si oxide layer 105b of the first insulating layer 105 on the first semiconductor layer 104 (second step). For example, the first opening 125b can be formed by etching using a well-known ICP etching method or the like using a resist pattern formed by a known photolithography technique or electron beam lithography technique as a mask. The first opening 125b can have a long side length of 1 μm and a short side length of 100 nm in a plan view. The opening dimensions can be appropriately set depending on the size of the desired heterostructure.

[0020] Next, as shown in FIG. 1G and FIG. 1H, a sacrificial pattern 106 made of amorphous Si is formed on the first insulating layer 105 (third step). The sacrificial pattern 106 is formed to have a rectangular planar shape with the long side in the [-110] direction of the first semiconductor layer 104 and the short side in the

[0001] direction. The sacrificial pattern 106 is formed to have an area larger than the first opening 125b when viewed from above, and is disposed so that the position of the first opening 125b is at the center. The sacrificial pattern 106 is formed to fill the first opening 125b and to have a flat surface.

[0021] For example, a sacrificial pattern 106 can be formed by depositing Si by chemical vapor deposition or the like to form a Si film, and then patterning the formed silicon film by known lithography or etching techniques. The dimensions of the long side, short side, thickness, etc. of the sacrificial pattern 106 can be appropriately set according to the size of a semiconductor device having a desired heterojunction structure. For example, the thickness of the sacrificial pattern 106 can be 50 nm.

[0022] Next, as shown in FIG. 1I, a second insulating layer 107 is formed on the first insulating layer 105 to cover the sacrificial pattern 106 (fourth step). The second insulating layer 107 is used as a selective growth mask for III-V compound semiconductors, and may be made of, for example, SiO2. The second insulating layer 107 may be formed to a thickness of, for example, about 100 nm.

[0023] 1J, through holes 127 reaching the sacrificial pattern 106 are formed in the second insulating layer 107 at locations not overlapping with the first openings 125b (fifth step). The through holes 127 are formed, for example, at the edge positions of each of the two short sides of the sacrificial pattern 106, which has a rectangular shape in a plan view.

[0024] Next, the sacrificial pattern 106 is removed through the two formed through holes 127 to form a hollow structure 126 between the first insulating layer 105 and the second insulating layer 107, as shown in FIG. 1K. Furthermore, a first lower opening 125a is formed in the Al oxide layer 105a below the first opening 125b to expose this region of the first semiconductor layer 104 (sixth step). The hollow structure 126 is formed to have a rectangular planar shape with its long sides in the [-110] direction of the first semiconductor layer 104 and its short sides in the

[0001] direction.

[0025] For example, the sacrificial pattern 106 can be selectively removed by dry etching using XeF2. Also, the first lower opening 125a can be formed in the Al oxide layer 105a by selective etching using TMAH (Methyl Ammonium Hydroxide).

[0026] Next, a III-V compound semiconductor is grown epitaxially from the surface of the first semiconductor layer 104 exposed in the region seen from the first opening 125b using the first insulating layer 105 as a selective growth mask to form the second semiconductor layer 108 as shown in Fig. 1L (seventh step). The second semiconductor layer 108 is grown between the first insulating layer 105 and the second insulating layer 107 (hollow structure 126) from the surface of the first semiconductor layer 104 exposed in the first opening 125b.

[0027] When this growth fills the first lower opening 125a and the first opening 125b and reaches the hollow structure 126, it proceeds in the [-110] direction of the first semiconductor layer 104 with the first opening 125b as the center. In the hollow structure 126, it proceeds left and right in the hollow structure 126 with the first opening 125b as the center, and a state is formed in which at least two side surfaces 138a and 138b are provided. These side surfaces 138a and 138b are facets of the crystal-grown III-V group compound semiconductor. The second semiconductor layer 108 is formed in a range in which the side surfaces 138a and 138b are disposed between the first insulating layer 105 and the second insulating layer 107.

[0028] For example, the first semiconductor layer 104 can be formed by epitaxially growing InP from an exposed surface (110) of the first semiconductor layer 104 made of InP using metal-organic chemical vapor deposition (MOCVD) (Reference 3). In this growth, by appropriately adjusting the growth temperature and the supply ratio of group V raw materials to group III raw materials, the growing side surfaces 138a and 138b of the second semiconductor layer 108 can be made into [-110] facets perpendicular to the surface of the Si substrate 101, and the crystal grows in the [-110] direction while maintaining this state.

[0029] The second semiconductor layer 108 is epitaxially grown until the side surfaces 138a and 138b reach a position several nm away from the region of the first opening 125b in a plan view. The growth of the second semiconductor layer 108 can be continued until it reaches the lower surface of the second insulating layer 107, which becomes the ceiling of the hollow structure 126, after filling the first opening 125b and reaching the hollow structure 126. As shown in FIG. 1L, the second semiconductor layer 108 is epitaxially grown until it reaches the lower surface of the second insulating layer 107, which becomes the ceiling of the hollow structure 126. + -The second semiconductor layer 108 made of InP is grown, and when it reaches the underside of the second insulating layer 107 which becomes the ceiling of the hollow structure 126, the growth is switched to non-doped InP to continue the formation of the second semiconductor layer 108a and the second semiconductor layer 108b.

[0030] Next, following the formation of the second semiconductor layer 108 (second semiconductor layer 108a, second semiconductor layer 108b) described above, a III-V compound semiconductor having a composition different from that of the second semiconductor layer 108 is crystallized (epitaxially grown) from the side surfaces 138a, 138b of the second semiconductor layer 108 (second semiconductor layer 108a, second semiconductor layer 108b) between the first insulating layer 105 and the second insulating layer 107. As a result, as shown in FIG. 1M, third semiconductor layers 109a, 109b that form a heterojunction with the side surfaces 138a, 138b of the second semiconductor layer 108 (second semiconductor layer 108a, second semiconductor layer 108b) are formed (8th step). The interface where the heterojunction is formed is a surface perpendicular to the plane of the Si substrate 101.

[0031] For example, in the growth of the second semiconductor layer 108 by the MOCVD method, the third semiconductor layer 109a and the third semiconductor layer 109b can be epitaxially grown by changing the raw material to be supplied at a predetermined point in time. For example, the third semiconductor layer 109a and the third semiconductor layer 109b can be formed by epitaxially growing non-doped InGaAs.

[0032] Subsequently, the fourth semiconductor layer 110a and the fourth semiconductor layer 110b are formed by epitaxially growing InGaAs doped with p-type impurities, and the fifth semiconductor layer 111a and the fifth semiconductor layer 111b are formed by growing InP doped with a high concentration of p-type impurities. The interface between the fourth semiconductor layer 110a and the fifth semiconductor layer 111a is a heterojunction interface, and the interface between the fourth semiconductor layer 110b and the fifth semiconductor layer 111b is also a heterojunction interface. Each interface is perpendicular to the plane of the Si substrate 101.

[0033] Thereafter, the second insulating layer 107 is removed to expose the second semiconductor layer 108, the second semiconductor layer 108a, the second semiconductor layer 108b, the third semiconductor layer 109a, the third semiconductor layer 109b, the fourth semiconductor layer 110a, the fourth semiconductor layer 110b, the fifth semiconductor layer 111a, and the fifth semiconductor layer 111b above the first insulating layer 105, as shown in FIG. 1O.

[0034] 1P, gate electrodes 114a and 114b are formed on the third semiconductor layers 109a and 109b via gate insulating layers 113a and 113b. Source electrodes 115a and 115b are formed in ohmic contact with the fifth semiconductor layers 111a and 111b. A drain electrode 116 is formed in ohmic contact with the second semiconductor layer 108.

[0035] As described above, a tunnel field effect transistor can be formed in which the n-type second semiconductor layer 108 is used as the drain, the p-type fourth semiconductor layer 110a and the fourth semiconductor layer 110b are used as the source, and quantum tunneling is modulated by the gate voltage applied to the gate electrodes 114a and 114b via a barrier formed by a heterointerface perpendicular to the plane of the Si substrate 101. The thickness, crystal composition, and doping concentration of each semiconductor layer can be appropriately designed by designing the transistor structure so as to obtain desired characteristics, and the designed values ​​can be applied.

[0036] In the above description, the crystal substrate 103 (first semiconductor layer 104) is made of InP, but the present invention is not limited to this. The crystal substrate 103 (first semiconductor layer 104) can be made of, for example, GaAs. In the above description, an example of fabricating a field-effect transistor by the method for forming a semiconductor layer according to the embodiment is shown, but the present invention is not limited to this. It goes without saying that the method for forming a semiconductor layer according to the embodiment can be applied to fabricating a quantum well structure using materials such as InGaAs, InP, and InGaAsP, and to fabricating a light-emitting device such as a laser using a microquantum well structure.

[0037] As described above, according to the present invention, a crystal substrate made of III-V compound semiconductor crystals with a (110) main surface is attached onto a Si substrate to form a first semiconductor layer on the Si substrate, so that a heterojunction with a heterointerface perpendicular to the substrate made of III-V compound semiconductor can be easily formed on the Si substrate. According to the present invention, it is possible to form a III-V semiconductor thin film crystal having a heterointerface perpendicular to the substrate on a Si substrate, and it is possible to fabricate an unprecedented device that integrates the functions of a III-V semiconductor device and a Si device.

[0038] It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0039] [Reference 1] M. Mitsuhara et al., "InP and related compounds grown on (110) InP substrates by metalorganic molecular beam epitaxy (chemical beam epitaxy)", Journal of Crystal Growth, vol. 136, pp. 195-199, 1994. [Reference 2] Y. Ogiso et al., "Static properties of planar Mach-Zehnder optical modulator on (110) InP substrate", Electronics Letters, vol. 49, no. 14, 2013. [Reference 3] A. Goswami et al., "Controlling facets and defects of InP nanostructures in confined epitaxial lateral overgrowth", PHYSICAL REVIEW MATERIALS, vol. 4, no. 12, 123403, 2020. [Explanation of symbols]

[0040] 101...Si substrate, 102...Si oxide layer, 103...crystal substrate, 104...first semiconductor layer, 105...first insulating layer, 105a...Al oxide layer, 105b...Si oxide layer, 106...sacrificial pattern, 107...second insulating layer, 108,108a,108b...second semiconductor layer, 109a,109b...third semiconductor layer, 110a,110b...fourth semiconductor layer, 111a,111b...fifth semiconductor layer, 113a,113b...gate insulating layer, 114a,114b...gate electrode, 115a,115b...source electrode, 116...drain electrode, 125a...first lower opening, 125b...first opening, 126...hollow structure, 127...through hole, 138a,138b...side surface.

Claims

1. a first step of attaching a crystal substrate made of a III-V compound semiconductor crystal having a (110) major surface on a Si substrate and thinning the attached crystal substrate to form a first semiconductor layer on the Si substrate; a second step of forming a first insulating layer on the first semiconductor layer, the first insulating layer having a first opening of a rectangular planar shape with a long side in the [001] direction of the first semiconductor layer and a short side in the [−110] direction; a third step of forming a sacrificial pattern made of amorphous Si on the first insulating layer, the sacrificial pattern having a rectangular planar shape with a long side in the [−110] direction of the first semiconductor layer and a short side in the [001] direction; a fourth step of forming a second insulating layer on the first insulating layer and covering the sacrificial pattern; a fifth step of forming a through hole reaching the sacrificial pattern in a portion of the second insulating layer that does not overlap the first opening; a sixth step of removing the sacrificial pattern through the through hole to expose a surface of the first semiconductor layer in the first opening; a seventh step of growing a III-V compound semiconductor crystal from a surface of the first semiconductor layer exposed in the first opening by using the first insulating layer having the first opening as a selective growth mask, and forming a second semiconductor layer between the first insulating layer and the second insulating layer in a state in which a side surface consisting of a facet of the crystal-grown III-V compound semiconductor is disposed between the first insulating layer and the second insulating layer; an eighth step of forming a third semiconductor layer by crystal-growing a III-V compound semiconductor having a different composition from the second semiconductor layer from the side surface of the second semiconductor layer between the first insulating layer and the second insulating layer, the third semiconductor layer forming a heterojunction with the side surface of the second semiconductor layer; A method for forming a semiconductor layer comprising:

2. 2. The method for forming a semiconductor layer according to claim 1, A method for forming a semiconductor layer, wherein the main surface of the first semiconductor layer is formed so as to be inclined at an angle of 3 to 6 degrees from a (110) plane toward a {111}B plane.

3. 3. The method for forming a semiconductor layer according to claim 1, 2. A method for forming a semiconductor layer, wherein the crystal substrate is made of InP or GaAs.

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