Gallium Nitride Power Transistor

Abstract

The present disclosure relates to a gallium nitride (GaN) power transistor (100), the GaN power transistor having a buffer layer (110), a barrier layer (111) deposited on the buffer layer (110), with a gate region (112) formed on the barrier layer (111), a p-type doped gallium nitride (GaN) layer (113) deposited on the barrier layer (111) in the gate region (112), and a metal gate layer (114) deposited on the p-type doped GaN layer (113), the metal gate layer (114) forming a Schottky barrier (115) in contact with the p-type doped GaN layer (113), wherein the thickness of the p-type doped GaN layer (113), the metal type of the metal gate layer (114), and the p-type doping concentration of the p-type doped GaN layer (113) are based on known relationships of p-type doping concentration and gate metal type to p-type GaN Schottky gate depletion region thickness.

Description

[Technical field]

[0001] The present disclosure relates to the field of gallium nitride (GaN) technology for power device applications. In particular, the present disclosure relates to GaN power transistors, and more particularly to GaN power field effect transistors (FETs) with stable pGaN Schottky operation and metal-semiconductor junctions for such GaN power transistors. [Background technology]

[0002] Intensive efforts have been made in the semiconductor industry for the past 15-20 years to develop gallium nitride technology as a possible replacement for traditional Si-based field effect transistors. The use of wide band gap materials offers the potential for unprecedented performance improvements at both device and system levels. Today, enhancement mode GaN power FETs are becoming a reality, with several major semiconductor manufacturers already having products in the market. The most mature GaN device concept utilized by the majority of players is the pGaN normally-off concept. Two general approaches are currently followed for the fabrication of normally-off pGaN power FETs. The main difference lies in the fabrication strategy of the metal / pGaN interface. The two possible approaches are i) Ohmic interface and ii) Schottky interface. With the Schottky approach, a significant reduction in DC gate current can be achieved, but at the expense of two main drawbacks: threshold voltage instability and poor gate reliability. Summary of the Invention

[0003] It is an object of this disclosure to provide a GaN power transistor that does not suffer from the above-mentioned drawbacks of threshold voltage instability and poor gate reliability, or at least a solution for a GaN power transistor in which the problems of threshold voltage instability and poor gate reliability are significantly reduced.

[0004] This object is achieved by means of the features of the independent claims. Further implementations become apparent from the dependent claims, the description and the drawings.

[0005] The embodiments of the present disclosure provide a specific set of guideline optimizations for p-gate Schottky gate modules of GaN power transistors.

[0006] In particular, a precise set of relationships between different dimensions and doping concentrations of pGaN gate modules will be provided in this disclosure, which makes it possible to optimize the overall performance and solve the main problems of state-of-the-art pGaN Schottky gates, namely, threshold voltage instability and gate reliability.

[0007] In this disclosure, a fully depleted pGaN Schottky gate solution is presented that can be achieved by appropriately dimensioning the pGaN gate geometry in relation to a specific p-type doping concentration, e.g., achieved by magnesium doping, although other dopings can be used as well.

[0008] What was found during testing with different parameters is that the preferred guideline optimization strategy for pGaN Schottky gate modules can be summarized as follows: (1) pGaN thickness < 65 nm (2) p-type doping concentration: [1e18cm -3 -1e19cm -3 ] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W, or any combination of these in a stacked configuration.

[0009] This disclosure presents a new pGaN Schottky gate module concept suitable for enhancement mode GaN-based power transistors, which allows for the following advantages: normally-off operation; stable threshold voltage and suppression of dynamic instabilities that characterize conventional pGaN Schottky gate approaches; and improved gate reliability due to a significant reduction in the peak electric field at the metal / pGaN interface and in the pGaN bulk.

[0010] To describe the invention in detail, the following terms, abbreviations and notations are used.

[0011] GaN Gallium Nitride FET Field Effect Transistor pGaN p-doped GaN AlGaN Aluminum Gallium Nitride 2DEG Two-dimensional electron gas HV High voltage (operating), e.g. >600V MV Medium voltage (operating), e.g. 200-600V V TH Threshold Voltage TDDB Time Dependent Dielectric Breakdown.

[0012] In this disclosure, two approaches to fabricating a metal / pGaN interface are described: an Ohmic interface approach and a Schottky interface approach.

[0013] In the ohmic interface approach, the interface between the metal gate and the pGaN surface is nearly ideal, which leads to a large DC current that sustains device operation during the on-state condition, but also complicates the driving strategy and significantly increases the driving losses.

[0014] The ohmic interface approach offers the following advantages: (i) the pGaN node is neatly connected to the gate metal terminal, and therefore the device is V TH(ii) the reliability is good, and gate breakdown is due to thermal runaway when a large DC current flows through the gate; (iii) a large amount of holes injected from the gate improves the dynamic performance.

[0015] However, the ohmic interface approach introduces the following drawbacks: (i) a large amount of holes injected into the buffer requires a negative off-phase gate voltage; (ii) hole accumulation can cause tail current; (iii) a dedicated driving scheme is required: a current-driven gate driver, an external RC network; and (iv) the large DC gate current leads to drive losses, limiting the scalability of the concept to high voltages (400-600 V) and large R DSON (>30mOhm).

[0016] In the Schottky interface approach, a reverse-biased Schottky diode is inserted in series with the pn-p GaN / AlGaN diode, which allows for a significant reduction in the DC gate current.

[0017] The Schottky interface approach offers the following advantages: (i) the pGaN node is isolated from the gate terminal by a reverse-biased Schottky diode; (ii) the V TH A low DC gate current is obtained at the expense of instability; (iii) a low DC current implies a more difficult dynamic effect optimization due to a smaller amount of holes injected into the buffer; (iv) the gate module breaks down via the TDDB mechanism (like the oxide in Si-MOS devices); (v) the dynamic effects, gate reliability, and V TH A difficult interplay between stability.

[0018] However, the Schottky interface approach presents the following drawbacks: (i) it does not offer the best FOM (figure of merit) (low C GS and C GD(ii) there is essentially no DC gate current; (iii) the approach allows standard driving schemes such as voltage driving approaches, no external RC network; (iv) the concept can be used in both HV and MV operation; (v) the concept has a very low R DSON Allows device scaling to

[0019] This disclosure focuses on providing optimized guidelines for the Schottky interface approach to overcome the above-mentioned shortcomings.

[0020] According to a first aspect, the present disclosure relates to a Gallium Nitride (GaN) power transistor having a buffer layer, a barrier layer deposited on the buffer layer, where a gate region is formed on the barrier layer, a p-type doped Gallium Nitride (GaN) layer deposited on the barrier layer in a gate region, and a metal gate layer deposited on the p-type doped GaN layer, where the metal gate layer is in contact with the p-type doped GaN layer to form a Schottky barrier, wherein a thickness of the p-type doped GaN layer, a metal type of the metal gate layer, and a p-type doping concentration of the p-type doped GaN layer are based on a known relationship of pGaN Schottky gate depletion region thickness to p-type doping concentration and gate metal type.

[0021] Such GaN power transistors offer a new pGaN Schottky-gate module concept suitable for enhancement-mode GaN-based power transistors, which allows for the following advantages: normally-off operation; stable threshold voltage and suppression of the dynamic instabilities that characterize conventional pGaN Schottky-gate approaches; and improved gate reliability due to a significant reduction in the peak electric field at the metal / pGaN interface and in the pGaN bulk.

[0022] In one exemplary implementation of the GaN power transistor, the thickness of the p-type doped GaN layer is less than 65 nanometers.

[0023] This provides the following advantages: The thickness of the p-doped GaN layer affects the selectivity of the etching process to define the gate region. A thinner layer of p-doped GaN results in better lithographic definition of the gate region. A further advantage is that minimizing the p-GaN layer results in an increase in device transconductance (gm). Furthermore, the device threshold voltage increases with increasing pGaN thickness. Thus, a p-doped GaN layer thickness smaller than 65 nanometers results in a stable threshold voltage of the transistor.

[0024] In one exemplary implementation of the GaN power transistor, the metal gate layer is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked configuration.

[0025] This provides the advantage that the different properties of these metals, such as conductivity, current carrying capacity, robustness, durability, acid resistance, electrical properties, etc., can be utilized to advantage.

[0026] In one exemplary implementation of the GaN power transistor, the p-type doping concentration of the p-type doped GaN layer is 1e18 cm -3 -1e19cm -3 is within the range.

[0027] When the p-type doping concentration of the p-type doped GaN layer is within such a range, the tunneling events of hole injection from the metal layer to the p-GaN layer are strongly attenuated. Using a p-type doping concentration within such a range allows a significant reduction in the static gate current under application of a positive voltage to the gate electrode.

[0028] In one exemplary implementation of the GaN power transistor, the p-type doped GaN layer is fully depleted during operation of the GaN power transistor.

[0029] When the p-type doped GaN layer is fully depleted, the transistor can operate with optimized performance, with high gate reliability, and without exhibiting threshold voltage instability.

[0030] In one exemplary implementation of the GaN power transistor, the known relationship of pGaN Schottky gate depletion region thickness to p-type doping concentration and gate metal type is based on a given data set that enables stable operation of the GaN power transistor.

[0031] By using such a predefined data set, for example as illustrated in FIG. 4, the overall performance of the GaN power transistor can be optimized.

[0032] In one exemplary implementation of the GaN power transistor, the predetermined data set enables optimal (or improved) operation of the GaN power transistor with respect to static performance, dynamic performance, and gate reliability.

[0033] Such GaN power transistors enable optimal (or improved) operation in normally-off operation, with stable threshold voltages, suppressed dynamic instabilities, and improved gate reliability due to the significant reduction in the peak electric field at the metal / pGaN interface.

[0034] In one exemplary implementation of the GaN power transistor, the GaN power transistor is configured to enable normally-off operation.

[0035] This offers the advantage that, for example, in power electronic systems, normally-off transistors can ensure safe operation.

[0036] In one exemplary implementation of the GaN power transistor, the p-type doped GaN layer and the metal gate layer are lithographically defined only in the gate region of the barrier layer.

[0037] This provides the advantage that the manufacturing process can be performed precisely, enabling the manufacture of GaN power transistors with high gate reliability.

[0038] In one exemplary implementation of the GaN power transistor, the buffer layer comprises a GaN layer or an aluminum gallium nitride (AlGaN) layer.

[0039] The buffer layer comprising GaN or AlGaN improves the electron mobility of the transistor, which in turn reduces the reverse leakage current in the transistor and improves the on-off ratio of the transistor.

[0040] In one exemplary implementation of the GaN power transistor, the barrier layer comprises an AlGaN layer.

[0041] Transistors having such barrier layers exhibit improved RF and DC performance.

[0042] In one exemplary implementation of the GaN power transistor, a buffer layer is formed on at least one transition layer formed on a silicon substrate.

[0043] Such a power transistor provides improved gate leakage current reduction.

[0044] According to a second aspect, the present disclosure provides a metal-semiconductor junction for a gallium nitride (GaN) power transistor, the metal-semiconductor junction having a p-type doped GaN layer and a metal gate layer deposited on the p-type doped GaN layer, the metal gate layer contacting the p-type doped GaN layer to form a Schottky barrier, the p-type doping concentration of the p-type doped GaN layer being greater than or equal to 1e18 cm -3 -1e19cm -3 is within the range.

[0045] Such metal-semiconductor junctions in GaN power transistors offer the following advantages: normally-off operation; stable threshold voltage and suppression of the dynamic instabilities that characterize conventional pGaN Schottky gate approaches; and improved gate reliability due to a significant reduction in the peak electric field at the metal / pGaN interface and within the pGaN bulk.

[0046] When the p-type doping concentration of the p-type doped GaN layer is within the above range, the tunneling events of hole injection from the metal layer to the p-type GaN layer are strongly attenuated. Using a p-type doping concentration within such a range allows a significant reduction in the static gate current under the application of a positive voltage to the gate electrode.

[0047] In one exemplary implementation of the metal-semiconductor junction, the thickness of the p-type doped GaN layer is less than 65 nanometers.

[0048] This provides the following advantages: The thickness of the p-doped GaN layer affects the selectivity of the etching process to define the gate region. A thinner layer of p-doped GaN results in better lithographic definition of the gate region. A further advantage is that minimizing the p-GaN layer results in an increase in device transconductance (gm). Furthermore, the device threshold voltage increases with increasing pGaN thickness. Thus, a p-doped GaN layer thickness smaller than 65 nanometers results in a stable threshold voltage of the transistor.

[0049] In one exemplary implementation of the metal-semiconductor junction, the metal gate layer is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked configuration.

[0050] This provides the advantage that the different properties of these metals, such as conductivity, current carrying capacity, robustness, durability, acid resistance, electrical properties, etc., can be utilized to advantage. [Brief description of the drawings]

[0051] Further embodiments of the present invention will now be described with reference to the following figures. [Figure 1] 1 shows a design of a GaN power transistor 100 with a Schottky barrier according to a first example. [Diagram 2] 2 shows a design of a GaN power transistor 200 with a Schottky barrier according to a second example. [Diagram 3] 3 illustrates an equivalent circuit design 300 of a gate module of a GaN power transistor with a Schottky barrier according to the present disclosure. [Figure 4] 4 illustrates an example of design guidelines 400 according to the present disclosure for a Schottky interface with respect to depletion region versus doping concentration. [Diagram 5] 5 shows an exemplary performance simulation 500 of threshold voltage stability of a pGaN Schottky gate as a function of stress time. [Figure 6] 6 illustrates a design of a metal-semiconductor junction 600 for a GaN power transistor according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] In the following detailed description, references are made to the accompanying drawings, which form a part of the detailed description, and which show, by way of illustration, specific aspects in which the present disclosure may be practiced. It is to be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0053] It is understood that a comment made in connection with a described method may also apply to a corresponding device or system configured to perform the method, and vice versa. For example, where a particular method step is described, a corresponding device may include units for performing the described method step, even if such units are not explicitly described or shown. It is also understood that features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0054] The semiconductor devices and systems described herein may be implemented in wireless communication schemes, particularly in communication schemes according to 5G. The described semiconductor devices may be used to produce integrated circuits and / or power semiconductors and may be manufactured according to various technologies. For example, these semiconductor devices may be used in logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, optical circuits, memory circuits, and / or integrated passive components.

[0055] A Schottky barrier, as described in this disclosure, is a potential energy barrier for electrons that forms at a metal-semiconductor junction. A Schottky barrier has rectifying properties that make it suitable for use as a diode. One of the main properties of a Schottky barrier is its Schottky barrier height. The Schottky barrier height depends on the metal and semiconductor combination. Not all metal-semiconductor junctions form a rectifying Schottky barrier, and metal-semiconductor junctions that conduct current in both directions without rectification, perhaps because their Schottky barrier is too low, are called ohmic contacts.

[0056] FIG. 1 shows the design of a GaN power transistor 100 with a Schottky barrier according to a first example.

[0057] The GaN power transistor 100 includes a buffer layer 110, a barrier layer 111 deposited on the buffer layer 110, on which a gate region 112 is formed, a p-type doped GaN layer 113 deposited on the barrier layer 111 in the gate region 112, and a metal gate layer 114 deposited on the p-type doped GaN layer 113, the metal gate layer 114 being in contact with the p-type doped GaN layer 113 to form a Schottky barrier 115. The thickness of the p-type doped GaN layer 113, the metal type of the metal gate layer 114, and the p-type doping concentration of the p-type doped GaN layer 113 are based on known relationships of pGaN Schottky gate depletion region thickness 401 to p-type doping concentration 402 and gate metal type, such as relationship 400 shown in FIG.

[0058] A source (S) metal layer 120 and a drain (D) metal layer 121 may be formed laterally relative to the barrier layer 111. The source metal layer 120 and the drain metal layer 121 may be separated from the pGaN layer 113 and the metal gate layer 114 by the barrier layer 111. The source metal layer 120 and the drain metal layer 121 may extend to the same height as the barrier layer 111 and therefore to a lower level than the metal gate layer 114.

[0059] The buffer layer 110 may comprise a GaN layer or an aluminum gallium nitride (AlGaN) layer. The barrier layer 111 may comprise an AlGaN layer.

[0060] In one example of transistor 100, the thickness of p-type doped GaN layer 113 may be less than 65 nanometers.

[0061] In one example of the transistor 100, the metal gate layer 114 may be comprised of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked configuration.

[0062] In one example of transistor 100, the p-type doping concentration of p-type doped GaN layer 113 is 1e18 cm -3 -1e19cm-3 The range may be:

[0063] In one example of transistor 100, p-type doped GaN layer 113 may be fully depleted during operation of the GaN power transistor 100.

[0064] In one example of transistor 100, a known relationship of pGaN Schottky gate depletion region thickness 401 to p-type doping concentration 402 and gate metal type (e.g., relationship 400 shown in FIG. 4) may be based on a predetermined data set that enables stable operation of GaN power transistor 100.

[0065] In one example of the transistor 100, the predetermined data set enables optimal (or improved) operation of the GaN power transistor 100 with respect to static performance, dynamic performance, and gate reliability.

[0066] What was found during testing with different parameters, a suitable data set for a pGaN Schottky gate module can be summarized as follows: (1) pGaN thickness < 65 nm (2) p-type doping concentration: [1e18cm -3 -1e19cm -3 ] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W, or any combination of these in a stacked configuration.

[0067] In one example of transistor 100, transistor 100 may be configured to allow for normally-off operation.

[0068] In one example of transistor 100 , p-type doped GaN layer 113 and metal gate layer 114 may be lithographically defined only in the gate region of barrier layer 111 .

[0069] In one example of transistor 100, buffer layer 110 may be formed on at least one transition layer (e.g., layers 202, 203 as shown in the example of FIG. 2) formed on a silicon substrate (e.g., substrate 201 as shown in the example of FIG. 2).

[0070] FIG. 2 shows a design of a GaN power transistor 200 with a Schottky barrier according to a second example.

[0071] GaN power transistor 200 may be designed similarly to transistor 100 described above with respect to FIG.

[0072] GaN power transistor 200 includes a buffer layer 110, a barrier layer 111 deposited on buffer layer 110 with a gate region 112 formed on barrier layer 111, a p-type doped GaN layer 113 deposited on barrier layer 111 in gate region 112, and a metal gate layer 114 deposited on p-type doped GaN layer 113 in contact with p-type doped GaN layer 113 to form a Schottky barrier 115. Buffer layer 110 is formed on a transition layer 203 which is formed on a nucleation layer 202. Nucleation layer 202 is formed on a silicon substrate 201.

[0073] The thickness of the p-type doped GaN layer 113, the metal type of the metal gate layer 114, and the p-type doping concentration of the p-type doped GaN layer 113 are based on known relationships of pGaN Schottky gate depletion region thickness 401 to p-type doping concentration 402 and gate metal type, such as relationship 400 shown in FIG.

[0074] Laterally to the barrier layer 111, a source (S) metal layer 120 and a drain (D) metal layer 121 may be formed. The source metal layer 120 and the drain metal layer 121 may be separated from the pGaN layer 113 and the metal gate layer 114 by a passivation layer 204. The source metal layer 120 and the drain metal layer 121 may extend to the same height as the metal gate layer 114. Alternatively, the source metal layer 120 and the drain metal layer 121 may extend to a lower level than the metal gate layer 114, for example according to the design shown in FIG.

[0075] The buffer layer 110 may comprise a GaN layer or an aluminum gallium nitride (AlGaN) layer. The barrier layer 111 may comprise an AlGaN layer.

[0076] In one example of transistor 200, the thickness of p-type doped GaN layer 113 may be less than 65 nanometers.

[0077] In one example of transistor 200, metal gate layer 114 may be comprised of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stacked configuration.

[0078] In one example of transistor 200, the p-type doping concentration of p-type doped GaN layer 113 is 1e18 cm -3 -1e19cm -3 The range may be:

[0079] In one example of transistor 100, p-type doped GaN layer 113 may be fully depleted during operation of GaN power transistor 200.

[0080] In one example of transistor 200, a known relationship of pGaN Schottky gate depletion region thickness 401 to p-type doping concentration 402 and gate metal type (e.g., relationship 400 shown in FIG. 4) may be based on a predetermined data set that enables stable operation of GaN power transistor 200.

[0081] In one example of transistor 200, the predetermined data set enables optimal (or improved) operation of GaN power transistor 200 with respect to static performance, dynamic performance, and gate reliability.

[0082] What was found during testing with different parameters, a suitable data set for a pGaN Schottky gate module can be summarized as follows: (1) pGaN thickness < 65 nm (2) p-type doping concentration: [1e18cm -3 -1e19cm -3 ] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W, or any combination of these in a stacked configuration.

[0083] In one example of transistor 200, transistor 200 may be configured to enable normally-off operation.

[0084] In one example of transistor 200 , the p-type doped GaN layer 113 and the metal gate layer 114 may be lithographically defined only in the gate region of the barrier layer 111 .

[0085] FIG. 3 shows an equivalent circuit design 300 of a gate module of a GaN power transistor with a Schottky barrier according to the present disclosure.

[0086] In the Schottky approach as shown in FIG. 3, a reverse-biased Schottky diode 302 is inserted in series with the pn-p GaN / AlGaN diode 301 as shown in the driving scheme 300b. This allows for a significant DC gate current reduction as shown in the example of FIG. 3. A capacitance C W A series connection of a reverse-biased Schottky diode 302 having a capacitance Cp in parallel with the reverse-biased Schottky diode 302 is shown in the equivalent circuit 300a.

[0087] Threshold voltage instability (positive and negative) is observed in the Schottky approach, which means that the device TH (in the case of positive V TH For example, dynamic behavior of the threshold voltage can be observed for pGaN Schottky gates when a positive stress voltage is applied to the gate electrode.

[0088] Weak gate robustness is also observed with the Schottky approach. Time-dependent dielectric breakdown (TDDB) behavior is observed, similar to the breakdown of the gate dielectric in conventional Si-based power devices. Several theories have been proposed to explain the gate failure mechanism, and one possible root cause has been identified as an impact ionization effect in the depletion region of the reverse-biased Schottky diode, caused by electrons injected into the pGaN layer from the AlGaN barrier. Tests with the electric field distribution in the pGaN layer under a positive voltage applied to the gate electrode show that the maximum electric field is located at the metal / pGaN interface.

[0089] Most Schottky-gate pGaN approaches today use very high doping (>5e19 cm) in the pGaN layer. -3 ) The typical thickness of the pGaN layer is generally between 80 and 250 nm. The p-type doping concentration can be extracted via conventional SIMS profile measurements.

[0090] It has been demonstrated that hole depletion and accumulation (time- and geometry-dependent) causes threshold voltage instability. Also, the very high doping concentration used in the pGaN layer induces a very narrow depletion region at the metal / pGaN interface. The main drawback of this approach is that the electric field in the narrow depletion region reaches very high values ​​(about 5-10 MV / cm), strongly compromising the overall gate reliability. It is believed that the high electric field in the depletion region causes a strong acceleration of electrons injected from the 2DEG into the pGaN layer. These accelerated electrons can promote carrier multiplication through impact ionization effects and the presence of a large number of high-energy carriers, causing damage (percolation pathways) at the metal / pGaN interface, ultimately compromising the overall gate reliability.

[0091] Several attempts have been investigated in the past few years to improve the gate reliability of pGaN gate modules and to mitigate the threshold voltage instability of pGaN Schottky gates. For example, a direct correlation between the static DC gate current and the overall gate reliability has been observed. A reduction in the static gate current unfortunately leads to a higher threshold voltage instability due to the presence of a large amount of floating holes in the pGaN layer that can be injected into the AlGaN barrier and / or recombine with electrons injected into the pGaN layer from the 2DEG without being replenished by the metal gate electrode.

[0092] For the reasons mentioned above, the present disclosure presents a solution of how to overcome the above-mentioned shortcomings of pGaN Schottky gate modules, which are large positive and negative threshold voltage instability and poor gate reliability.

[0093] The solution according to the present disclosure provides a specific set of guidelines optimization for the p-gate Schottky gate module of GaN power transistors. A set of precise relationships between different dimensions and doping concentrations of the pGaN gate module is provided in this disclosure, which allows optimizing the overall performance and solving the main problems of state-of-the-art pGaN Schottky gates, namely, threshold voltage instability and gate reliability. By properly dimensioning the pGaN gate geometry in relation to a specific p-type doping concentration, a fully depleted pGaN Schottky gate solution can be achieved, for example, by magnesium doping, although other dopings can be used as well.

[0094] As discussed above with respect to FIGS. 1 and 2, such a preferred guideline optimization strategy for a pGaN Schottky gate module can include one or more of the following features: (1) pGaN thickness < 65 nm (2) p-type doping concentration: [1e18cm -3 -1e19cm -3 ] (3) Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W, or any combination of these in a stacked configuration.

[0095] FIG. 4 illustrates an example of design guidelines 400 according to the present disclosure for a Schottky interface with respect to depletion region versus doping concentration.

[0096] In the example of Figure 4, the thickness of the depletion region at the metal / pGaN interface, e.g. between layers 114 and 113 shown in Figures 1, 2 and 6, is shown as a function of the p-type doping concentration for e.g. Mg used as the dopant element. However, other dopant elements can be used as well. The bold line with symbols 410 defines the extent of the depletion region formed at the interface between the metal gate 114 and the underlying p-type doped GaN layer 113 as a function of the p-type doping concentration used in the pGaN layer 113 for a particular metal type of the metal gate 114. Figure 4 also shows the dependence of the depletion region on the metal type of the metal gate 114 used to create the Schottky interface 115 with the underlying pGaN layer 113.

[0097] FIG. 4 also shows one horizontal line B and one vertical line A. These two lines, together with the depletion region line, represent the boundaries of the safe operating area of ​​the Schottky pGaN gate module. In particular, line A represents the threshold p-type doping concentration below which the tunneling events of hole injection from the metal layer to the pGaN layer are strongly attenuated. Reducing the p-type doping concentration below this threshold also allows a significant reduction in the static gate current under the application of a positive voltage to the gate electrode.

[0098] On the other hand, line B represents the maximum thickness of the pGaN layer 113 that is proposed to have optimized operation of the pGaN Schottky gate module. This maximum thickness is chosen according to three main guiding criteria:

[0099] 1) pGaN etch process optimization: The metal gate 114 and the p-type doped layer 113 must be lithographically defined only in the gate region 112. The metal gate 114 and the p-type doped layer 113 typically undergo several masking steps followed by an etching step. The etching must be carefully controlled to selectively stop at the pGaN / AlGaN barrier interface 113, 111. If this etching step is not properly controlled, undesired etching of the AlGaN barrier 111 can occur with resulting degradation of device performance. The thickness of the p-type GaN can also affect the selectivity of the etching process.

[0100] 2) Transconductance optimization: The pGaN layer 113 must be minimized to increase the device transconductance (gm).

[0101] 3) Threshold voltage: The device threshold voltage increases with increasing pGaN thickness.

[0102] In this disclosure, the following ranges of device dimensions and doping concentrations are presented that allow having optimal (or improved) operation of pGaN Schottky gate modules based on the following guidelines for gate module optimization, where optimal (or improved) operation is defined in terms of static performance (threshold voltage, gate current), dynamic performance (dynamic threshold voltage), and last but not least, improved gate reliability.

[0103] In particular, FIG. 4 shows the simulated performance of a pGaN Schottky gate as a function of the voltage applied to the gate electrode for different values ​​of p-type doping concentration used in the pGaN layer 113. It can be observed how the reduction of the p-type concentration, following the guidelines given below, suppresses the dynamic threshold voltage instability and at the same time achieves a dramatic reduction in the peak electric field at the metal / pGaN interface 114, 113. The reduction in the peak electric field translates directly into an improvement in the overall gate module reliability. In fact, the main reason for Schottky pGaN gate breakdown is believed to be caused by impact ionization events, which are promoted and sustained by the high electric field in the Schottky depletion region.

[0104] The depletion region also depends on the metal type of the metal gate.

[0105] It has been shown that a gradual reduction in the p-type concentration in the pGaN layer 113, together with geometry optimization of the gate module, can provide significant benefits in terms of both threshold voltage instability and reduction of the peak electric field in the pGaN layer.

[0106] The preferred guideline optimization strategy for pGaN Schottky gate modules can be summarized as follows: 1. pGaN thickness < 65nm 2. P-type doping concentration: [1e18cm -3 -1e19cm -3 ] 3. Metal type of metal gate: Al, Ti, TiN, Au, Pd, Ni, W or any combination of these in stacks.

[0107] FIG. 4 illustrates an example data set 403 that follows these guidelines.

[0108] FIG. 5 shows an example performance simulation 500 of the threshold voltage stability 501 of a pGaN Schottky gate as a function of stress time 502.

[0109] The first graph 510 shows the results for the guidelines described in this disclosure, i.e., pGaN thickness < 65 nm, [1e18 cm -3 -1e19cm -3 5 shows the performance of pGaN Schottky gates designed according to p-type doping concentrations between 501 and 502, and metal gate types Al, Ti, TiN, Au, Pd, Ni, W, or any combination of these in a stacked configuration, with the threshold voltage being very stable and also stable over long stress times 502.

[0110] A second graph 511 shows the performance of another pGaN Schottky gate designed close to the guidelines above. The threshold voltage of graph 511 is also fairly stable, with small instabilities occurring only after long stress times 502.

[0111] The third graph 512 and the fourth graph 513 were not designed according to the guidelines of this disclosure. Instead, they show very high doping in the pGaN layer (>5e19 cm -3 ) and having a pGaN layer thickness between 80 nm and 250 nm. The threshold voltages of both graphs 512 and 513 show unstable behavior from the start.

[0112] 6 shows a design of a metal-semiconductor junction 600 of a GaN power transistor according to an example. The metal-semiconductor junction 600 may be implemented, for example, in a GaN power transistor 100 as shown in FIG. 1 or a GaN power transistor 200 as shown in FIG.

[0113] The metal-semiconductor junction 600 includes a p-type doped GaN layer 113 and a metal gate layer 114 deposited on the p-type doped GaN layer 113. The metal gate layer 114 contacts the p-type doped GaN layer 113 to form a Schottky barrier 115. The p-type doping concentration of the p-type doped GaN layer 113 is 1e18 cm -3 From 1e19cm -3 is within the range.

[0114] The thickness of the p-type doped GaN layer 113 may be less than 65 nanometers.

[0115] The metal gate layer 114 may be made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stack.

[0116] The thickness of the p-type doped GaN layer 113, the metal type of the metal gate layer 114, and the p-type doping concentration of the p-type doped GaN layer 113 can be based on the known relationship 400 of pGaN Schottky gate depletion region thickness 401 to p-type doping concentration 402 and gate metal type, as shown in FIG. 4 and described above with respect to FIGS. 1 and 2.

[0117] Although a particular feature or aspect of the present disclosure may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of other implementations as may be desirable and advantageous for any given or particular application. Also, to the extent that the terms "including," "having," "comprising," or other variations thereof are used in either the detailed description or the claims, such terms are intended to be as inclusive as the term "having." Also, the terms "exemplary," "for example," and "example" are not meant to be best or optimal, but merely as an example. Along with derivatives, the terms "coupled" and "connected" may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact with each other or are not in direct contact with each other.

[0118] While specific aspects have been illustrated and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific aspects illustrated and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects described herein.

[0119] Although elements in the following claims are described in a particular order with corresponding labeling, the elements are not necessarily intended to be limited to being implemented in that particular order, unless the claim recitation otherwise indicates a particular order for implementing some or all of those elements.

[0120] In light of the above teachings, numerous alternatives, modifications, and variations will be apparent to those skilled in the art. Of course, those skilled in the art will readily recognize that there are many applications of the present invention other than those described herein. Although embodiments of the present invention have been described with reference to one or more specific embodiments, those skilled in the art will recognize that numerous modifications can be made thereto without departing from the scope of the embodiments of the present invention. It is therefore to be understood that, within the scope of the appended claims and their equivalents, the present invention may be practiced other than as specifically described herein.

Claims

1. 1. A gallium nitride (GaN) power transistor, comprising: A buffer layer; a barrier layer deposited on the buffer layer, the barrier layer having a gate region formed thereon; a p-type doped gallium nitride (GaN) layer deposited on the barrier layer in the gate region; a metal gate layer deposited on the p-type doped GaN layer, the metal gate layer in contact with the p-type doped GaN layer forming a Schottky barrier; having the thickness of the p-type doped GaN layer, the metal type of the metal gate layer, and the p-type doping concentration of the p-type doped GaN layer are based on a known relationship of pGaN Schottky gate depletion region thickness to p-type doping concentration and gate metal type; the thickness of the p-type doped GaN layer is less than 65 nanometers; the metal gate layer is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stack; the p-type doping concentration of the p-type doped GaN layer is in the range of 1e18 cm −3 -1e19 cm −3 , and The p-type doped GaN layer is fully depleted during operation of the GaN power transistor. GaN power transistor.

2. the known relationship of the pGaN Schottky gate depletion region thickness to the p-type doping concentration and the gate metal type is based on a predetermined data set that enables stable operation of the GaN power transistor.

2. The GaN power transistor of claim 1.

3. the predetermined data set enables optimal operation of the GaN power transistor with respect to static performance, dynamic performance, and gate reliability; 3. The GaN power transistor of claim 2.

4. The GaN power transistor is configured to enable normally-off operation.

4. A GaN power transistor according to claim 1.

5. the p-type doped GaN layer and the metal gate layer are lithographically defined only in the gate region of the barrier layer.

5. A GaN power transistor according to claim 1.

6. The buffer layer comprises a GaN layer or an aluminum gallium nitride (AlGaN) layer.

6. A GaN power transistor according to claim 1.

7. The barrier layer comprises an AlGaN layer.

7. A GaN power transistor according to any one of claims 1 to 6.

8. the buffer layer is formed on at least one transition layer formed on a silicon substrate; 8. A GaN power transistor according to any one of claims 1 to 7.

9. A metal-semiconductor junction in a gallium nitride (GaN) power transistor, the metal-semiconductor junction comprising: a p-type doped GaN layer; a metal gate layer deposited on the p-type doped GaN layer; having the metal gate layer is in contact with the p-type doped GaN layer to form a Schottky barrier; The p-type doping concentration of the p-type doped GaN layer is 1e18 cm －３ -1e19cm －３ is within the range the thickness of said p-type doped GaN layer is less than 65 nanometers; the metal gate layer is made of one of the following metals: Al, Ti, TiN, Au, Pd, Ni, W, or any combination thereof in a stack; and The p-type doped GaN layer is fully depleted during operation of the GaN power transistor. Metal-semiconductor junction.

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