Method for manufacturing nitride semiconductor device

Abstract

To provide a technique of activating impurities injected into a nitride semiconductor layer while the formation of pit that may affect the electric characteristics is suppressed.SOLUTION: A manufacturing method for a nitride semiconductor device 1 includes an ion injection step of ion-injecting impurities into an ion injection region 24A in a nitride semiconductor layer 20 including the ion injection region and a non-ion injection region 23A on one main surface, a light absorption film forming step of forming light absorption films 44, 54, and 66 in a part over the one main surface of the nitride semiconductor layer, in which the light absorption films are selectively formed over the ion injection region of the nitride semiconductor layer, and a light irradiation step of irradiating the light absorption film with light, in which the energy of the light is larger than the energy of the bandgap of the light absorption film.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] Development of nitride semiconductor devices is underway. To manufacture this type of nitride semiconductor device, a technique is required to implant impurity ions into a nitride semiconductor layer and activate the implanted impurity ions to form an n-type or p-type diffusion region.

[0003] In order to activate the impurity ions implanted into the nitride semiconductor layer, a high-temperature annealing process is required. For example, the p-type impurity magnesium requires an annealing process at approximately 1400°C or higher. However, it is known that such a high-temperature annealing process decomposes the nitride semiconductor layer and forms pits in the surface layer of the nitride semiconductor layer. In particular, if a large pit that penetrates the diffusion region is formed, it can cause leakage current to flow.

[0004] Patent Document 1 proposes a technique for suppressing the formation of pits by performing a high-temperature annealing treatment under an atmospheric pressure equal to or higher than the saturated vapor pressure of a nitride semiconductor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2020-155469 A Summary of the Invention [Problem to be solved by the invention]

[0006] The present specification provides a technique capable of activating impurities ion-implanted into a nitride semiconductor layer while suppressing the formation of pits that would affect electrical characteristics. [Means for solving the problem]

[0007] The method for manufacturing a nitride semiconductor device disclosed in this specification may include an ion implantation step, a light absorbing film formation step, and a light irradiation step. In the ion implantation step, impurities are ion-implanted into one of the main surfaces of a nitride semiconductor layer (20) having an ion implantation region (24A) and a non-ion implantation region (23A). In the light absorbing film formation step, a light absorbing film (44, 54, 66) is formed on a part above the one of the main surfaces of the nitride semiconductor layer. In the light absorbing film formation step, the light absorbing film is further selectively formed above the one of the main surfaces of the ion implantation region of the nitride semiconductor layer. In the light irradiation step, light is irradiated onto the light absorbing film. The energy of the light is greater than the band gap energy of the light absorbing film.

[0008] According to this manufacturing method, the one main surface side of the nitride semiconductor layer is heated by the heat of the light absorbing film that absorbs the light in the light irradiation step. Therefore, the entire nitride semiconductor layer is not heated, and the one main surface side of the nitride semiconductor layer is heated. Furthermore, the light absorbing film is selectively provided above the ion implantation region of the nitride semiconductor layer. Therefore, the ion implantation region of the nitride semiconductor layer can be efficiently heated. This makes it possible to activate the impurities ion-implanted in the ion implantation region while suppressing the formation of large pits that penetrate the ion implantation region. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a main portion of a nitride semiconductor device; [Diagram 2] 1 is a schematic cross-sectional view of a main part in a manufacturing process of a first manufacturing method of a nitride semiconductor device. [Diagram 3] 1 is a schematic cross-sectional view of a main part in a manufacturing process of a first manufacturing method of a nitride semiconductor device. [Figure 4] 1 is a schematic cross-sectional view of a main part in a manufacturing process of a first manufacturing method of a nitride semiconductor device. [Diagram 5]1 is a schematic cross-sectional view of a main part in a manufacturing process of a first manufacturing method of a nitride semiconductor device. [Figure 6] 1 is a schematic cross-sectional view of a main part in a manufacturing process of a first manufacturing method of a nitride semiconductor device. [Figure 7] 1 is a schematic cross-sectional view of a main part in a manufacturing process of a first manufacturing method of a nitride semiconductor device. [Figure 8] 5A and 5B are schematic cross-sectional views of essential parts in a manufacturing process of a second manufacturing method for a nitride semiconductor device. [Figure 9] 5A and 5B are schematic cross-sectional views of essential parts in a manufacturing process of a second manufacturing method for a nitride semiconductor device. [Figure 10] 5A and 5B are schematic cross-sectional views of essential parts in a manufacturing process of a second manufacturing method for a nitride semiconductor device. [Figure 11] 10A and 10B are schematic cross-sectional views of a main part in a manufacturing process of a third manufacturing method for a nitride semiconductor device. [Figure 12] 10A and 10B are schematic cross-sectional views of a main part in a manufacturing process of a third manufacturing method for a nitride semiconductor device. [Figure 13] 10A and 10B are schematic cross-sectional views of a main part in a manufacturing process of a third manufacturing method for a nitride semiconductor device. [Figure 14] 10A and 10B are schematic cross-sectional views of a main part in a manufacturing process of a third manufacturing method for a nitride semiconductor device. [Figure 15] 10A and 10B are schematic cross-sectional views of a main part in a manufacturing process of a third manufacturing method for a nitride semiconductor device. [Figure 16] 10A and 10B are schematic cross-sectional views of a main part in a manufacturing process of a third manufacturing method for a nitride semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] 1, the nitride semiconductor device 1 includes a nitride semiconductor layer 20, a drain electrode 32 provided so as to cover the back surface of the nitride semiconductor layer 20, a source electrode 34 provided so as to cover a part of the front surface of the nitride semiconductor layer 20, and a planar type insulated gate portion 36 provided on a part of the front surface of the nitride semiconductor layer 20. The nitride semiconductor layer 20 includes an n-type drain region 21, an n-type drift region 22, an n-type JFET region 23, a p-type body region 24, and an n-type source region 25.

[0011] The drain region 21 is provided at a position exposed on the lower surface of the nitride semiconductor layer 20, and is in ohmic contact with the drain electrode 32. The drain region 21 is, for example, gallium nitride (GaN) containing n-type impurities.

[0012] The drift region 22 is provided on the drain region 21, and is disposed between the drain region 21 and the JFET region 23, and between the drain region 21 and the body region 24. The drift region 22 is, for example, gallium nitride (GaN) containing n-type impurities.

[0013] The JFET region 23 is provided on the drift region 22, at a position exposed on the surface of the nitride semiconductor layer 20, extends in the thickness direction from the surface of the drift region 22 to the surface of the nitride semiconductor layer 20, and has a form protruding from the surface of the drift region 22. In other words, the JFET region 23 extends from the surface of the nitride semiconductor layer 20 through the body region 24 to the drift region 22. The JFET region 23 is, for example, gallium nitride (GaN) containing n-type impurities. In this example, the impurity concentration of the JFET region 23 is equal to the impurity concentration of the drift region 22, and can be said to be a part of the drift region 22.

[0014] The body region 24 is provided on the drift region 22 and is adjacent to the side of the JFET region 23. The body region 24 is, for example, gallium nitride (GaN) containing p-type impurities.

[0015] The source region 25 is provided on the body region 24, at a position exposed on the surface of the nitride semiconductor layer 20, and is separated from the drift region 22 and the JFET region 23 by the body region 24. The source region 25 is, for example, gallium nitride (GaN) containing n-type impurities. The source region 25 is in ohmic contact with the source electrode 34.

[0016] The insulating gate portion 36 is provided on a portion of the surface of the nitride semiconductor layer 20, and has a gate insulating film 36a made of silicon oxide and a gate electrode 36b made of polysilicon. The gate electrode 36b faces the channel region CH of the body region 24 in a portion separating the JFET region 23 and the source region 25, and the JFET region 23, via the gate insulating film 36a.

[0017] Next, the operation of the nitride semiconductor device 1 will be described. During use, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 36b, an inversion layer is formed in the channel region CH between the JFET region 23 and the source region 25, and electrons flow from the source region 25 to the JFET region 23 through the inversion layer. The electrons that flow into the JFET region 23 flow vertically through the JFET region 23 toward the drain electrode 32. This brings the drain electrode 32 and the source electrode 34 into conduction, and the nitride semiconductor device 1 is turned on. When the gate electrode 36b is grounded, the inversion layer disappears, and the nitride semiconductor device 1 is turned off. In this way, the nitride semiconductor device 1 can perform a switching operation of switching on and off between the drain electrode 32 and the source electrode 34 based on the voltage applied to the gate electrode 36b.

[0018] (First Manufacturing Method of Nitride Semiconductor Device 1) First, as shown in FIG. 2, an n-type GaN drift region 22 is epitaxially grown from the surface of a drain region 21, which is a GaN substrate, using an epitaxial growth technique to form a nitride semiconductor layer 20.

[0019] 3, a mask 42 is formed by using photolithography to cover a part of the surface of the nitride semiconductor layer 20. The mask 42 is selectively formed on the surface of the nitride semiconductor layer 20 in a region 23A where the JFET region 23 (see FIG. 1) is to be formed. In other words, the mask 42 has an opening formed in a region 24A where the body region 24 (see FIG. 1) is to be formed. The region 23A where the JFET region 23 (see FIG. 1) is to be formed is an example of a non-ion-implanted region, and the region 24A where the body region 24 (see FIG. 1) is to be formed is an example of an ion-implanted region.

[0020] 4, magnesium ions are implanted as a p-type impurity into the ion implantation region 24A in the surface layer of the nitride semiconductor layer 20 using an ion implantation technique (ion implantation step). Magnesium may be implanted in multiple stages into the ion implantation region 24A of the nitride semiconductor layer 20 by changing the implantation energy.

[0021] Next, as shown in Fig. 5, a light absorbing film 44 is formed by using a deposition technique so as to cover the surface of the nitride semiconductor layer 20. Since the light absorbing film 44 is formed on the surface of the nitride semiconductor layer 20 while the mask 42 remains, the light absorbing film 44 is also formed on the top surface of the mask 42. Next, as shown in Fig. 6, the mask 42 is selectively removed by using a wet etching technique. This removes the light absorbing film 44 formed on the top surface of the mask 42. As a result, the light absorbing film 44 is selectively formed on the surface of the ion implantation region 24A of the nitride semiconductor layer 20 (light absorbing film forming step).

[0022] The material of the light absorbing film 44 is a material whose band gap energy is smaller than that of the nitride semiconductor layer 20, i.e., that of gallium nitride (GaN). Furthermore, the material of the light absorbing film 44 is a material whose melting point is higher than that of the nitride semiconductor layer 20, i.e., that of gallium nitride (GaN). In this example, the material of the light absorbing film 44 is, for example, carbon (C) or aluminum gallium arsenide (AlGaAs), which satisfies these requirements. The light absorbing film 44 made of carbon may be metastable graphite in the carbon phase diagram, or may have a structure containing graphite. Such a light absorbing film 44 can be formed by using, for example, CVD technology or sputtering technology.

[0023] Next, as shown in FIG. 7, light is irradiated toward the surface of the nitride semiconductor layer 20 using a flash lamp annealing technique (light irradiation step). This light irradiation step is performed under normal pressure. The wavelength of the irradiated light is selected from a wavelength range in which the energy of the light is smaller than the band gap energy of the nitride semiconductor layer 20, i.e., the band gap energy of gallium nitride (GaN). Therefore, the irradiated light is not absorbed by the nitride semiconductor layer 20. On the other hand, the wavelength of the irradiated light is selected from a wavelength range in which the energy of the light is larger than the band gap energy of the light absorbing film 44. Therefore, the irradiated light is absorbed by the light absorbing film 44. The irradiated light is not particularly limited, but is, for example, infrared light.

[0024] When the light absorbing film 44 absorbs light in the light irradiation step, the temperature of the light absorbing film 44 rises. The heat of the light absorbing film 44 is conducted to the surface side of the nitride semiconductor layer 20, the surface side of the nitride semiconductor layer 20 is heated, and the magnesium ions implanted in the ion implantation region 24A are activated to form the body region 24. At the same time, the non-ion implantation region 23A, which was a part of the drift region 22, becomes the JFET region 23.

[0025] In this light irradiation process, the entire nitride semiconductor layer 20 is not heated, but the surface side of the nitride semiconductor layer 20 is heated. For example, in this light irradiation process, the temperature profile in the thickness direction of the nitride semiconductor layer 20 is controlled so that the temperature is 1400° C. or higher at the surface of the nitride semiconductor layer 20 and 800° C. or lower at the junction between the drift region 22 and the body region 24. The temperature of 1400° C. is the temperature at which magnesium, an ion-implanted p-type impurity, is activated. The temperature of 800° C. is the decomposition temperature of gallium nitride (GaN) at normal pressure. By controlling the temperature to obtain such a temperature profile, it is possible to suppress the decomposition of gallium nitride (GaN) in the drift region 22 while activating magnesium on the surface side of the nitride semiconductor layer 20. Therefore, as shown in FIG. 7, the pit 10 formed in the surface portion of the nitride semiconductor layer 20 is suppressed from becoming large enough to penetrate the body region 24. As a result, in the nitride semiconductor device 1 manufactured, an increase in the leakage current between the drain and source is suppressed.

[0026] Furthermore, the light absorbing film 44 is selectively provided above the ion implantation region 24A of the nitride semiconductor layer 20. Therefore, the ion implantation region 24A of the nitride semiconductor layer 20 can be efficiently heated. This makes it possible to suppress heating of the non-ion implantation region 23A, and therefore suppress the formation of pits in the JFET region 23. Pits formed in the JFET region 23 cause electric field concentration in the insulating gate portion 36 above it, which causes an increase in gate leakage current. The above manufacturing method can also suppress such an increase in gate leakage current.

[0027] Next, by forming the source region 25, the gate insulating film 36a, the gate electrode 36b, the drain electrode 32, and the source electrode 34 using known manufacturing techniques, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.

[0028] (Second Manufacturing Method of Nitride Semiconductor Device 1) The second manufacturing method is similar to the first manufacturing method up to the step shown in Fig. 3. However, in the second manufacturing method, the mask 42 is removed before proceeding to the next step.

[0029] As shown in FIG. 8, a protective film 52 is formed by utilizing a deposition technique so as to cover the surface of the nitride semiconductor layer 20 (protective film forming step). The protective film 52 is formed on both the surfaces of the non-ion-implanted region 23A and the ion-implanted region 24A of the nitride semiconductor layer 20. The material of the protective film 52 is a material having a melting point higher than the melting point of the nitride semiconductor layer 20, i.e., the melting point of gallium nitride (GaN). Furthermore, the material of the protective film 52 is a material having a band gap larger than the energy of light irradiated in the light irradiation step described below. In this example, the material of the protective film 52 is, for example, aluminum nitride (AlN), which satisfies these requirements.

[0030] 9, a light absorbing film 54 is formed by using photolithography and deposition techniques so as to cover the surface of the protective film 52. The light absorbing film 54 is selectively formed above the ion implantation region 24A of the nitride semiconductor layer 20 (light absorbing film forming process). The material of the light absorbing film 54 may be the same as that of the light absorbing film 44 in the first manufacturing method.

[0031] Next, as shown in FIG. 10, light is irradiated toward the surface of the nitride semiconductor layer 20 using a flash lamp annealing technique (light irradiation step). This light irradiation step is performed under normal pressure. When the light absorbing film 54 absorbs light in the light irradiation step, the temperature of the light absorbing film 54 increases. Heat from the light absorbing film 54 is thermally conducted to the surface side of the nitride semiconductor layer 20 via the protective film 52, the surface side of the nitride semiconductor layer 20 is heated, and the magnesium ions implanted in the ion implantation region 24A are activated to form the body region 24. As with the first manufacturing method, the second manufacturing method can activate the magnesium ions implanted in the ion implantation region 24A to form the body region 24 while suppressing the formation of large pits 10 that penetrate the body region 24.

[0032] Furthermore, in the second manufacturing method, a protective film 52 is formed on the surface of the nitride semiconductor layer 20. A material having a melting point higher than that of the nitride semiconductor layer 20 is used as the material of the protective film 52. By being covered with the protective film 52 having such a high melting point, decomposition of the nitride semiconductor layer 20 is suppressed, and the formation of the pits 10 is further suppressed. In particular, in the second manufacturing method, since the protective film 52 is formed on the surface of the JFET region 23, the formation of the pits 10 in the JFET region 23 can be effectively suppressed compared to the first manufacturing method in which no film is formed on the surface of the JFET region 23.

[0033] Next, by forming the source region 25, the gate insulating film 36a, the gate electrode 36b, the drain electrode 32, and the source electrode 34 using known manufacturing techniques, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.

[0034] (Third Manufacturing Method of Nitride Semiconductor Device 1) In the third manufacturing method, the steps up to the step shown in FIG. 2 are the same as those in the first manufacturing method.

[0035] 11, a protective film 62 is formed by utilizing a vapor deposition technique so as to cover the surface of the nitride semiconductor layer 20 (protective film forming step). The material of the protective film 62 can be the same as that of the protective film 52 in the second manufacturing method.

[0036] 12, a mask 64 is formed by photolithography to cover a part of the surface of the protective film 62. The mask 64 is selectively formed above the nitride semiconductor layer 20 in correspondence with the non-ion-implanted region 23A. In other words, the mask 64 has an opening formed in correspondence with the ion-implanted region 24A.

[0037] 13, magnesium is ion-implanted as a p-type impurity into the ion-implanted region 24A in the surface layer of the nitride semiconductor layer 20 using an ion implantation technique (ion implantation step). Magnesium may be implanted in multiple stages into the ion-implanted region 24A of the nitride semiconductor layer 20 by changing the implantation energy. In this way, the protective film 62 also functions as a through film during ion implantation, and can adjust the amount and depth of magnesium ion implantation.

[0038] As shown in FIG. 14, a light absorbing film 66 is formed so as to cover the surface of the protective film 62. The material of the light absorbing film 66 can be the same as that of the light absorbing film 44 in the first manufacturing method. The light absorbing film 66 is formed on the surface of the protective film 62 while the mask 64 remains, and therefore is also formed on the top surface of the mask 64. Next, as shown in FIG. 15, the mask 64 is selectively removed using a wet etching technique. This removes the light absorbing film 66 formed on the top surface of the mask 64. As a result, the light absorbing film 66 is selectively formed above the ion implantation region 24A of the nitride semiconductor layer 20 (light absorbing film forming process).

[0039] Next, as shown in FIG. 16, light is irradiated toward the surface of the nitride semiconductor layer 20 using a flash lamp annealing technique (light irradiation step). This light irradiation step is performed under normal pressure. When the light absorbing film 66 absorbs light in the light irradiation step, the temperature of the light absorbing film 66 rises. The heat of the light absorbing film 66 is thermally conducted to the surface side of the nitride semiconductor layer 20 via the protective film 62, the surface side of the nitride semiconductor layer 20 is heated, and the magnesium ion-implanted in the ion-implanted region 24A is activated to form the body region 24. As with the first manufacturing method, the third manufacturing method can activate the magnesium ion-implanted in the ion-implanted region 24A to form the body region 24 while suppressing the formation of a large pit 10 that penetrates the body region 24. Furthermore, as with the second manufacturing method, the third manufacturing method can effectively suppress the formation of a pit 10 in the JFET region 23 because the protective film 62 is formed on the surface of the JFET region 23.

[0040] Next, by forming the source region 25, the gate insulating film 36a, the gate electrode 36b, the drain electrode 32, and the source electrode 34 using known manufacturing techniques, the nitride semiconductor device 1 shown in FIG. 1 can be manufactured.

[0041] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0042] The method for manufacturing a nitride semiconductor device disclosed in this specification may include an ion implantation step of ion-implanting impurities into an ion-implanted region of a nitride semiconductor layer having an ion-implanted region and a non-ion-implanted region on one main surface side, a light-absorbing film formation step of forming a light-absorbing film on a part above the one main surface of the nitride semiconductor layer, the light-absorbing film being selectively formed above the ion-implanted region of the nitride semiconductor layer, and a light irradiation step of irradiating the light-absorbing film with light, the energy of the light being greater than the band gap energy of the light-absorbing film. The impurity to be ion-implanted is not particularly limited, but may be, for example, magnesium, which is a p-type impurity. Magnesium requires a high temperature to be activated well. For this reason, the manufacturing method disclosed in this specification is particularly useful for activating magnesium, which requires such a high-temperature annealing treatment. The light-absorbing film may be formed directly on the one main surface of the nitride semiconductor layer, or may be formed via another layer.

[0043] In the above manufacturing method, the energy of the light irradiated in the light irradiation step may be smaller than the band gap energy of the nitride semiconductor layer. Although not particularly limited, for example, infrared light can be used as the light irradiated in the light irradiation step. The energy of the infrared light is smaller than the band gap of the nitride semiconductor layer. When the light under such conditions is used, the light is not absorbed by the nitride semiconductor layer in the light irradiation step, so that heating of the entire nitride semiconductor layer is suppressed.

[0044] The above manufacturing method may further include a protective film forming step of forming a protective film having a melting point higher than that of the nitride semiconductor layer on a part of the one main surface of the nitride semiconductor layer, the protective film being formed on at least the one main surface of the non-ion-implanted region of the nitride semiconductor layer. In this case, the energy of the light irradiated in the light irradiation step may be smaller than the band gap energy of the protective film. By forming such a protective film, it is possible to suppress the formation of pits in the non-ion-implanted region.

[0045] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful. [Explanation of symbols]

[0046] 1: nitride semiconductor device, 20: nitride semiconductor layer, 21: drain region, 22: drift region, 23: JFET region, 23A: non-ion-implanted region, 24: body region, 24A: ion-implanted region, 25: source region, 32: drain electrode, 34: source electrode, 36: insulated gate portion, 36a: gate insulating film, 36b: gate electrode, 44, 54, 66: light absorbing film, 52, 62: protective film

Claims

1. A method for manufacturing a nitride semiconductor device (1), comprising the steps of: a protective film forming step of forming a protective film (62) having a melting point higher than that of the nitride semiconductor layer on one main surface of the nitride semiconductor layer (20) having an ion implantation region (24A) and a non-ion implantation region (23A) on the one main surface side; an ion implantation step of ion-implanting impurities into the ion implantation region through the protective film; a light absorbing film forming step of forming a light absorbing film (66) on a part of the protective film, the light absorbing film being selectively formed above the ion implantation region of the nitride semiconductor layer; A light irradiation step of irradiating the light absorbing film with light, the energy of the light being greater than the band gap energy of the light absorbing film; the energy of the light irradiated in the light irradiation step is smaller than the band gap energy of the nitride semiconductor layer, The method for manufacturing a nitride semiconductor device, wherein the energy of the light irradiated in the light irradiation step is smaller than the band gap energy of the protective film.

2. 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said impurity ions implanted in said ion implantation step are magnesium.

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