Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of maintaining pressure resistance.SOLUTION: There is provided a semiconductor device using a compound semiconductor having a wurtzite structure. The semiconductor device includes a drift layer of a first conductivity type. The semiconductor device includes a body layer of a second conductivity type in contact with the top face of the drift layer. The semiconductor device includes a source region of the first conductivity type arranged on the top of the body layer. The semiconductor device includes a trench penetrating through the source region and the body layer from the top face of the source region to reach the drift layer. The trench includes a side wall formed by an m-plane and a first bottom face formed by a c-plane. The semiconductor device includes a specific film arranged on the first bottom face. The semiconductor device includes a gate insulating film arranged on the top face of the specific film and the side wall. A first corner with roundness is formed between the first bottom face and the side wall. The specific film covers the first corner.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Non-Patent Documents 1 and 2 disclose techniques for fabricating vertical trench MOSFETs using GaN as the material. A trench is formed by dry etching, and then wet etching is performed using a TMAH chemical solution to form flat sidewalls (m-planes) that become channels. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching(Applied Physics Express 1 021104 (2008)) [Non-Patent Document 2] T. Ishida, S. Yamada, T. Narita, and T. Kachi, ISPlasma2019, 2019, 19pF16O Summary of the Invention [Problem to be solved by the invention]

[0004] In wet etching of GaN using a TMAH chemical solution, the etching rates of the m-plane and c-plane are slower than those of other planes. Therefore, by etching a trench with a TMAH chemical solution, it is possible to form flat sidewalls (m-plane) and bottom surface (c-plane). However, as a result of flattening the sidewalls and bottom surface of the trench, sharp corners are formed where the sidewalls and bottom surface intersect perpendicularly. Electric field concentration at these corners may reduce the breakdown voltage of the semiconductor device. [Means for solving the problem]

[0005] The semiconductor device disclosed in this specification is a semiconductor device that uses a compound semiconductor having a wurtzite structure. The semiconductor device includes a drift layer of a first conductivity type. The semiconductor device includes a body layer of a second conductivity type in contact with an upper surface of the drift layer. The semiconductor device includes a source region of a first conductivity type disposed on an upper portion of the body layer. The semiconductor device includes a trench that extends from an upper surface of the source region through the source region and the body layer to reach the drift layer. The trench includes a sidewall formed on the m-plane and a first bottom surface formed on the c-plane. The semiconductor device includes a specific film disposed on the first bottom surface. The semiconductor device includes a gate insulating film disposed on an upper surface and a sidewall of the specific film. A first corner portion having a rounded shape is formed between the first bottom surface and the sidewall. The specific film covers the first corner portion.

[0006] In the semiconductor device, the first corner of the first bottom surface of the trench is covered with a specific film. Since the first corner can be protected by the specific film, the first corner can be maintained in a rounded state during the trench formation process. Since the electric field concentration at the first corner can be mitigated, the breakdown voltage of the semiconductor device can be maintained. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device 1 according to a first embodiment. [Diagram 2] 2 is a flow diagram illustrating a manufacturing method of the semiconductor device 1. FIG. [Diagram 3] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. [Figure 4] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. [Diagram 5] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. [Figure 6] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. [Figure 7]FIG. 11 is a cross-sectional view of a semiconductor device 1a according to a second embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing method of the semiconductor device 1a. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing method of the semiconductor device 1a. [Figure 10] 1A to 1C are cross-sectional views illustrating a manufacturing method of the semiconductor device 1a. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The technical elements disclosed in this specification are listed below. Note that each of the technical elements below is useful independently.

[0009] In one example of the semiconductor device disclosed in this specification, the specific film may be a dielectric film.

[0010] According to this configuration, the specific film can reduce the electric field.

[0011] In an example semiconductor device disclosed in the present specification, the trench may have a second bottom surface formed of a c-plane. The second bottom surface may be disposed between the first bottom surface and the sidewall and disposed above the first bottom surface. The first bottom surface may be connected to the second bottom surface via a first corner portion. The second bottom surface may be connected to the sidewall via a second corner portion. The radius of curvature of the second corner portion may be smaller than the radius of curvature of the first corner portion. The second bottom surface and the second corner portion may be covered with a gate insulating film.

[0012] According to this configuration, the first bottom surface can be disposed below the second bottom surface. The electric field is concentrated at the first bottom surface, which is the lowest part of the trench, but since the radius of curvature of the corners of the first bottom surface is large, the electric field can be alleviated at the first bottom surface. It is possible to suppress the electric field concentration at the second corners of the second bottom surface.

[0013] In one example of the semiconductor device disclosed in the present specification, a specific region of a second conductivity type may be formed below the first bottom surface and in contact with the first bottom surface. In a top view of the semiconductor device, the width of the specific region may be smaller than the width between the sidewalls of the trench.

[0014] According to this configuration, a depletion layer can be formed by the pn junction between the specific region of the second conductivity type and the drift layer of the first conductivity type, so that the electric field can be relaxed at the bottom of the trench. In addition, when the semiconductor device is on, a channel inversion layer is generated in the region facing the trench sidewall, so that a current path is formed along the trench sidewall. Since the width of the specific region is smaller than the width between the sidewalls of the trench, the effect of the depletion layer formed by the specific region on the current path can be suppressed. It is possible to suppress an increase in the on-resistance of the semiconductor device.

[0015] A method for manufacturing a semiconductor device according to an example disclosed in the present specification includes a trench forming step of forming a trench having a longitudinal direction in the <11-20> direction from a surface of a compound semiconductor substrate having a wurtzite structure and a c-plane. A corner portion connecting a bottom surface and a sidewall of the trench is rounded. The manufacturing method includes a step of forming a specific film on the bottom surface and sidewall of the trench, the film thickness of which is thicker than that of the sidewall. The manufacturing method includes a step of etching the specific film so that the specific film remains on the bottom surface and the corner portions and the sidewall is exposed. The manufacturing method includes a sidewall etching step of etching the sidewall using an etchant whose etching rate of the specific film is lower than that of the compound semiconductor substrate and whose etching rate of the m-plane is lower than that of other surfaces. The manufacturing method includes a step of forming a gate insulating film on an upper surface and sidewall of the specific film.

[0016] According to this manufacturing method, the sidewalls can be etched while the corners of the bottom surface of the trench are protected by a specific film. In the sidewall etching process, the corners can be kept rounded. Since the electric field concentration at the corners can be mitigated, the breakdown voltage of the semiconductor device can be maintained.

[0017] In the example method for manufacturing a semiconductor device disclosed in this specification, the specific film may be a dielectric film.

[0018] According to this configuration, the specific film can reduce the electric field.

[0019] In the example semiconductor device manufacturing method disclosed in the present specification, the trench formed in the trench forming step may have a tapered cross-sectional shape in which the width of the opening is larger than the width of the bottom surface. The trench after the sidewall etching step may have a rectangular cross-sectional shape in which the width of the bottom surface is expanded to approximately the same as the width of the opening.

[0020] According to this manufacturing method, a flat m-plane can be exposed on the sidewall by the sidewall etching process. An electric field is concentrated on the bottom surface of the trench, which is covered with a specific film, but the radius of curvature of the corners of this bottom surface is large, so the electric field can be alleviated. It is possible to suppress the electric field concentration on the newly formed corners of the bottom surface.

[0021] The method for manufacturing a semiconductor device according to the example disclosed herein may further include, after the trench forming step, a step of ion-implanting an impurity into the bottom surface of the trench, the impurity being an impurity for forming a conductivity type opposite to that of a compound semiconductor substrate in which the bottom surface of the trench is disposed.

[0022] According to this manufacturing method, a region having a conductivity type opposite to that of the compound semiconductor substrate can be formed below the bottom surface. A depletion layer due to a pn junction can be formed below the bottom surface, which enables electric field relaxation at the bottom surface of the trench. EXAMPLES

[0023] (Structure of Semiconductor Device 1) FIG. 1 shows a cross-sectional view of a side surface of a semiconductor device 1. The semiconductor device 1 is a power semiconductor element known as a MOSFET. The semiconductor device 1 is of a trench gate type. In FIG. 1, reference numeral 10 indicates a GaN substrate. The GaN substrate 10 is a compound semiconductor substrate having a wurtzite structure. A surface 10s of the GaN substrate 10 is a (0001) plane (c-plane). A source electrode 30 is formed on the surface 10s of the GaN substrate 10, and a drain electrode 31 is formed on the back surface. The GaN substrate 10 is an n + A drain layer 11, an n-type drift layer 12, a p-type body layer 13, + Source region 14 of type and p + The semiconductor device has a body contact region 15.

[0024] In the GaN substrate 10, a trench 20 is formed, which penetrates from the upper surface of the source region 14 through the source region 14 and the body layer 13 to reach the drift layer 12. The trench 20 includes a sidewall 20s, a first bottom surface 20b1, and a first corner portion 20c1. The sidewall 20s is a surface formed by the m-plane of GaN. The first bottom surface 20b1 is a surface formed by the c-plane of GaN. The m-plane is a general term for the (1-100) plane, the (10-10) plane, the (-1010) plane, the (-1100) plane, the (01-10) plane, and the (0-110) plane. The m-plane is a non-polar plane. The m-plane is a plane parallel to the c-axis in the

[0001] direction and perpendicular to the c-plane. The first corner portion 20c1 is a portion that connects the first bottom surface 20b1 and the sidewall 20s, and has a rounded shape.

[0025] A specific film 21 is disposed on the first bottom surface 20b1. In this embodiment, the specific film 21 is a silicon nitride film (Si3N4) and is a dielectric. The specific film 21 covers the first corner portion 20c1. A gate insulating film 22 is disposed on the upper surface and sidewall 20s of the specific film 21. The gate insulating film 22 can be a film type different from the specific film 21, specialized for gate performance. The film type of the gate insulating film 22 can be, for example, an Al2O3-based or SiO2-based film. The inside of the trench 20 is filled with a conductive trench gate electrode 23 via the gate insulating film 22. An interlayer insulating film 24 is formed on the upper surface of the trench gate electrode 23. The interlayer insulating film 24 insulates the trench gate electrode 23 from the source electrode 30.

[0026] (Method of Manufacturing Semiconductor Device 1) A method for manufacturing the semiconductor device 1 will be described with reference to the flow in Fig. 2 and the cross-sectional views in Fig. 3 to Fig. 6. In step S10, a GaN substrate 10 is prepared in which a drain layer 11, a drift layer 12, and a body layer 13 are stacked in this order. Ions are implanted from a surface 10s of the GaN substrate 10 to form a source region 14 and a body contact region 15.

[0027] In step S20, a trench 20 having a longitudinal direction in the <11-20> direction is formed from the surface 10s of the GaN substrate 10 (see FIG. 3). Since the surface 10s of the GaN substrate 10 is a c-plane, the sidewall 20s is an m-plane and the first bottom surface 20b1 is a c-plane. The trench 20 can be formed by known photolithography and dry etching techniques. By adjusting the dry etching conditions, the sidewall 20s can be formed to be approximately perpendicular to the surface 10s of the substrate and the first corner 20c1 can be formed to be rounded.

[0028] In step S30, a specific film 21 (silicon nitride film) is formed on the first bottom surface 20b1 and the sidewall 20s of the trench 20 (see FIG. 4). The specific film 21 is formed so that the film thickness T1 on the first bottom surface 20b1 is thicker than the film thickness T2 on the sidewall 20s. Such a specific film 21 may be formed by a film formation method having anisotropy such that the film thickness on the bottom surface is thicker than that on the sidewall. For example, a CVD method or a PVD method with poor step coverage may be used.

[0029] In step S40, the specific film 21 is etched so that the specific film 21 remains on the first bottom surface 20b1 and the first corner portion 20c1, and the specific film 21 on the sidewall 20s is removed (see FIG. 5). This allows only the sidewall 20s to be exposed while the first corner portion 20c1 is covered with the specific film 21. Specifically, since the film thickness T1 of the first bottom surface 20b1 is thicker than the film thickness T2 of the sidewall 20s, the specific film 21 on the sidewall 20s alone can be selectively removed by isotropically etching the specific film 21. In this embodiment, the specific film 21 (silicon nitride film) was etched by wet etching using hot phosphoric acid.

[0030] In step S50, the sidewall 20s is etched using an etching method in which the etching rate of the specific film 21 is lower than that of the GaN substrate 10 and the etching rate of the m-plane is lower than that of the other planes. In this embodiment, wet etching using TMAH (tetramethylammonium hydroxide) is performed. This allows the sidewall 20s to be etched while the first corner portion 20c1 is protected by the specific film 21. In addition, in the etching of the sidewall 20s, the etching automatically stops at the m-plane, so the sidewall 20s can be flattened. Since the sidewall 20s becomes a channel, flattening the sidewall 20s can improve device characteristics.

[0031] In the trench formation process in step S20, the sidewall 20s is formed substantially perpendicular to the surface 10s of the substrate. Since the sidewall 20s is formed substantially on the m-plane, the amount of etching of the sidewall 20s in step S50 is very small. Therefore, the change in the cross-sectional shape and width of the trench 20 before and after etching can be made negligible.

[0032] In step S60, a gate insulating film 22 is formed on the upper surface and sidewalls 20s of the specific film 21 (see FIG. 6). The gate insulating film 22 can be formed by a method with better step coverage than the specific film 21. In this embodiment, the gate insulating film 22 is an aluminum silicate (AlSiO) film formed by the ALD method.

[0033] In step S70, the trench gate electrode 23, the interlayer insulating film 24, the source electrode 30, and the drain electrode 31 are formed. Through the above steps, the semiconductor device 1 shown in FIG.

[0034] (effect) In step S50, the sidewall 20s can be etched while the first corner 20c1 is protected by the specific film 21, so that the first corner 20c1 can be maintained in a rounded state. Since the electric field concentration at the first corner 20c1 can be mitigated, the breakdown voltage of the semiconductor device 1 can be maintained.

[0035] During operation of the semiconductor device 1, an electric field is concentrated on the first bottom surface 20b1, which is the lowest part of the trench 20. By disposing a specific film 21 (silicon nitride film) that is a dielectric on the first bottom surface 20b1, the dielectric film thickness on the first bottom surface 20b1 can be made thicker than the dielectric film thickness on the sidewall 20s. Since the electric field can be relaxed on the first bottom surface 20b1, it is possible to maintain the breakdown voltage of the semiconductor device 1. EXAMPLES

[0036] (Structure of semiconductor device 1a) The semiconductor device 1a (FIG. 7) according to the second embodiment has a different shape of the bottom surface of the trench compared to the semiconductor device 1 (FIG. 1) according to the first embodiment. The same reference numerals are used to designate parts common to the semiconductor device 1 according to the first embodiment, and description thereof will be omitted.

[0037] The trench 20a includes a sidewall 20s, a first bottom surface 20b1, a first corner portion 20c1, a second bottom surface 20b2, and a second corner portion 20c2. The second bottom surface 20b2 is formed by a c-plane. The second bottom surface 20b2 is disposed between the first bottom surface 20b1 and the sidewall 20s and is disposed above the first bottom surface 20b1. The first bottom surface 20b1 is connected to the second bottom surface 20b2 via the first corner portion 20c1. The second bottom surface 20b2 is connected to the sidewall 20s via the second corner portion 20c2. The radius of curvature of the second corner portion 20c2 is smaller than the radius of curvature of the first corner portion 20c1. In other words, the first corner portion 20c1 is more rounded than the second corner portion 20c2. The first bottom surface 20b1 and the first corner portion 20c1 are covered with a specific film 21. The second bottom surface 20b2, the second corner portion 20c2 and the upper surface of the specific film 21 are covered with a gate insulating film 22.

[0038] In addition, a p-type specific region 16 is disposed below the first bottom surface 20b1. The specific region 16 is formed in contact with the first bottom surface 20b1. A width W1 of the specific region 16 is smaller than a width W2 between the sidewalls 20s of the trench 20a.

[0039] (Manufacturing method of semiconductor device 1a) In the flow diagram (FIG. 2) of Example 1, only the steps specific to Example 2 will be described. Fig. 8 shows trench 20a of Example 2 formed in the trench forming process of step S20. Trench 20a has a tapered cross-sectional shape in which width W12 of an opening is larger than width W11 of first bottom surface 20b1.

[0040] In the second embodiment, after the trench formation process in step S20, a process of ion-implanting a p-type impurity (e.g., magnesium) into the first bottom surface 20b1 is further included. This allows the specific region 16 to be formed below the first bottom surface 20b1, as shown in Fig. 8. The specific region 16 is a region having a p-type conductivity opposite to that of the n-type drift layer 12 in which the first bottom surface 20b1 is disposed.

[0041] In step S30, the specific film 21 is formed, and in step S40, the specific film 21 is etched. As a result, as shown in FIG 9, it is possible to expose only the sidewall 20s while the first corner portion 20c1 and the first bottom surface 20b1 are covered with the specific film 21.

[0042] In step S50, the sidewall 20s is etched using TMAH. In wet etching of GaN using a TMAH chemical, the etching rate of the m-plane and the c-plane is slower than that of other planes. Therefore, in etching the sidewall 20s, the etching automatically stops at the m-plane. Since the m-plane is perpendicular to the c-plane, the etching proceeds laterally so that the sidewall 20s becomes a plane perpendicular to the surface 10s of the substrate. In addition, the first corner 20c1 and the first bottom surface 20b1 are protected by the specific film 21, so they are not etched. Therefore, the etching proceeds so as to spread laterally with the upper surface 21s of the specific film 21 as a reference. As a result, as shown in FIG. 10, the width of the bottom surface of the trench 20a is expanded to approximately the same as the width W12 of the opening. Then, a second bottom surface 20b2, which is a new bottom surface, is formed in the same plane as the upper surface 21s of the specific film 21. Since the etching automatically stops at the c-plane, the second bottom surface 20b2 becomes the c-plane. Since the second bottom surface 20b2 (c-plane) and the side wall 20s (m-plane) intersect perpendicularly to each other, the cross-sectional shape of the trench 20a is rectangular. A second corner 20c2 with a small roundness is formed at the intersection. As a result, a structure can be formed in which the first bottom surface 20b1 covered with the specific film 21 protrudes below the second bottom surface 20b2. Thereafter, steps S60 and S70 are performed to complete the semiconductor device 1a shown in FIG. 7.

[0043] (effect) In the semiconductor device 1a (FIG. 7), the first bottom surface 20b1 can be disposed below the second bottom surface 20b2. The electric field is concentrated at the first bottom surface 20b1, which is the lowest part of the trench 20a, but since the radius of curvature of the first corner portion 20c1 of the first bottom surface 20b1 is large, the electric field can be alleviated at the first bottom surface 20b1. It is possible to suppress the electric field concentration at the second corner portion 20c2 of the second bottom surface 20b2.

[0044] Since a depletion layer can be formed by the pn junction between the p-type specific region 16 and the n-type drift layer, the electric field can be relaxed at the bottom of the trench 20a. Furthermore, when the semiconductor device 1a is turned on, a channel inversion layer IL is generated in the region facing the sidewall 20s, so a current path is formed along the sidewall 20s. Since the width W1 of the specific region 16 is smaller than the width W2 between the sidewalls 20s of the trench 20a, the effect of the depletion layer formed by the specific region 16 on the current path can be suppressed. It is possible to suppress an increase in the on-resistance of the semiconductor device 1a.

[0045] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility.

[0046] (Modification) The semiconductor device 1a (FIG. 7) of the second embodiment may be configured without the specific region 16. Even with this configuration, the effect of suppressing the electric field concentration at the second corner portion 20c2 can be obtained.

[0047] The compound semiconductor substrate constituting the semiconductor device 1 is not limited to GaN, but may be any compound semiconductor having a wurtzite structure, such as AlN.

[0048] The specific film 21 is not limited to a dielectric film. In step S50, any film may be used as long as it has an etching rate sufficiently lower than the etching rate of the compound semiconductor substrate. The specific film 21 is not limited to a silicon nitride film (Si3N4). For example, it may be a silicon oxide film.

[0049] The gate insulating film 22 is not limited to an AlSiO film, and may be, for example, a silicon oxide film formed by a CVD method.

[0050] The n-type is an example of a first conductivity type, and the p-type is an example of a second conductivity type. [Explanation of symbols]

[0051] 1: semiconductor device 12: drift layer 13: body layer 14: source region 16: specific region 20: trench 20b1: first bottom surface 20b2: second bottom surface 20c1: first corner portion 20c2: second corner portion 21: specific film 22: gate insulating film

Claims

1. A semiconductor device using a compound semiconductor having a wurtzite structure, A drift layer of a first conductivity type; a body layer of a second conductivity type in contact with an upper surface of the drift layer; a source region of a first conductivity type disposed on the body layer; a trench extending from an upper surface of the source region through the source region and the body layer to reach the drift layer, the trench including a sidewall formed in an m-plane, a first bottom surface formed in a c-plane, and a second bottom surface formed in a c-plane, the second bottom surface being disposed between the first bottom surface and the sidewall and above the first bottom surface; A specific film disposed on the first bottom surface; a gate insulating film disposed on an upper surface and a side wall of the specific film; Equipped with a first corner portion having a rounded shape is formed between the first bottom surface and the side wall; the first bottom surface is connected to the second bottom surface via the first corner portion, the specific film covers the first corner portion, the second bottom surface is connected to the side wall via a second corner portion; The radius of curvature of the second corner portion is smaller than the radius of curvature of the first corner portion, the second bottom surface and the second corner portion are covered with the gate insulating film.

2. a second conductivity type specific region formed below the first bottom surface in contact with the first bottom surface, The semiconductor device according to claim 1 , wherein a width of the specific region is smaller than a width between the side walls of the trench when viewed from above the semiconductor device.

3. A method for manufacturing a semiconductor device, comprising: A trench formation step of forming a trench having a longitudinal direction in a <11-20> direction from a surface of a compound semiconductor substrate having a wurtzite structure and a c-plane surface, the trench having rounded corners connecting a bottom surface and a sidewall of the trench; forming a specific film on a bottom surface and a side wall of the trench, the specific film having a thickness on the bottom surface greater than a thickness on the side wall; etching the specific film so that the specific film remains on the bottom surface and the corners and the sidewalls are exposed; a sidewall etching step of etching the sidewall using an etchant having an etching rate for the specific film lower than an etching rate for the compound semiconductor substrate and an etching rate for an m-plane lower than an etching rate for other planes; forming a gate insulating film on an upper surface and a side wall of the specific film; A manufacturing method of a semiconductor device comprising:

4. The method for manufacturing a semiconductor device according to claim 3 , wherein the specific film is a dielectric film.

5. The trench formed in the trench forming step has a tapered cross-sectional shape in which the width of the opening is larger than the width of the bottom surface, 5. The method for manufacturing a semiconductor device according to claim 3, wherein the trench after the sidewall etching step has a rectangular cross-sectional shape in which the width of the bottom surface is expanded to approximately the same as the width of the opening.

6. The method further includes a step of ion-implanting an impurity into the bottom surface after the trench forming step, 6. The method for manufacturing a semiconductor device according to claim 5, wherein the impurity is an impurity for forming a conductivity type opposite to a conductivity type of the compound semiconductor substrate on which the bottom surface of the trench is disposed.

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