Semiconductor Device

Abstract

A semiconductor device, having: an Si substrate (1); a first transistor (111) formed on the Si substrate (1), the first transistor (111) having a first source electrode (11), a first gate region (13), and a first drain electrode (14); and a second transistor (112) formed on the Si substrate (1), the second transistor (112) having a second source electrode (18), a second gate region (17), and a second drain electrode (15). The first source electrode (11), the second gate region (17), and the second source electrode (18) are essentially at the same potential, and the first drain electrode (14) and the second drain electrode (15) are essentially at the same potential.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device having a power transistor for switching. [Background technology]

[0002] In recent years, GaN transistors have been commercialized as power transistors for switching. GaN transistors are generally field-effect transistors that use GaN as a channel layer, AlGaN as a barrier layer, and two-dimensional electron gas generated by spontaneous polarization and piezoelectric polarization at the heterointerface formed by these two layers as a channel. The concentration of this two-dimensional electron gas can be adjusted by the film thickness and Al composition ratio of AlGaN. In general, increasing the concentration of two-dimensional electron gas reduces the on-resistance, but the threshold voltage also decreases. For switching transistors, it is desirable to have a positive and high threshold voltage for safe operation. Therefore, in GaN transistors, there is a trade-off between lowering the on-resistance and increasing the threshold voltage.

[0003] On the other hand, in the use of power transistors, the load is generally inductive. In this case, it is often necessary to pass a return current from the source to the drain when the power transistor is off. In a MOSFET, which is a power transistor that uses silicon as a semiconductor material, a body diode, which is a parasitic element, is built into the MOSFET due to the device structure, and this body diode acts as a return diode that passes the return current. However, in GaN transistors, there is generally no parasitic element such as a body diode. Therefore, a technology has been disclosed in Patent Document 1 in which a GaN Schottky barrier diode (SBD) is built in anti-parallel to a GaN transistor.

[0004] In addition, Patent Documents 2 and 3 disclose a technique for flowing a current in the reverse direction from source to drain using a channel formed from the drain to the source of a GaN transistor. In general, in a field effect transistor, when the gate and source are shorted, a current starts to flow from the source to the drain when the value of the source voltage (source-drain voltage) relative to the drain voltage exceeds the threshold voltage of the transistor. In a silicon MOSFET, the turn-on voltage of the body diode is about 0.7 V, which is lower than the threshold voltage (about 3 V), so the reflux current flows to the body diode before flowing through the channel. In contrast, a GaN transistor does not have a body diode, and the threshold voltage is generally low, about 1 to 2 V, to reduce the on-resistance, so that when the source-drain voltage exceeds the threshold voltage, a current automatically flows from the source to the drain through the channel of the GaN transistor.

[0005] Furthermore, Patent Document 4 discloses a technique in which a second transistor is disposed to protect the source-gate of a first transistor from a surge voltage, and a terminal that shorts the gate and source of the second transistor is connected to the source of the first transistor, and the drain terminal of the second transistor is connected to the gate of the first transistor. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2003-229566 A [Patent Document 2] JP 2007-215389 A [Patent Document 3] Special Publication No. 2011-512119 [Patent Document 4] JP 2011-165749 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the GaN power transistor of Patent Document 1, the method of incorporating a GaN-SBD has a problem in that the Schottky leakage of the GaN-SBD is large, making it difficult to achieve a high withstand voltage.

[0008] For example, GaN power transistors with a breakdown voltage of 600V or more can be fabricated relatively easily by using p-type GaN in the gate region or by using a MIS (Metal-Insulator-Semiconductor) structure. However, when forming a GaN-SBD on the same chip as a GaN power transistor, it is difficult to achieve a breakdown voltage of 600V or more due to the large Schottky leakage. The reason for the large Schottky leakage is thought to be that a good Schottky interface cannot be formed between the Schottky metal and GaN due to the large number of crystal defects in GaN.

[0009] In addition, in GaN power transistors for switching, in order to prevent false firing or to realize high-speed switching, a negative bias is often applied to the gate. When this negative bias driving is performed, if a method is used in which a return current is passed from the source to the drain using the transistor channel, the source-drain voltage at which a current starts to flow from the source to the drain is the sum of the threshold voltage and the absolute value of the negative bias voltage. For example, when a GaN power transistor with a threshold voltage of 1.5V is negatively biased by applying -3V to the gate, the return current does not flow unless the source-drain voltage exceeds 4.5V. Therefore, for example, in Patent Documents 2 to 4, when negative bias driving is performed, there is a problem that the power loss when passing the return current is large.

[0010] In view of the above problems, an object of the present disclosure is to provide a semiconductor device that can easily achieve high voltage resistance and reduce power loss when a return current flows even during negative bias driving. [Means for solving the problem]

[0011] In order to solve the above problem, a semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate, a first transistor formed on the semiconductor substrate, the first transistor having a first source electrode, a first gate region, and a first drain electrode, and a second transistor formed on the semiconductor substrate, the second transistor having a second source electrode, a second gate region, and a second drain electrode, wherein the first source electrode, the second gate region, and the second source electrode are at substantially the same potential, and the first drain electrode and the second drain electrode are at substantially the same potential. Effect of the Invention

[0012] According to the semiconductor device according to the present disclosure, it is possible to easily achieve a high withstand voltage and reduce power loss when a return current flows during negative bias driving. [Brief description of the drawings]

[0013] [Figure 1A] FIG. 1A is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment. [Figure 1B] FIG. 1B is a plan view showing a configuration example of the semiconductor device in the first embodiment. [Figure 1C] FIG. 1C is a diagram showing an equivalent circuit of the semiconductor device according to the first to eighth embodiments. [Figure 2A] FIG. 2A is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment. [Figure 2B] FIG. 2B is a cross-sectional view showing a modification of the semiconductor device in the second embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing a configuration example of a semiconductor device according to the third embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration example of a semiconductor device according to the fourth embodiment. [Diagram 5] FIG. 5 is a cross-sectional view showing a configuration example of a semiconductor device according to the fifth embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a configuration example of a semiconductor device according to the sixth embodiment. [Figure 7A]FIG. 7A is a cross-sectional view showing a configuration example of a semiconductor device in accordance with the seventh embodiment. [Figure 7B] FIG. 7B is a plan view showing a configuration example of the semiconductor device in the seventh embodiment. [Figure 8A] FIG. 8A is a cross-sectional view showing a configuration example of a semiconductor device in accordance with an eighth embodiment. [Figure 8B] FIG. 8B is a cross-sectional view showing a modification of the semiconductor device in the eighth embodiment. [Figure 8C] FIG. 8C is a cross-sectional view showing another modified example of the semiconductor device in accordance with the eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, the realization of the present disclosure is not limited to the current independent claims, and may be expressed by other independent claims.

[0015] Note that each figure is a schematic diagram and is not necessarily a precise illustration. Also, in each figure, duplicated explanations may be omitted or simplified. In the first to eighth embodiments, the same components are denoted by the same reference numerals except for the most significant digit, and duplicated explanations may be omitted.

[0016] (Embodiment 1) 1A and 1B respectively show a cross-sectional view and a plan view of a semiconductor device 101 of embodiment 1. Fig. 1A shows a cross-sectional view taken along line IA-IA in Fig. 1B. Fig. 1C shows an equivalent circuit of the semiconductor device 101. The equivalent circuit in Fig. 1C is common to the semiconductor devices of all embodiments.

[0017] First, an example of a circuit configuration of semiconductor device 101 will be described with reference to FIG. 1C.

[0018] The semiconductor device 101 includes a first transistor 111 and a second transistor 112 .

[0019] The first transistor 111 is a power switching element that switches a high voltage, which is, for example, 400 V or higher.

[0020] The second transistor 112 has its source and gate shorted and functions as a diode. Such a transistor with its source and gate shorted is called a transistor-type diode or a lateral field effect rectifier, but hereafter it will be referred to as a transistor-type diode. The second transistor 112 operates as a freewheeling diode connected in antiparallel to the first transistor 111.

[0021] The breakdown voltage of this transistor-type diode can be made equal to that of the first transistor 111, for example, by making the gate-drain distance of the first transistor 111 equal to that of the second transistor 112. That is, unlike a GaN-SBD, a transistor-type diode can easily achieve a high breakdown voltage of, for example, 600 V or more. In this way, the transistor-type diode formed from the second transistor 112 can have a higher breakdown voltage than an SBD, and can also reduce power loss even when negative bias driving is performed during the off period of the first transistor 111.

[0022] Furthermore, while the turn-on voltage of an SBD is determined by the Schottky barrier height between the semiconductor surface and the metal, in a transistor-type diode, the turn-on voltage is equal to the threshold voltage of the transistor that constitutes it. Therefore, while it is difficult to adjust the turn-on voltage of an SBD, it is possible to lower the turn-on voltage of a transistor-type diode by appropriately designing the gate structure. In other words, a transistor-type diode can pass a reflux current at a lower turn-on voltage than an SBD, making it possible to reduce the loss that occurs during this process.

[0023] Also, even if the first transistor 111 is driven to apply a negative bias to the gate during the off period, if the voltage between the source and drain exceeds the turn-on voltage of the transistor-type diode, a reflux current will flow regardless of the value of the negative bias. When using the channel of the power transistor to flow a drain current from the source, as in the conventional technology, the reflux current will not flow unless the voltage obtained by adding the absolute value of the threshold voltage of the power transistor and the negative bias voltage is applied between the source and drain. On the other hand, since the transistor-type diode is connected in inverse parallel to the first transistor 111, a reflux current will flow if a voltage equal to or greater than the turn-on voltage of the transistor-type diode is applied between the source and drain. Therefore, the power loss when the reflux current flows is reduced. In other words, even when negative bias driving is performed, it is possible to reduce the power loss during the off period.

[0024] Next, a specific device structure and circuit configuration of semiconductor device 101 will be described with reference to the cross-sectional views and plan views of FIG. 1A and FIG. 1B.

[0025] 1A, the semiconductor device 101 includes a Si substrate 1, which is a semiconductor substrate, and a first transistor 111 and a second transistor 112 formed on the Si substrate 1. The first transistor 111 has a first source electrode 11, a first gate electrode 12, a first gate region 13, and a first drain electrode 14. The second transistor 112 has a second source electrode 18, a second gate region 17, a second gate electrode 16, and a second drain electrode 15.

[0026] The first source electrode 11, the second gate region 17, and the second source electrode 18 are substantially at the same potential. The first drain electrode 14 and the second drain electrode 15 are substantially at the same potential. Here, substantially at the same potential typically means that they are connected by conductive wiring, but is not limited to this. Since the second gate region 17 is in direct contact with the second gate electrode 16, it can be said that it is substantially at the same potential as the first source electrode 11 and the second source electrode 18 connected to the second gate electrode 16 by wiring. Furthermore, substantially at the same potential includes not only the case where two or more potentials are the same, but also the case where they are within the error range. The error range is, for example, within the range of plus or minus 5%.

[0027] In addition, an AlN layer 2 as a nucleation layer, a buffer layer 3, a channel layer 4 containing GaN, and a barrier layer 5 containing AlGaN are formed on a Si substrate 1. At the interface between the channel layer 4 and the barrier layer 5, a high concentration of two-dimensional electron gas is formed due to the effects of piezoelectric polarization and spontaneous polarization. In order to increase the resistance of the two-dimensional electron gas, an element isolation region 6 is formed by ion implantation. The region in which the two-dimensional electron gas exists without ion implantation is called an active region 10 shown in FIG. 1B. The boundary between the active region 10 and the element isolation region 6 is an element isolation boundary 6A. In order to reduce the leakage current flowing through the buffer layer 3, the ion implantation for forming the element isolation region 6 is set to reach the buffer layer 3. As the ion implantation species, helium, boron, nitrogen, oxygen, etc., which have a relatively small mass number, are used.

[0028] A first source electrode 11, a first gate electrode 12, a first gate region 13 made of p-GaN, and a first drain electrode 14 constituting a first transistor 111 are formed above the Si substrate 1. A second source electrode 18, a second gate electrode 16, a second gate region 17 made of p-GaN, and a second drain electrode 15 constituting a second transistor 112 are formed above the Si substrate 1. Here, the first gate region 13 made of p-GaN and the second gate region 17 made of p-GaN are both formed to cover the recess region formed in the AlGaN barrier layer 5 so as to fill it. This recess region is not necessarily required in this embodiment, but has the effect of suppressing the amount of two-dimensional electron gas generated and making it easier to obtain the normally-off characteristics required for a power transistor to ensure safety.

[0029] As shown in Fig. 1A, the first drain electrode 14 and the second drain electrode 15 are electrically shorted, and the first source electrode 11, the second source electrode 18 and the second gate electrode 16 are electrically shorted. The shorting method for each electrode can be performed by a general wiring technique for semiconductor devices. A source terminal 121, a gate terminal 122 and a drain terminal 123 are shown in Fig. 1A as external terminals of the semiconductor device, and correspond to the source terminal, the gate terminal and the drain terminal in the equivalent circuit diagram in Fig. 1C.

[0030] The second transistor 112 has the second gate electrode 16 and the second source electrode 18 shorted, and if the device is designed so that the threshold voltage is a positive value (for example, 1.5 V), it becomes a transistor-type diode with a turn-on voltage of 1.5 V. In other words, a transistor-type diode is connected in anti-parallel to the first transistor, and this transistor-type diode acts as an element for passing the return current of the first transistor.

[0031] In addition, in power transistors, in order to prevent false firing and to achieve high-speed switching, gate drive is often performed in which a negative bias is applied to the gate during the off period of the transistor. In conventional GaN transistors, a channel was often used to pass a return current from the source to the drain. In that case, unless a voltage greater than the sum of the absolute value of the threshold voltage of the transistor and the negative bias voltage is applied to the source with respect to the drain, the return current does not flow, resulting in large power loss. However, in the present disclosure, since a transistor-type diode is built in, even if negative bias drive is performed, a return current will flow if a voltage greater than the threshold voltage of the second transistor constituting the transistor-type diode is applied between the source and drain. In other words, the effect of reducing the power loss when passing the return current is obtained.

[0032] As described above, the semiconductor device of embodiment 1 comprises a Si substrate 1 which is a semiconductor substrate, a first transistor 111 having a first source electrode 11, a first gate region 13, and a first drain electrode 14 formed on the Si substrate 1, and a second transistor 112 having a second source electrode 18, a second gate region 17, and a second drain electrode 15 formed on the Si substrate 1, wherein the first source electrode 11, the second gate region 17, and the second source electrode 18 are at substantially the same potential, and the first drain electrode 14 and the second drain electrode 15 are at substantially the same potential.

[0033] According to this, the second transistor 112 constitutes a transistor-type diode with its source and gate shorted, and operates as a free wheel diode connected in anti-parallel to the first transistor 111. Therefore, the second transistor 112 can have a higher withstand voltage than an SBD, and can reduce power loss even when negative bias driving is performed during the off period of the first transistor 111.

[0034] Here, in a particular direction, the first source electrode 11, the first gate region 13, the first drain electrode 14, the second drain electrode 15, the second gate region 17, and the second source electrode 18 may be arranged in this order.

[0035] This allows the first drain electrode 14 and the second drain electrode 15 to be disposed adjacent to each other, making wiring easier and reducing wiring capacitance. The specific direction is a direction parallel to the surface of the semiconductor device 101, and in FIG. 1B, for example, is a direction parallel to line IA-IA among directions parallel to the surface of the semiconductor device 101.

[0036] Here, on a Si substrate 1 which is a semiconductor substrate, there is a channel layer 4 which is a first nitride semiconductor layer in which channels of a first transistor 111 and a second transistor 112 are formed, and a barrier layer 5 which is a second nitride semiconductor layer having a larger band gap than that of the channel layer 4, and the first gate region 13 and the second gate region 17 may be composed of a p-type nitride semiconductor.

[0037] According to this, the semiconductor device is made of a nitride semiconductor, which is a material suitable for a power switching element.

[0038] (Embodiment 2) In the second embodiment, a configuration example of a semiconductor device in which a first drain electrode and a second drain electrode are integrated to form one common drain electrode will be described.

[0039] A cross-sectional view of a semiconductor device 201 according to the second embodiment is shown in FIG. 2A.

[0040] A first source electrode 21, a first gate electrode 22, a first gate region 23 made of p-GaN, and a first drain electrode (common drain electrode 24) constituting a first transistor 211 are formed above the Si substrate 1, and a second source electrode 28, a second gate electrode 26, a second gate region 27 made of p-GaN, and a second drain electrode (common drain electrode 24) constituting a second transistor 212 are formed. Here, the first gate region 23 made of p-GaN and the second gate region 27 made of p-GaN are both formed so as to fill and cover the recess region formed in the AlGaN barrier layer 5. This recess region is not necessarily required in this embodiment, but has the effect of suppressing the generation of two-dimensional electron gas and making it easier to obtain the normally-off characteristics required for a power transistor to ensure safety.

[0041] 2A, the semiconductor device 201 has a common drain electrode 24 instead of the first drain electrode and the second drain electrode. The first source electrode 21, the second source electrode 28, and the second gate electrode 26 are electrically shorted. The shorting method may be a general wiring technique for semiconductor devices.

[0042] In the first embodiment, the first drain electrode 14 and the second drain electrode 15 are formed separately, but in the present embodiment, the first drain electrode and the second drain electrode are formed as a common drain electrode 24.

[0043] This configuration reduces the drain-source capacitance of the semiconductor device 201, and the reason for this will be described below. In GaN transistors, it is common to form an electrode on the back surface of the Si substrate 1 and connect it to the source when used. In that case, the capacitance generated between the drain and the substrate of the second transistor is added to the drain-source capacitance of the first transistor. Therefore, by reducing the area of ​​the drain electrode of the second transistor, the drain-source capacitance is reduced. Therefore, in the second embodiment, the drain electrode of the first transistor 211 and the drain electrode of the second transistor 212 are made into a common drain electrode 24, which makes it possible to reduce the sum of the areas of the drain electrodes, thereby reducing the drain-source capacitance. Furthermore, since the wiring of the first drain electrode and the wiring of the second drain electrode can be made common, the drain-source capacitance and the gate-drain capacitance generated in the wiring are also reduced. When each capacitance is reduced, high-speed switching is possible, and switching loss is reduced.

[0044] Furthermore, by using the common drain electrode 24 as the drain electrode, the transistor can be made smaller, and the chip area can also be reduced.

[0045] (Modification of the second embodiment) A cross-sectional view of a semiconductor device 202 according to a modification of the second embodiment is shown in FIG. 2B.

[0046] A first source electrode 21, a first gate electrode 22, a first gate region 23 made of p-GaN, and a first drain electrode (common drain electrode 24) constituting a first transistor 211 are formed above the Si substrate 1, and a second source electrode 28, a second gate electrode 26, a second gate region 27 made of p-GaN, and a second drain electrode (common drain electrode 24) constituting a second transistor 212 are formed. Here, the first gate region 23 made of p-GaN and the second gate region 27 made of p-GaN are both formed to cover the recess regions formed in the AlGaN barrier layer 5 so as to fill them. Although this recess region is not necessarily required in this modification, it has the effect of suppressing the generation of two-dimensional electron gas and making it easier to obtain normally-off characteristics required for a power transistor to ensure safety.

[0047] 2B, the first drain electrode and the second drain electrode form a common drain electrode 24, and the first source electrode 21, the second source electrode 28, and the second gate electrode 26 are electrically short-circuited. Each of these electrodes can be short-circuited by a common wiring technique for semiconductor devices.

[0048] In this modification, the distance Lgd2 between the gate and drain of the second transistor 212 is longer than the distance Lgd1 between the gate and drain of the first transistor 211. When the thickness of the buffer layer 3 and the channel layer 4 is sufficiently thick, the off-state breakdown voltage of the transistor is almost proportional to the gate-drain distance. Therefore, in this modification, the off-state breakdown voltage of the second transistor 212, i.e., the reverse breakdown voltage of the transistor-type diode connected in anti-parallel to the first transistor 211, is larger than the off-state breakdown voltage of the first transistor 211. Therefore, the number of defects due to insufficient breakdown voltage of the transistor-type diode is reduced, and the yield is improved. As an example, it is sufficient to set Lgd1=15 μm and Lgd2=18 μm.

[0049] Depending on the application in which the transistors are used, it may be better for the distance Lgd2 between the gate and drain of the second transistor 212 to be shorter than the distance Lgd1 between the gate and drain of the first transistor 211. In this case, it is possible to cause the second transistor 212 to break down at a voltage lower than the breakdown voltage of the first transistor 211, thereby allowing the second transistor to function as a clamp diode that prevents the first transistor from breaking down.

[0050] 1A, the distance Lgd1 corresponds to the distance between the first drain electrode 14 and the first gate region 13. The distance Lgd2 corresponds to the distance between the second drain electrode 15 and the second gate region 17.

[0051] As described above, in the semiconductor device according to the second embodiment, the first drain electrode 14 and the second drain electrode 15 form an integrated common drain electrode 24.

[0052] According to this, by integrating the first drain electrode 14 and the second drain electrode 15, the semiconductor device can be miniaturized, and further, the source-drain capacitance can be reduced, and the parasitic capacitance of the wiring connected to the common drain electrode can also be reduced.

[0053] Here, the distance Lgd2 between the second drain electrode 15 (or the common drain electrode 24) and the second gate region 17 (or 27) may be larger than the distance Lgd1 between the first drain electrode 14 (or the common drain electrode 24) and the first gate region 13 (or 23).

[0054] According to this, by designing the withstand voltage of the second transistor to be higher than that of the first transistor, the number of defects in the transistor-type diode formed by the second transistor is reduced, and the yield can be improved.

[0055] Here, the distance Lgd2 between the second drain electrode 15 (or the common drain electrode 24) and the second gate region 17 (or 27) may be smaller than the distance Lgd1 between the first drain electrode 14 (or the common drain electrode 24) and the first gate region 13 (or 23).

[0056] With this, the second transistor also functions as a clamp diode that clamps the drain-source of the first transistor, and can be used as a protection element when a positive excessive voltage is applied between the drain-source of the first transistor.

[0057] (Embodiment 3) In the third embodiment, a configuration example of a semiconductor device having a high resistance region below a common drain electrode 24 will be described.

[0058] A cross-sectional view of a semiconductor device 301 according to the third embodiment is shown in FIG.

[0059] A first source electrode 31, a first gate electrode 32, a first gate region 33 made of p-GaN, and a first drain electrode (common drain electrode 34) constituting a first transistor 311 are formed above the Si substrate 1, and a second source electrode 38, a second gate electrode 36, a second gate region 37 made of p-GaN, and a second drain electrode (common drain electrode 34) constituting a second transistor 312 are formed. Here, the first gate region 33 made of p-GaN and the second gate region 37 made of p-GaN are both formed to cover the recessed region formed in the AlGaN barrier layer 5 so as to fill it. This recessed region is not necessarily required in this embodiment, but has the effect of suppressing the generation of two-dimensional electron gas and making it easier to obtain the normally-off characteristics required for a power transistor to ensure safety.

[0060] 3, the first drain electrode and the second drain electrode form a common drain electrode 34, and the first source electrode 31, the second source electrode 38, and the second gate electrode 36 are electrically short-circuited. Each of these electrodes can be short-circuited by a common wiring technique for semiconductor devices.

[0061] In this embodiment, the high resistance region 7 is formed below the center of the common drain electrode 34. The high resistance region 7 can be formed simultaneously with the element isolation region 6, so the number of steps does not increase. Furthermore, an insulating film 35 is formed between the common drain electrode 34 and the high resistance region 7. With this configuration, the capacitance generated between the common drain electrode 34 and the Si substrate 1 is reduced, and the drain-source capacitance of the semiconductor device 301 is reduced.

[0062] As described above, in the semiconductor device according to the third embodiment, the high-resistance region 7 is formed below the common drain electrode .

[0063] This makes it possible to reduce the parasitic capacitance between the common drain electrode 34 and the Si substrate 1, and therefore the parasitic capacitance between the source and drain.

[0064] (Embodiment 4) In the fourth embodiment, a configuration example of a semiconductor device in which the second gate region and the second source electrode are in contact with each other will be described.

[0065] A cross-sectional view of a semiconductor device 401 according to the fourth embodiment is shown in FIG.

[0066] A first source electrode 41, a first gate electrode 42, a first gate region 43 made of p-GaN, and a first drain electrode (common drain electrode 44) constituting a first transistor 411 are formed above the Si substrate 1, and a second source electrode 48, a second gate region 47 made of p-GaN, and a second drain electrode (common drain electrode 44) constituting a second transistor 412 are formed. Here, the first gate region 43 made of p-GaN and the second gate region 47 made of p-GaN are both formed to cover the recess regions formed in the AlGaN barrier layer 5 so as to fill them. This recess region is not necessarily required in this embodiment, but has the effect of suppressing the amount of two-dimensional electron gas generated and making it easier to obtain normally-off characteristics required for a power transistor to ensure safety.

[0067] 4, the first drain electrode and the second drain electrode form a common drain electrode 44, and the first source electrode 41 and the second source electrode 48 are electrically short-circuited. The first source electrode 41 and the second source electrode 48 can be short-circuited by connecting them using a general wiring technique for semiconductor devices.

[0068] In this embodiment, the second source electrode 48 is formed so as to cover the second gate region 47 made of p-GaN, and therefore also serves as the gate electrode of the second transistor 412. This configuration allows the second gate region 47 to be thinned, which in turn allows the device area to be reduced. In addition, the area electrically shorted with the source electrode in the semiconductor device 401 is reduced, thereby reducing the gate-source capacitance.

[0069] As described above, in the semiconductor device according to the fourth embodiment, the second gate region 47 and the second source electrode 48 are in contact with each other.

[0070] This allows the semiconductor device to be miniaturized.

[0071] (Embodiment 5) In the fifth embodiment, an example configuration of a semiconductor device is described in which the threshold voltage of the second transistor can be set to a positive value lower than the threshold voltage of the first transistor by adjusting the depth of the recess regions of the barrier layers formed in the first gate region and the second gate region, respectively.

[0072] A cross-sectional view of a semiconductor device 501 according to the fifth embodiment is shown in FIG.

[0073] A first source electrode 51, a first gate electrode 52, a first gate region 53 made of p-GaN, and a first drain electrode (common drain electrode 54) constituting a first transistor 511 are formed above the Si substrate 1, and a second source electrode 58, a second gate electrode 56, a second gate region 57 made of p-GaN, and a second drain electrode (common drain electrode 54) constituting a second transistor 512 are formed. Here, the first gate region 53 made of p-GaN and the second gate region 57 made of p-GaN are both formed to cover and fill recess regions formed in the AlGaN barrier layer 5.

[0074] 5, the first drain electrode and the second drain electrode form a common drain electrode 54, and the first source electrode 51, the second source electrode 58, and the second gate electrode 56 are electrically short-circuited. Each of these electrodes can be short-circuited by a common wiring technique for semiconductor devices.

[0075] In this embodiment, the first gate region 53 has a first recess portion 53r and a first cover portion 53c. The first recess portion 53r is a portion of the first gate region 53 that is embedded in the recess region of the barrier layer 5. The first cover portion 53c is a portion of the first gate region 53 that covers the first recess portion 53r.

[0076] Similarly, the second gate region 57 has a second recess portion 57r and a second cover portion 57c. The second recess portion 57r is a portion of the second gate region 57 that is embedded in the recess region of the barrier layer 5. The second cover portion 57c is a portion of the second gate region 57 that covers the second recess portion 57r.

[0077] As shown in FIG. 5, the depth D2 of the second recessed portion 57r is shallower than the depth D1 of the first recessed portion 53r. In other words, the depth D2 of the recessed region of the second transistor 512 is shallower than the depth D1 of the recessed region of the first transistor 511. Furthermore, the values ​​of the depths D1 and D2 are set so that the threshold voltage Vth2 of the second transistor is a positive value. With this configuration, the threshold voltage Vth2 of the second transistor 512 is a positive value and is lower than the threshold voltage Vth1 of the first transistor 511. As a result, the turn-on voltage of the transistor-type diode formed of the second transistor 512 is lowered, and the power loss when the return current flows is reduced. For example, the value of D1 may be set so that the threshold voltage Vth1 of the first transistor 511 is 1.5V, and the value of D2 may be set so that the threshold voltage Vth2 of the second transistor 512 is 0.7V.

[0078] In order to realize this embodiment, the recess etching process of the first gate region 53 and the recess etching process of the second gate region 57 may be performed separately. However, if the recess length of the second gate region 57 is designed to have a dimension that slows down the dry etching rate, it is possible to perform the recess etching process once. For example, the recess length of the first gate region 53 may be set to about 0.6 μm, and the recess length of the second gate region 57 may be set to about 0.2 μm.

[0079] As described above, in the semiconductor device according to the fifth embodiment, the threshold voltage Vth2 of the second transistor 512 is lower than the threshold voltage Vth1 of the first transistor 511 and has a positive value.

[0080] This makes it possible to further reduce the power loss during the off period of the first transistor.

[0081] Here, the first gate region 53 has a first recess portion 53r embedded in a recess region of the barrier layer 5, which is the second nitride semiconductor layer, and a first cover portion 53c covering the first recess portion 53r, and the second gate region 57 has a second recess portion 57r embedded in another recess region of the barrier layer 5 and a second cover portion 57c covering the second recess portion 57r, and a depth D2 of the second recess portion 57r is shallower than a depth D1 of the first recess portion.

[0082] According to this, the threshold voltage Vth2 of the second transistor 512 can be made lower than the threshold voltage Vth1 of the first transistor 511 according to the design values ​​of the depth D1 and the depth D2.

[0083] (Embodiment 6) In the sixth embodiment, an example configuration of a semiconductor device is described in which the threshold voltage Vth2 of the second transistor can be set to a positive value lower than the threshold voltage Vth1 of the first transistor by adjusting the width of each of the first gate region and the second gate region.

[0084] A cross-sectional view of a semiconductor device 601 according to the sixth embodiment is shown in FIG.

[0085] A first source electrode 61, a first gate electrode 62, a first gate region 63 made of p-GaN, and a first drain electrode (common drain electrode 64) constituting a first transistor 611 are formed above the Si substrate 1, and a second source electrode 68, a second gate electrode 66, a second gate region 67 made of p-GaN, and a second drain electrode (common drain electrode 64) constituting a second transistor 612 are formed. Here, the first gate region 63 made of p-GaN and the second gate region 67 made of p-GaN are both formed to cover and fill recess regions formed in the AlGaN barrier layer 5.

[0086] 6, the first drain electrode and the second drain electrode form a common drain electrode 64, and the first source electrode 61, the second source electrode 68, and the second gate electrode 66 are electrically short-circuited. Each of these electrodes can be short-circuited by a common wiring technique for semiconductor devices.

[0087] In this embodiment, the first gate region 63 has a first recess portion 63r and a first cover portion 63c. The first recess portion 63r is a portion of the first gate region 63 that is embedded in a recess region of the barrier layer 5, which is the second nitride semiconductor layer. The first cover portion 63c is a portion of the first gate region 63 that covers the first recess portion 63r.

[0088] Similarly, the second gate region 67 has a second recess portion 67r and a second cover portion 67c. The second recess portion 67r is a portion of the second gate region 67 that is embedded in the recess region of the barrier layer 5. The second cover portion 67c is a portion of the second gate region 67 that covers the second recess portion 67r.

[0089] As shown in FIG. 6, the width W2 of the second recessed portion 67r is narrower than the width W1 of the first recessed portion 63r. In other words, the width W2 of the recessed region of the second transistor 612 is smaller than the width W1 of the recessed region of the first transistor 611 to such an extent that a short channel effect occurs. With this configuration, the threshold voltage Vth2 of the second transistor 612 can be made positive and lower than the threshold voltage Vth1 of the first transistor 611. As a result, the turn-on voltage of the transistor-type diode formed by the second transistor 612 is lowered, and the power loss when the return current flows is reduced. For example, the value of the width W1 may be set so that the threshold voltage Vth1 of the first transistor 611 is 1.5V, and the value of the width W2 may be set so that the threshold voltage Vth2 of the second transistor 612 is 0.7V. In this case, the specific widths of the recessed regions may be W1 of 0.5 μm and W2 of 0.1 μm.

[0090] In this embodiment, the two recess regions can be formed simultaneously by etching, which has the effect of preventing an increase in the number of steps.

[0091] As described above, in the semiconductor device of embodiment 6, the first gate region 63 has a first recess portion 63r embedded in a recess region of the barrier layer 5, which is the second nitride semiconductor layer, and a first cover portion 63c covering the first recess portion 63r, and the second gate region 67 has a second recess portion 67r embedded in another recess region of the second nitride semiconductor layer and a second cover portion 57c covering the second recess portion 67r, and the width W2 of the second recess portion 67r is narrower than the width W1 of the first recess portion 63r.

[0092] This allows the threshold voltage Vth2 of the second transistor 612 to be lower than the threshold voltage Vth1 of the first transistor 611 according to the design values ​​of the widths W1 and W2.

[0093] (Embodiment 7) In the seventh embodiment, a configuration example of a semiconductor device in which a plurality of unit transistors, each of which is made up of a first transistor and a second transistor, are efficiently arranged will be described.

[0094] Figures 7A and 7B respectively show a cross-sectional view and a plan view of a semiconductor device 701 of embodiment 7. Note that Figure 7A shows a cross-sectional view taken along line VIIA-VIIA in Figure 7B.

[0095] A first source electrode 71, a first gate electrode 72, a first gate region 73 made of p-GaN, and a first drain electrode (common drain electrode 74) constituting a first transistor 711 are formed above the Si substrate 1, and a second source electrode 78, a second gate electrode 76, a second gate region 77 made of p-GaN, and a second drain electrode (common drain electrode 74) constituting a second transistor 712 are formed. Here, the first gate region 73 made of p-GaN and the second gate region 77 made of p-GaN are both formed to cover the recess regions formed in the AlGaN barrier layer 5 so as to fill them. This recess region is not necessarily required in this embodiment 7, but has the effect of suppressing the amount of two-dimensional electron gas generated and making it easier to obtain normally-off characteristics required for a power transistor to ensure safety.

[0096] 7A and 7B, the first drain electrode and the second drain electrode form a common drain electrode 74, and the first source electrode 71, the second source electrode 78, and the second gate electrode 76 are electrically short-circuited. Each of these electrodes can be short-circuited by connecting them using a general wiring technique for semiconductor devices.

[0097] Here, the area sandwiched between the center line of first source electrode 71 on the left side of the figure and the center line of second source electrode 78 is defined as unit transistor 721A. The layout of unit transistor 721A mirror-inverted with respect to the center line of the second source electrode is unit transistor 722A. Similarly, unit transistor 722A is mirror-inverted with respect to the center line of the first source electrode to obtain unit transistor 721B. By repeating this process until the desired gate width for the power transistor is obtained, the required power transistor layout can be obtained. In Figures 7A and 7B, mirror inversion here refers to mirror inversion with line VIIA-VIIA as the normal line.

[0098] Although this embodiment has been described using embodiment 2, other embodiments may be used. For example, if it is desired to widen the interval between unit transistors in order to improve heat dissipation, the element isolation region 6 between the first transistor 111 and the second transistor 112 in embodiment 1 of FIG. 1A may be widened. Also, embodiment 3 may be used to widen the high resistance region 7.

[0099] As described above, the semiconductor device of embodiment 7 comprises a plurality of unit transistors, each of which is composed of a first transistor 711 and a second transistor 712. The plurality of unit transistors are arranged side by side in a particular direction, and the internal arrangement of each of the plurality of unit transistors is a mirror image of the other adjacent unit transistors when viewed in a plan view of the semiconductor substrate.

[0100] This allows a plurality of unit transistors to be arranged efficiently.

[0101] (Embodiment 8) In the eighth embodiment, a configuration example of a semiconductor device in which a first source electrode and a second source electrode are integrated to form one common source electrode will be described.

[0102] A cross-sectional view of a semiconductor device 801 according to the eighth embodiment is shown in FIG. 8A.

[0103] A first drain electrode 84, a first gate electrode 82, a first gate region 83 made of p-GaN, and a first source electrode (common source electrode 81) constituting a first transistor 811 are formed above the Si substrate 1, and a second drain electrode 85, a second gate electrode 86, a second gate region 87 made of p-GaN, and a second source electrode (common source electrode 81) constituting a second transistor 812 are formed. Here, the first gate region 83 made of p-GaN and the second gate region 87 made of p-GaN are both formed to cover the recess regions formed in the AlGaN barrier layer 5 so as to fill them. This recess region is not necessarily required in this embodiment 8, but has the effect of suppressing the amount of two-dimensional electron gas generated and making it easier to obtain normally-off characteristics required for a power transistor to ensure safety.

[0104] 8A, the first source electrode and the second source electrode form a common source electrode 81, the common source electrode 81 and the second gate electrode 86 are electrically shorted, and the first drain electrode 84 and the second drain electrode 85 are electrically shorted. Each of these electrodes can be shorted by connecting them using a general wiring technique for semiconductor devices.

[0105] In the second embodiment, the first drain electrode and the second drain electrode in FIG. 2A are formed as a common drain electrode 24, but in this embodiment, the first source electrode and the second source electrode are formed as a common source electrode 81.

[0106] With this configuration, the source electrode of the semiconductor device 801 becomes the common source electrode 81, thereby reducing the source electrode area. As a result, the gate-source capacitance becomes small, enabling high-speed switching. Furthermore, by using the common source electrode 81 as the source electrode, the transistor can be made smaller, and the chip area can be reduced.

[0107] Although a common source electrode 81 is used in this embodiment, it is also possible to provide the first transistor 811 and the second transistor 812 with separate first source electrodes 8a and second source electrodes 8b as shown in the semiconductor device 802 of FIG. 8B.

[0108] 8C, a layout may be used in which the unit transistor shown in FIG. 8A is used as a unit transistor and mirror inversion of a plurality of unit transistors is repeated, as in embodiment 7. This makes it possible to obtain a layout for a power transistor having a desired gate width.

[0109] As described above, in the semiconductor device of embodiment 8, the first drain electrode 84, the first gate region 83, the first source electrode 8a, the second source electrode 8b, the second gate region 87, and the second drain electrode 85 are arranged in this order in a specific direction.

[0110] According to this, the first source electrode 8a and the second source electrode 8b can be disposed adjacent to each other, which facilitates wiring and reduces wiring capacitance.

[0111] Here, the first source electrode 8a and the second source electrode 8b may be integrated to form a common source electrode 81.

[0112] According to this, by integrating the first source electrode 8a and the second source electrode 8b, the semiconductor device can be miniaturized, and further, the gate-source capacitance can be reduced, and the parasitic capacitance of the wiring connected to the common source electrode 81 can also be reduced.

[0113] Here, the device comprises a plurality of unit transistors, each of which is composed of a first transistor 811 and a second transistor 812, the plurality of unit transistors are arranged side by side in a particular direction, and the internal arrangement of each of the plurality of unit transistors may be a mirror image of the other adjacent unit transistors when viewed in a plan view of the semiconductor substrate.

[0114] This allows a plurality of unit transistors to be arranged efficiently.

[0115] In all the configurations of the first to eighth embodiments, the value of Ron·A (on-resistance × chip area), which is one of the indices of power transistor performance, generally deteriorates (becomes larger) as the chip area becomes larger compared to when the transistor-type diode is not built in. However, when a GaN power transistor is operated at a high frequency of 1 MHz or more, the interval between the unit transistors constituting the power transistor is often intentionally widened to improve heat dissipation. If a transistor-type diode is placed between the widened unit transistors, the Ron·A does not deteriorate, and a high-frequency power transistor with excellent heat dissipation can be realized. Furthermore, the area in the chip where the current flows when the transistor is on and the area in the chip where the return current flows when the transistor is off are separated. As a result, compared to the conventional technology in which the return current flows using the transistor channel, the heat generating parts are dispersed, so the temperature in the chip is uniformed and the maximum temperature in the chip is lower. In other words, compared to the conventional technology, higher current and higher voltage operation is possible, and the reliability of the power transistor is improved.

[0116] In addition, the semiconductor device according to one or more aspects has been described based on the embodiments, but the present disclosure is not limited to these embodiments. As long as it does not deviate from the spirit of the present disclosure, various modifications conceived by a person skilled in the art to the present embodiment and forms constructed by combining components in different embodiments may also be included within the scope of one or more aspects. [Industrial Applicability]

[0117] The semiconductor device according to the present disclosure can be used as a switching transistor that operates at a high frequency of 1 MHz or more, and is particularly applicable to a GaN power transistor. [Explanation of symbols]

[0118] 1. Si substrate 2 AlN layer 3. Buffer layer 4. Channel Layer 5. Barrier Layer 6. Isolation region 6A Isolation boundary 7 High resistance region 10 Active area 11, 21, 31, 41, 51, 61, 71, 8a First source electrode 12, 22, 32, 42, 52, 62, 72, 82 First gate electrode 13, 23, 33, 43, 53, 63, 73, 83 First gate region 14, 84 First drain electrode 15, 85 Second drain electrode 16, 26, 36, 56, 66, 76, 86 Second gate electrode 17, 27, 37, 47, 57, 67, 77, 87, 8b Second gate region 18, 28, 38, 48, 58, 68, 78 Second source electrode 24, 34, 44, 54, 64, 74 Common drain electrode 35 Insulating film 53c, 63c First cover part 53r, 63r First recess 57c, 67c Second cover part 57r, 67r Second recess 81 Common source electrode 101, 201, 301, 401, 501, 601, 701, 801 Semiconductor device 111, 211, 311, 411, 511, 611, 711, 811 First transistor 112, 212, 312, 412, 512, 612, 712, 812 Second transistor 121 Source terminal 122 Gate terminal 123 Drain terminal 202, 802, 803 Semiconductor device 721A, 721B, 722A, 722B Unit Transistor 821A, 821B, 822A, 822B Unit transistors

Claims

1. A semiconductor substrate; a first transistor formed on the semiconductor substrate, the first transistor having a first source electrode, a first gate region, and a first drain electrode; a second transistor formed on the semiconductor substrate, the second transistor having a second source electrode, a second gate region, and a second drain electrode; the first source electrode, the second gate region and the second source electrode are at substantially the same potential; the first drain electrode and the second drain electrode are at substantially the same potential; In a specific direction, the first source electrode, the first gate region, the first drain electrode, the second drain electrode, the second gate region, and the second source electrode are arranged in this order; the first drain electrode and the second drain electrode constitute an integrated common drain electrode; A high resistance region is formed under the common drain electrode. Semiconductor device.

2. The second gate region and the second source electrode are in contact with each other. The semiconductor device according to claim 1 .

3. The threshold voltage of the second transistor is lower than the threshold voltage of the first transistor and has a positive value. The semiconductor device according to claim 1 .

4. a first nitride semiconductor layer on the semiconductor substrate, in which channels of the first transistor and the second transistor are formed, and a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer; The first gate region and the second gate region are made of a p-type nitride semiconductor. The semiconductor device according to claim 1 .

5. The first gate region is a first recess portion embedded in a recess region of the second nitride semiconductor layer; a first cover portion covering the first recess portion, The second gate region is a second recess portion embedded in another recess region of the second nitride semiconductor layer; a second cover portion covering the second recess portion, The depth of the second recessed portion is shallower than the depth of the first recessed portion. The semiconductor device according to claim 4.

6. The first gate region is a first recess portion embedded in a recess region of the second nitride semiconductor layer; a first cover portion covering the first recess portion, The second gate region is a second recess portion embedded in another recess region of the second nitride semiconductor layer; a second cover portion covering the second recess portion, The width of the second recessed portion is narrower than the width of the first recessed portion. The semiconductor device according to claim 4.

7. The distance between the second drain electrode and the second gate region is greater than the distance between the first drain electrode and the first gate region. The semiconductor device according to claim 1 .

8. The distance between the second drain electrode and the second gate region is smaller than the distance between the first drain electrode and the first gate region. The semiconductor device according to claim 1 .

9. A plurality of unit transistors are provided, each of the plurality of unit transistors is composed of the first transistor and the second transistor; the plurality of unit transistors are arranged side by side in the specific direction, The internal arrangement of each of the plurality of unit transistors is a mirror image of the adjacent unit transistors when viewed from above the semiconductor substrate. The semiconductor device according to claim 1 .

10. A plurality of unit transistors are provided, each of the plurality of unit transistors is composed of the first transistor and the second transistor; The internal arrangement of each of the plurality of unit transistors is a mirror image of the adjacent unit transistors when viewed from above the semiconductor substrate. The semiconductor device according to claim 1 .

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