Semiconductor device manufacturing method and laser annealing device

Abstract

This semiconductor device manufacturing method comprises: a step for preparing a semiconductor substrate (1) which has a first surface extending in a first direction (X) and in a second direction (Y) perpendicular to the first direction (X), and in which a first impurity region is formed; and a first annealing step for annealing the first impurity region by irradiating the first surface with a laser beam emitted from an optical system. A first width in the first direction (X) of a beam spot formed on the first surface by the laser beam is smaller than a second width of the beam spot in the second direction (Y). The first surface has a plurality of regions that are arranged in at least one among the first direction (X) and the second direction (Y) and that each have a first width in the first direction (X) and a second width in the second direction. In the first annealing step, an irradiation step for forming a beam spot in one region among the plurality of regions is performed multiple times. A first step for scanning the first surface only the first width in the first direction (X) with respect to the optical system, and a second step for, after completing the first step, scanning the first surface only the second width in the second direction (Y) with respect to the optical system are performed between the irradiation steps performed multiple times.

Description

[Technical field]

[0001] The present disclosure relates to a manufacturing method of a semiconductor device and a laser annealing apparatus. [Background technology]

[0002] 2. Description of the Related Art In a conventional method for manufacturing a semiconductor device, a laser annealing process is performed in which a semiconductor substrate is irradiated with laser light to anneal an impurity region formed therein, in order to activate the impurity region.

[0003] In the laser annealing process, the semiconductor substrate is divided into a plurality of irradiation areas, and the beam spot of the laser light is formed on each irradiation area in sequence. In this case, in order to prevent the formation of impurity areas that are not sufficiently annealed, an overlap ratio is generally set between adjacent irradiation areas, and the laser light is continuously irradiated to two adjacent irradiation areas with the overlap ratio.

[0004] International Publication No. 2019 / 244665 (Patent Document 1) discloses a technique for setting the irradiation order and arrangement of a plurality of irradiation regions so that two irradiation regions with consecutive incidence orders do not have overlapping parts, but two irradiation regions with non-consecutive incidence orders have overlapping parts. If a process of sequentially irradiating each of a plurality of irradiation regions with laser light is considered as one laser annealing process, each overlapping part is formed within the one laser annealing process. In other words, in Patent Document 1, the time difference between the first irradiation of the laser light and the second irradiation of the laser light for forming each overlapping part is longer than that in the case where the laser light is continuously irradiated to two adjacent irradiation regions with a set overlap rate, but is set to be shorter than the time required to sequentially irradiate each of the plurality of irradiation regions with the laser light once. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 244665 Summary of the Invention [Problem to be solved by the invention]

[0006] In the conventional technology, each of the multiple irradiation regions has an overlapping portion, and the time difference between the two irradiations for forming each overlapping portion is relatively short, so that the temperature of the semiconductor substrate tends to become relatively high because the semiconductor substrate, which is in a heated state due to the first laser light irradiation, is reheated by the second laser light irradiation.

[0007] If the semiconductor substrate becomes hot, it may deteriorate structures formed on the semiconductor substrate before the laser annealing process. One example of such structures is a protective film that is formed on the surface of the semiconductor substrate opposite to the surface irradiated with the laser light before the laser annealing process and is removed after the laser annealing process.

[0008] The main object of the present disclosure is to provide a method for manufacturing a semiconductor device, which can suppress a temperature rise in a semiconductor substrate compared to conventional techniques while preventing the formation of impurity regions that are not sufficiently annealed, and a laser annealing apparatus for realizing the manufacturing method. [Means for solving the problem]

[0009] The method for manufacturing a semiconductor device according to the present disclosure includes the steps of: preparing a semiconductor substrate having a first surface extending along a first direction and a second direction perpendicular to the first direction, a plurality of element formation regions arranged on the first surface, and a first impurity region formed in each of the plurality of element formation regions; and a first annealing step of sequentially irradiating each of the plurality of element formation regions with a laser beam to anneal the first impurity region. A first width in the first direction of a beam spot formed by the laser beam on the first surface is narrower than a second width in the second direction of the beam spot. In the first annealing step, irradiation is performed while the beam spot is scanned relative to the first surface, and a relative movement distance of the beam spot in the first direction is set to a first width, and a relative movement distance of the beam spot in the second direction is set to a second width.

[0010] The laser annealing apparatus according to the present disclosure includes a holding unit that holds a semiconductor substrate having a first surface extending along a first direction and a second direction perpendicular to the first direction and in which a first impurity region is formed, an optical system that irradiates a laser beam onto the first surface of the semiconductor substrate held by the holding unit and forms a beam spot in one of a plurality of regions on the first surface arranged in at least one of the first direction and the second direction, and a scanning unit that scans one of the semiconductor substrate and the optical system relative to the other. The optical system is provided to form a beam spot on the first surface, the first width of which in the first direction is narrower than a second width in the second direction. After the optical system forms one beam spot, the scanning unit scans the first surface in the first direction by the first width relative to the optical system, scans the first surface in the first direction by the first width relative to the optical system, and then scans the first surface in the second direction by the second width relative to the optical system. Effect of the Invention

[0011] According to the present disclosure, it is possible to provide a manufacturing method for a semiconductor device, which can prevent the formation of impurity regions that are not sufficiently annealed while suppressing a temperature rise in the semiconductor substrate compared to conventional techniques, and a laser annealing apparatus for realizing the manufacturing method. [Brief description of the drawings]

[0012] [Figure 1] 1 is a partial cross-sectional view showing an example of a semiconductor device according to a first embodiment. [Diagram 2] 4 is a flowchart showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3] 3A to 3C are diagrams showing examples of the shape of a beam spot of laser light and examples of intensity distribution of the laser light along each of a first direction and a second direction in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 4] 3 is a diagram for explaining a scanning path of a beam spot in the first laser annealing step shown in FIG. 2. FIG. [Diagram 5] 7 is a diagram for more specifically explaining the scanning path of the beam spot shown in FIG. 6. FIG. [Figure 6] 1 is a block diagram showing an example of a laser annealing apparatus according to a first embodiment. [Figure 7] FIG. 7 is a diagram for explaining an example of the intensity waveforms of the pulsed laser beams output from the first laser oscillator and the second laser oscillator of the laser annealing apparatus shown in FIG. 6, and the laser beam obtained by combining the two in a combining optical system. [Figure 8] 10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 9] 13 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a third embodiment. [Figure 10] 13 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 11] 13 is a flowchart showing an example of a method for manufacturing a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0014] Embodiment 1 The semiconductor device 101 according to the first embodiment is formed by dicing a plurality of chips formed on a semiconductor substrate 1 by a manufacturing method of the semiconductor device 101 described later. As shown in Fig. 1, the semiconductor device 101 is, as an example, a reverse conducting insulated gate bipolar transistor (RC-IGBT), in which a trench gate IGBT and a free wheeling diode (FWD) connected in anti-parallel to the IGBT are built into and integrated into one semiconductor substrate 1.

[0015] The semiconductor substrate 1 has a first surface 1A and a second surface 1B located on the opposite side to the first surface 1A. In the following, in the thickness direction of the semiconductor substrate 1 perpendicular to each of the first direction X and the second direction Y, the direction in which the first surface 1A faces is referred to as downward, and the direction in which the second surface 1B faces is referred to as upward. The first surface 1A is the lower surface of the semiconductor substrate 1. The second surface 1B is the upper surface of the semiconductor substrate 1.

[0016] 1 includes an IGBT region 101A which is an operating region for an IGBT, and an FWD region 101B which is an operating region for an FWD. The IGBT region 101A and the FWD region 101B are arranged in parallel to each other in an active region on the same semiconductor substrate 1. The active region is a region through which current flows in an on-state.

[0017] IGBT 101A includes an n-type drift layer 2, a p-type base layer 3, a p+-type contact layer 4, an n+-type emitter layer 5, a gate insulating film 6, a gate electrode 7, an n-type buffer layer 8, a p-type collector layer 9, an interlayer insulating film 10, a barrier metal 11, a plug 12, an emitter electrode 13A, and a collector electrode 14A.

[0018] The p-type base layer 3 is disposed on the upper surface of the n-type drift layer 2. The p+ type contact layer 4 and the n+ type emitter layer 5 are each disposed on the upper surface of the p-type base layer 3. The n+ type emitter layer 5 is disposed so as to surround the p+ type contact layer 4. The n-type buffer layer 8 is disposed on the lower surface of the n- type drift layer 2. The p-type collector layer 9 is disposed on the lower surface of the n- type drift layer 2.

[0019] A plurality of trenches T are formed in the IGBT region 101A. In the IGBT region 101A, each of the plurality of trenches T penetrates from the upper surface of the n+ type emitter layer 5 through the n+ type emitter layer 5 and the p type base layer 3 to reach the n- type drift layer 2. A gate insulating film 6 and a gate electrode 7 are embedded inside the trench T. The gate insulating film 6 is disposed along the inner wall surface of the trench T. The gate electrode 7 faces the p type base layer 3 via the gate insulating film 6. Each of the plurality of trenches T is disposed at intervals in a plan view, for example, in a direction in which the IGBT region 101A and the FWD region 101B are arranged side by side (the horizontal direction in FIG. 1). Each of the plurality of trenches T extends, for example, in a direction perpendicular to the direction in which the IGBT region 101A and the FWD region 101B are arranged side by side (the depth direction in FIG. 1). The plurality of trenches T are disposed, for example, in a stripe shape in a plan view.

[0020] Note that the n+ type emitter layer 5 is disposed in each of the spaces (mesa regions) between adjacent trenches T, but is not limited thereto. It is sufficient that the n+ type emitter layer 5 is disposed in at least one mesa region between adjacent trenches T (mesa regions). There may be a mesa region in which no n+ type emitter layer 5 is disposed. Furthermore, a plurality of n+ type emitter layers 5 may be disposed at predetermined intervals in the direction in which the trenches T extend in a striped shape (depth direction in FIG. 1).

[0021] The interlayer insulating film 10 covers the upper surface of the gate electrode 7. The interlayer insulating film 10 is provided so as to electrically insulate the gate electrode 7 disposed under the interlayer insulating film 10 from the emitter electrode 13A disposed on the interlayer insulating film 10. Contact holes are formed in the interlayer insulating film 10, and the p+ type contact layer 4 and the n+ type emitter layer 5 are exposed in the contact holes.

[0022] The barrier metal 11 is disposed so as to cover the surfaces of the interlayer insulating film 10 and the contact hole. The barrier metal 11 is in contact with the upper surfaces of the p+ type contact layer 4 and the n+ type emitter layer 5 exposed in the contact hole. The plug 12 is buried on the barrier metal 11 in the contact hole.

[0023] Emitter electrode 13A is disposed on barrier metal 11 and plug 12. An aluminum alloy is generally used for emitter electrode 13A. Emitter electrode 13A is in contact with n+ type emitter layer 5 and p+ type contact layer 4 via barrier metal 11 and plug 12. Collector electrode 14A is in contact with p-type collector layer 9.

[0024] The FWD region 101B of the semiconductor device 101 includes an n- type drift layer 2, a p-type anode layer 15, a p+-type anode layer 16, a gate insulating film 6, a dummy gate electrode 17, an n-type buffer layer 8, an n+-type cathode layer 18, an electrode 13B, and a cathode electrode 14B.

[0025] The p-type anode layer 15 is disposed on the upper surface of the n- type drift layer 2. The p+ type anode layer 16 is disposed on the upper surface of the p-type anode layer 15. The n- type buffer layer 8 is disposed on the lower surface of the n- type drift layer 2. The n+ type cathode layer 18 is disposed on the lower surface of the n- type buffer layer 8.

[0026] A plurality of trenches T are formed in each of the FWD regions 101B. In the FWD regions 101B, each of the plurality of trenches T penetrates from the upper surface of the p+ type anode layer 16 through the p+ type anode layer 16 and the p-type anode layer 15 to reach the n- type drift layer 2. The gate insulating film 6 and the dummy gate electrode 17 are embedded inside the trenches T.

[0027] The FWD region 101B includes an n-type drift layer 2, a gate insulating film 6, and an n-type buffer layer 8 in common with the IGBT region 101A.

[0028] The upper surface of the dummy gate electrode 17 is covered with the interlayer insulating film 10. The dummy gate electrode 17 is electrically insulated from the electrode 13B arranged on the interlayer insulating film 10 by the interlayer insulating film 10. The electrode 13B is provided integrally with the emitter electrode 13A. In other words, the second electrode 13 as a single member is formed across both the IGBT region 101A and the FWD region 101B, and a part of the second electrode 13 constitutes the emitter electrode 13A, and the remaining part of the second electrode 13 constitutes the electrode 13B. The dummy gate electrode 17 may be electrically connected to the electrode 13B. The cathode electrode 14B is joined to the n+ type cathode layer 18. The cathode electrode 14B is provided integrally with the collector electrode 14A. In other words, the first electrode 14 as a single member is formed across both the IGBT region 101A and the FWD region 101B, with a part of the first electrode 14 constituting the collector electrode 14A and the remaining part of the first electrode 14 constituting the cathode electrode 14B.

[0029] The n- type drift layer 2, the p-type base layer 3, the p+ type contact layer 4, the n+ type emitter layer 5, the gate insulating film 6, the gate electrode 7, the n- type buffer layer 8, and the p-type collector layer 9 are disposed between the first surface 1A and the second surface 1B of the semiconductor substrate 1. The collector electrode 14A is disposed on the first surface 1A. The interlayer insulating film 10, the barrier metal 11, the plug 12, and the emitter electrode 13A are disposed on the second surface 1B.

[0030] The semiconductor device 101 may include a breakdown voltage structure such as a guard ring provided in an edge termination region that is arranged to surround the active region.

[0031] <Method of Manufacturing Semiconductor Device> 2, the method for manufacturing semiconductor device 101 includes a step (S10) of preparing semiconductor substrate 1 having a first impurity region formed therein, and a first annealing step (S20) of irradiating the first surface with laser light to anneal the first impurity region. In the first embodiment, the first impurity region includes an impurity region to become n-type buffer layer 8, an impurity region to become p-type collector layer 9, and an impurity region to become n+-type cathode layer 18.

[0032] In step (S10), semiconductor substrate 1 having p-type collector layer 9 and n+-type cathode layer 18 formed thereon is prepared as an object to be subjected to laser annealing in a first annealing step (S20). This semiconductor substrate 1 is manufactured, for example, by carrying out the following steps (S1) to (S4) in order.

[0033] In the step (S1), an element structure is formed on the second surface 1B side of the semiconductor substrate 1 in each of the IGBT region 101A and the FWD region 101B.

[0034] In step (S1), first, a semiconductor substrate 1 is prepared. The semiconductor substrate 1 has a third surface and a second surface 1B located on the opposite side to the third surface. The third surface and the second surface 1B each extend along a first direction X and a second direction Y perpendicular to the first direction X. The material constituting the semiconductor substrate 1 may be any semiconductor material, such as silicon (Si) or silicon carbide (SiC). The conductivity type of the semiconductor substrate 1 is n-type.

[0035] In step (S1), next, a p-type base layer 3, a p-type anode layer 15, a p+-type contact layer 4, and an n+-type emitter layer 5 are formed on the upper surface (second surface 1B) of the semiconductor substrate 1. Each of the p-type base layer 3, the p+-type contact layer 4, and the n+-type emitter layer 5 is formed by an ion implantation method using a mask pattern formed by a photolithography method. For example, a set of a step of forming a mask pattern using a photolithography method, an ion implantation step using the mask pattern, and a step of removing the mask pattern are repeatedly performed under different conditions. The p-type base layer 3 and the p-type anode layer 15 are formed, for example, by one ion implantation step. In other words, the p-type base layer 3 and the p-type anode layer 15 are formed so that one of the p-type base layer 3 and the p-type anode layer 15 serves as the other. The p+-type contact layer 4 and the n+-type emitter layer 5 are selectively formed inside the p-type base layer 3 in the IGBT region 101A.

[0036] In step (S1), a field oxide film is then formed in the edge termination region to cover second surface 1B. The field oxide film is formed, for example, by thermally oxidizing second surface 1B of semiconductor substrate 1. Next, a plurality of trenches T are formed in each of IGBT region 101A and FWD region 101B. As described above, the plurality of trenches T are formed, for example, in a striped pattern in a plan view.

[0037] In step (S1), next, in each of the IGBT region 101A and the FWD region 101B, a gate insulating film 6 is formed inside the multiple trenches T. The gate insulating film 6 is formed along the inner wall surface of each trench T. The gate insulating film 6 is formed, for example, by thermally oxidizing the inner wall surface of each trench T.

[0038] In step (S1), next, in each of the IGBT region 101A and the FWD region 101B, the gate electrode 7 and the dummy gate electrode 17 are formed inside the multiple trenches T. For example, after a polysilicon film is formed on the gate insulating film 6 so as to fill the inside of each of the multiple trenches T, the polysilicon film on the second surface 1B is removed by an etch-back process. As a result, the polysilicon film left inside each trench T becomes each of the gate electrode 7 and the dummy gate electrode 17.

[0039] In this manner, a MOS gate having a trench gate structure is formed, which is composed of the n- type drift layer 2, p type base layer 3, p+ type contact layer 4, n+ type emitter layer 5, gate insulating film 6, and gate electrode 7. Note that the p+ type contact layer 4 and n+ type emitter layer 5 may be formed after the gate electrode 7 is formed.

[0040] In step (S1), next, an interlayer insulating film 10, a barrier metal 11, a plug 12, and a second electrode 13 are formed in each of the IGBT region 101A and the FWD region 101B. The interlayer insulating film 10 is formed on the second surface 1B. A plurality of contact holes are formed in the interlayer insulating film 10. Each contact hole penetrates the interlayer insulating film 10 in a direction perpendicular to the second surface 1B. In each contact hole, the p+ type contact layer 4 and the n+ type emitter layer 5 are exposed. The barrier metal 11 is formed on the upper surfaces of the p+ type contact layer 4 and the n+ type emitter layer 5 exposed from each contact hole, the inner wall surfaces of each contact hole, and the upper surface of the interlayer insulating film 10. The plug 12 is formed on the barrier metal 11 so as to fill the inside of each contact hole. The second electrode 13 is formed on the barrier metal 11 and the plug 12. In this manner, an element structure is formed on the second surface 1B side of the semiconductor substrate 1 in each of the IGBT region 101A and the FWD region 101B.

[0041] Next, a protective film is formed on the second surface 1B (step (S2)). The protective film is formed so as to cover the structures such as the second electrode 13 formed on the second surface 1B in order to protect the structures. The material constituting the protective film includes at least one selected from the group consisting of, for example, polyimide, resist, and silicon oxide. The protective film may be a film or tape-like member. The protective film may be a coating film. Here, the temperature at which the protective film does not deform or deteriorate is referred to as the heat-resistant temperature of the protective film. The heat-resistant temperature of the protective film is higher than the temperature reached by the protective film in a process subsequent to this step (S2). The heat-resistant temperature of the protective film is, for example, lower than the glass transition temperature (Tg) of the material constituting the protective film.

[0042] Next, in each of the IGBT region 101A and the FWD region 101B, the semiconductor substrate 1 is ground (back-ground) from the third surface side to thin the semiconductor substrate 1 (step (S3)). Through this step (S3), the thickness of the semiconductor substrate 1 becomes the thickness of the semiconductor substrate 1 in the semiconductor device 101. A first surface 1A is formed on the side of the semiconductor substrate 1 opposite to the second surface 1B.

[0043] Next, in each of the IGBT region 101A and the FWD region 101B, an impurity region to become the n-type buffer layer 8, an impurity region to become the p-type collector layer 9, and an impurity region to become the n+ type cathode layer 18 are formed on the first surface 1A side of the semiconductor substrate 1 (step (S4)).

[0044] In this step (S4), for example, an impurity region to become n-type buffer layer 8, an impurity region to become p-type collector layer 9, and an impurity region to become n+-type cathode layer 18 are formed in this order. Each impurity region is formed by repeating a set of steps, for example, a step of forming a mask pattern using photolithography, a step of implanting ions using the mask pattern, and a step of removing the mask pattern, under different conditions.

[0045] First, n-type ions for forming the n-type buffer layer 8 are implanted into the semiconductor substrate 1 using a mask pattern that exposes the first surface 1A of each of the IGBT region 101A and the FWD region 101B. The n-type ions are, for example, phosphorus (P). Next, p-type ions for forming the p-type collector layer 9 are implanted into the semiconductor substrate 1 using a mask pattern that exposes the first surface 1A of the IGBT region 101A. The p-type ions are, for example, boron (B). Next, n-type ions for forming the n+ type cathode layer 18 are implanted into the semiconductor substrate 1 using a mask pattern that exposes the first surface 1A of the FWD region 101B. The n-type ions are, for example, P.

[0046] In this manner, semiconductor substrate 1 is prepared, in which an impurity region to become n-type buffer layer 8, an impurity region to become p-type collector layer 9, and an impurity region to become n+-type cathode layer 18 are formed.

[0047] Next, a first annealing step (S20) is performed on the prepared semiconductor substrate 1. In this step (S20), a laser beam is irradiated onto each of the impurity regions to become the n-type buffer layer 8, the impurity regions to become the p-type collector layer 9, and the impurity regions to become the n+ type cathode layer 18. As a result, in each element formation region, each of the impurity regions to become the n-type buffer layer 8, the impurity regions to become the p-type collector layer 9, and the impurity regions to become the n+ type cathode layer 18 are annealed, and the impurities in each impurity region are activated. An example of a laser annealing apparatus for performing this step (S20) will be described later.

[0048] 3, the width in a first direction X (first width) of the beam spot S of the laser light irradiated onto the first surface 1A in step (S20) is narrower than the width in a second direction Y (second width) of the beam spot S. In other words, the beam spot S has an elongated shape with the first direction X as the short side direction and the second direction Y as the long side direction. The shape of the beam spot S may be any elongated shape, and is, for example, rectangular.

[0049] 3, a beam profile P1 in a first direction X of the laser light irradiated onto the first surface 1A in step (S20) and a beam profile P2 in a second direction Y of the laser light L each have a flat-top shape. The beam spot S shown in FIG. 3 can be formed by irradiating the first surface 1A with a laser light shaped by a beam homogenizer.

[0050] The first surface 1A has a plurality of irradiated areas arranged side by side in each of the first direction X and the second direction Y, and having a first width in the first direction X and a second width in the second direction Y. In other words, the first surface 1A is divided into a plurality of irradiated areas having the same dimensions as the beam spot. The plurality of irradiated areas includes a first group of irradiated areas, a second group of irradiated areas, and a third group of irradiated areas. Each of the first group of irradiated areas, the second group of irradiated areas, and the third group of irradiated areas includes a plurality of irradiated areas arranged side by side in the first direction X, and arranged side by side in order in the second direction Y.

[0051] Each of the plurality of irradiated regions may or may not correspond to each of the plurality of element formation regions of the semiconductor substrate 1 described above. Each of the irradiated regions may be an area overlapping one element formation region and an inner peripheral area of ​​a dicing region (dicing line) arranged so as to surround the element formation region. Each of the irradiated regions may be an area overlapping a portion of a plurality of element formation regions and a dicing region (dicing line) arranged in a lattice pattern so as to surround the element formation regions.

[0052] In this process (S20), an irradiation process for forming a beam spot in one of the plurality of irradiated regions is performed a plurality of times, and between each of the plurality of irradiation processes, a first process is performed in which the first surface is scanned by a first width in a first direction X with respect to an optical system that emits laser light, a second process is performed in which the first surface is scanned by a second width in a second direction Y with respect to the optical system, or a third process is performed in which the first surface is scanned by the first width in a direction opposite to the first direction X with respect to the optical system.

[0053] 4 is a diagram for explaining the path along which the beam spot scans the first surface 1A. In FIG. 4, the irradiated region is not shown.

[0054] As shown in FIG. 4, in step (S20), first, the irradiation step is sequentially performed on a first group of irradiation areas that are located at one end in the second direction Y (the upper end in the plane of FIG. 4) and arranged in line in the first direction X among the multiple irradiation areas. Specifically, the irradiation step is first performed on one irradiation area that is located at one end in the first direction X of the first surface 1A (the left end in the plane of FIG. 4) among the first group of irradiation areas. Thereafter, the first step and the irradiation step are repeatedly performed. This scanning path is along the line segment 61 in FIG. 4. The final irradiation step is performed on one irradiation area that is located at the other end in the first direction X of the first surface 1A (the right end in the plane of FIG. 4) among the first group of irradiation areas.

[0055] Next, the second process is performed. The scanning path for this process is along the line segment 62 in FIG. Next, the above-mentioned irradiation process is sequentially performed on the second group of irradiation areas that are aligned with the first group of irradiation areas in the second direction Y and aligned with the first group of irradiation areas in the first direction X. Specifically, the above-mentioned irradiation process is first performed on one of the second group of irradiation areas that is located at the other end of the first direction X of the first surface 1A (the right end as viewed in FIG. 4). Thereafter, the third process and the above-mentioned irradiation process are repeatedly performed. This scanning path is along the line segment 63 in FIG. 4. In the final irradiation process, the irradiation process is performed on one of the second group of irradiation areas that is located at one end of the first direction X of the first surface 1A (the left end as viewed in FIG. 4).

[0056] Next, the second process is performed. The scanning path for this process is along the line segment 64 in FIG. Next, the above-mentioned irradiation process is sequentially performed on the third group of irradiation areas that are aligned with the second group of irradiation areas in the second direction Y and aligned with the second group of irradiation areas in the first direction X. Specifically, the above-mentioned irradiation process is first performed on one of the third group of irradiation areas located at one end of the first surface 1A in the first direction X (the left end as viewed in FIG. 4). Thereafter, the first process and the above-mentioned irradiation process are repeatedly performed. This scanning path is along the line segment 65 in FIG. 4. In the final irradiation process, the irradiation process is performed on one of the third group of irradiation areas located at the other end of the first surface 1A in the first direction X (the right end as viewed in FIG. 4). At least a part of the third group of irradiation areas is in contact with each of the second group of irradiation areas.

[0057] 5(a) to 5(h) are diagrams for explaining the scanning path in more detail. In Fig. 5(a) to 5(h), each of the irradiation areas arranged in four rows in the first direction X and two rows in the second direction Y among the multiple irradiation areas and each coordinate of the irradiation areas, and a beam spot S formed on one irradiation area are shown.

[0058] As shown in Fig. 5(a), the above-mentioned irradiation step is performed on the irradiated area with coordinates (0,0) among the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area with coordinates (0,0). Next, the first step is performed.

[0059] Next, as shown in FIG. 5(b), the above-mentioned irradiation step is performed on the irradiated area with coordinates (1,0) out of the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area with coordinates (1,0). This beam spot S is formed so as to be in contact with, but not overlap with, the irradiated area with coordinates (0,0) on which the beam spot S was previously formed. The beam spot S is formed so that its long side is in contact with the long side of the irradiated area with coordinates (0,0) on which the beam spot S was previously formed. Next, the first step is performed.

[0060] Next, as shown in FIG. 5(c), the above-mentioned irradiation step is performed on the irradiated area at coordinates (2,0) out of the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area at coordinates (2,0). This beam spot S is formed so as to be in contact with, but not overlap with, the irradiated area at coordinates (1,0) on which the beam spot S was previously formed. The beam spot S is formed so that its long side is in contact with the long side of the irradiated area at coordinates (1,0) on which the beam spot S was previously formed. Next, the first step is performed.

[0061] Next, as shown in Fig. 5(d), the above-mentioned irradiation step is performed on the irradiated area at coordinates (3,0) out of the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area at coordinates (3,0). This beam spot S is formed so as to be in contact with, but not overlap with, the irradiated area at coordinates (2,0) on which the beam spot S was previously formed. The beam spot S is formed so that its long side is in contact with the long side of the irradiated area at coordinates (2,0) on which the beam spot S was previously formed.

[0062] Next, the second step is performed. Here, instead of the second step, the first step and the second step may be performed at least once, and the third step may be performed at least once, in that order. In other words, when the beam spot is scanned in the second direction Y, it may be scanned outside the end of the first surface 1A in the first direction X.

[0063] Next, as shown in FIG. 5(e), the above-mentioned irradiation step is performed on the irradiated area at coordinates (3,1) out of the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area at coordinates (3,1). This beam spot S is formed so as to be in contact with, but not overlap with, the irradiated area at coordinates (3,0) on which the beam spot S was previously formed. The beam spot S is formed so that its short side is in contact with the short side of the irradiated area at coordinates (3,0) on which the beam spot S was previously formed. Next, the third step is performed.

[0064] Next, as shown in FIG. 5(f), the above-mentioned irradiation step is performed on the irradiated area at coordinates (2,1) among the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area at coordinates (2,1). This beam spot S is formed so as to be in contact with, but not overlap, the irradiated area at coordinates (2,0) on which the beam spot S was previously formed, and the irradiated area at coordinates (3,1) on which the beam spot S was previously formed. The beam spot S is formed so that its long side is in contact with the long side of the irradiated area at coordinates (3,1) on which the beam spot S was previously formed, and its short side is in contact with the short side of the irradiated area at coordinates (2,0) on which the beam spot S was previously formed. Next, the third step is performed.

[0065] Next, as shown in FIG. 5(g), the above-mentioned irradiation step is performed on the irradiated area at coordinates (1,1) among the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area at coordinates (1,1). This beam spot S is formed so as to be in contact with, but not overlap, the irradiated area at coordinates (1,0) where the beam spot S was previously formed, and the irradiated area at coordinates (2,1) where the beam spot S was previously formed. The beam spot S is formed so that its long side is in contact with the long side of the irradiated area at coordinates (2,1) where the beam spot S was previously formed, and its short side is in contact with the short side of the irradiated area at coordinates (1,0) where the beam spot S was previously formed. Next, the third step is performed.

[0066] Next, as shown in FIG. 5(h), the above-mentioned irradiation step is performed on the irradiated area of ​​coordinates (0,1) among the eight irradiated areas. As a result, a beam spot S is formed on the irradiated area of ​​coordinates (0,1). This beam spot S is formed so as to be in contact with, but not overlap with, the irradiated area of ​​coordinates (0,0) on which the beam spot S was previously formed, and the irradiated area of ​​coordinates (1,1) on which the beam spot S was previously formed. The beam spot S is formed so that its long side is in contact with the long side of the irradiated area of ​​coordinates (1,1) on which the beam spot S was previously formed, and its short side is in contact with the short side of the irradiated area of ​​coordinates (0,0) on which the beam spot S was previously formed.

[0067] In the method for manufacturing a semiconductor device according to the present embodiment, the first annealing step (S20) is repeated twice. The scanning path in the second first annealing step (S20) is the same as the scanning path in the first first annealing step (S20). The second first annealing step (S20) is performed continuously after the first first annealing step (S20) is completed. The intensity of the laser light in each of the first and second first annealing steps (S20) is set to be, for example, equal to the intensity of the laser light in the first first annealing step (S20).

[0068] Next, the protective film is removed (step (S30)). The method for removing the protective film is, for example, at least one of a dry etching method and a wet etching method.

[0069] Next, a first electrode 14 is formed on the first surface 1A (step (S40)). Next, each of the plurality of element formation regions of the semiconductor substrate 1 is diced into individual pieces, thereby obtaining a plurality of semiconductor devices 101.

[0070] In the above step (S20), a laser annealing apparatus 200 shown in Fig. 6 is used. The laser annealing apparatus 200 mainly includes an optical system 30, a holding unit 31, a scanning unit 32, and a control unit 33. The optical system 30 mainly includes a first laser oscillator 40, a second laser oscillator 41, a plurality of mirrors 42, a coupling optical system 43, a beam homogenizer 44, and a condenser lens 45.

[0071] Each of the first laser oscillator 40 and the second laser oscillator 41 outputs a pulsed laser beam. The pulsed laser output from the first laser oscillator 40 is called the first pulsed laser beam, and the pulsed laser output from the second laser oscillator 41 is called the second pulsed laser beam. The second laser oscillator 41 outputs the second pulsed laser beam after a predetermined delay time has elapsed since the first laser oscillator 40 outputs the first pulsed laser beam. The first pulsed laser beam passes through a mirror 42 and enters a coupling optical system 43. The second pulsed laser beam passes through a mirror 42 and enters the coupling optical system 43.

[0072] The combining optical system 43 combines the first pulsed laser beam and the second pulsed laser beam into one laser beam. For example, the first pulsed laser beam is reflected by the combining optical system 43, and the second pulsed laser beam is transmitted through the combining optical system 43. The first pulsed laser beam reflected by the combining optical system 43 is combined with the second pulsed laser beam transmitted through the combining optical system 43.

[0073] The laser light combined by the combining optical system 43 passes through a mirror 42 and enters a beam homogenizer 44. The beam homogenizer 44 shapes the shape and beam profile of the beam spot of the laser light on the first surface 1A. The laser light shaped by the beam homogenizer 44 is collected by a collecting lens 45, and then irradiated as laser light L onto the first surface 1A.

[0074] The holding part 31 holds the semiconductor substrate 1. For example, the holding part 31 holds the first surface 1A of the semiconductor substrate 1 horizontally. The first direction X and the second direction Y are each set to be a direction along the horizontal direction. The semiconductor substrate 1 is placed on the holding part 31 such that, for example, a protective film formed on the second surface 1B contacts the upper surface of the holding part 31.

[0075] The scanning unit 32 moves the semiconductor substrate 1 held by the holding unit 31 in both the first direction X and the second direction Y. The scanning unit 32 is an XY stage that is movable in both the first direction X and the second direction Y.

[0076] The control unit 33 controls the intensity of the pulsed laser light output from each of the first laser oscillator 40 and the second laser oscillator 41, a delay time described later, and the moving distance of the semiconductor substrate 1 by the scanning unit 32. The control unit 33 reads a signal from an encoder attached to the holding unit 31 to obtain position information of the semiconductor substrate 1. Based on the position information of the semiconductor substrate 1, one shot of pulsed laser light is output from each of the first laser oscillator 40 and the second laser oscillator 41, and the laser light is irradiated from the optical system 30 to a target irradiation area. As a result, the beam spot is formed in the area.

[0077] Fig. 7 is a diagram for explaining how the intensities of the first pulsed laser beam, the second pulsed laser beam, and the laser beam obtained by combining these beams in the combining optical system 43 change over time. The horizontal axis of Fig. 7 represents time, and the vertical axis represents intensity. In Fig. 7, waveform 201 represents the intensity waveform of the first pulsed laser beam, waveform 202 represents the intensity waveform of the second pulsed laser beam, and waveform 210 represents the intensity waveform of the laser beam irradiated from the optical system 30.

[0078] 7, the laser light is generated by combining a first pulsed laser light with a second pulsed laser light output after a delay time td has elapsed since the first pulsed laser light was output from the first laser oscillator 40. By generating the laser light as described above, it is possible to sufficiently secure the time te during which the intensity of the laser light becomes equal to or greater than intensity P1, while suppressing the intensity of the laser light to equal to or less than intensity P2.

[0079] Strength P1 is a strength required for activating the impurities in each of the impurity regions to become n-type buffer layer 8, the impurity region to become p-type collector layer 9, and the impurity region to become n+ type cathode layer 18. Strength P2 is a strength that may alter the protective film formed on second surface 1B.

[0080] The delay time td can be set arbitrarily by adjusting the output timing of a trigger signal from the control unit 33. The time te can be adjusted to an arbitrary value by changing the delay time td, the intensities of the first pulse laser beam and the second pulse laser beam, and the like.

[0081] In this embodiment, a first peak and a second peak appear in the waveform 210 of the laser beam. The delay time Td and the intensities of the first pulsed laser beam and the second pulsed laser beam are set so that the intensity PP1 of the first peak, which appears at a relatively early time, is equal to or less than the intensity PP2 of the second peak, which appears at a relatively later time.

[0082] Each of the first pulsed laser light and the second pulsed laser light is visible light. The wavelength of each of the first pulsed laser light and the second pulsed laser light is set to 400 nm or more and less than 600 nm. Each of the first pulsed laser light and the second pulsed laser light is, for example, the second harmonic of a Nd:YLF laser, the second harmonic of a Nd:YAG laser, or the second harmonic of a Nd:YVO4 laser. Preferably, the pulse half-width of each of the first pulsed laser light and the second pulsed laser light is 100 ns or more and less than 5 μs. If the pulse half-width is smaller than 100 ns, heat may not sufficiently reach a region of the semiconductor substrate 1 from the first surface 1A to a depth of about 1 μm, and impurities present in the region may not be sufficiently activated. Also, if the pulse half-width is 5 μs or more, heat may be transmitted to the second surface 1B of the semiconductor substrate 1, causing thermal damage to the structure on the second surface 1B.

[0083] The delay time td also depends on the pulse half-widths of the first and second pulse laser beams, but preferably, the delay time td is set to be 200 ns or more and in accordance with the pulse half-widths and intensity ratio of the first and second pulse laser beams such that the first peak value PP1 is equal to or less than the second peak value PP2.

[0084] Preferably, the pulse repetition frequency of each of the first pulsed laser light and the second pulsed laser light is set between the order of kHz and the order of 10 kHz. If the pulse repetition frequency is too high, the pulse generation interval becomes short, and the cooling time of the semiconductor substrate cannot be sufficiently secured, so that heat is accumulated in the semiconductor substrate, and the semiconductor substrate may melt. If the pulse repetition frequency is too low, the activation process time becomes long.

[0085] <Effects> In the manufacturing method of the semiconductor device according to the first embodiment, in the first annealing step (S20), between each of the multiple irradiation steps, a first step is performed in which the optical system 30 scans the first surface 1A in a first direction X by a first width, or a second step is performed in which the optical system 30 scans the first surface 1A in a second direction Y by a second width.

[0086] That is, the beam spots S formed on the first surface 1A by each of the multiple irradiation steps are formed sequentially on the entire surface of each of the multiple irradiated regions without overlapping each other. In other words, in the first annealing step (20), the number of times that the laser light is irradiated onto each irradiated region is one. Therefore, in the manufacturing method for a semiconductor device according to this embodiment, the beam profile of the laser light is equivalent to that in the manufacturing method for a semiconductor device according to this embodiment, and the temperature rise of the semiconductor substrate 1 is suppressed compared to the conventional technology in which the beam spots are formed so as to overlap each other in one annealing step in which the beam spots are formed sequentially on the entire surface of the multiple irradiated regions.

[0087] Specifically, in the first annealing step (S20), in each of a plurality of irradiation steps, each irradiated region on the first surface 1A is irradiated with a laser beam having an intensity sufficient to activate the first impurity region. Therefore, in each irradiation step, the first surface 1A, which is the irradiated surface, is heated, and heat generated on the first surface 1A side is conducted in the depth direction from the first surface 1A to reach the second surface 1B, thereby increasing the temperature of the entire irradiated region in the depth direction.

[0088] When the beam spots are formed so as to overlap each other in one annealing step as in the conventional technology, the amount of heat stored is relatively large, and the temperature of the non-irradiated surface becomes high. As a result, structures such as a protective film formed on the non-irradiated surface may be deteriorated. If the protective film is deteriorated, it may not be removed in the step of removing the protective film (S30), and a residue may be generated.

[0089] In contrast, in the method for manufacturing a semiconductor device according to the present embodiment, the beam spots do not overlap each other in one annealing step. Therefore, if the laser light irradiation conditions are the same, the amount of heat stored in the present embodiment is relatively smaller than that in the conventional technology, so that the temperature of the second surface 1B, which is the non-irradiated surface, becomes relatively low, and structures such as the protective film formed on the second surface 1B are less likely to deteriorate. As a result, for example, in the step (S30) of removing the protective film, residues are less likely to be generated.

[0090] In addition, since the first annealing step (S20) is repeated twice, the first impurity region can be activated more sufficiently than when the first annealing step (S20) is performed only once. The time required for one irradiated region irradiated with the laser light in the first first annealing step (S20) to be irradiated with the laser light in the second first annealing step (S20) is longer than the time between the first and second irradiations for forming an overlapping portion of the beam spots in the conventional technology. Therefore, according to the manufacturing method of the semiconductor device according to the first embodiment, the temperature reached by the second surface 1B in the second first annealing step (S20) can be suppressed to be lower than the temperature reached by the non-irradiated surface in the conventional technology.

[0091] Embodiment 2 As shown in FIG. 8, the method for manufacturing a semiconductor device according to the second embodiment has a basically similar configuration to the method for manufacturing a semiconductor device according to the first embodiment, but differs from the method for manufacturing a semiconductor device according to the first embodiment in that the intensity of the laser light in the second first annealing step (S20) is set lower than the intensity of the laser light in the first first annealing step (S20).

[0092] When the semiconductor substrate 1 becomes amorphous through the first first annealing step (S20), the semiconductor substrate 1 becomes more liable to absorb laser light, so that the first impurity region can be sufficiently activated even if the intensity of the laser light in the second first annealing step (S10) is lower than that in the first first annealing step (S20). Furthermore, since the intensity of the laser light in the second first annealing step (S10) is lower than that in the first first annealing step (S20), the temperature reached by the second surface 1B is relatively lower during the second first annealing step (S20) than when the two are equal, and structures such as a protective film formed on the second surface 1B are less likely to be altered.

[0093] The semiconductor device 100 can also be manufactured by the method for manufacturing a semiconductor device according to the second embodiment.

[0094] Embodiment 3 9, the method for manufacturing a semiconductor device according to the third embodiment has a basically similar configuration to that of the method for manufacturing a semiconductor device according to the first embodiment, but differs from the method for manufacturing a semiconductor device according to the first embodiment in that the first annealing step (S20) is repeated three times. The following mainly describes the differences from the first embodiment.

[0095] The intensity E3 of the laser light in the third first annealing step (S20) is set to be equal to the intensities E1, E2 of the laser light in the first and second first annealing steps (S20), for example.

[0096] In this way, even if it is difficult to sufficiently activate the first impurity region by only repeating the first annealing step (S20) twice, the first impurity region can be sufficiently activated by performing the first annealing step (S20) a third time.

[0097] The semiconductor device manufacturing method according to the third embodiment may have the same configuration as the semiconductor device manufacturing method according to the second embodiment, except that the first annealing step (S20) is repeated three times. That is, the intensity of the laser light in the third first annealing step (S20) may be set to be lower than the intensity of the laser light in the first first annealing step (S20), for example, and equal to or lower than the intensity of the laser light in each second first annealing step (S20). In this way, the same effect as in the second embodiment can be achieved.

[0098] The semiconductor device 100 can also be manufactured by the method for manufacturing a semiconductor device according to the third embodiment.

[0099] Embodiment 4 The method for manufacturing a semiconductor device according to the fourth embodiment has a basically similar configuration to the method for manufacturing a semiconductor device according to the first embodiment, but differs from the method for manufacturing a semiconductor device according to the first embodiment in that it includes a second annealing step (S50) for annealing a second impurity region in addition to a first annealing step (S20) for annealing a first impurity region, as shown in Fig. 10. The following mainly describes the differences from the first embodiment.

[0100] In the fourth embodiment, the first impurity region includes an impurity region that is to become n-type buffer layer 8. The second impurity region includes an impurity region that is to become p-type collector layer 9, and an impurity region that is to become n+ type cathode layer 18.

[0101] 10, in the method for manufacturing a semiconductor device according to the fourth embodiment, after step (S3), a first impurity region to become n-type buffer layer 8 is formed (step (S5)). Step (S5) is performed in the same manner as the step of forming the impurity region to become n-type buffer layer 8 in the first embodiment. In this way, a semiconductor substrate 1 is prepared in which a first impurity region to become n-type buffer layer 8 is formed.

[0102] Next, a first annealing step (S20) is performed on the first impurity region. The first annealing step (S20) is performed in the same manner as the first annealing step (S20) in the first embodiment. This activates the first impurity region.

[0103] After the first annealing step (S20), an impurity region which is to become p-type collector layer 9, and an impurity region which is to become n+-type cathode layer 18 are formed (step (S6)).

[0104] This step (S6) is performed in the same manner as the step of forming the impurity region to become p-type collector layer 9 and the impurity region to become n+ type cathode layer 18 in the first embodiment. As a result, the impurity region to become p-type collector layer 9 and a second impurity region to become n+ type cathode layer 18 are formed in semiconductor substrate 1.

[0105] Next, a second annealing step (S50) is performed in which the first surface 1A is irradiated with laser light emitted from the optical system 30 to anneal the second impurity region. The second annealing step (S50) is performed in the same manner as the first annealing step (S20). The laser annealing device 200 shown in FIG. 3 is also used in the second annealing step (S50). The scanning shown in FIG. 4 and FIG. 5 is also performed in the second annealing step (S50).

[0106] The second annealing step (S50) is repeated, for example, twice. The intensity E5 of the laser light in the second second annealing step (S50) is set to be equal to the intensity E4 of the laser light in the first second annealing step (S50), for example.

[0107] After the second annealing step (S50) is completed, the protective film removing step (S30) and the first electrode 14 forming step (S40) are carried out.

[0108] In this manner, in the fourth embodiment, the first annealing step (S20) for the first impurity region among the multiple impurity regions formed on the first surface 1A side and the second annealing step (S50) for the second impurity region are performed as separate steps. The semiconductor device 100 can also be manufactured by such a manufacturing method for a semiconductor device according to the fourth embodiment.

[0109] In the fourth embodiment, the second annealing step (S50) may be repeated three or more times. The intensity of the laser light in the third second annealing step (S50) may be set to be lower than the intensity of the laser light in the first second annealing step (S50), and may be set to be equal to or lower than the intensity of the laser light in each second second annealing step (S50).

[0110] In the fourth embodiment, the first annealing step (S20) may be performed in the same manner as the first annealing step (S20) in the second or third embodiment.

[0111] In the method for manufacturing a semiconductor device according to the first or fourth embodiment, each of the first annealing step (S20) and the second annealing step (S50) may be performed only once.

[0112] Embodiment 5. 11, the method for manufacturing a semiconductor device according to the fifth embodiment has a basically similar configuration to the method for manufacturing a semiconductor device according to the first embodiment, but differs from the method for manufacturing a semiconductor device according to the first embodiment in that the delay time td2 of the laser light in the second first annealing step (S20) is different from the delay time td1 of the laser light in the first first annealing step (S20). The following mainly describes the differences from the first embodiment.

[0113] The laser light used in the first first annealing step (S20) is generated by combining the first pulsed laser light output from the first laser oscillator 40 with the second pulsed laser light output from the second laser oscillator after a delay time td1 has elapsed since the first pulsed laser light was output from the first laser oscillator 40. The laser light used in the second first annealing step (S20) is generated by combining the first pulsed laser light output from the first laser oscillator 40 with the second pulsed laser light output from the second laser oscillator after a delay time td2 has elapsed since the first pulsed laser light was output from the first laser oscillator 40. In this embodiment, the delay time td2 of the laser light in the second first annealing step (S20) is different from the delay time td1 of the laser light in the first first annealing step (S20).

[0114] The delay time td2 of the laser beam in the second first annealing step (S20) may be longer than the delay time td1 of the laser beam in the first first annealing step (S20).

[0115] In the case where the shorter the delay time of the laser beam is, the easier it is to activate the impurity region, the delay time td2 of the laser beam in the second first annealing step (S20) is preferably longer than the delay time td1 of the laser beam in the first first annealing step (S20).

[0116] The intensity of the laser light in the second first annealing step (S20) is equal to or lower than the intensity of the laser light in the first first annealing step (S20). The intensity of the laser light in the second first annealing step (S20) may be equal to the intensity of the laser light in the first first annealing step (S20).

[0117] For example, when the intensities of the laser beams in the first and second first annealing steps (S20) are equal to each other and the shorter the delay time of the laser beam, the easier it is to activate the impurity region, the first impurity region can be sufficiently activated even if the delay time td2 of the laser beam in the second first annealing step (S20) is longer than the delay time td1 of the laser beam in the first first annealing step (S20). This is because when the semiconductor substrate 1 becomes amorphous in the first first annealing step (S20), the semiconductor substrate 1 becomes more likely to absorb the laser beam. Furthermore, in the above case, the temperature reached by the second surface 1B is relatively low in the second first annealing step (S20) compared to the case where the intensities and delay times of the laser beams in the first and second first annealing steps (S20) are equal to each other, and structures such as a protective film formed on the second surface 1B are less likely to be altered.

[0118] Also in this embodiment, the intensity of the laser light in the second first annealing step (S20) may be lower than the intensity of the laser light in the first first annealing step (S20).

[0119] Although the embodiment of the present disclosure has been described above, the above-mentioned embodiment can be modified in various ways. The scope of the present disclosure is not limited to the above-mentioned embodiment. The scope of the present disclosure is defined by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims. [Explanation of symbols]

[0120] 1 semiconductor substrate, 1A first surface, 1B second surface, 2 n-type drift layer, 3 p-type base layer, 4 p+-type contact layer, 5 n+-type emitter layer, 6 gate insulating film, 7 gate electrode, 8 n-type buffer layer, 9 p-type collector layer, 10 interlayer insulating film, 11 barrier metal, 12 plug, 13 second electrode, 13A emitter electrode, 13B electrode, 14 first electrode, 14A collector electrode, 14B cathode electrode, 15 p-type anode layer, 16 p+-type anode layer, 17 dummy gate electrode, 18 n+-type cathode layer, 30 optical system, 31 holding unit, 32 scanning unit, 33 control unit, 40 first laser oscillator, 41 second laser oscillator, 42 mirror, 43 coupling optical system, 44 beam homogenizer, 45 condenser lens, 101 semiconductor device, 101A IGBT area, 101B FWD area, 200 laser annealing equipment.

Claims

1. preparing a semiconductor substrate having a first surface extending along a first direction and a second direction perpendicular to the first direction, the semiconductor substrate having a first impurity region formed therein; a first annealing step of irradiating the first surface with laser light emitted from an optical system to anneal the first impurity region; in the first annealing step, the laser light is generated by combining a first pulsed laser light and a second pulsed laser light output after a delay time has elapsed since the output of the first pulsed laser light, a first width in the first direction of a beam spot formed by the laser light on the first surface is narrower than a second width in the second direction of the beam spot; the first surface has a plurality of regions that are arranged side by side in at least one of the first direction and the second direction, and have the first width in the first direction and the second width in the second direction; In the first annealing step, The irradiation step of forming the beam spot in one of the plurality of regions is performed a plurality of times, During each of the multiple irradiation steps, a first step of scanning the first surface in the first direction by the first width with respect to the optical system and a second step of scanning the first surface in the second direction by the second width with respect to the optical system after the first step is completed are performed, The first annealing step is repeated twice; A method for manufacturing a semiconductor device, wherein the delay time of the laser light in a second time of the first annealing step is different from the delay time of the laser light in a first time of the first annealing step.

2. the plurality of regions includes a first group of regions arranged side by side in the first direction, and a second group of regions arranged side by side in the first direction and side by side with the first group of regions in the second direction, the multiple irradiation steps include a first group irradiation step of forming the beam spot in one region of the first group of regions, and a second group irradiation step of forming the beam spot in one region of the second group of regions, In the first annealing step, each of the first group of irradiation steps is repeatedly performed with the first step interposed therebetween, and the beam spots are sequentially formed in the first group of regions from a first end to a second end in the first direction; Then, the second step is carried out, 2. The method for manufacturing a semiconductor device according to claim 1, wherein each of the second group of irradiation processes is then sandwiched between a third process in which the optical system scans the first surface by the first width in a direction opposite to the first direction, and the beam spot is formed sequentially from a third end to a fourth end in the first direction of the region of the second group.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the first annealing step, the beam spot formed in one of the multiple irradiation steps is formed so as to be in contact with a region in which the beam spot was formed in the irradiation step performed immediately before.

4. 2 . The method of claim 1 , wherein an intensity of said laser light in a second time of said first annealing step is equal to or lower than an intensity of said laser light in a first time of said first annealing step.

5. The first annealing step is repeated three times; 5. The method of claim 4, wherein an intensity of the laser light in the third first annealing step is equal to or lower than an intensity of the laser light in the second first annealing step.

6. preparing a semiconductor substrate having a first surface extending along a first direction and a second direction perpendicular to the first direction, the semiconductor substrate having a first impurity region formed therein; a first annealing step of irradiating the first surface with laser light emitted from an optical system to anneal the first impurity region; in the first annealing step, the laser light is generated by combining a first pulsed laser light and a second pulsed laser light output after a delay time has elapsed since the output of the first pulsed laser light, a first width in the first direction of a beam spot formed by the laser light on the first surface is narrower than a second width in the second direction of the beam spot; the first surface has a plurality of regions that are arranged side by side in at least one of the first direction and the second direction, and have the first width in the first direction and the second width in the second direction; In the first annealing step, The irradiation step of forming the beam spot in one of the plurality of regions is performed a plurality of times, During each of the multiple irradiation steps, a first step of scanning the first surface in the first direction by the first width with respect to the optical system and a second step of scanning the first surface in the second direction by the second width with respect to the optical system after the first step is completed are performed, The first annealing step is repeated twice; a delay time of the laser light in a second first annealing step is different from a delay time of the laser light in a first first annealing step, and an intensity of the laser light in the second first annealing step is equivalent to an intensity of the laser light in the first first annealing step.

7. In the preparing step, the semiconductor substrate further having a second impurity region formed therein is prepared, a second annealing step of irradiating the second impurity region with the laser light to anneal the second impurity region; In the second annealing step, The multiple irradiation steps; The first step or the second step is carried out between each of the multiple irradiation steps, The second annealing step is repeated multiple times; 7. The method for manufacturing a semiconductor device according to claim 1, wherein an intensity of the laser light in a second time of the second annealing step is equal to or lower than an intensity of the laser light in a first time of the second annealing step.

8. In the preparing step, the semiconductor substrate is prepared, the semiconductor substrate having a second surface located on an opposite side to the first surface, forming a protective film on the second surface after the preparing step and before the first annealing step; and removing the protection film after annealing the first impurity region.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature reached by said protective film in said first annealing step is lower than a heat-resistant temperature of said protective film.

9. a holding part that holds a semiconductor substrate having a first surface extending along a first direction and a second direction perpendicular to the first direction, the semiconductor substrate having a first impurity region formed therein; an optical system that irradiates the first surface of the semiconductor substrate held by the holding unit with laser light and forms a beam spot in one of a plurality of regions on the first surface that are arranged side by side in at least one of the first direction and the second direction; a scanning unit configured to scan one of the semiconductor substrate and the optical system relative to the other, the optical system includes a first laser oscillator that outputs a first pulsed laser beam, a second laser oscillator that outputs a second pulsed laser beam after a delay time has elapsed since the first laser oscillator outputted the first pulsed laser beam, and a combining optical system that combines the first pulsed laser beam and the second pulsed laser beam into one laser beam, the optical system is provided to form the beam spot on the first surface, the beam spot having a first width in the first direction narrower than a second width in the second direction; the scanning unit scans the first surface in the first direction by the first width relative to the optical system after the optical system has formed one of the beam spots, and scans the first surface in the first direction by the first width relative to the optical system after scanning the first surface in the first direction by the first width relative to the optical system, and then scans the first surface in the second direction by the second width relative to the optical system; a control unit that controls the delay time of the laser light irradiated from the optical system to the first surface, The control unit controls the delay time of the laser light in the second first annealing step, when the first annealing step of irradiating the laser light from the optical system to the first surface and annealing the first impurity region is repeated twice, so that the delay time of the laser light in the second first annealing step is different from the delay time of the laser light in the first first annealing step.

10. a holding part that holds a semiconductor substrate having a first surface extending along a first direction and a second direction perpendicular to the first direction, the semiconductor substrate having a first impurity region formed therein; an optical system that irradiates the first surface of the semiconductor substrate held by the holding unit with laser light and forms a beam spot in one of a plurality of regions on the first surface that are arranged side by side in at least one of the first direction and the second direction; a scanning unit configured to scan one of the semiconductor substrate and the optical system relative to the other, the optical system includes a first laser oscillator that outputs a first pulsed laser beam, a second laser oscillator that outputs a second pulsed laser beam after a delay time has elapsed since the first laser oscillator outputted the first pulsed laser beam, and a combining optical system that combines the first pulsed laser beam and the second pulsed laser beam into one laser beam, the optical system is provided to form the beam spot on the first surface, the beam spot having a first width in the first direction narrower than a second width in the second direction; the scanning unit scans the first surface in the first direction by the first width relative to the optical system after the optical system has formed one of the beam spots, and scans the first surface in the first direction by the first width relative to the optical system after scanning the first surface in the first direction by the first width relative to the optical system, and then scans the first surface in the second direction by the second width relative to the optical system; a control unit that controls a delay time of the laser light irradiated from the optical system to the first surface and an intensity of the laser light, The control unit controls the delay time of the laser light in the second first annealing step so that it is different from the delay time of the laser light in the first first annealing step, when the first annealing step of irradiating the laser light from the optical system to the first surface and annealing the first impurity region is repeated twice, and controls the intensity of the laser light in the second first annealing step so that it is equivalent to the intensity of the laser light in the first first annealing step.

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