Signal processing circuit, photoelectric conversion device and equipment

Abstract

To provide a technique to ensure faster response of a reference signal in a signal processing circuit.SOLUTION: A signal processing circuit includes a reference signal line, a processing unit that processes potential of the reference signal line and potential of an input signal, a first reference voltage supply unit that outputs a predetermined potential to one end of the reference signal line, and a second reference voltage supply unit that outputs predetermined potential to the other end of the reference signal line.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] Recent CMOS image sensors are required to achieve high frame rates and improved signal-to-noise ratios (S / N) using analog-digital converters (hereafter abbreviated as ADCs). Single-slope ADCs are the most common form of ADC. Single-slope ADCs use a comparator to compare the signal level from the pixel with a reference signal whose voltage value changes over time, and perform AD conversion by digitally counting the inversion time of the comparator output.

[0003] An example of the configuration and driving method of a reference signal generation circuit for a single-slope ADC is disclosed in Patent Document 1. Patent Document 1 describes a method of applying an offset to suppress degradation of linearity caused by a settling error of the reference signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-259407 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in order to realize high-speed response of the reference signal, it is becoming insufficient to simply apply the technique described in Patent Document 1, and the following problems arise.

[0006] For example, the responsiveness of the reference signal is affected not only by the time until the settling error of Patent Document 1 reaches a predetermined level or less, but also by the settling time of the offset itself. In addition, the reset time of the reference voltage also has an effect. Since these times are greatly influenced by the parasitic element components of the transmission line of the reference signal, a means is required to effectively reduce the influence of the parasitic element components while improving the responsiveness of the reference signal.

[0007] Therefore, the present invention provides a technique for ensuring faster response of a reference signal in a signal processing circuit. [Means for solving the problem]

[0008] The present disclosure relates to a reference signal line, a processing unit that processes a potential of the reference signal line and a potential of an input signal; a first reference voltage supplying unit that outputs a predetermined potential to one end of the reference signal line; a second reference voltage supplying unit that outputs a predetermined potential to the other end of the reference signal line; a connection means for switching a connection between the second reference voltage supply unit and the other end of the reference signal line from a connected state to a disconnected state, or from a disconnected state to a connected state; Have death, During at least a part of a period during which the first reference voltage supply unit outputs the predetermined potential to the one end of the reference signal line, the connection unit switches the connection between the second reference voltage supply unit and the other end of the reference signal line from a connected state to a disconnected state, or from a disconnected state to a connected state. Includes a signal processing circuit. The present disclosure also provides a reference signal line, a processing unit that processes a potential of the reference signal line and a potential of an input signal; a first reference voltage supplying unit that outputs a predetermined potential to one end of the reference signal line; a second reference voltage supplying unit that outputs a predetermined potential to the other end of the reference signal line; a connection means for switching a connection between the second reference voltage supply unit and the other end of the reference signal line from a connected state to a disconnected state, or from a disconnected state to a connected state; having The first reference voltage supply unit and the second reference voltage supply unit include a signal processing circuit that supplies the same potential to the reference signal line.

[0009] The present disclosure also provides a light-emitting diode (LED) having a photoelectric conversion unit that outputs a signal according to incident light; The signal processing circuit described above processes a signal output from the photoelectric conversion unit; The photoelectric conversion device includes a photoelectric conversion device having the following components:

[0010] The present disclosure also provides a photoelectric conversion device, an optical system that forms an image on the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; Mechanical devices having moving or propelling parts; At least one of the six This includes equipment equipped with: Effect of the Invention

[0011] According to the present invention, it is possible to ensure faster response of a reference signal in a signal processing circuit. [Brief description of the drawings]

[0012] [Figure 1] Block diagram of a photoelectric conversion device according to a first embodiment. [Diagram 2] FIG. 1 is a circuit diagram showing an example of the configuration of a first reference voltage supply unit according to a first embodiment; [Diagram 3] FIG. 1 is a circuit diagram showing an example of the configuration of a second reference voltage supply unit according to a first embodiment; [Figure 4] 1 is a timing chart showing the operation of the photoelectric conversion device according to the first embodiment; [Diagram 5] FIG. 1 is a small signal equivalent circuit diagram of a circuit of a photoelectric conversion device according to a first embodiment. [Figure 6] FIG. 11 is a circuit diagram showing another example of the configuration of the reference voltage supply unit according to the first embodiment; [Figure 7] FIG. 1 is a block diagram showing another configuration of a photoelectric conversion device according to a first embodiment. [Figure 8] Block diagram of a photoelectric conversion device according to a second embodiment. [Figure 9] 11 is a timing chart showing the operation of the photoelectric conversion device according to the second embodiment. [Figure 10] 11 is another timing chart showing the operation of the photoelectric conversion device according to the second embodiment. [Figure 11] 13 is yet another timing chart showing the operation of the photoelectric conversion device according to the second embodiment. [Figure 12] FIG. 11 is a block diagram showing another configuration of a photoelectric conversion device according to the second embodiment. [Figure 13] FIG. 11 is a diagram for explaining an apparatus according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. Also, some of the components, members, and processes will be omitted in each drawing.

[0014] (First embodiment) Next, a first embodiment of the present invention will be described with reference to the drawings.

[0015] 1 is a circuit block diagram of the photoelectric conversion device according to the first embodiment, and also serves as a layout diagram of the circuit blocks in a plan view. Here, "plan view" refers to a view from a direction perpendicular to the main surface of the semiconductor substrate. The main surface of the semiconductor substrate may be a light incidence surface of a semiconductor substrate including a photoelectric conversion unit, a surface on which multiple ADCs are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device.

[0016] As shown in FIG. 1, the circuit of the photoelectric conversion device 1 according to the present embodiment includes a pixel array 100, a vertical scanning unit 200, a signal processing circuit 10, a horizontal scanning unit 600, and an output unit 700. The pixel array 100 is a photoelectric conversion unit in which pixels 110, each including a photodiode (PD) as a component that outputs a predetermined voltage value in response to incident light on the photoelectric conversion device, are arranged in a two-dimensional array. A vertical signal line 120 is connected to each pixel column of the pixel array 100. The vertical signal line 120 is a signal line for transmitting an output signal from the pixel 110 of the pixel array 100 to a subsequent circuit. A current source 130 is connected to each vertical signal line 120, which serves as a load for operating an amplifier circuit of the pixel 110, typically a source follower circuit. The signal processing circuit 10 includes a column ADC array 300, a first reference voltage supply unit 400, and a second reference voltage supply unit 500.

[0017] The vertical scanning unit 200 is connected to the pixel array 100 , and selects and controls the readout rows and reset rows of the pixel array 100 .

[0018] The column ADC array 300 receives the potential of the vertical signal line 120, which is an output signal from the pixel array 100, as an input, and converts the potential into a digital value. The column ADC array 300 has a reference signal line 301, a comparator 302, and a counter memory 303. The reference signal line 301 is connected to the first reference voltage supply unit 400 and the second reference voltage supply unit 500, and transmits a reference signal for a predetermined period. The comparator 302 is a processing unit that executes a process of comparing the potential of an analog signal input from the vertical signal line 120 as an input signal line with the potential of the reference signal line 301. As shown in FIG. 1, a plurality of comparators 302 are provided in the column ADC array 300, and the reference signal line 301 is connected to the plurality of comparators 302. In addition, the vertical signal lines 120 corresponding to each of the plurality of comparators 302 are connected. The counter memory 303 digitally counts the inversion time of the output from the comparator 302 and holds the count result.

[0019] The first reference voltage supply unit 400 and the second reference voltage supply unit 500 output a predetermined potential to the reference signal line 301. The predetermined potential is a reference signal, for example, a ramp signal.

[0020] 2 and 3 are circuit block diagrams of the first reference voltage supply unit 400 and the second reference voltage supply unit 500, respectively. As shown in FIG. 2, the first reference voltage supply unit 400 has a current control counter 410, an offset control unit 420, a current source 430, and a load resistor 440. The current i1 of the current source 430 is transiently controlled by the current control counter 410 and the offset control unit 420, and a potential according to the product of the current i1 and the resistance r1 of the load resistor 440 is output from the first reference voltage supply unit 400. 400 appears in the output out.

[0021] 3, the second reference voltage supply unit 500 has the same configuration as the first reference voltage supply unit 400, and includes a current control counter 510, an offset control unit 520, a current source 530, and a load resistor 540. The current control counter 510 and the offset control unit 520 transiently control the current i2 of the current source 530, and a potential according to the product of the current i2 and the resistance r2 of the load resistor 540 appears at the output out of the second reference voltage supply unit 500. The current control counter 510 and the offset control unit 520 correspond to a power control means for controlling the power of the second reference voltage supply unit 500.

[0022] In this embodiment, the resistance values ​​of the resistors r1 and r2 are equal to each other, and the current control counters 410, 510 and the offset control units 420, 520 operate so that the current amounts of the currents i1 and i2 are equal. As a result, the first reference voltage supply unit 400 and the second reference voltage supply unit 500 supply the same potential to the reference signal line 301. Here, the potential being the same means that the potentials are the same by design, and there may be a potential difference due to a manufacturing error.

[0023] The horizontal scanning section 600 is connected to the column ADC array 300, and generates a control signal for sequentially reading out the digital signals held in the counter memory 303 to the outside of the chip via an output section 700.

[0024] Next, the operation relating to AD conversion of the photoelectric conversion device having the circuit shown in FIG. 1 will be described with reference to the timing chart of FIG.

[0025] As shown in FIG. 4, as a preparatory operation for early stabilization of the linearity of the ramp signal, in the period from time t1 to time t3, the current amounts of the currents i1 and i2 are increased from ia to ib, respectively, based on the control signals from the offset control units 420 and 520. As a result, the potential ( V ref) rises from V1 to V2. The settling time (t2-t1) from the potential V1 to the potential V2 at this time is called the "offset time."

[0026] Then, at time t3, the current amounts of currents i1 and i2 change from ib to ia, and thereafter, the current control counters 410 and 510 operate so that the currents i1 and i2 decrease at a constant rate over time, thereby starting the ramp operation of the potential Vref.

[0027] At this time, in the period from time t3 to time t4, AD conversion is not performed in order to suppress deterioration of linearity caused by a settling error of the potential Vref. Then, at the point in time (time t4) when the settling error becomes equal to or less than a predetermined allowable value, the counter memory 303 starts counting and AD conversion. Here, the time from time t3 to time t4 (t4-t3) is referred to as the "run-up time."

[0028] The period from time t4 to time t5 is an AD conversion period, during which the column ADC array 300 counts a count number n according to the resolution of the ADC, and stores the count value when the comparator 302 inverts during the AD conversion period as a digital value in the counter memory 303.

[0029] Then, when the column ADC array 300 finishes counting and the potential Vref drops to V3 (time t6), the current control counters 410, 510 are reset. Also, the amount of current i1 and i2 is increased from ic to ia, the potential Vref is reset to V1, and the device enters a standby state until the next AD conversion operation. The settling time (t7-t6) from the potential V3 to the potential V1 at this time is called the "reset time." The above is a series of operations related to AD conversion in the photoelectric conversion device 1.

[0030] In the above description, the offset time, run-up time, and reset time are determined by the currents i1 and i2, the load resistances r1 and r2, and the parasitic resistance rp and parasitic capacitance cp of the reference signal line 301 in the section indicated by "A" in FIG. 1. The parasitic resistance rp is the total resistance value seen from both ends of the column ADC array 300. The parasitic capacitance cp includes not only the parasitic capacitance of the wiring but also the input capacitance of the comparator 302. As described above, the current amounts of the currents i1 and i2 are equal to each other for the first reference voltage supply unit 400 and the second reference voltage supply unit 500, and the resistance values ​​of the resistors r1 and r2 are equal to each other. For this reason, the first reference voltage supply unit 400 and the second reference voltage supply unit 500 can be regarded as equivalent circuits.

[0031] From the above, the reference signal line 301, the first reference voltage supply unit 400, and the second reference voltage supply unit 500 can be replaced with a small signal equivalent circuit as a model showing the potential of the reference signal line 301 at the center of the column ADC array 300 where the parasitic impedance becomes large. An example of this small signal equivalent circuit is shown in Fig. 5. In Fig. 5, it is assumed that i(t) = i1(t) = i2(t) and r = r1 = r2.

[0032] As shown in FIG. 1, the first reference voltage supply unit 400 is disposed at one end of the column ADC array 300, and the second reference voltage supply unit 500 is disposed at the other end, and the reference signal line 301 is driven from both ends, so that the effective parasitic resistance is rp / 4 as shown in FIG. 5. In other words, the processing unit is disposed so as to be sandwiched between the first reference voltage supply unit 400 and the second reference voltage supply unit 500 in a plan view of the signal processing circuit 10. Note that the processing unit, the first reference voltage supply unit 400, and the second reference voltage supply unit 500 do not necessarily need to be arranged on a straight line. In other words, the processing unit may be shifted in a direction perpendicular to the straight line connecting the first reference voltage supply unit 400 and the second reference voltage supply unit 500. It is preferable that at least a part of the column ADC array 300 including the processing unit is located on the straight line. As a result, when the signal processing circuit 10 is viewed in one direction (for example, the left and right direction in the figure), the geometric centers of the multiple comparators 302 are located between the geometric center of the first reference voltage supply unit 400 and the geometric center of the second reference voltage supply unit 500. The geometric center of the voltage supplying unit 400, the geometric center of the comparator 302, and the geometric center of the second reference voltage supplying unit 500 do not necessarily need to be aligned on a straight line.

[0033] For example, the first reference voltage supply unit 400 and the second reference voltage supply unit 500 are arranged close to one end of the column ADC array 300. In this case, the side where the first reference voltage supply unit 400 and the second reference voltage supply unit 500 are arranged is more susceptible to the influence of parasitic impedance. In the column ADC array 300, the parasitic resistance at the end opposite to the side where the first reference voltage supply unit 400 and the second reference voltage supply unit 500 are arranged is rp. From this, it can be seen that the parasitic resistance is reduced by (3×rp) / 4 by configuring the column ADC array 300 as described above.

[0034] In the photoelectric conversion device according to the present embodiment, the comparator 302 is arranged between the first reference voltage supply unit 400 and the second reference voltage supply unit 500 in a plan view of the signal processing circuit. Due to the effective parasitic resistance reduction effect obtained by such an arrangement, the responsiveness of the reference signal is improved in the signal processing circuit, and the offset time, run-up time, and reset time can be shortened. The shortening of these times is synonymous with the shortening of the time from time t1 to time t7 required for one AD conversion shown in FIG. 4. Therefore, according to the photoelectric conversion device according to the present embodiment using such a signal processing circuit, it is possible to shorten the readout time per pixel row and increase the frame rate of the CMOS image sensor.

[0035] The above effect is not limited to a configuration using two or more reference voltage supply units, but can also be obtained in a configuration using a single reference voltage supply unit. Even when the reference signal line 301 is driven from one end side of the column ADC array 300 using a single reference voltage supply unit equivalent to the voltage generation unit illustrated in FIG. 5, the same effect of increasing the frame rate due to the reduction in parasitic resistance as described above can be obtained. In addition, according to the photoelectric conversion device of this embodiment, it is also possible to suppress a local increase in current density in the device, and therefore it is also possible to reduce crosstalk and pattern noise caused by a local increase in current density.

[0036] In addition, the circuit configurations of the first reference voltage supply unit 400 and the second reference voltage supply unit 500 in this embodiment are not limited to the circuit configurations shown in FIG. 2 and FIG. 3. For example, the first reference voltage supply unit 400 and the second reference voltage supply unit 500 may be replaced with a reference voltage supply unit having a circuit shown in FIG. 6. The reference voltage supply unit shown in FIG. 6 has a current source 431, an integral capacitance 450, and a reset unit 460. In the reference voltage supply unit shown in FIG. 6, the current source 431, the integral capacitance 450, and the reset unit 460 are connected to the output out connected to the reference signal line 301 in FIG. 1. The reset unit 460 controls the connection of the potential V1 to the current source 431. Note that instead of generating the voltage of the potential V1 internally by the current source 431, a voltage may be supplied to the reset unit 460 from an external voltage source.

[0037] 6, after the reference signal line 301 is reset to potential V1 by the reset unit 460, the charge held in the integral capacitance 450 is extracted by the current source 431, thereby lowering the potential over time to generate a reference signal. At this time, as in the case of using the circuits shown in FIGS. 2 and 3, it is possible to shorten the run-up time and reset time by reducing the parasitic resistance described above.

[0038] In addition, in the photoelectric conversion device according to this embodiment, the arrangement of the first reference voltage supply unit 400 and the second reference voltage supply unit 500 shown in Fig. 1 is not necessarily limited to the positions at both ends of the column ADC array 300. For example, the configuration of a photoelectric conversion device 1' that is a CMOS image sensor having a stacked structure shown in Fig. 7 may be adopted. Note that Fig. 7 also serves as a layout diagram of circuit blocks in a plan view of each substrate, similar to Fig. 1.

[0039] In FIG. 7, the photoelectric conversion device 1' has a pixel substrate 800 and a circuit substrate 810. The pixel substrate 800 has a pixel array 100 in which the pixels 110 shown in FIG. 1 are arranged in an array, and a connection section 820. The pixel array 100 and the connection section 820 are connected by a vertical signal line 120. The circuit substrate 810 also has a vertical scanning section 200, a column ADC array 300, first and second reference voltage supply sections 400 and 500, a horizontal scanning section 600, and an output section 700 shown in FIG. 1. The circuit substrate 810 also has a connection section 830 similar to the connection section 820 of the pixel substrate 800. The column ADC array 300 and the connection section 830 are connected to the vertical signal line 120 and the current source 130. The column ADC array 300 has a reference signal line 301, a comparator 302, and a counter memory 303, similar to FIG. 1. It should be noted that detailed explanations of components that are the same as those in FIG. 1 and are designated by the same reference numerals will be omitted here.

[0040] The pixel substrate 800 and the circuit substrate 810 transmit and receive signals via a connection portion 820. As shown in FIG. 7, due to restrictions on the chip size of the pixel substrate 800 and the circuit substrate 810 and the associated restrictions on the circuit layout of the connection portion 820 and the vertical scanning portion 200, it may not be possible to arrange the first and second reference voltage supplying portions 400 and 500 at both ends of the column ADC array 300. Even in such a case, as shown in FIG. 7, the first reference voltage supplying portion 400 and the second reference voltage supplying portion 500 can be arranged at the upper end of the column ADC array 300. If the parasitic impedance associated with the routing of the reference signal line 301 from the first and second reference voltage supplying portions 400 and 500 to the column ADC array 300 is smaller than the parasitic impedance in the column ADC array 300, the same effect as in FIG. 1 can be obtained.

[0041] As described above, in the signal processing circuit according to this embodiment and the photoelectric conversion device using the signal processing circuit, it is possible to provide a degree of freedom in the arrangement of the first reference voltage supply unit 400 and the second reference voltage supply unit 500 while obtaining the effect of reducing parasitic resistance.

[0042] Second embodiment Next, a second embodiment of the present invention will be described with reference to Fig. 8. In the following description, the same components as those in the first embodiment are given the same reference numerals, and detailed description thereof will be omitted.

[0043] As shown in Fig. 8, the signal processing circuit 20 of the photoelectric conversion device 2 according to this embodiment has a switch 900. The switch 900 is a connection means that controls the connection between the output of the second reference voltage supply unit 500 and the reference signal line 301 by a pulse p1. Here, when the pulse p1 is High, the output of the second reference voltage supply unit 500 and the reference signal line 301 are electrically connected, and when the pulse p1 is Low, the output of the second reference voltage supply unit 500 and the reference signal line 301 are not electrically connected. The configurations other than the signal processing circuit 20 are similar to those of the photoelectric conversion device 1 according to the first embodiment.

[0044] Next, the operation of the circuit having the configuration shown in FIG. 8 regarding AD conversion will be described with reference to the timing chart shown in FIG.

[0045] In FIG. 9, in the period from time t1 to time t3 including the offset time, pulse p1 is High, and the reference signal line 301 is driven from both ends by the first reference voltage supply unit 400 and the second reference voltage supply unit 500.

[0046] Next, when the pulse p1 changes from High to Low at time t3, the switch 900 disconnects the output of the second reference voltage supply unit 500 from the reference signal line 301. Then, during the period from time t3 to time t7, which includes the AD conversion period, the reference signal line 301 is driven only by the first reference voltage supply unit 400.

[0047] After that, at time t7, the pulse p1 changes from Low to High, and during the reset operation including the above-mentioned reset time, the reference signal line 301 is again driven from both ends of the reference signal line 301 by the first reference voltage supply unit 400 and the second reference voltage supply unit 500.

[0048] In this way, during the AD conversion period, the reference signal line 301 is driven by only one reference voltage supply unit, thereby making it possible to reduce the variation in the reference signal characteristics for each pixel column caused by the difference in characteristics between the first reference voltage supply unit 400 and the second reference voltage supply unit 500. This will be described in further detail below.

[0049] When the photoelectric conversion device 2 is used as a multi-pixel CMOS image sensor, the first reference voltage supply unit 400 and the second reference voltage supply unit 500 are disposed apart from each other, and therefore the device is easily affected by the variation in the relative characteristics of elements such as transistors and resistors. In such a case, there is a concern that a slight difference occurs in the characteristics of the reference signals generated by the first reference voltage supply unit 400 and the second reference voltage supply unit 500. Then, the two signals having such a characteristic difference are superimposed on one signal node and used as a reference for arithmetic processing such as AD conversion. Then, depending on the positional relationship between the first reference voltage supply unit 400 and the second reference voltage supply unit 500, differences also occur in the characteristics of the reference signals input to the comparators 302 of each pixel column. As a result, the conversion coefficient varies for each pixel column, and fixed pattern noise that cannot be ignored depending on the specifications required for the photoelectric conversion device 2 occurs, deteriorating the image quality.

[0050] In consideration of this, in this embodiment, as shown in Figures 8 and 9, during the AD conversion period, the reference signal line 301 is driven only by the first reference voltage supply unit 400, so that the AD conversion performance is determined by one reference signal. Then, during periods other than the AD conversion period, in order to achieve a high frame rate, the switch 900 connects the second reference voltage supply unit 500 to the node of the reference signal line 301, so that the reference signal line 301 is also driven by the second reference voltage supply unit 500. This shortens the offset time and reset time, making it possible to achieve both high image quality and a high frame rate in the photoelectric conversion device 2.

[0051] The voltage waveform of the second reference voltage supply unit 500 in the second embodiment is not limited to that shown in Fig. 9, and may be, for example, a voltage waveform as shown in Fig. 10, and the second reference voltage supply unit 500 may be configured by a circuit that realizes such a voltage waveform. In Fig. 10, the output potential Vref2 from the second reference voltage supply unit 500 is timeDuring the period from t1 to t3 when pulse p1 is High, the reference signal line 301 is driven at the same potential as the first reference voltage supply unit 400. Then, this output potential Vref2 is reset to a predetermined potential (potential V1 in FIG. 10) during part of the period when pulse p1 is Low. By controlling the output potential Vref2 in this way, the second reference voltage supply unit 500 only needs to output voltages of potentials V1 and V2, so that the configuration of the second reference voltage supply unit 500 can be further simplified. This allows for a more advantageous configuration in terms of the circuit area and power consumption in the photoelectric conversion device 2.

[0052] Similarly, the second reference voltage supply unit 500 may be driven according to the voltage waveform shown in Fig. 11. In Fig. 11, it is assumed that the first reference voltage supply unit 400 and the second reference voltage supply unit 500 are realized by the circuit configurations shown in Figs.

[0053] 11, the first reference voltage supply unit 400 operates in the same manner as in the first embodiment. In the second reference voltage supply unit 500, the current i2 is set so that the amount of current is the same as the current i1 of the first reference voltage supply unit 400 while the pulse p1 is High. However, when the pulse p1 goes Low and the connection with the reference signal line 301 is changed from a connected state to a disconnected state, the second reference voltage supply unit 500 changes the amount of current to id as shown in the period from time t4 to time t6 in FIG. In this way, during the period in which the second reference voltage supply unit 500 is disconnected from the reference signal line 301 and driving of the second reference voltage supply unit 500 becomes unnecessary, it is possible to reduce the power supplied to the second reference voltage supply unit 500.

[0054] Moreover, the first reference voltage supply unit 400 and the second reference voltage supply unit 500 do not necessarily have to have the same circuit configuration. For example, as shown in Fig. 12, the first reference voltage supply unit 400 may be realized by the circuit shown in Fig. 2, and the second reference voltage supply unit 500 may be realized by a circuit that operates to supply the potential Vref2 shown in Fig. 10. With such a circuit configuration, the same effect as above can be obtained.

[0055] Third embodiment 13 is a schematic diagram illustrating a semiconductor device APR according to this embodiment. The semiconductor device APR includes a semiconductor device IC, and may include a package PKG for mounting the semiconductor device IC in addition to the semiconductor device IC. In this embodiment, the semiconductor device APR is a photoelectric conversion device (imaging device) according to the first or second embodiment. The semiconductor device IC has a pixel region PX in which pixel circuits PXC are arranged in a matrix and a peripheral region PR therearound. A peripheral circuit can be provided in the peripheral region PR.

[0056] The semiconductor device APR is provided in an equipment EQP, which may include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a machine device MCHN.

[0057] The semiconductor device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and bonding members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device IC.

[0058] The equipment EQP may include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical system OPT forms an image on the semiconductor device APR. The optical system OPT is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the semiconductor device APR. The control device CTRL is, for example, a photoelectric conversion device such as an ASIC.

[0059] The processing device PRCS processes the signal output from the semiconductor device APR. The processing device PRCS is a photoelectric conversion device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device DSPL is an EL display device or a liquid crystal display device for displaying information (images) obtained by the semiconductor device APR. Place The MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device APR. The storage device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0060] The machine MCHN has a moving part or a propulsion part such as a motor or an engine. In the equipment EQP, the signal output from the semiconductor device APR is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) included in the equipment EQP. For this purpose, the equipment EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit and arithmetic circuit included in the semiconductor device APR. The machine MCHN may be controlled based on the signal output from the semiconductor device APR.

[0061] The device EQP is suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable terminals) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device MCHN in the camera can drive components of the optical system OPT for zooming, focusing, and shutter operation.

[0062] The equipment EQP may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device MCHN in the transportation equipment may be used as a moving device. The equipment EQP as transportation equipment is suitable for transporting the semiconductor device APR or for assisting and / or automating driving (piloting) by using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device MCHN as a moving device based on information obtained by the semiconductor device APR. Alternatively, the equipment EQP may be a medical device such as an endoscope, a measuring device such as a distance sensor, an analytical device such as an electron microscope, or an office machine such as a copier.

[0063] (Other embodiments) The above-described embodiment merely shows a specific example of the present invention. The scope of the present invention is not limited to the configuration of the above-described embodiment, and various embodiments can be adopted without departing from the gist of the present invention.

[0064] For example, the photoelectric conversion device may have a structure (a stacked chip structure) in which a first semiconductor chip provided with pixels and a second semiconductor chip provided with a readout circuit (peripheral circuit) are stacked. The readout circuits (peripheral circuits) in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The readout circuits (peripheral circuits) in the second semiconductor chip may be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected to each other by through-hole vias (TSVs), inter-chip wiring by direct bonding of a metal such as copper (Cu), or connection by microbumps between the chips. [Explanation of symbols]

[0065] 1, 1', 2, 2': Photoelectric conversion device 120: Vertical signal line 301: Reference signal line 302: Comparator 400: First reference voltage supply unit 500: Second reference voltage supply unit

Claims

1. A reference signal line; a processing unit that processes a potential of the reference signal line and a potential of an input signal; a first reference voltage supplying section that outputs a predetermined potential to one end of the reference signal line; a second reference voltage supplying section that outputs a predetermined potential to the other end of the reference signal line; a connection means for switching a connection between the second reference voltage supply unit and the other end of the reference signal line from a connected state to a disconnected state, or from a disconnected state to a connected state; having During at least a part of a period during which the first reference voltage supply unit outputs the predetermined potential to the one end of the reference signal line, the connection means switches the connection between the second reference voltage supply unit and the other end of the reference signal line from a connected state to a disconnected state, or from a disconnected state to a connected state. A signal processing circuit comprising:

2. A reference signal line; a processing unit that processes a potential of the reference signal line and a potential of an input signal; a first reference voltage supplying section that outputs a predetermined potential to one end of the reference signal line; a second reference voltage supplying section that outputs a predetermined potential to the other end of the reference signal line; a connection means for switching a connection between the second reference voltage supply unit and the other end of the reference signal line from a connected state to a disconnected state, or from a disconnected state to a connected state; having The first reference voltage supply unit and the second reference voltage supply unit supply the same potential to the reference signal line. A signal processing circuit comprising:

3. 3. The signal processing circuit according to claim 1, wherein the processing section is disposed so as to be sandwiched between the first reference voltage supply section and the second reference voltage supply section in a plan view of the signal processing circuit.

4. 2. The signal processing circuit according to claim 1, wherein the first reference voltage supply section and the second reference voltage supply section supply the same potential to the reference signal line.

5. each of the first reference voltage supply unit and the second reference voltage supply unit includes a current control counter, an offset control unit, a current source, and a load resistor; The current of the current source is controlled by the current control counter and the offset control unit, and a potential based on the current and the load resistance is supplied to the reference signal line.

5. The signal processing circuit according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

6. each of the first reference voltage supply unit and the second reference voltage supply unit includes a current source, an integral capacitance, and a reset unit; After the potential of the reference signal line is reset by the reset unit, a reference signal is generated by the current source and the integral capacitance.

5. The signal processing circuit according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

7. 7. The signal processing circuit according to claim 1, wherein the first reference voltage supply unit outputs a reference signal to the one end of the reference signal line during a period in which the processing unit is executing the processing.

8. 8. The signal processing circuit according to claim 7, wherein the connection means disconnects the connection between the second reference voltage supply unit and the other end of the reference signal line during a period in which the processing unit is performing the processing, and connects the connection between the second reference voltage supply unit and the other end of the reference signal line during a period in which the processing unit is not performing the processing.

9. 9. The signal processing circuit according to claim 6, further comprising a power control means for controlling a power supplied to the second reference voltage supply unit during a period in which the second reference voltage supply unit and the other end of the reference signal line are in a disconnected state by the connection means to be smaller than a power supplied to the second reference voltage supply unit during a period in which the second reference voltage supply unit and the other end of the reference signal line are in a connected state by the connection means.

10. 10. The signal processing circuit according to claim 1, wherein at least one of the first reference voltage supply unit and the second reference voltage supply unit outputs a ramp signal whose potential changes over time, and the processing unit compares the potential of the ramp signal with the potential of the input signal.

11. 11. The signal processing circuit according to claim 1, wherein the processing performed by the processing unit is a process of converting the input signal into a digital signal.

12. A photoelectric conversion unit that outputs a signal according to incident light; A signal processing circuit according to claim 1 , which processes a signal output from the photoelectric conversion unit; A photoelectric conversion device comprising:

13. The photoelectric conversion device according to claim 12 ; an optical system that forms an image on the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; Mechanical devices having moving or propelling parts; At least one of the six Equipment comprising:

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