High electron mobility transistor epitaxial method

Abstract

To provide a method for reducing the generation of defects in a high electron-mobility transistor.SOLUTION: A high electron-mobility transistor epitaxial method includes the steps of: providing a substrate; forming a nucleation layer above the substrate; forming a buffer layer above the nucleation layer; forming a first nitride layer above the buffer layer, the first nitride layer being in contact with the buffer layer; forming a second nitride layer above the first nitride layer and doping carbon in the second nitride layer, the second nitride layer being in contact with the first nitride layer; forming a channel layer above the second nitride layer; and forming a barrier layer above the channel layer, two-dimensional electron gas being formed in the channel layer along a boundary located between the channel layer and the barrier layer. A growth temperature of the second nitride layer is smaller than that of the first nitride layer, and a film thickness of the first nitride layer is smaller than that of the second nitride layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to semiconductor technology, and in particular to high electron mobility transistors. [Background technology]

[0002] A known high electron mobility transistor (HEMT) is a transistor having a two dimensional electron gas (2-DEG) adjacent to a heterojunction between two materials with different energy gaps. The high electron mobility transistor does not use a doped region as the carrier channel of the transistor, but uses a two dimensional electron gas with high electron mobility as the carrier channel of the transistor. Therefore, the high electron mobility transistor has characteristics such as a high breakdown voltage, high electron mobility, low conduction resistance, and low input capacitance, and can be widely applied to high power semiconductor devices.

[0003] However, in the commonly used high electron mobility transistor structure, since each layer has a different component material and each layer has a different thermal expansion coefficient, when the temperature changes, the different stresses between the materials cause cracks to form on the surface, warping, cracking, etc., which ultimately affects the withstand voltage of the high electron mobility transistor. Therefore, how to reduce defects such as cracks, warping, and cracking in the high electron mobility transistor structure is a problem that needs to be solved. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of this, an object of the present invention is to provide a high electron mobility transistor epitaxial method capable of reducing the occurrence of defects such as cracks, warping, and cracks in a high electron mobility transistor structure. [Means for solving the problem]

[0005] In order to achieve the above object, the present invention provides a method for epitaxially growing a high electron mobility transistor, comprising the steps of: providing a substrate; forming a nucleation layer on the substrate; forming a buffer layer on the nucleation layer; forming a first nitride layer on the buffer layer, the first nitride layer being in contact with the buffer layer; forming a second nitride layer on the first nitride layer and doping the second nitride layer with carbon, the second nitride layer being in contact with the first nitride layer; forming a channel layer above the second nitride layer; and forming a barrier layer on the channel layer, such that a two-dimensional electron gas is formed in the channel layer along a boundary between the channel layer and the barrier layer, wherein a growth temperature of the second nitride layer is lower than a growth temperature of the first nitride layer, and a thickness of the first nitride layer is smaller than a thickness of the second nitride layer. Effect of the Invention

[0006] The advantage of the present invention is that defects such as cracks, warpage and cracks in the high electron mobility transistor structure can be effectively reduced by designing the structures of the first nitride layer and the second nitride layer. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram illustrating a high electron mobility transistor epitaxial structure according to a preferred embodiment of the present invention. [Diagram 2] 2 is a flow chart illustrating a high electron mobility transistor epitaxial method according to a preferred embodiment of the present invention. [Diagram 3] 2 is a flow chart illustrating a high electron mobility transistor epitaxial method according to a preferred embodiment of the present invention. [Figure 4] FIG. 1 is a schematic diagram showing an epitaxial structure of a high electron mobility transistor according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In order to make the present invention clearer, the present invention will be described in detail below with reference to the drawings based on the preferred embodiment. As shown in FIG. 1, a high electron mobility transistor epitaxial structure 1 according to the preferred embodiment of the present invention includes a substrate 10, a nucleation layer 20, a buffer layer 30, a first nitride layer 40, a second nitride layer 50, a channel layer 60 and a barrier layer 70.

[0009] The substrate 10 may be, for example, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a sapphire (Al 2 O 3 ) substrate. The nucleation layer 20 may be, for example, an aluminum nitride (AlN) or aluminum gallium nitride (AlGaN) layer. In this embodiment, the buffer layer 30 is made of aluminum gallium nitride (AlGaN), the aluminum (Al) concentration at the surface of the buffer layer is 25±10%, and both the first nitride layer 40 and the second nitride layer 50 are gallium nitride (GaN) layers. The channel layer 60 may be, for example, an aluminum gallium nitride (AlGaN) or gallium nitride (GaN) channel layer. The barrier layer 70 may be, for example, an aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), or aluminum indium gallium nitride (AlInGaN) barrier layer.

[0010] In this embodiment, the high electron mobility transistor epitaxial structure 1 includes a passivation layer 80 and a third nitride layer 52, and the passivation layer 80 can be, for example, a silicon nitride (SiN) or gallium nitride (GaN) passivation layer. The third nitride layer 52 is a gallium nitride (GaN) layer. The second nitride layer 50, the third nitride layer 52 and the first nitride layer 40 have a V / III ratio ratio of 1:4:5. As shown in FIG. 1, the nucleation layer 20 is located above the substrate 10. The buffer layer 30 is located above the nucleation layer 20. The first nitride layer 40 is located above and in contact with the buffer layer 30. The second nitride layer 50 is located above and in contact with the first nitride layer 40. The channel layer 60 is located above the second nitride layer 50. A two-dimensional electron gas forms in the channel layer 60 along the boundary between the channel layer 60 and the barrier layer 70. The third nitride layer 52 is above and in contact with the second nitride layer 50. The third nitride layer 52 is between the second nitride layer 50 and the channel layer 60, and the channel layer 60 is above the third nitride layer 52. The passivation layer 80 is above the barrier layer 70. In other embodiments, the third nitride layer 52 is not required.

[0011] In this embodiment, the thickness of the first nitride layer 40 is smaller than the thickness of the second nitride layer 50. The ratio between the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 satisfies the range of 1 or more and 6 or less, and preferably, the ratio between the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 is 3. The sum of the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 is 1 um or less, and preferably, the sum of the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 is 0.5 um or more and 1 um or less.

[0012] In this embodiment, the second nitride layer 50 has carbon doping, the carbon concentration in the first nitride layer 40 is smaller than the carbon concentration in the second nitride layer 50, and the ratio between the carbon concentration in the second nitride layer 50 and the carbon concentration in the first nitride layer 40 is greater than or equal to 10.

[0013] In this embodiment, the third nitride layer 52 has a thickness of 2.5 to 3.5 um, includes a plurality of third nitride films, and is a superlattice layer formed by overlapping the third nitride films, and the ratio between the relatively high carbon concentration and the relatively low carbon concentration in adjacent third nitride films satisfies the range of 10 or more. In this embodiment, the third nitride layer 52 includes a low doping nitride layer 521 and a high doping nitride layer 522 as an example, but in other embodiments, the third nitride layer 52 includes one or more low doping nitride layers and one high doping nitride layer, and the low doping nitride layer and the high doping nitride layer are arranged to overlap each other in a staggered manner.

[0014] In this embodiment, the absolute value of bow (BOW) in the high electron mobility transistor epitaxial structure 1 is less than 30 um. The high electron mobility transistor epitaxial structure 1 is an 8-inch wafer. The bow is a numerical value of the wafer curvature, and positive and negative values ​​are the wafer curvature directions, with a positive value being the wafer curvature that curves upward and a negative value being the wafer curvature that curves downward. The passivation layer 80 has less than 10 defects with a diameter of more than 0.5 um per square centimeter on the surface. The defects are, for example, defects commonly found in epitaxial production, such as hexagonal defects, basal stacking faults, and hole defects, and do not include defects formed by external forces, such as dust or scratches. The high electron mobility transistor epitaxial structure 1 has a longest crack length extending inward from the outer periphery of the passivation layer 80 of 3 mm or less. For example, the crack may extend from an outer edge of the wafer into the wafer. The high electron mobility transistor epitaxial structure 1 has a breakdown voltage of 0.09 V / nm or greater. When analyzed by an X-ray diffraction method, the high electron mobility transistor epitaxial structure has a full width at half maximum (FWHM) of less than 700 arcsec in a (102) plane. The high electron mobility transistor epitaxial structure has a full width at half maximum (FWHM) of less than 600 arcsec in a (002) plane.

[0015] 3 is a flow chart showing a high electron mobility transistor epitaxial method according to a preferred embodiment of the present invention, which is used to form the above-mentioned high electron mobility transistor epitaxial structure 1. The high electron mobility transistor epitaxial method includes the following steps:

[0016] Step S02 provides a substrate 10. As described above, the substrate 10 may be a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, or a sapphire (Al 2 O 3 ) substrate.

[0017] Step S04 forms a nucleation layer on the substrate 10. The nucleation layer 20 may be formed on the substrate 10 by metalorganic chemical vapor deposition (MOCVD). The nucleation layer 20 may be, for example, an aluminum nitride (AlN) or aluminum gallium nitride (AlGaN) layer.

[0018] Step S06 forms a buffer layer 30 on the nucleation layer 20. The buffer layer may be formed on the nucleation layer 20 by metalorganic chemical vapor deposition (MOCVD). The buffer layer 30 is made of aluminum gallium nitride (AlGaN), and the surface of the buffer layer 30 has an aluminum (Al) concentration of 25±10%.

[0019] Step S08 forms a first nitride layer 40 on the buffer layer 30, where the first nitride layer 40 is in contact with the buffer layer 30. The first nitride layer 40 may be formed on the buffer layer 30 by metal-organic chemical vapor deposition (MOCVD). The first nitride layer 40 is a gallium nitride (GaN) layer.

[0020] Step S10 forms a second nitride layer 50 on the first nitride layer 40 and carbon-dopes the second nitride layer 50 so that the second nitride layer 50 contacts the first nitride layer 40. The second nitride layer 50 may be formed on the first nitride layer by metalorganic chemical vapor deposition (MOCVD). The second nitride layer 50 is a gallium nitride (GaN) layer.

[0021] The growth temperature of the second nitride layer 50 is lower than that of the first nitride layer 40. In this embodiment, the difference between the growth temperatures of the first nitride layer 40 and the second nitride layer 50 is 100 degrees Celsius or more. The V / III ratio of the second nitride layer 50 is lower than that of the first nitride layer 40. The ratio between the carbon concentration of the second nitride layer 50 and the carbon concentration of the first nitride layer 40 is 10 or more. The thickness of the first nitride layer 40 is smaller than that of the second nitride layer 50. The ratio between the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 satisfies the range of 1 or more and 6 or less, and preferably, the ratio between the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 is 3. The sum of the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 is 1 um or less, and preferably, the sum of the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 is 0.5 um or more and 1 um or less. That is, the first nitride layer 40 and the second nitride layer 50 are formed under different growth conditions such as different temperatures, V / III gas flow ratios, thicknesses, carbon doping concentrations, etc.

[0022] Step S12 forms a channel layer 60 above the second nitride layer 50, and the third nitride layer 52 contacts the second nitride layer 50 and is located between the channel layer 60 and the second nitride layer 50. The channel layer 60 may be formed on the second nitride layer 50 by metalorganic chemical vapor deposition (MOCVD). The channel layer 60 may be, for example, an aluminum gallium nitride (AlGaN) or gallium nitride (GaN) channel layer. In this embodiment, the channel layer 60 has a thickness of 100 to 500 nm.

[0023] Step S14 forms a barrier layer 70 on the channel layer 60, and a two-dimensional electron gas is formed in the channel layer 60 along the boundary between the channel layer 60 and the barrier layer 70. The barrier layer 70 may be formed on the second nitride layer 50 by metalorganic chemical vapor deposition (MOCVD). The barrier layer 70 may be, for example, an aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), or aluminum indium gallium nitride (AlInGaN) barrier layer.

[0024] In this embodiment, the high electron mobility transistor epitaxial method further includes a step S11 between the step S10 and the step S12, of forming a third nitride layer 52 on the second nitride layer 50. The third nitride layer 52 may be formed on the second nitride layer 50 by metal organic chemical vapor deposition (MOCVD). The third nitride layer 52 contacts the second nitride layer 50 and is located between the channel layer 60 and the second nitride layer 50. The third nitride layer 52 is a gallium nitride (GaN) layer. In another embodiment, as shown in FIG. 2, the step S11 may not be performed.

[0025] In this embodiment, the growth temperature of the second nitride layer 50 is lower than that of the third nitride layer 52. Preferably, the growth temperature of the second nitride layer 50 is lower than that of the first nitride layer 40 and the third nitride layer 52, and the temperature difference between the growth temperature of the second nitride layer 50 and the growth temperature of the first nitride layer 40 and the third nitride layer 52 is greater than 100 degrees Celsius. The ratio of the V / III ratio of the second nitride layer 50, the third nitride layer 52, and the first nitride layer 40 is 1:4:5. The third nitride layer 52 has a film thickness of 2.5 to 3.5 um. The third nitride layer 52 includes a plurality of third nitride films. The third nitride layer 52 is a superlattice layer formed by overlapping the third nitride films, and the ratio between the relatively high carbon concentration and the relatively high carbon concentration in two adjacent third nitride films satisfies a range of 10 or more.

[0026] In this embodiment, the high electron mobility transistor epitaxial method further includes, after step S14, step S16 of forming a passivation layer 80 on the barrier layer 70. The passivation layer 80 may be formed on the barrier layer 70 by metalorganic chemical vapor deposition (MOCVD). The barrier layer may be, for example, an aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), or aluminum indium gallium nitride (AlInGaN) barrier layer.

[0027] In this embodiment, the high electron mobility transistor epitaxial method includes inspecting the high electron mobility transistor epitaxial structure 1 formed by the high electron mobility transistor epitaxial method, and the absolute value of bow (BOW) in the high electron mobility transistor epitaxial structure 1 is less than 30 um. Wherein, the inspected high electron mobility transistor epitaxial structure 1 is an 8-inch wafer. The bow is a numerical value representing the curvature of the wafer, with positive and negative representing the direction of the wafer curvature, with a positive value representing the curvature of the wafer curvature upward and a negative value representing the curvature of the wafer curvature downward. The passivation layer 80 has less than 10 defects with a diameter greater than 0.5 um per square centimeter on the surface. The defects are, for example, defects commonly found in epitaxial production, such as hexagonal defects, basal stacking faults, and hole defects, and do not include defects formed by external forces, such as dust or scratches. The high electron mobility transistor epitaxial structure 1 has a longest crack length extending inward from the outer edge of the passivation layer 80 of 3 mm or less. For example, the crack may extend from the outer edge of an 8-inch wafer into the wafer. The high electron mobility transistor epitaxial structure 1 has a breakdown voltage of 0.09 V / nm or more. When analyzed by X-ray diffraction method, the high electron mobility transistor epitaxial structure has a full width at half maximum (FWHM) of less than 700 arcsec on the (102) plane. The high electron mobility transistor epitaxial structure has a full width at half maximum (FWHM) on the (002) plane of less than 600 arcsec.

[0028] The following describes the present invention with reference to comparative examples and examples.

[0029] Comparative Example 1 4, the high electron mobility transistor epitaxial structure 2 according to Comparative Example 1 has a structure that is almost the same as the high electron mobility transistor epitaxial structure 1 according to the above-mentioned embodiment, and similarly includes a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 60, a barrier layer 70, and a passivation layer 80. The difference is that the first nitride layer 40, the second nitride layer 50, and the third nitride layer 52 are not provided in the high electron mobility transistor epitaxial structure 2 according to Comparative Example 1.

[0030] Example 1 As shown in FIG. 1, the high electron mobility transistor structure 1 is formed by the high electron mobility transistor epitaxial method.

[0031] The growth conditions for the first nitride layer 40 are as follows: The growth temperature was 1050 degrees Celsius, and the nitrogen (N) / hydrogen (H) gas flow ratio was 1:1. The epitaxial thickness of the first nitride layer was 250 nm, and the first nitride layer was not doped with carbon. The first nitride layer had a background carbon concentration of 5E17 cm -3 Less than. The growth conditions for the second nitride layer 50 are as follows: The growth temperature was 940 degrees Celsius, the nitrogen (N) / hydrogen (H) gas flow ratio was 6:4, the epitaxial thickness of the second nitride layer was 750 nm, and the second nitride layer was doped with carbon. The second nitride layer had a carbon concentration of 5E18-5E19 cm -3 is located. The growth conditions for the third nitride layer 52 are as follows: The growth temperature is 1055 degrees Celsius, and the nitrogen (N) / hydrogen (H) gas flow ratio is 1:2. The third nitride layer 52 has a thickness of 2.5 to 3.5 um. The third nitride layer 52 includes a low-doped nitride layer 521 and a high-doped nitride layer 522. The third nitride layer 52 is a superlattice layer formed by overlapping the low-doped nitride layer 521 and the high-doped nitride layer 522. The low-doped nitride layer 521 has an epitaxial thickness of 10 to 100 nm, and the low-doped nitride layer 521 is not doped with carbon. The low-doped nitride layer 521 has a carbon concentration of 1E18 cm -3 The highly doped nitride layer 522 has an epitaxial thickness of 100 to 500 nm, and is doped with carbon. The highly doped nitride layer 522 has a carbon concentration of 5E18 to 5E19 cm -3 is located.

[0032] It should be noted again that the V / III ratios of the second nitride layer 50, the third nitride layer 52 and the first nitride layer 40 are in a proportion of 1:4:5.

[0033] Referring to Table 1 below, the results of inspection of the high electron mobility transistor epitaxial structures according to Comparative Example 1 and Example 1 are shown. As can be seen, the longest crack length, bow (BOW), full width at half maximum (FWHM) of the (102) plane, and defect density of Comparative Example 1, in which the first nitride layer 40 and the second nitride layer 50 are not provided, are all worse than those of the results of inspection of the high electron mobility transistor epitaxial structure according to Example 1. That is, by providing the first nitride layer 40 and the second nitride layer 50, Example 1 can effectively prevent cracks, bows, and defects from occurring in the high electron mobility transistor structure 1. Moreover, the epitaxial quality of the high electron mobility transistor structure can be improved.

[0034] Moreover, the first nitride layer 40, the second nitride layer 50, and the third nitride layer 52 were not provided in the high electron mobility transistor configuration 2 according to Comparative Example 1. As can be seen from Table 1, the high electron mobility transistor configuration 2 according to Comparative Example 1 is clearly worse in terms of breakdown voltage than the high electron mobility transistor configuration 1 according to Example 1. That is, in Example 1, the first nitride layer 40, the second nitride layer 50, and the third nitride layer 52 are provided, thereby making it possible to improve the breakdown voltage of the high electron mobility transistor configuration 1.

[0035] [Table 1] Several comparative examples will be described below.

[0036] It should be explained again that in this Example 1, the thickness of the channel layer 60 is 100-500 nm, the film thickness of the third nitride layer 52 is 2.5-3.5 um, the film thickness of the first nitride layer 40 accounts for 25% of the total film thickness of the first nitride layer 40 and the second nitride layer 50, and the film thickness of the second nitride layer 50 accounts for 75% of the total film thickness of the first nitride layer 40 and the second nitride layer 50. In other words, the ratio between the film thickness of the second nitride layer 50 and the film thickness of the first nitride layer 40 is 3.

[0037] [Comparative Examples 2 to 5] Comparative Examples 2 to 5 have a high electron mobility transistor configuration that is almost the same as that of Example 1. The channel layer 60 has a thickness of 100 to 500 nm, and the third nitride layer 52 has a thickness of 2.5 to 3.5 um. The differences are that the thickness of the first nitride layer according to Comparative Example 2 accounts for 0% of the total thickness of the first nitride layer and the second nitride layer, and the thickness of the second nitride layer according to Comparative Example 2 accounts for 100% of the total thickness of the first nitride layer and the second nitride layer. The thickness of the first nitride layer according to Comparative Example 3 accounts for 50% of the total thickness of the first nitride layer and the second nitride layer. The thickness of the second nitride layer according to Comparative Example 3 accounts for 50% of the total thickness of the first nitride layer and the second nitride layer. The thickness of the first nitride layer according to Comparative Example 4 accounts for 75% of the total thickness of the first nitride layer and the second nitride layer. The thickness of the second nitride layer in Comparative Example 4 accounts for 25% of the total thickness of the first nitride layer and the second nitride layer. The thickness of the first nitride layer in Comparative Example 5 accounts for 100% of the total thickness of the first nitride layer and the second nitride layer. The thickness of the second nitride layer in Comparative Example 5 accounts for 0% of the total thickness of the first nitride layer and the second nitride layer.

[0038] Referring to Table 2 below, the results of measuring the high electron mobility transistor epitaxial structures according to Example 1 and Comparative Examples 2 to 5 are as follows. As can be seen from the table below, the high electron mobility transistor epitaxial structure according to Example 1 has a good withstand voltage and a relatively low defect density compared to the high electron mobility transistor epitaxial structures according to Comparative Examples 2 to 5. Therefore, when the ratio between the thickness of the second nitride layer 50 and the thickness of the first nitride layer 40 is 3, the high electron mobility transistor epitaxial structure 1 has a good withstand voltage and a relatively low defect density.

[0039] [Table 2]

[0040] In summary, the effect of the present invention is that by designing the configurations of the first nitride layer 40 and the second nitride layer 50, the occurrence of defects such as cracks, warping, and cracks in the high electron mobility transistor structure 1 can be effectively reduced, and by providing the first nitride layer 40, the second nitride layer 50, and the third nitride layer 52, the withstand voltage of the high electron mobility transistor epitaxial structure 1 can be increased.

[0041] The above are merely preferred embodiments of the present invention, and any equivalent replacement based on the specification and scope of the present invention is obviously within the scope of the patent of the present invention. [Explanation of symbols]

[0042] 1, 2 High electron mobility transistor epitaxial structure 10 Substrate 20 Nucleation layer 30 Buffer Layer 40 First nitride layer 50 Second nitride layer 52 Third nitride layer 521 Low doping nitride layer 522 Highly doped nitride layer 60 Channel Layer 70 Barrier Layer 80 Passivation Layer S02, S04, S06, S08, S10, S11, S12, S14, S16 steps

Claims

1. A high electron mobility transistor epitaxial method for forming a high electron mobility transistor epitaxial structure, comprising: Providing a substrate; forming a nucleation layer on the substrate; forming a buffer layer on the nucleation layer; forming a first nitride layer on the buffer layer in contact with the buffer layer; forming a second nitride layer on the first nitride layer in contact with the first nitride layer and doping the second nitride layer with carbon; forming a channel layer above the second nitride layer; and forming a barrier layer on the channel layer, and a two-dimensional electron gas being formed in the channel layer along an interface between the channel layer and the barrier layer; a growth temperature of the second nitride layer is lower than a growth temperature of the first nitride layer, and a thickness of the first nitride layer is smaller than a thickness of the second nitride layer; a first nitride layer formed on the first nitride layer and a second nitride layer formed on the second nitride layer;

2. 2. The high electron mobility transistor epitaxial method according to claim 1, wherein the difference between the growth temperatures of the first nitride layer and the second nitride layer is 100 degrees Celsius or more.

3. 2. The high electron mobility transistor epitaxial method of claim 1, wherein the V / III ratio of the second nitride layer is less than the V / III ratio of the first nitride layer.

4. 2. The high electron mobility transistor epitaxial method according to claim 1, wherein a ratio of a carbon concentration in the second nitride layer to a carbon concentration in the first nitride layer is 10 or more.

5. 2. The high electron mobility transistor epitaxial method according to claim 1, wherein a ratio of a thickness of the second nitride layer to a thickness of the first nitride layer is greater than 1 and is not greater than 6.

6. forming a third nitride layer on the second nitride layer, the third nitride layer in contact with the second nitride layer; the third nitride layer is located between the channel layer and the second nitride layer; 2. The high electron mobility transistor epitaxial method of claim 1, wherein a growth temperature of the second nitride layer is lower than a growth temperature of the third nitride layer.

7. 7. The high electron mobility transistor epitaxial method of claim 6, wherein the ratio of V / III gas flow ratios during formation of the second nitride layer, the third nitride layer and the first nitride layer is 1:4:

5.

8. 7. The high electron mobility transistor epitaxial method of claim 6, wherein the first nitride layer, the second nitride layer, and the third nitride layer comprise gallium nitride.

9. 7. The high electron mobility transistor epitaxial method according to claim 6, wherein the third nitride layer has a thickness of 2.5 to 3.5 um.

10. 10. The high electron mobility transistor epitaxial method of claim 9, wherein the third nitride layer includes a plurality of third nitride films, the third nitride films being stacked on top of each other, and the ratio of the relatively high carbon concentration to the relatively low carbon concentration in two adjacent third nitride films is in a range of 10 or more.

11. 2. The high electron mobility transistor epitaxial method of claim 1, further comprising forming a passivation layer on the barrier layer.

12. 9. The high electron mobility transistor epitaxial method of claim 8, wherein the absolute value of bow (BOW) in the high electron mobility transistor epitaxial structure is less than 30 um.

13. 12. The high electron mobility transistor epitaxial method of claim 11, wherein the full width at half maximum (FWHM) of a (102) plane in the high electron mobility transistor epitaxial structure is less than 700 arcsec.

14. 12. The high electron mobility transistor epitaxial method of claim 11, wherein the full width at half maximum (FWHM) of a (002) plane in the high electron mobility transistor epitaxial structure is less than 600 arcsec.

15. 12. The high electron mobility transistor epitaxial method of claim 11, wherein the number of defects greater than 0.5 um in diameter per square centimeter on the surface of the passivation layer is less than 10.

16. 12. The high electron mobility transistor epitaxial method of claim 11, wherein the longest crack length extending inward from the outer periphery of the passivation layer is 3 mm or less.

17. 12. The high electron mobility transistor epitaxial method of claim 11, wherein the breakdown voltage of the high electron mobility transistor epitaxial structure is 0.09 V / nm or greater.

18. 2. The high electron mobility transistor epitaxial method according to claim 1, wherein the buffer layer is made of AlGaN and has an Al concentration of 25±10% at a surface of the buffer layer.

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