Semiconductor device and module

Abstract

To provide a semiconductor device capable of reducing generation of noise even when a plurality of semiconductor devices are connected in parallel and used simultaneously, with a simple structure.SOLUTION: A semiconductor device includes: a plurality of transistor cells 18 formed in an SiC epitaxial layer 28; a gate pad 4 for electrical connection for controlling the plurality of transistor cells; a pad peripheral unit 12 formed around the gate pad so as to continuously surround the gate pad; a built-in resistor 21 composed of polysilicon, partially arranged below the gate pad and electrically connecting the gate pad and the pad peripheral unit; and a plurality of source pads 6 for electrical connection. The gate pad is physically separated from the pad periphery unit in the same layer so that space is formed between the gate pad and the pad peripheral unit, and is formed around an edge portion of the epitaxial layer. A connection portion to which a connection member is connected is selectively formed on a surface of the gate pad.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. and modules that have multiple Regarding. [Background technology]

[0002] Patent Document 1 discloses a gate pad, a gate connection wiring made of polysilicon, and a gate connection A semiconductor device including a gate metal wiring formed on the wiring and integrally continuing with the gate pad. When a voltage is applied to the gate pad, the gate metal wiring and the gate interconnect wiring Power is supplied via lines to MOSFETs formed in the active region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-238885 A Summary of the Invention [Problem to be solved by the invention]

[0004] In practice, modules are used that have multiple semiconductor devices (chips) connected in parallel. The module may include a single chip with a single, electrically connected gate. A gate terminal is provided. By applying a control voltage to the gate terminal, each built-in chip A voltage is simultaneously applied to the gates of the two transistors to perform a switching operation.

[0005] However, such modules have the problem that they tend to generate noise when turned on. This is because there is variation between multiple chips in terms of gate resistance, and This is because the current is concentrated in the chip with a relatively low gate resistance. The variation in resistance is due to the variation in processing accuracy (etching dimensions, etc.) when manufacturing the chip. Since this phenomenon arises as a result of the

[0006] On the other hand, an external gate resistor with a resistance value larger than that of the gate resistor in each chip is Although it would be possible to provide a separate module for each chip, this would complicate the module structure and make assembly difficult. This gives rise to another problem.

[0007] Therefore, an object of the present invention is to provide a semiconductor device having a simple structure, which can reduce noise generation even when a plurality of semiconductor devices are connected in parallel and used simultaneously. and modules that have multiple The purpose of this project is to provide [Means for solving the problem]

[0008] One embodiment of the present invention includes a semiconductor layer, a plurality of cells formed in the semiconductor layer, A control pad for electrical connection to control the plurality of cells, and a connecting member for connecting the control pads A pad peripheral portion is formed around the control pad so as to surround the control pad. A built-in resistor made of polysilicon partially disposed on the control pad and the The device is provided with a built-in resistor that electrically connects to the pad periphery and a plurality of source pads for electrical connection. The control pad is arranged so that a space is formed between the control pad and the peripheral portion of the pad. The pad is physically separated from the pad periphery in the same layer, and the control pad is A connection portion formed around the edge of the semiconductor layer and to which a connection member is connected is The built-in resistor is selectively formed on the surface of the pad, and the built-in resistor is located at the connection portion in a plan view. To provide a semiconductor device in which a semiconductor device is selectively arranged in a region avoiding a defect.

[0009] In one embodiment of the present invention, the connection portion is formed such that, in a plan view, it is half of the surface area of ​​the control pad. It accounts for more than a minute.

[0010] In one embodiment of the present invention, the semiconductor device further includes a gate finger extending from the periphery of the pad. can.

[0011] In one embodiment of the present invention, the gate fingers are arranged in three directions from the periphery of the pad. Extend.

[0012] In one embodiment of the present invention, the gate fingers extend to the four corners of the semiconductor device. The part has

[0013] In one embodiment of the present invention, the width of the gate finger is narrower than the width of the built-in resistor. stomach.

[0014] In one embodiment of the present invention, the built-in resistor has a rectangular shape in a plan view.

[0015] In one embodiment of the present invention, the control pad is made of a material including aluminum. There are.

[0016] In one embodiment of the present invention, the peripheral portion of the pad is made of a material containing aluminum. is.

[0017] In one embodiment of the present invention, each of the source pads is made of a material including aluminum. It is composed of:

[0018] In one embodiment of the present invention, the semiconductor device has a rectangular shape in a plan view, The control pad is provided near the center of one side of the semiconductor device in a plan view.

[0019] In one embodiment of the present invention, the pad periphery has the same thickness as the control pad.

[0020] In one embodiment of the present invention, the built-in resistor is partially disposed in the region below the control pad. An interlayer film is selectively disposed between the built-in resistor and the control pad.

[0021] In one embodiment of the present invention, the connection portion is formed in a central portion of the control pad. do.

[0022] The above and other objects, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: These will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG. [Diagram 3] 3a and 3b are enlarged views of the area surrounded by the dashed double-dashed line III in FIG. 2, with FIG. 3a showing a plan view and FIG. 3b showing a cross-sectional view of the semiconductor device taken along the line IIIb-IIIb in FIG. 3a. [Figure 4] FIG. 4 is a diagram showing a modified example of the cell structure. [Diagram 5] FIG. 5 is an electric circuit diagram showing an electric circuit of a module to which a semiconductor device according to one embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present invention. For the sake of clarity, the semiconductor device 1 is not exposed on its outermost surface in an actual plan view. The part is shown by a solid line.

[0026] The semiconductor device 1 is a semiconductor device using SiC, and the top surface of the semiconductor device is, for example, When viewed from the line direction (hereinafter simply referred to as "planar view"), the chip is in the shape of a square. has been formed.

[0027] The semiconductor device 1 includes an active region 2 and a termination region 3 surrounding the active region 2. In this embodiment, the active region 2 is located in the inner region of the semiconductor device 1. The active area is generally formed in a substantially rectangular shape in plan view, but the shape is not particularly limited. Between the region 2 and the termination region 3, a guard ring (see FIG. (not shown) may be formed.

[0028] In the active region 2, a gate metal 44 as an example of a control pad of the present invention, a source Metal 43 and a gate finger 5 as an example of the finger of the present invention are formed. A passivation film 40 is formed on the top surface of the semiconductor device 1 so as to cover these. The passivation film 40 includes a part of the gate metal 44 and the source Parts of the metal 43 are exposed as the gate pad 4 and the source pad 6, respectively. On the other hand, the gate finger 5 is entirely made of a passivation material. The semiconductor device is covered with a film 40 .

[0029] The gate metal 44, the gate finger 5 and the source metal 43 are, for example, Al( The wiring is made of metal such as aluminum, AlCu (aluminum-copper alloy), and Cu (copper). do.

[0030] By constructing the gate finger 5 with metal wiring that has a lower resistance than polysilicon, , the transistor cell 18 (FIG. 2) in a short time. Since the processability is good (easy to process), the process of forming these wirings can be simplified. On the other hand, AlCu can reduce the power consumption of the semiconductor device 1 compared to when Al is used. The resistance to cracking can be improved, and the bonding wire can be connected to the gate pad 4. When Cu is used, the bonding strength of Al and AlCu can be improved. This has the advantage that the resistivity can be reduced compared to the case where the

[0031] The gate metal 44 is formed in a part of the periphery of the active region 2 (near the boundary with the termination region 3). The gate finger 5 is selectively formed from the gate pad 4 to the active The direction is divided into a direction along the periphery of the active area 2 and a direction toward the inside of the active area 2. As a result, in the active region 2, different layers are formed with the gate metal 44 interposed therebetween. A portion defined by a plurality of gate fingers 5 extending in a direction perpendicular to the surface of the gate electrode 1 and a portion of the gate fingers 5 In the outer region, cell regions 7 and 45 are formed.

[0032] More specifically, in this embodiment, the gate metal 44 is formed in a rectangular shape in plan view. , which is selectively disposed in the center of one side 8 of the active area 2. The other side of the gate metal 44 is the side 9 opposite the side 8. The edges 10 and 11 are continuous with both ends of the edges 8 and 9, respectively.

[0033] The gate fingers 5 are spaced apart from each other and surround the gate metal 44. a portion 12, a direction from the pad peripheral portion 12 along the side 8 of the active region 2, and A first finger 13 and a second finger each extending in a direction perpendicular to the side 8 Includes 14 and 15.

[0034] The pad peripheral portion 12 is formed in a rectangular ring shape in a plan view along the periphery of the gate metal 44. .

[0035] The first finger 13 is oriented toward the side 10 and the opposite side 11 with respect to the pad peripheral portion 12. A pair of these is formed along side 8 in this direction.

[0036] The second finger 14 has an active area extending to the side 9 in a direction perpendicular to the first finger 13. 2, and a linear main portion 15 that crosses the main portion 15 and is integrally connected to the main portion 15. and a plurality of branches 16 extending along the first finger 13 from the first finger 13. The branches 16 are In this embodiment, the main portion 15 is connected to two points, the tip portion and the middle portion of the main portion 15, to form a total of two pairs. However, there is no particular limit to this number.

[0037] Thus, in the active area 2, a first finger 13 and a second finger 14 (main The cell regions 7, 45 are defined by the portion 15 and the branch portion 16. one at each corner of the intersection formed by the main portion 15 and the central branch 16 of the second finger 14. In addition, the periphery of the active area 2 and the gate electrode 1 are formed in a total of four inner cell areas 7. Between the center finger 5 and the center finger 6, an annular outer cell region 45 is formed along the periphery of the active area 2. is formed.

[0038] The source metal 43 is formed so as to cover substantially the entire inner and outer cell regions 7, 45. The passivation film 40 has a source pad 6 for each inner cell region 7. A total of four openings 42 are formed so that the openings 42 are arranged in a circular pattern.

[0039] In addition, the source metal 43 has a recess 17 formed therein in accordance with the shape of the gate metal 44. The recess 17 is formed by forming the gate metal 44 on the first finger 13 in the active region 2. The gate metal 44 is set back on the inner side and is shaped to avoid this. It is a depression that has been created.

[0040] FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG. 2 is an enlarged view of the base pad 4 and its surrounding area. Therefore, some of the elements that are not exposed on the top surface of the semiconductor device 1 in an actual plan view are shown by solid lines. There are.

[0041] As shown in FIG. 2, the gate finger 5 (pad peripheral portion 12, first finger 13 and The inner and outer cell regions 7, 45 defined by the first finger 14) are provided with a plurality of transistors. Transistor cells 18 are arranged.

[0042] The plurality of transistor cells 18 are arranged in this embodiment in inner and outer cell regions 7, 45. In each of the gate electrodes, the gate electrodes are arranged in a matrix in plan view. The plurality of transistor cells 18 are aligned in accordance with the shape of the gate finger 5 . For example, the plurality of transistor cells 18 are bent to fit the shape of the corners of the pad peripheral portion 12. The second finger 14 is bent and aligned to match the shape of the main portion 15 of the second finger 14, which is linear. The source metal 43 is formed so as to cover the plurality of transistor cells 18. It is being done.

[0043] In FIG. 2, for clarity, a plurality of transistor cells are shown covered with source metal 43. The transistor cells 18 are arranged in a matrix. However, the shape may be, for example, a stripe shape, a staggered shape, or the like. The planar shape of the filter 18 is not limited to a quadrangle, but may be, for example, a circle, a triangle, a hexagon, or the like. It is also possible.

[0044] Between the adjacent transistor cells 18, a gate electrode as an example of a control electrode of the present invention is provided. The gate electrode 19 is formed in the inner and outer cell regions 7 and 45. The transistor cells 18 are arranged between each other in a matrix, and are generally shaped like a lattice in a plan view. On the other hand, the gate electrode 19 is formed not only in the inner and outer cell regions 7 and 45 but also in the The gate electrode 1 is also formed in the area where the gate finger 5 is arranged. This portion is in contact with the gate finger 5.

[0045] In this embodiment, a portion of the gate electrode 19 is formed between the first finger 13 and the second finger 14. The first finger 13 and the second finger 14 are formed in a lower region of the contact portion. 2, for clarity, the shape of the lower region of the gate electrode 19 is not shown. The hatched areas show the areas where the two adjacent The gate electrode 19 in the side cell region 7 is a gate electrode 19 that crosses the second finger 14 below. The continuous form of the gate electrode 19 is such that the inner part adjacent to the gate metal 44 is The same is true between the side cell region 7 and the outer cell region 45. The gate electrode 19 is continuous with the gate electrode 19 that crosses the first finger 13 below. There are.

[0046] The first finger 13 and the second finger 14 are respectively provided with A gate contact 20 is connected to the gate electrode 19. The port contacts 20 are spaced from each side edge of the first finger 13 and the second finger 14. In the center of each finger, the gap is formed linearly along the longitudinal direction. do.

[0047] In this embodiment, a plurality of built-in resistors 21 are disposed below the gate metal 44. The multiple built-in resistors 21 are arranged at approximately equal intervals from the center of gravity of the planar shape of the gate metal 44. By arranging the built-in resistors 21 at positions of distance, the arrangement of the built-in resistors 21 is made symmetrical. In this embodiment, the plurality of built-in resistors 21 are preferably formed of gate metal having a rectangular shape in a plan view. The gate metal 44 is disposed at each corner of the gate metal 44 at an equal distance from the center of gravity G of the gate metal 44. This provides symmetry to the four built-in resistors 21.

[0048] There are various possible patterns of symmetry. For example, the two built-in resistors 21 are arranged in a symmetrical manner. They may be disposed at two corners of the gate metal 44 in a corner relationship, or may be disposed at opposite sides. The gate metal 44 is disposed on each of the two sides of the gate metal 44 so as to face each other. For example, when the gate metal 44 has a circular shape in a plan view, two built-in resistors 21 may be disposed at both ends of the diameter of the gate metal 44, or When the metal 44 has a triangular shape in a plan view, the three built-in resistors 21 are arranged in such a manner that the gate metal 44 One may be disposed at each of the three corners.

[0049] Each built-in resistor 21 is formed by a gate metal 44 and a gate finger 5 (pad peripheral portion 12). The annular gap region 26 between the two is crossed and formed to span the gap region. The built-in resistor 21 faces both the gate metal 44 and the gate finger 5. The gate metal 44 and the gate finger 5 (pad peripheral portion 12) are A via hole as an example of the contact via of the present invention is formed on the built-in resistor 21 arranged in the lower region. The electrodes are connected by a head side contact 22 and a cell side contact 23 .

[0050] In this embodiment, the four built-in resistors 21 are formed by connecting two gate metals 44 that are in a pair. From below each peripheral edge 24 of the side, extending in an outward direction perpendicular to the side, below the pad peripheral portion 12 Each built-in resistor 21 is formed in a rectangular shape in a plan view. The size is less than 0μm square (less than 200μm × 200μm). If the size of each of the 21 is 200 μm or less, the SiC epitaxial layer 28 (FIG. 3b) The area of ​​the region sacrificed for the built-in resistor 21 can be reduced, and It is possible to save space.

[0051] The pad side contact 22 and the cell side contact 23 are gate metal The grooves 44 and 46 are formed in parallel straight lines along the sides of the pad peripheral portion 12 .

[0052] The built-in resistor 21 is disposed below the peripheral portion 24 avoiding the central portion of the gate metal 44, and In addition, the region above the region where the built-in resistor 21 is disposed is covered with a passivation film 40. Therefore, in the center of the gate metal 44, the wire region of the present invention surrounded by the built-in resistor 21 is formed. The gate pad 4 is secured as a gate electrode. The gate pad 4 is connected to a bonding wire. This is an area that continues to be explored.

[0053] That is, in this embodiment, each corner of the gate metal 44 where the built-in resistor 21 is arranged The gate metal 44 is selectively covered with a passivation film 40, and the other portions of the gate metal 44 are exposed through an opening 41. As a result, the top surface of the semiconductor device 1 has a flat surface with each corner recessed inward. The gate pad 4, which is rectangular in plan view, is exposed. In this manner, the built-in resistor 21 is arranged. By covering the upper region with a passivation film 40, the connection of the bonding wires is prevented. When the gate metal 44 is connected to the built-in resistor 21, the bonding wire is mistakenly attached to the part of the gate metal 44 that overlaps the built-in resistor 21. As a result, when bonding wires are bonded, ultrasonic waves or the like can be prevented from being applied. The built-in resistor 21 may be damaged or destroyed by the impact of the can be suppressed.

[0054] 3a and 3b are enlarged views of the area surrounded by the two-dot chain line III in FIG. 2. 3b is a plan view of the semiconductor device 1 taken along line IIIb-IIIb in FIG. 3a. 3a and 3b, the cross-sectional views are shown. Note that in FIG. 3a and FIG. 3b, the scale of each component is not the same as that in FIG. 2, and the scale of each component may differ between FIG. 3a and FIG. 3b. In addition, in order to clarify the above, in FIG. 3a and FIG. 3b, the semiconductor device is not actually shown in a plan view. Some of the elements not exposed on the top surface of device 1 are shown by solid lines.

[0055] Next, a more detailed configuration of the built-in resistor 21 and its surrounding area will be described with reference to the cross-sectional structure of the semiconductor device 1. will be explained together.

[0056] The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The epitaxial layer 28 is laminated on the SiC substrate 27, and this laminate structure is the Si C semiconductor layer.

[0057] The SiC substrate 27 and the SiC epitaxial layer 28 are each + Type and n - Type It is SiC. + The impurity concentration of the SiC substrate 27 is, for example, 1×10 17 cm -3 ~1×10 21 cm -3 On the other hand, n - Impurities in the SiC epitaxial layer 28 The concentration of the substance is, for example, 1×10 14 cm -3 ~1×10 17 cm -3 In addition, n-type As the impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used (hereinafter Same below).

[0058] In the inner cell region 7, a plurality of transistors are formed on the surface of the SiC epitaxial layer 28. The transistor cells 18 are formed in a plurality of transistor cells, each of which is a p - A mold body region 29; p - The n-type body region 29 is selectively formed in an inner region spaced from the periphery thereof. + Type saw area 30 and n +The source region 30 is selectively formed in an inner region spaced from the periphery thereof. Retard p + The n-type body contact region 31 of the SiC epitaxial layer 28 is also included. - The mold portion serves as a common drain region for multiple transistor cells 18 .

[0059] As shown in FIG. 3a, in a plan view, the track along the pad periphery 12 (gate finger 5) Except for transistor cell 18, p + The n-type body contact region 31 is surrounded by + Type A source region 30 is formed, and further, + The p - Type body The region 29 is formed. - In the type body region 29, n + The source region 30 The surrounding annular region is a channel region 32 in which a channel is formed when the semiconductor device 1 is turned on. Although not shown in FIGS. 3a and 3b, the multiple transistors in the outer cell region 45 The starter cell 18 has a similar structure.

[0060] On the other hand, in the transistor cells 18 along the pad periphery 12 (gate finger 5), p - Type body region 29 and p + The body contact regions 31 are p - Type region 34 and p + It is electrically connected to the mold region 33 .

[0061] p - The impurity concentration of the mold body region 29 is, for example, 1×10 14 cm -3 ~1×10 1 9 cm -3 and n+ The impurity concentration of the source region 30 is, for example, 1×10 17 cm -3 ~1×10 21 cm -3 and p + The impurity concentration of the body contact region 31 is For example, 1×10 19 cm -3 ~1×10 21 cm -3 It is.

[0062] To form these regions 29 to 31, for example, the surface of the SiC epitaxial layer 28 is The surface is doped with p by ion implantation. - The p body region 29 is then formed. - Mold body By sequentially implanting n-type impurities and p-type impurities into the surface portion of region 29, n + type source region 30 and p + A mold body contact region 31 is formed. The transistor cell 18 is formed by the regions 29 to 31. For example, B (boron), Al (aluminum), etc. can be used (the same applies below).

[0063] In the active area 2, the area other than the inner and outer cell areas 7 and 45, specifically, In the area below the gate metal 44, the gate finger 5 and the gap region 26, a SiC epitaxial layer is formed. The surface of the taxial layer 28 is p - A mold region 34 is formed. - Surface portion of mold area 34 p + A mold area 33 is formed.

[0064] p + The mold region 33 is a region of the SiC epitaxial layer 28 facing the built-in resistor 21. te,p - Type region 34 p- The mold part is selectively exposed on the SiC surface, and the other areas are In this case, please use your own p + The gate metal 44 etc. are formed so that the mold part is selectively exposed on the SiC surface. That is, the gate metal 44 and the gate The finger 5 has a p - It faces the mold part , and in most other areas, p + It faces the mold part. + mold area 3 3 and p - The mold regions 34 are formed so as to extend below the source metal 43. Under the source metal 43 (in this embodiment, the portion outside the source pad 6), In that respect, p + The body contact region 31 and the p - Integral connection to mold body region 29 In FIG. 3a, the transistors along the pad periphery 12 (gate finger 5) are Dystacel 18 p + Type body contact region 31 and p + The mold area 33 is hatched. In practice, p + The body contact region 31 is a source metal 43 This causes p + The type region 33 is stable at 0V. Therefore, as in this embodiment, most of the gate metal 44 and the gate fingers 5 are p + It is preferable to have it facing the mold area 33 .

[0065] p + Type region 33 and p - The type regions 34 are each + Mold body contact area 31 and p -It is formed in the same process as the mold body region 29, and has the same impurity concentration and depth. It is.

[0066] A gate insulating film, which is an example of an insulating film of the present invention, is formed on the surface of the SiC epitaxial layer 28. The gate insulating film 35 is made of an insulating material such as silicon oxide. For example, the gate insulating film 35 has a thickness of 0.001 μm to 1 μm. 9 and the built-in resistor 21 from the SiC epitaxial layer 28. be.

[0067] A gate electrode 19 and a built-in resistor 21 are formed on the gate insulating film 35. The gate electrode 19 is disposed in the channel region 32 of each transistor cell 18 with a gate insulating film 35 sandwiched therebetween. On the other hand, the built-in resistor 21 is formed so as to face each other at p - Exposure p of mold region 34 - Type The gate insulating film 35 is formed in each of the first and second electrodes 31 and 32 so as to face each other.

[0068] The gate electrode 19 and the built-in resistor 21 are both made of p-type polysilicon. In this embodiment, the gate electrode 19 and the built-in resistor 21 may be formed in a process. It contains B (boron) as a type impurity. B (boron)-containing polysilicon is a type of It has a high resistivity against phosphorus (P)-containing polysilicon, which is commonly used in biomedical devices. Therefore, even if the boron-containing polysilicon (built-in resistor 21) achieves the same resistance value, Therefore, the SiC epitaxial layer 2 requires a smaller area than phosphorus-containing polysilicon. Since the area occupied by the built-in resistor 21 on the substrate 8 can be reduced, the space can be effectively utilized. This can be done.

[0069] The concentration of p-type impurities contained in the polysilicon is The concentration can be appropriately changed according to the design resistance value of each resistor. The sheet resistance of the built-in resistor 21 is set to be 10 Ω / □ or more. If the sheet resistance of the resistor 21 is 10 Ω / □ or more, the area of ​​the resistor 21 does not need to be increased. The resistance value of the entire resistor 21 can be easily made larger than the variation in resistance value among the plurality of semiconductor devices 1. For example, when the variation in resistance value is 0.1Ω to 20Ω, With a small area, the resistance value of the built-in resistor 21 can be set to 2Ω to 40Ω. The area of ​​the region on the epitaxial layer 28 that is sacrificed for the built-in resistor 21 is reduced. This reduces the impact on the layout of other elements. The total resistance value of the resistance of the contact electrode 19 and the resistance value of the built-in resistor 21 is 4 Ω to 50 Ω. It is preferable that

[0070] Moreover, the thickness of the gate electrode 19 and the built-in resistor 21 is preferably 2 μm or less. By making the thickness of the built-in resistor 21 2 μm or less, the resistance value of the entire built-in resistor 21 can be reduced to It is possible to easily make the resistance larger than the variation in resistance value between the plurality of semiconductor devices 1. If the built-in resistor 21 is too thick, the resistance value becomes too low, which is not preferable.

[0071] An interlayer film 3 is formed on the gate insulating film 35 so as to cover the gate electrode 19 and the built-in resistor 21. The interlayer film 36 is made of an insulating material such as silicon oxide. It has a thickness of .1μm to 5μm.

[0072] The interlayer film 36 is formed on the gate insulating film 35 so as to cover the gate electrode 19 and the built-in resistor 19 . The resistor 21 is formed so as to penetrate into the region (first region) where the resistor 21 is not arranged. In the region where the built-in resistor 21 is not arranged, the SiC epitaxial layer 28 and the gate Since the distance between the metal 44 and the insulating film (thickness T) can be increased, the capacitance between them can be reduced. It is possible.

[0073] The pad side contact 22 and the cell side contact 2 are formed so as to penetrate the interlayer film 36. The pad side contact 22 and the cell side contact 23 are respectively formed. , which is formed integrally with the gate metal 44 and the gate finger 5 (pad peripheral portion 12). The metal vias are

[0074] The interlayer film 36 contains n + type source region 31 and p + Mold body contact area 31 A source contact 46 for making contact with the source metal 43 penetrates through the The source contact 46 is a metal that is integrally formed with the source metal 43. Made of Rubia.

[0075] On the interlayer film 36, a gate metal 44, a gate finger 5, and a source metal 43 are provided. , are formed at intervals from each other.

[0076] Then, the gate metal 44, the gate finger 5 and the source metal 43 are covered with A passivation film 40 is formed on the interlayer film 36. In the semiconductor device, openings 41 and 42 are formed to expose a part of the gate metal 44 and the source metal 43. It has been done.

[0077] As described above, according to the semiconductor device 1, as shown in FIGS. 3a and 3b, A polysilicon resistor (built-in resistor) is provided between the gate finger 5 (pad peripheral portion 12) and the gate finger 44. 21) is interposed. In other words, the current path leading from the outside to the multiple transistor cells 18 An internal resistor 21 is interposed in the middle.

[0078] By adjusting the resistance value of the built-in resistor 21, the resistance value of the gate electrode 19 and the internal The resistance value of the built-in resistor 21 is the sum of the resistance values ​​of the built-in resistor 21 (gate resistance). Therefore, the resistance of the gate electrode 19 can be varied. Even when the semiconductor devices 1 are connected in parallel, the resistance value of the built-in resistor 21 can be adjusted to the desired value without causing any variation. By setting the resistance of the gate electrode 19 to be larger than the resistance of the gate electrode 19, the semiconductor device has a relatively low resistance. This limits the current flow to 1. As a result, noise generation during use is reduced. It is possible to reduce the damage caused by the

[0079] Moreover, the polysilicon constituting the built-in resistor 21 can be easily modified by implanting impurities, etc. It is a material whose values ​​can be controlled, and its processing can be performed using conventional semiconductor manufacturing techniques. Therefore, when the built-in resistor 21 is introduced, the semiconductor device 1 itself and This also makes it possible to avoid a module having a complicated structure.

[0080] The built-in resistor 21, like the gate electrode 19, is also formed during the manufacture of the semiconductor device 1. The size and thickness vary depending on the processing accuracy (etching dimensions, etc.) of the However, the processing dimensions are smaller than those of the gate electrode 19. Resistor 21 variations rarely cause noise.

[0081] In addition, since the built-in resistor 21 is connected to the gate metal 44 below the gate metal 44, Therefore, the gate current flows at the entrance of the current path leading from the outside to the multiple transistor cells 18. This allows the inrush current to be limited to only a specific transistor cell 18. It is possible to prevent the flow of

[0082] For example, in FIG. 2, the built-in resistor 21 is connected to the first finger 13 of the gate finger 5 or A bypass is formed in the middle of the second finger 14 as a detour between the fingers 13 and 14. In this case, on the side closer to the gate metal 44 than the built-in resistor 21, , through the gate contact 20 from the fingers 13 and 14 before reaching the built-in resistor 21. In this case, an inrush current may flow to the gate electrode 19. If the gate current can be limited at the entrance of the current path, the This can reduce the variation in switching speed.

[0083] Furthermore, as shown in FIG. 2, the built-in resistors 21 are arranged symmetrically. This also reduces the variation in switching speed among the multiple transistor cells 18. It is possible.

[0084] As shown in FIG. 3a and FIG. 3b, in the SiC epitaxial layer 28, The area facing resistor 21 is 1×10 19 cm -3 p with impurity concentration of - type area Therefore, the dielectric breakdown of the gate insulating film 35 can be effectively suppressed. Furthermore, p - Since it is more difficult for carriers to accumulate in the n-type region than in the n-type region, the gate insulating film 35 is The internal resistors 21 and p - It is also possible to reduce the capacitance between the mold region 34. do.

[0085] As shown in FIG. 3a and FIG. 3b, the gate metal 44 and the built-in resistor 21 are The pad side contact 22 is made of a via. The position of the via 22 is changed along the surface of the SiC epitaxial layer 28, and the diameter of the via is changed. In the current path leading from the outside to the multiple transistor cells 18, The resistance contributed by resistor 21 can be easily adjusted.

[0086] For example, the pad side contact 37 shown in dashed lines in FIG. 22, the contact position for the built-in resistor 21 can be easily The distance from the pad periphery 12 to the pad periphery 12 can be easily shortened from D1 to D2. As a result, the resistance value of the built-in resistor 21 can be reduced. If the resistance value of the built-in resistor 21 is increased, the resistance value of the built-in resistor 21 can be increased. The via diameter of the pad side contact 38 is smaller than that of the pad side contact 22. By doing so, the resistance value of the current path toward the built-in resistor 21 can be increased. By increasing the resistance of the path, the resistance value of the path can be reduced.

[0087] Moreover, these processes are performed when forming the pad side contact 22 (via), and It is only necessary to use a mask that matches the via diameter design, which prevents the manufacturing process from becoming complicated. You can also stop it.

[0088] Although the embodiment of the present invention has been described above, the present invention may be embodied in other forms. It is also possible.

[0089] For example, in the above embodiment, the transistor cell 18 is a MOS transistor having a planar gate structure. The case of a FET cell has been described above. The transistor cell 18 is a transistor as shown in FIG. The MOSFET cell may have a trench gate structure. In this case, the gate electrode 19 has multiple A gate insulating film 35 is formed in a gate trench 39 formed between each of the transistor cells 18. It is buried through.

[0090] The transistor cell 18 is an I type having a planar gate structure or a trench gate structure. In this case, n + Instead of the type SiC substrate 27, + type SiC group A plate 27 may be used.

[0091] In addition, the built-in resistor 21 must be embedded in the interlayer film 36 below the gate metal 44. For example, the gate metal 44 and the gate finger 5 are connected to the surface of the interlayer film 36. The polysilicon wiring may be formed as the built-in resistor of the present invention.

[0092] In addition, the material of the built-in resistor 21 is made of a gate metal 44 and a gate The material has a resistance value equal to or greater than that of the base finger 5 (for example, Al (Al)). Using metal wiring such as aluminum, AlCu (aluminum-copper alloy), and Cu (copper) Even if the built-in resistor 21 is made of metal, the gate metal 44 and the gate finger 5 may be Since the distance between the gate electrodes can be increased, the total resistance of the gate electrode 19 and the built-in resistor 21 can be increased to The resistance value can be increased.

[0093] In addition, the built-in resistor 21 does not need to be formed under the gate metal 44. For example, it may be formed below the gate finger 5 .

[0094] The built-in resistor 21 may be formed in a straight line along a part of the peripheral portion 24 of the gate metal 44. Alternatively, it may be an annular shape that extends along the entire periphery of the peripheral portion 24 of the gate metal 44 .

[0095] In addition, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 described above is inverted may be adopted. For example, in the semiconductor device 1, the p-type portion is n-type, and the n-type portion is p-type. This is also fine.

[0096] FIG. 5 shows an electric circuit of a module to which a semiconductor device according to an embodiment of the present invention is applied. FIG.

[0097] The module 100 includes a plurality of semiconductor devices (chips) 101 to 104 and a drain terminal 1 Each of the semiconductor devices 101 to 105 includes a source terminal 106 and a gate terminal 107. 1 to 3. Each semiconductor device 101 is composed of the semiconductor device 1 shown in FIG. 1 to 104 may be composed of the semiconductor device shown in FIG. 01 to 104 are connected in parallel.

[0098] Each of the semiconductor devices 101 to 104 includes a plurality of transistor cells 18 (FIG. 2) connected in parallel. 3a and 3b) and four built-in resistors 41 (see FIGS. 2, 3a and 3b) connected in parallel. 5, the transistor cells 1 are connected in parallel. 8 is represented as one transistor cell Tr, and the four built-in resistors 41 connected in parallel are represented as one It is represented by resistance R.

[0099] The gate electrodes of the semiconductor devices 101 to 104 are connected to the gate electrodes via the built-in resistors R. and connected to a gate terminal 107 of the module 100. The drain electrode of each semiconductor element 4 is connected to the drain terminal 105 of the module 100. The source electrodes of the body devices 101 to 104 are connected to the source terminal 106 of the module 100. There are.

[0100] In this module 100, each of the semiconductor devices 101 to 104 includes A built-in resistor R having a resistance value larger than that of the gate resistor in 104 is built in. Therefore, in this module 100, the gate resistance is larger than that of each of the semiconductor devices 101 to 104. When an external gate resistor having a large resistance value is provided in each of the semiconductor devices 101 to 104, In comparison, the module structure is simpler.

[0101] Although the embodiments of the present invention have been described in detail, these do not clarify the technical content of the present invention. These are merely examples used to illustrate the invention, and the present invention should not be construed as being limited to these examples. Rather, the scope of the present invention is limited only by the appended claims.

[0102] This application is a joint application of Japanese Patent Application No. 2013-24 filed with the Japan Patent Office on November 28, 2013. No. 6474, the entire disclosure of which is incorporated herein by reference. do.

[0103] Further features of the present invention can be extracted from the specification as follows:

[0104] "A1" SiC semiconductor layer, A control voltage input to a control pad formed on the front surface side of the SiC semiconductor layer is controlled by the control voltage. A plurality of transistor cells that are turned on / off controlled by receiving the electrodes; The control pad and the control voltage and electrically connecting the electrodes to the plurality of transistor cells, and and a built-in resistor for reducing The surface of the control pad is exposed from the surface insulating film formed on the top surface. A first wire region to which a wire is connected is selectively formed; The built-in resistor, in a plan view seen from a normal direction of the SiC semiconductor layer, is being selectively disposed in an area avoiding the wire area; Above the plurality of transistor cells, one main electrode of the plurality of transistor cells is provided. a main electrode pad different from the control pad is disposed on the main electrode pad; A bonding wire is connected to the surface of the main electrode pad, the bonding wire being exposed from the surface insulating film. a second wire region is selectively formed in the semiconductor device.

[0105] In this configuration, the control pad is disposed closer to the SiC semiconductor layer than the control pad, and the control electrode This electrically connects the transistor cells and reduces the variation in the on-resistance of the multiple transistor cells. By adjusting the resistance value of the built-in resistor, the control electrode The resistance of the built-in resistor is the sum of the resistance of the control resistor and the resistance of the built-in resistor. Therefore, it is possible to make the resistance value of the control electrode the dominant one. Even when semiconductor devices are connected in parallel, the resistance value of the built-in resistor must be set to a value lower than the variation. By setting the resistance of the control electrode to a large value, the current As a result, the generation of noise during use can be reduced. This can be done.

[0106] "A2" The control pad is formed independently and surrounded by the surface insulating film. And, The built-in resistor is connected to the first wire region in the region below the control pad through an interlayer film. The semiconductor device according to "A1", which is arranged in an outlying region.

[0107] According to this configuration, the current path extending from the bottom of the control pad, that is, the outside to the multiple cells, It is possible to limit the flow of control current at the inlet. This allows This prevents the inrush current from flowing only through the transistor. This can reduce the variation in switching speed between the first and second cells.

[0108] "A3" A portion of the built-in resistor is disposed in a region below the control pad; In a first region below the control pad where the built-in resistor is not arranged, The semiconductor device according to "A2", wherein the interlayer film is buried.

[0109] "A4" further includes an insulating film disposed between the built-in resistor and the SiC semiconductor layer. , In the first region, a film formed by an extension of the insulating film is formed between the interlayer film and the SiC semiconductor. The semiconductor device according to "A3", wherein the semiconductor layer is disposed between the first and second layers.

[0110] According to this configuration, in the first region where the built-in resistor is not arranged, the SiC semiconductor layer and The distance to the control pad (thickness of the insulating film) can be increased, reducing the capacitance between them. It is possible.

[0111] "A5" In the SiC semiconductor layer, the insulating film is sandwiched between the built-in resistor The area is 1×10 19 cm -3 An impurity region having the following concentration is selectively formed: The semiconductor device described in "A4".

[0112] According to this configuration, the concentration of the impurity region facing the built-in resistor is 1×10 19 cm -3 below Therefore, the dielectric breakdown of the insulating film can be effectively suppressed. The layer is an n-type SiC semiconductor layer, and the semiconductor layer has a region facing the built-in resistor with an insulating film sandwiched therebetween. 1×10 19 cm -3 The following p - It is preferable that the aryl group has a type region. - The type domain is Since it is more difficult for carriers to accumulate in the n-type region, the built-in resistors facing each other with an insulating film between them andp - The capacitance between the mold area can also be reduced.

[0113] "A6" The part of the built-in resistor is disposed below the peripheral edge of the control pad. the law of nature, The first wire region is formed in a central portion of the control pad surrounded by the peripheral portion. The semiconductor device according to any one of "A1" to "A5",

[0114] "A7" penetrates the interlayer film and electrically connects the control pad and the built-in resistor The semiconductor device according to any one of "A2" to "A5", further comprising a contact via.

[0115] According to this configuration, the position of the contact via can be changed along the surface of the SiC semiconductor layer. By modifying the diameter of vias or other processes, the current path from the outside to multiple transistor cells is The resistance value contributed by the built-in resistor can be easily adjusted. When forming contact vias, it is necessary to use a mask that matches the distance design and via diameter design. Since only the above-mentioned step is required, the manufacturing process can be prevented from becoming complicated.

[0116] "A8" The built-in resistor, in a plan view seen from the normal direction of the SiC semiconductor layer, A semiconductor device according to any one of "A1" to "A7" that is arranged symmetrically with respect to each other. body equipment.

[0117] This configuration makes it possible to prevent an inrush current from flowing only to a specific transistor cell. Therefore, it is possible to reduce the variation in switching speed among multiple transistor cells. can.

[0118] "A9" The control electrode is any one of "A1" to "A8" made of p-type polysilicon. The semiconductor device according to any one of the preceding claims.

[0119] "A10" The control electrode contains B (boron) as a p-type impurity, "A9" The semiconductor device according to claim 1 .

[0120] B (boron)-containing polysilicon is a type of P (phosphorus)-containing polysilicon that is commonly used in Si semiconductor devices. The resistivity is high compared to boron-containing polysilicon. Resistors) require a smaller area than phosphorus-containing polysilicon to achieve the same resistance. This reduces the area occupied by the built-in resistor on the SiC semiconductor layer, resulting in a smaller space. This will enable more effective use of the resources.

[0121] "A11" The resistance value of the built-in resistor is 2Ω to 40Ω, "A1" to "A10" The semiconductor device according to any one of the preceding claims.

[0122] "A12" The total resistance value of the control electrode and the built-in resistor is The semiconductor device according to any one of "A1" to "A11", which has an impedance of 4 Ω to 50 Ω.

[0123] "A13" The sheet resistance of the built-in resistor is 10Ω / □ or more, "A1" to "A1 2". A semiconductor device according to any one of claims 1 to 2.

[0124] In practice, if the sheet resistance of the built-in resistor is 10Ω / □ or more, the area of ​​the built-in resistor should be increased. The resistance value of the entire built-in resistors can be measured more easily than the variation in resistance values ​​between multiple semiconductor devices. As a result, the area on the SiC semiconductor layer that is used for the built-in resistor can be increased. The area of ​​the area sacrificed can be reduced, so the impact on the layout of other elements is reduced. nothing.

[0125] "A14" The size of the built-in resistor in a plan view seen from the normal direction of the SiC semiconductor layer The size is 200μm□ or less per piece, as described in any of "A1" to "A13". Semiconductor device.

[0126] In practice, if the size of the built-in resistor is 200 μm or less per resistor, This reduces the area of ​​the region that is sacrificed for the built-in resistor, thereby saving space. It is possible.

[0127] "A15" Any one of claims 1 to 14, wherein the thickness of the built-in resistor is 2 μm or less. Item 1. The semiconductor device according to item 1.

[0128] By making the thickness of the built-in resistor 2μm or less, the resistance value of the entire built-in resistor can be The resistance variation between the conductor devices can be easily increased. If the thickness is too thick, the resistance value becomes too low, which is not preferable.

[0129] "A16" is arranged on the front side of the semiconductor device similarly to the control pad, Fingers extending from the control pad to divide the transistor cell area into a plurality of regions. Further including The built-in resistor electrically connects the control pad and the finger. " to "A15".

[0130] In this way, the present invention can be applied to devices in which fingers extend from the control pads. The features of the above can be applied well.

[0131] "A17" The finger is a part arranged to surround the periphery of the control pad. The semiconductor device according to "A16" has the following.

[0132] "A18" The semiconductor device according to "A16", wherein the finger is made of metal wiring. By constructing the fingers with metal wiring, which has a lower resistance than polysilicon, It is possible to supply control current in a short time even to cells located relatively far from the head. Cut.

[0133] "A19" The metal wiring is made of one of Al, AlCu, or Cu. The semiconductor device according to "A17".

[0134] When the metal wiring is made of Al, since Al is easy to process, the finger formation process When the metal wiring is made of AlCu, the finger The power cycle resistance can be improved compared to the case of Al wiring. When the wiring is made of Cu, the resistance is higher than when the fingers are made of Al wiring or AlCu wiring. The resistance can be reduced.

[0135] "A20" The transistor cell constitutes a MOSFET cell, the control pad is connected to a control electrode of the MOSFET cell; the main electrode pad is connected to a source electrode of the MOSFET cell; "A1" to "A19" including a drain electrode formed on the back side of the SiC semiconductor layer 2. The semiconductor device according to claim 1 ,

[0136] "A21" The MOSFET cell described in "A20" includes a planar gate structure. Semiconductor device.

[0137] "A22" The MOSFET cell described in "A20" includes a trench gate structure. Semiconductor device.

[0138] "A23" The transistor cell constitutes an IGBT cell, the control pad is connected to a control electrode of the IGBT cell; the main electrode pad is connected to an emitter electrode of the IGBT cell; "A1" to "A19" including a collector electrode formed on the back side of the SiC semiconductor layer 2. The semiconductor device according to claim 1 ,

[0139] "A24" The plurality of transistor cells are arranged in a lattice pattern, "A1" to " A semiconductor device according to any one of "A23".

[0140] "A25" semiconductor layer; A control electrode receives a control voltage input to a control pad formed on the front surface side of the semiconductor layer. a plurality of transistor cells that are controlled to be turned on / off by a The control is performed so as to divide an area in which the plurality of transistor cells are formed into a plurality of areas. a finger extending from the pad and electrically connected to the control pad; The control pad and the finger are disposed on the semiconductor layer side. a resistor that is equal to or larger than the resistor of the finger; and a built-in resistor made of a material having a value, The surface of the control pad is exposed from the surface insulating film formed on the top surface. A first wire region is selectively formed to which a wire is bonded; The built-in resistor is, in a plan view seen from a normal direction of the semiconductor layer, selectively placed in an area avoiding the area; Above the plurality of transistor cells, one main electrode of the plurality of transistor cells is provided. a main electrode pad different from the control pad is disposed on the main electrode pad; A bonding wire is connected to the surface of the main electrode pad, the bonding wire being exposed from the surface insulating film. a second wire region is selectively formed in the semiconductor device.

[0141] "A26" The semiconductor device according to "A25", wherein the built-in resistor is made of metal.

[0142] "A27" A semiconductor device according to any one of "A1" to "A26" is connected in parallel. A semiconductor module comprising: [Explanation of symbols]

[0143] 1 Semiconductor device 2. Active Area 4 Gate Pad 5 Gate Finger 7 Inner Cell Area 12 Pad Surroundings 13 First Finger 14 Second Finger 15 Main parts 16 Branch 18 Transistor Cell 19 Gate electrode 20 Gate Contact 21 Built-in resistor 22 Pad side contact 23 Cell side contact 24 Periphery 27 SiC substrate 28 SiC epitaxial layer 29 pages - Type Body Area 30n + Type Body Area 31 p + Mold body contact area 32 Channel Area 33 p + type area 34 p - type area 35 Gate insulating film 36 Interlayer Film 37 Pad side contact 38 Pad side contact 39 Gate Trench 44 Gate Metal

Claims

1. A gate metal; a plurality of gate fingers including the gate metal and a pad periphery spaced apart from each other, the gate fingers extending in different directions; a plurality of built-in resistors each located below the gate metal in a plan view and each extending across the gate metal and a periphery of the pad; the plurality of built-in resistors are positioned symmetrically with respect to a planar shape of the gate metal in a plan view and are positioned at approximately the same distance from each other from a center of gravity of the planar shape of the gate metal.

2. The plurality of built-in resistors includes two built-in resistors, 2 . The semiconductor device according to claim 1 , wherein the two built-in resistors are located on two opposite sides of the gate metal in a plan view.

3. The plurality of built-in resistors includes two built-in resistors, 2 . The semiconductor device according to claim 1 , wherein the two built-in resistors are located at two diagonally opposite corners of the gate metal in a plan view.

4. A semiconductor device described in any one of claims 1 to 3, wherein each of the multiple built-in resistors has a rectangular shape when viewed in a planar view.

5. A semiconductor device as described in claim 4, wherein each of the multiple built-in resistors has a size of 200 μm square or less.

6. A passivation film covering the gate metal and the gate fingers and having an opening exposing a portion of the gate metal as a gate pad, 6. The semiconductor device according to claim 1, wherein the passivation film covers an area above which the plurality of built-in resistors are located.

7. The semiconductor device described in Claim 6, wherein the passivation film has the opening between areas in the gate metal that overlap the multiple built-in resistors in a planar view.

8. A semiconductor device described in any one of claims 1 to 7, wherein the thickness of the multiple built-in resistors is 2 μm or less.

9. A semiconductor device described in any one of claims 1 to 8, wherein the gate metal and the gate finger are arranged on a semiconductor layer, and the gate metal and the gate finger face a p-type region formed in the semiconductor layer.

10. The semiconductor device of claim 9, wherein the p-type region is at the same potential as a source metal.

11. A semiconductor device described in any one of claims 1 to 8, wherein the gate metal and the gate fingers are arranged on a semiconductor layer, and the gate metal and the gate fingers face a p-type region formed in the semiconductor layer via the multiple built-in resistors.

12. The semiconductor device according to claim 11, wherein the p-type region has an impurity concentration of 1×10 19 cm −3 or less.

13. A semiconductor memory device comprising: a plurality of transistor cells; 13. The semiconductor device according to claim 1, wherein the plurality of transistor cells are MOSFET cells having a planar gate structure or MOSFET cells having a trench gate structure.

14. A semiconductor device comprising a plurality of semiconductor devices according to any one of claims 1 to 13, a gate resistor connected to each of the gate metals of the plurality of semiconductor devices; a resistance value of a parallel circuit of the plurality of built-in resistors in each semiconductor device is greater than a gate resistance in the semiconductor device.

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