Semiconductor Device

Abstract

To provide a semiconductor device which includes a semiconductor element in a trench gate structure that can secure the avalanche resistance.SOLUTION: A semiconductor device includes a saturation current suppression layer having a first deep layer 4 and a JFET part 3, an n-type layer 6, a p-type base region 7 and an interlayer insulating film 13 in a connection region Ra. A contact opening 13b surrounding a cell region Rc is formed in the interlayer insulating film 13. The semiconductor device also includes an outer peripheral deep layer 5a which is formed so as to extend from at least a surface of the n-type layer 6 to the first deep layer 4 and is formed with the same impurity density as the second deep layer 5, and outer peripheral source wiring 20 which is formed on the interlayer insulating film 13, has a straight portion that is arranged so as to surround the cell region Rc and goes along the longitudinal direction of the trench gate structure and is connected to the outer peripheral deep layer 5a through the contact opening 13b. The outer peripheral deep layer 5a is arranged immediately below the outer peripheral source wiring 20 and extends along the straight portion of the outer peripheral source wiring 20.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a connecting region and a voltage-resistance holding region as an outer peripheral region surrounding the outer periphery of a cell region, and is particularly suitable for application to a SiC semiconductor device that uses silicon carbide (hereinafter referred to as SiC) as a semiconductor material. [Background technology]

[0002] Conventionally, a MOSFET with a trench gate structure is known as a power device using SiC. In a MOSFET with a trench gate structure, there is a problem that an electric field concentration occurs at the bottom of a trench for forming the trench gate structure, and the gate insulating film is easily destroyed. For this reason, as shown in Patent Document 1, in order to alleviate the electric field concentration at the bottom of the trench, a striped first deep layer is formed at the bottom of the trench along a direction intersecting with the longitudinal direction of the trench. In addition, the first deep layer and the base region are connected by the second deep layer, and a contact region formed in the surface layer part of the base region is electrically connected to the source electrode, so that the first deep layer is fixed to the source potential through the base region and the second deep layer. By providing such a first deep layer, it is possible to make it difficult for a high electric field to enter the gate insulating film side, and it is possible to suppress the dielectric breakdown of the gate insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-46908 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to prevent the avalanche resistance of a semiconductor device from decreasing, it is important not to allow the avalanche current to flow in a relatively low-concentration, high-resistance region such as the base region. Therefore, in the peripheral region located on the periphery of the cell region, it is desirable to allow the current during avalanche to flow from the first deep layer through the second deep layer to the peripheral source wiring provided on the periphery of the cell region. However, depending on the layout of the second deep layer in the peripheral region, the current during avalanche may flow a long distance through the base region, resulting in a problem of a decrease in the avalanche resistance.

[0005] In view of the above, an object of the present invention is to provide a semiconductor device including a semiconductor element having a trench gate structure capable of ensuring avalanche resistance. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure comprises a semiconductor layer (1) of a first or second conductivity type, and a first layer (2) of the first conductivity type formed on the semiconductor layer and having a lower impurity concentration than the semiconductor layer, and has a cell region (Rc), a voltage-withstanding region (Rb) having a peripheral voltage-withstanding structure surrounding the periphery of the cell region, and an outer periphery region (Ro) including a connecting region (Ra) located between the voltage-withstanding region and the cell region.

[0007] The cell region includes a saturation current suppression layer (3, 4) including a first deep layer (4) of a second conductivity type formed on the first layer and arranged in stripes with one direction as the longitudinal direction, a JFET section (3) of a first conductivity type having a portion in which a plurality of lines are arranged in stripes alternately with the first deep layer with one direction as the longitudinal direction, a second layer (6) of a first conductivity type formed on the saturation current suppression layer, a second deep layer (5) of a second conductivity type formed so as to extend from at least the surface of the second layer to the first deep layer, a base region (7) of the second conductivity type formed on the second layer, a source region (8) of the first conductivity type formed on the base region and having a higher first conductivity type impurity concentration than the first layer, and a second deep layer (9) of a second conductivity type different from the source region on the base region. The semiconductor device further comprises a contact region (9) formed at a position adjacent to the source region and having a higher second conductivity type impurity concentration than the base region, a gate trench (10) penetrating the source region and the base region, a gate insulating film (11) covering the inner wall surface of the gate trench and a gate electrode (12) arranged on the gate insulating film, and a trench gate structure in which a plurality of gate insulating films are arranged in a stripe shape with a longitudinal direction intersecting one direction, an interlayer insulating film (13) in which a first contact opening (13a) is formed that covers the gate electrode and exposes the source region and the contact region, a source electrode (14) electrically connected to the source region through the first contact opening, and a drain electrode (15) formed on the back surface side of the semiconductor layer.

[0008] The connection region includes a saturation current suppression layer including a first deep layer and a JFET section, a second layer, a base region, and an interlayer insulating film, in which a second contact opening (13b) surrounding the cell region is formed, a peripheral deep layer (5a) formed at least from the surface of the second layer to the first deep layer and formed with the same second conductivity type impurity concentration as the second deep layer, and a peripheral source wiring (20) formed on the interlayer insulating film, arranged to surround the cell region, has a linear portion along the longitudinal direction of the trench gate structure, and is connected to the peripheral deep layer through the second contact opening. The peripheral deep layer is arranged directly below the peripheral source wiring and extends along the linear portion of the peripheral source wiring.

[0009] In this way, the outer deep layer is provided directly under the outer source wiring in the connection region. This allows carriers generated on the outer side of the connection region to pass through the outer deep layer and escape to the outer source wiring. In other words, carriers can flow directly into the outer source wiring without passing through the base region. This makes it possible to provide a semiconductor device that can suppress the decrease in avalanche resistance.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing a cross-sectional configuration of a SiC semiconductor device according to a first embodiment. [Diagram 2] 2 is a perspective cross-sectional view showing a part of the SiC semiconductor device shown in FIG. [Diagram 3] 2 is a diagram showing a top surface layout of a semiconductor chip including the SiC semiconductor device shown in FIG. [Figure 4] FIG. 4 is an enlarged view of a region R in FIG. [Diagram 5] 13 is a diagram showing a flow of holes in a cross section of a boundary region in the outer periphery region and the boundary region side of the cell region. FIG. [Figure 6] 4 is an enlarged view showing the vicinity of a joint region as a comparative example, and corresponds to a region R in FIG. 3. [Figure 7] FIG. 11 is a cross-sectional view showing the flow of holes in a connecting region in the outer periphery region as a comparative example. [Figure 8A] 3A to 3C are perspective cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. 2. [Figure 8B] 8B is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 8A. [Figure 8C] 8C is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 8B. [Figure 8D]8D is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 8D. [Figure 8F] FIG. 8C is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 8E. [Figure 8G] FIG. 8C is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 8F. [Figure 9A] 6A to 6C are diagrams illustrating a manufacturing process of a SiC semiconductor device in the cross section shown in FIG. 5. [Figure 9B] 9B is a diagram showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 9A. [Figure 9C] 9C is a diagram showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 9B. [Figure 9D] 9C is a diagram showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 9C. [Figure 9E] 9E is a diagram showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 9D. [Figure 9F] 9C is a diagram showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 9E. [Figure 9G] 9B is a diagram showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 9F. [Figure 10] 4 is an enlarged view corresponding to a region R in FIG. 3 and showing the vicinity of a joint region of the SiC semiconductor device according to the second embodiment. [Figure 11] 10 is an enlarged view corresponding to a region R in FIG. 3 and showing the vicinity of a joint region of a SiC semiconductor device described in a modified example of the second embodiment. [Figure 12] 13 is a diagram showing a top surface layout of a semiconductor chip including a SiC semiconductor device described in another embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) The first embodiment will be described with reference to Figures 1 to 9. In this embodiment, a SiC semiconductor device using SiC as a semiconductor material will be described as an example, but a semiconductor device made of other semiconductor materials such as silicon (Si) may also be used.

[0014] The SiC semiconductor device according to this embodiment is formed with an inverted vertical MOSFET having a trench gate structure as shown in FIG. 1 and FIG. 2 as a semiconductor element. As shown in FIG. 3 and FIG. 4, the SiC semiconductor device is configured to have a cell region Rc and an outer peripheral region Ro surrounding the cell region Rc, and the vertical MOSFET shown in FIG. 1 and FIG. 2 is provided in the cell region Rc. In the following, as shown in FIG. 1 to FIG. 4, directions perpendicular to each other are respectively defined as the X direction, the Y direction, and the Z direction. Specifically, the depth direction of the vertical MOSFET is defined as the X direction, the width direction of the vertical MOSFET intersecting with the X direction is defined as the Y direction, and the thickness direction or depth direction of the vertical MOSFET, i.e., the normal direction to the XY plane is defined as the Z direction.

[0015] Note that Fig. 1 shows a cross section taken along line II in Fig. 4, and Fig. 5 shows a cross section taken along line VV in Fig. 4. Fig. 2 is a perspective cross-sectional view showing a part of the cell region Rc, but in order to make the layout of each part easier to see, some of the configuration of the SiC semiconductor device is omitted.

[0016] As shown in FIG. 1 and FIG. 2, the SiC semiconductor device includes a n-type semiconductor device made of SiC. + A type substrate 1 is used as a semiconductor substrate. In both the cell region Rc and the peripheral region Ro, + On the main surface of the substrate 1, + The n-type substrate 1 is a lower concentration drift layer. - A mold layer 2 is formed. + The n-type substrate 1 corresponds to a semiconductor layer. - The type layer 2 corresponds to a first layer of a first conductivity type.

[0017] [Configuration of cell region Rc] In cell region Rc, n - On the mold layer 2, an n-type JFET section 3 and a p-type first deep layer 4 are formed, which constitute a part of a drift layer made of SiC. - The mold layer 2 is n + It is connected to a JFET section 3 on the opposite side to the mold substrate 1.

[0018] The JFET section 3 and the first deep layer 4 constitute a saturation current suppression layer, and are both extended in the Y direction as the longitudinal direction, and are arranged alternately and repeatedly in the X direction. + When viewed from the normal direction to the main surface of the mold substrate 1, at least a part of the JFET section 3 and the first deep layer 4 are each formed into a plurality of lines, in other words, stripes, which are arranged alternately.

[0019] In this embodiment, the JFET section 3 is formed below the first deep layer 4. Therefore, the striped portions of the JFET section 3 are connected below the first deep layer 4, but each striped portion is disposed between a plurality of first deep layers 4.

[0020] The first deep layer 4 is composed of a p-type impurity layer. As described above, the first deep layer 4 is striped, and each linear portion of the striped first deep layer 4 has a constant width and is disposed at equal intervals, so that the p-type impurity concentration is constant in the depth direction.

[0021] Furthermore, an n-type layer 6 that constitutes a part of the drift layer made of SiC and corresponds to the second layer of the first conductivity type is formed on the JFET section 3 and the first deep layer 4. The n-type layer 6 has an n-type impurity concentration of n - It may be the same as the type layer 2, but by making it taller, it is possible to allow the current flowing through the channel of the vertical MOSFET to diffuse in the Y direction.

[0022] In this embodiment, n- The n-type layer 2, the JFET section 3, and the n-type layer 6 constitute a drift layer. However, the configuration of the drift layer is arbitrary. For example, - Type layers 2 and n + A buffer layer may be provided between the mold substrate 1 and the substrate.

[0023] A p-type base region 7 made of SiC is formed on the n-type layer 6, and a n-type base region 8 made of SiC is formed on the p-type base region 7. + A type source region 8 is formed. In addition, p-type impurities are implanted into the p-type base region 7 and a portion of the n-type layer 6, so that a second deep layer 5 made of SiC is formed so as to extend from the surface of the p-type base region 7 to the first deep layer 4. The second deep layer 5 has a higher p-type impurity concentration than the p-type base region 7, and the p-type base region 7 has a lower p-type impurity concentration than the first deep layer 4. In addition, + The n-type source region 8 has a higher n-type impurity concentration than the n-type layer 6.

[0024] Also, n + A contact p is formed from the surface of the source region 8 to the second deep layer 5 or the p-type base region 7, the contact p being equivalent to a contact region having a higher p-type impurity concentration than the p-type base region 7. + A mold layer 9 is formed. + As shown in FIG. 2, the mold layer 9 extends in the Y direction intersecting with the trench gate structure described later, but here, it also extends in the X direction between the trench gate structures at a ratio of one to a plurality of trench gate structures. + The second deep layer 5 is formed below a portion of the mold layer 9 that extends in the X direction. Although the second deep layer 5 is formed in the entire area between both sidewalls of adjacent gate trenches 10 here, it is not necessarily required to form it in the entire area.

[0025] Contact +The contact layer 9 serves to connect the p-type base region 7 to a source electrode 14 (described later) in order to fix the first deep layer 4 as well as the p-type base region 7 to the source potential. + The mold layer 9 is connected to the source electrode 14, forming a contact p + The p-type base region 7 is fixed to the source potential through the n-type layer 9, and the first deep layer 4 is also fixed to the source potential through the second deep layer 5 or the p-type base region 7. + The source region 8 and the contact p + The surface of the mold layer 9 reacts with the electrode material contained in the source electrode 14 to form a silicide layer. + The source region 8 and the contact p + The mold layer 9 and the source electrode 14 are in ohmic contact with each other.

[0026] Furthermore, the p-type base region 7 and the n + A gate trench 10 having a predetermined width and a predetermined depth is formed so as to penetrate through the n-type source region 8 and reach the n-type layer 6. The p-type base region 7 and the n-type base region 8 are in contact with the side surface of the gate trench 10. + The source region 8 and the contact p + 2 as its width direction and a direction intersecting the longitudinal direction of the JFET section 3 and the first deep layer 4, in this case, the X direction is its longitudinal direction and the Z direction is its depth direction. As shown in FIGS. 1, 2 and 4, the gate trenches 10 are formed in a stripe shape with a plurality of gate trenches 10 arranged at equal intervals in the Y direction, and the p-type base region 7 and the n-type base region 8 are disposed between the gate trenches 10. + A type source region 8 is arranged.

[0027] As shown in Figure 4, +The gate trenches 10 are arranged in a stripe shape when viewed from the normal direction to the main surface of the mold substrate 1, but it is sufficient that the gate trenches 10 have a structure having at least a stripe-shaped portion. For example, the gate trenches 10 may be laid out so that two adjacent linear gate trenches 10 form a pair, with both ends of the pair being connected to each other in a semicircular shape.

[0028] The portion of the p-type base region 7 located on the side of the gate trench 10 is converted into an n + The inner wall surface of the gate trench 10 including the channel region is covered with a gate insulating film 11, which serves as a channel region connecting between the n-type source region 8 and the n-type layer 6. A gate electrode 12 made of doped poly-Si is formed on the surface of the gate insulating film 11, and the gate insulating film 11 and the gate electrode 12 are disposed in the gate trench 10 to form a trench gate structure. Furthermore, an interlayer insulating film 13 is formed so as to cover the gate electrode 12. The interlayer insulating film 13 may extend outside the gate trench 10, but here it is disposed within the gate trench 10, and the gate trench 10 is completely filled with the gate insulating film 11, the gate electrode 12, and the interlayer insulating film 13.

[0029] Also, as shown in Figure 1, + A source electrode 14 and a gate wiring (not shown) are formed on the surface of the n-type source region 8 and the surface of the gate electrode 12 via an interlayer insulating film 13. The source electrode 14 and the gate wiring are made of a plurality of metals, for example, Ni / Al. Among the plurality of metals, at least n-type SiC, specifically n + The portion in contact with the n-type source region 8 or the gate electrode 12 in the case of n-type doping is made of a metal capable of making ohmic contact with n-type SiC. +The portion in contact with the p-type layer 9 is made of a metal capable of making ohmic contact with the p-type SiC. The source electrode 14 is formed on the interlayer insulating film 13 and is electrically insulated from the SiC portion. As shown in FIGS. 4 and 5, the source electrode 14 is electrically insulated from the SiC portion through a contact opening 13a formed in the interlayer insulating film 13. + type source region 8 and contact p + The contact opening 13a corresponds to a first contact opening, and is formed in the interlayer insulating film 13 at a position corresponding to the cell region Rc. + type source region 8 and contact p + The gate electrode 12 is in contact with the mold layer 9. The gate wiring is also in contact with a gate liner drawn out from the tip of the gate electrode 12 through a contact opening (not shown) formed in the interlayer insulating film 13.

[0030] On the other hand, n + The back side of the mold substrate 1 is + A drain electrode 15 is formed and electrically connected to the substrate 1. With this structure, an n-channel type inversion type vertical MOSFET with a trench gate structure is formed. A plurality of such vertical MOSFETs are arranged to form a cell region Rc.

[0031] [Configuration of outer peripheral region Ro] 3 and 4, the outer peripheral region Ro is configured to surround the cell region Rc, and has a joint region Ra and a voltage resistance holding region Rb. The joint region Ra is a region between the cell region Rc and the voltage resistance holding region Rb.

[0032] As shown in FIG. 5, the connecting region Ra is also n + On the main surface of the mold substrate 1 - The saturation current suppression layer including the type layer 2, the JFET section 3 and the first deep layer 4, the n-type layer 6, and the p-type base region 7 are formed. +The mold layer 9 is formed. The second deep layer 5 is formed in a rectangular shape with rounded corners so as to surround the cell region Rc. As shown in FIG. 5, the contact p + A mold layer 9 is also formed.

[0033] In the junction region Ra, an interlayer insulating film 13 is also formed on the p-type base region 7 and the like, and a peripheral source wiring 20 that is set to source potential is further formed on the interlayer insulating film 13. For example, the peripheral source wiring 20 is set to source potential by being connected to a source electrode 14 at a predetermined position within the chip surface. Hereinafter, the portion of the second deep layer 5 that is formed in the junction region Ra is referred to as the peripheral deep layer 5a. The peripheral deep layer 5a is formed at the same time as the second deep layer 5 that is formed in the cell region Rc, and has the same impurity concentration. In addition, the contact p + The portion of the mold layer 9 formed in the connecting region Ra is called the peripheral contact portion 9a. The peripheral contact portion 9a is also connected to the contact p formed in the cell region Rc. + It is formed at the same time as the mold layer 9 and has the same impurity concentration.

[0034] In the interlayer insulating film 13, outside the contact opening 13a formed at a position corresponding to the cell region Rc, a contact opening 13b is formed so as to surround the contact opening 13a. In other words, the contact opening 13b is formed at an intermediate position between the cell region Rc and the breakdown voltage holding region Rb in the connecting region Ra. The contact opening 13b corresponds to a second contact opening and has a rectangular shape with rounded corners. Through this contact opening 13b, the peripheral contact portion 9a and the peripheral source wiring 20 are electrically connected in the connecting region Ra. Although not shown in FIG. 5 and the like, a gate runner may be disposed between the source electrode 14 and the peripheral source wiring 20. In addition, the gate insulating film 11 and a field oxide film (not shown) may be disposed under the interlayer insulating film 13. In that case, for example, the gate runner may be disposed on the gate insulating film 11 and the field oxide film and under the interlayer insulating film 13.

[0035] Here, the peripheral deep layer 5a, the peripheral contact portion 9a, and the peripheral source wiring 20 are provided to facilitate the escape of holes generated in the connection region Ra. As described above, the peripheral deep layer 5a and the peripheral source wiring 20 are rectangular with rounded corners. If the cell region Rc is rectangular with sides H1 and H2 perpendicular to each other, the rectangular shape formed by the peripheral deep layer 5a and the peripheral source wiring 20 is laid out so that the perpendicular sides L1 and L2 face the sides H1 and H2. The sides H1 and L1 are set to be sides along the X direction, that is, the longitudinal direction of the trench gate structure, and the sides H2 and L2 are set to be sides perpendicular to the Y direction, that is, the longitudinal direction of the trench gate structure. The sides L1 and L2 here correspond to the first side and the second side, respectively.

[0036] As shown in FIG. 5, the peripheral deep layer 5a, the peripheral contact portion 9a, and the peripheral source wiring 20 are laid out so as to overlap each other. That is, the peripheral deep layer 5a and the peripheral contact portion 9a are arranged directly under the peripheral source wiring 20. In this embodiment, the peripheral deep layer 5a is formed only directly under the peripheral source wiring 20, more specifically, only directly under the contact surface of the peripheral source wiring 20 with the SiC arranged in the contact opening 13b. However, this is an example, and the peripheral deep layer 5a may be formed protruding from the contact surface of the peripheral source wiring 20 with the SiC on the cell region Rc side, which is the inner periphery, or the breakdown voltage holding region Rb side, which is the outer periphery. The peripheral contact portion 9a may also be formed only directly under the peripheral source wiring 20.

[0037] The dimensions of each peripheral deep layer 5a are arbitrary, but here the width, i.e., the dimension in the short direction, is set to the same width as that of the portion of the second deep layer 5 arranged in the cell region Rc, for example, 1 to 2 μm. In addition, when the peripheral contact portion 9a is formed only directly under the peripheral source wiring 20, the width, i.e., the dimension in the short direction of the peripheral contact portion 9a is set to the same width as that of the contact p +The width is the same as that of the portion of the mold layer 9 that is arranged in the cell region Rc, and is, for example, 1 to 2 μm.

[0038] The second deep layer 5 including the peripheral deep layer 5a is formed by, for example, ion-implanting a p-type impurity into the n-type layer 6. + The type layer 9 is, for example, a p-type base region 7 or an n + The outer peripheral deep layer 5a and the outer peripheral contact portion 9a are formed by ion implanting p-type impurities into the p-type source region 8. At this time, a larger area of ​​the opening of the oxide film used as a mask for ion implantation is supplied with a larger amount of etching gas than a smaller area. For this reason, the SiC underlying layer may be over-etched during mask patterning. However, if the outer peripheral deep layer 5a and the outer peripheral contact portion 9a are formed in a line shape, the individual outer peripheral deep layer 5a and the outer peripheral contact portion 9a can be prevented from becoming too large, and therefore the underlying layer can be prevented from being over-etched.

[0039] Such an etching suppression effect can be obtained at least if the width of the outer periphery deep layer 5a or the outer periphery contact portion 9a is 10 μm or less, and the narrower the width, the higher the effect, and especially if the width is 2 μm or less, a high effect can be obtained. However, since the outer periphery deep layer 5a and the outer periphery contact portion 9a are intended to facilitate the escape of holes generated on the outer periphery side of the connection region Ra, it is desirable that the internal resistance is small. In consideration of this, the width of the outer periphery deep layer 5a is set to 1 μm or more, but since this width also depends on the impurity concentration of the outer periphery deep layer 5a, it may be set to less than 1 μm.

[0040] Furthermore, a breakdown voltage holding region Rb is formed outside the connecting region Ra in the outer peripheral region Ro. The breakdown voltage holding region Rb has a peripheral breakdown voltage structure such as a p-type guard ring or an EQR (Equivalent Potential Ring) (not shown) configured therein, which makes it possible to suppress electric field concentration and hold the breakdown voltage of the SiC semiconductor device.

[0041] In this embodiment, as shown in Fig. 3, a pad 30 serving as a signal terminal is arranged in a part of a joint region Ra in a semiconductor chip 100 constituting a SiC semiconductor device. This pad 30 is formed on an interlayer insulating film 13 in the joint region Ra, and is connected to a desired electrode of a vertical MOSFET. In this structure, a peripheral deep layer 5a and a peripheral source wiring 20 are added to the cell region Rc and formed to surround the pad 30.

[0042] In this manner, the SiC semiconductor device including the vertical MOSFET according to this embodiment is configured.

[0043] The SiC semiconductor device having the vertical MOSFET configured in this manner can be operated, for example, by applying a gate voltage Vg of 20 V to the gate electrode 12 with the source voltage Vs set to 0 V and the drain voltage Vd set to 1 to 1.5 V. That is, when the gate voltage Vg is applied, the vertical MOSFET operates in such a way that a channel region is formed in the p-type base region 7 in contact with the gate trench 10, and a current flows between the drain and source.

[0044] At this time, the JFET section 3 and the first deep layer 4 function as a saturation current suppression layer, and by exerting a saturation current suppression effect, it is possible to maintain a low saturation current while achieving a low on-resistance. Specifically, since the striped portion of the JFET section 3 and the first deep layer 4 are repeatedly formed alternately, the operation is as follows.

[0045] First, when the drain voltage Vd is a voltage applied during normal operation, such as 1 to 1.5 V, the depletion layer extending from the first deep layer 4 side to the JFET section 3 extends only to a width smaller than the width of the striped portion of the JFET section 3. Therefore, even if the depletion layer extends into the JFET section 3, a current path is secured. In addition, when the n-type impurity concentration of the JFET section 3 is set to n - If it is made higher than the mold layer 2, the current path can be configured with low resistance, and therefore, a low on-resistance can be achieved.

[0046] Furthermore, when the drain voltage Vd becomes higher than the voltage during normal operation due to a load short circuit or the like, the depletion layer extending from the first deep layer 4 side to the JFET section 3 extends wider than the width of the striped portion of the JFET section 3. Then, the JFET section 3 is immediately pinched off before the n-type layer 6. This makes it possible to maintain a low saturation current and improve the resistance of the SiC semiconductor device to load short circuits and the like.

[0047] In this way, the JFET portion 3 and the first deep layer 4 function as saturation current suppression layers and exert a saturation current suppression effect, making it possible to obtain a SiC semiconductor device that can achieve both low on-resistance and low saturation current.

[0048] Furthermore, by providing the first deep layer 4 so as to sandwich the JFET section 3, the striped portion of the JFET section 3 and the first deep layer 4 are alternately and repeatedly formed. Therefore, even if the drain voltage Vd becomes high, the n - The depletion layer extending into the n-type layer 2 is suppressed by the first deep layer 4, and it is possible to prevent the depletion layer from extending into the trench gate structure. Therefore, an electric field suppression effect that reduces the electric field applied to the gate insulating film 11 is exhibited, and the gate insulating film 11 is prevented from being destroyed, making it possible to obtain a highly reliable element with high withstand voltage. Since the depletion layer is prevented from extending into the trench gate structure in this way, - The n-type impurity concentration in the type layer 2 and the JFET section 3 can be made relatively high, making it possible to achieve a low on-resistance.

[0049] Therefore, it is possible to obtain a SiC semiconductor device having a vertical MOSFET with low on-resistance and high reliability.

[0050] On the other hand, in the SiC semiconductor device of this embodiment, when the gate voltage Vg is not applied, a channel region is not formed, so that the semiconductor element is a normally-off type in which no current flows between the drain and source. Also, the JFET section 3 is a normally-on type because it does not pinch off unless the drain voltage Vd becomes higher than the voltage during normal operation, even when the gate voltage Vg is not applied.

[0051] In this manner, in this embodiment, it is possible to improve the resistance of the SiC semiconductor device to load short circuits, etc., but an avalanche test is performed assuming that an avalanche breakdown occurs at the PN junction when the drain electrode 15 side becomes a high voltage. In other words, a test is performed to check the avalanche resistance of the SiC semiconductor device.

[0052] First, the inventors performed an avalanche test on a structure in which the peripheral deep layers 5a of this embodiment are arranged linearly at equal intervals in the same layout as the second deep layers 5 provided in the cell region Rc, as shown in Fig. 6. However, it was confirmed that such a structure cannot obtain the desired avalanche resistance.

[0053] As shown in FIG. 6 and FIG. 7, the peripheral deep layer 5a is formed at a position away from the peripheral source wiring 20. Therefore, holes generated during avalanche pass from the peripheral deep layer 5a through the p-type base region 7 and then pass through the peripheral source wiring 20, but the holes pass through a long distance through the p-type base region 7. This makes it impossible to obtain the desired avalanche resistance. In other words, passing through a long distance through the p-type base region 7, which has a relatively low impurity concentration, means that the holes pass through a long distance through a high resistance region. This reduces the avalanche resistance. In order to prevent the avalanche resistance from being reduced, it is important not to allow the avalanche current to flow through a relatively low concentration and high resistance region such as the p-type base region 7. For this reason, it is desirable to allow the current during avalanche to pass through the peripheral source wiring 20 without passing through the p-type base region 7 for a long distance in the peripheral region Ro located on the periphery of the cell region Rc.

[0054] In contrast, as shown in FIG. 3 to FIG. 5, in this embodiment, the peripheral deep layer 5a is formed directly under the peripheral source wiring 20. More specifically, the peripheral deep layer 5a is laid out in a substantially rectangular shape so as to overlap the peripheral source wiring 20 in accordance with the peripheral source wiring 20, which is substantially rectangular. Therefore, as shown by the arrow in FIG. 5, holes generated on the outer periphery side of the connection region Ra can pass through the peripheral deep layer 5a directly under the peripheral source wiring 20 and pass through to the peripheral source wiring 20. In other words, the holes can flow directly into the peripheral source wiring 20 without passing through the p-type base region 7. Therefore, it is possible to suppress the decrease in avalanche resistance. Furthermore, in this embodiment, the peripheral contact portion 9a is also formed directly under the peripheral source wiring 20. Therefore, the current can flow into the peripheral source wiring 20 without passing through the p-type base region 7, and the decrease in avalanche resistance can be further suppressed.

[0055] Next, a method for manufacturing a SiC semiconductor device according to this embodiment will be described with reference to FIGS. 8A to 8G and 9A to 9G.

[0056] [Steps shown in Figures 8A and 9A] First, a semiconductor substrate is made of, for example, SiC. + A mold substrate 1 is prepared. Then, an n-type silicon nitride film is formed by epitaxial growth using a CVD (chemical vapor deposition) apparatus (not shown). + A n-type substrate 1 is formed on the main surface of the n-type substrate 1. - A mold layer 2 is formed. At this time, n + On the main surface of the mold substrate 1, - A so-called epitaxial substrate on which the type layer 2 is grown may be used. - A JFET portion 3 made of SiC is epitaxially grown on the mold layer 2 .

[0057] [Steps shown in Figures 8B and 9B] The first deep layer 4 is formed in a predetermined region of the JFET section 3. For example, a mask 17 made of an oxide film or the like is placed on the surface of the JFET section 3, and then the mask 17 is patterned to open the region where the first deep layer 4 is to be formed. Then, the first deep layer 4 is formed by ion-implanting p-type impurities. Thereafter, the mask 17 is removed.

[0058] Although the first deep layer 4 is formed by ion implantation here, the first deep layer 4 may be formed by a method other than ion implantation. For example, the JFET section 3 is selectively anisotropically etched to form a recess at a position corresponding to the first deep layer 4, and a p-type impurity layer is epitaxially grown on the recess, and then the p-type impurity layer is flattened in the portion located above the JFET section 3 to form the first deep layer 4. In this manner, the first deep layer 4 can also be formed by epitaxial growth.

[0059] [Steps shown in Figures 8C and 9C] Subsequently, n-type SiC is epitaxially grown on the JFET section 3 and the first deep layer 4 using a CVD apparatus (not shown), thereby forming an n-type layer 6.

[0060] [Steps shown in Figures 8D and 9D] The p-type base region 7 is epitaxially grown on the n-type layer 6. Then, a mask 18 made of an oxide film or the like with an opening at a position corresponding to the second deep layer 5 is formed on the p-type base region 7. The second deep layer 5 is then formed by ion-implanting p-type impurities using the mask 18. At this time, the peripheral deep layer 5a is also formed at the same time in the connecting region Ra in the peripheral region Ro. Therefore, the peripheral deep layer 5a has the same p-type impurity concentration as the second deep layer 5 in the cell region Rc. The mask 18 is then removed.

[0061] [Steps shown in Figures 8E and 9E] On the p-type base region 7 + The n-type source region 8 is formed. + The type source region 8 may be formed by epitaxial growth or by ion implantation.

[0062] [Steps shown in Figures 8F and 9F] p-type base region 7 and n + A contact p on the source region 8 + A mask (not shown) is formed with openings at positions corresponding to the mold layer 9. Then, the mask is used to implant p-type impurities into the contact p-type layer 9 including the peripheral contact portion 9a. + A mold layer 9 is formed. After this, the mask is removed.

[0063] [Steps shown in Figures 8G and 9G] n + After a mask (not shown) is formed on the source region 8 and the like, an opening is made in the mask in a region where the gate trench 10 is to be formed. Then, the mask is used to perform anisotropic etching such as RIE, thereby forming the gate trench 10.

[0064] Thereafter, the mask is removed, and then, for example, an oxide film is deposited or thermal oxidation is performed to form a gate insulating film 11. The gate insulating film 11 covers the inner wall surface of the gate trench 10 and the n-type insulating film 12. +The gate electrode 12 is formed by depositing polysilicon doped with p-type or n-type impurities in the gate trench 10, and then etched back to leave the polysilicon in the gate trench 10. This completes the trench gate structure.

[0065] Further, an interlayer insulating film 13 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 12 and the gate insulating film 11. Then, n + type source region 8 and contact p + The interlayer insulating film 13 is etched until the mold layer 9 is exposed, forming contact openings 13a and leaving the interlayer insulating film 13 in the gate trench 10. At this time, a mask (not shown) is used to etch the interlayer insulating film 13 at positions corresponding to the peripheral contact portions 9a, thereby forming contact openings 13b in the shape of a rectangular frame with rounded corners.

[0066] Although the subsequent steps are not shown, the following steps are performed. That is, after forming an electrode material, for example, made of a laminated structure of multiple metals on the surface of the interlayer insulating film 13, the electrode material is patterned to form the source electrode 14 as well as the peripheral source wiring 20 and the gate wiring (not shown). + A drain electrode 15 is formed on the back surface side of the mold substrate 1. In this manner, the SiC semiconductor device according to this embodiment is completed.

[0067] As described above, in the SiC semiconductor device of this embodiment, the peripheral deep layer 5a and the peripheral contact portion 9a are provided in the connection region Ra directly below the peripheral source wiring 20. This allows holes generated on the outer periphery side of the connection region Ra to pass through the peripheral deep layer 5a and the peripheral contact portion 9a and exit to the peripheral source wiring 20. In other words, holes can flow directly into the peripheral source wiring 20 without passing through the p-type base region 7. This allows the SiC semiconductor device to suppress a decrease in avalanche resistance.

[0068] Furthermore, the SiC semiconductor device of this embodiment can provide the following effects.

[0069] (1) In this embodiment, the peripheral deep layer 5a and the peripheral contact portion 9a are formed in a substantially rectangular shape to match the peripheral source wiring 20, and are arranged to surround the cell region Rc. This makes it possible to configure a wider range of paths through which holes generated on the outer peripheral side of the connection region Ra can escape. This makes it easier for holes to escape to the peripheral source wiring 20, and further makes it possible to suppress a decrease in avalanche resistance.

[0070] (2) In this embodiment, the peripheral deep layer 5a and the peripheral contact portion 9a are configured in a line shape. This prevents the peripheral deep layer 5a and the peripheral contact portion 9a from becoming large in area. This prevents the SiC underlying layer in the region where the peripheral deep layer 5a is to be formed from being over-etched by etching when forming an opening in the ion implantation mask 18 when forming the second deep layer 5 including the peripheral deep layer 5a by ion implantation. Also, the contact p including the peripheral contact portion 9a is configured in a line shape. This prevents the peripheral deep layer 5a and the peripheral contact portion 9a from becoming over-etched by etching when forming an opening in the ion implantation mask 18 when forming the second deep layer 5 including the peripheral deep layer 5a by ion implantation. + The same effect can be obtained when the mold layer 9 is formed by ion implantation.

[0071] (3) The width of each peripheral deep layer 5a is the same as that of the portion of the second deep layer 5 that is arranged within the cell region Rc. Therefore, when forming the second deep layer 5 including the peripheral deep layer 5a by ion implantation, it is possible to match the width of the opening of the mask 18 for ion implantation between the cell region Rc and the peripheral region Ro. This allows the etching rate when forming the opening in the mask 18 to be matched between the cell region Rc and the peripheral region Ro, preventing the occurrence of any portion where the SiC underlying layer is over-etched. Also, the width of the peripheral contact portion 9a is also set to the same as that of the contact p + Since the width is the same as that of the portion of the mold layer 9 that is arranged in the cell region Rc, the same effect can be obtained.

[0072] Second embodiment A second embodiment will be described. This embodiment is similar to the first embodiment except that the layout of the outer circumferential deep layer 5a is changed, and therefore only the differences from the first embodiment will be described.

[0073] As shown in FIG. 10, in this embodiment, the peripheral deep layer 5a is configured in a straight line along the X direction so as to overlap with the peripheral source wiring 20 at the upper and lower parts of the semiconductor chip 100 in the connection region Ra, that is, at both sides in the Y direction sandwiching the cell region Rc. Also, the peripheral deep layer 5a is configured so as to extend from the second deep layer 5 formed in the cell region Rc at the left and right parts of the semiconductor chip 100 in the connection region Ra, that is, at both sides in the X direction sandwiching the cell region Rc. And, the peripheral deep layer 5a is configured to intersect with the peripheral source wiring 20. In other words, while the peripheral deep layer 5a is arranged in a stripe shape, the peripheral source wiring 20 and the peripheral deep layer 5a are configured to overlap linearly at the upper and lower parts of the semiconductor chip 100 and to overlap in a dot shape at the left and right parts of the semiconductor chip 100.

[0074] In this way, even if the layout of the peripheral deep layer 5a is changed, by providing the peripheral deep layer 5a directly below the peripheral source wiring 20, it is possible to obtain the same effects as in the first embodiment.

[0075] (Modification of the second embodiment) In the second embodiment, the peripheral deep layer 5a is formed on both the left and right sides of the semiconductor chip 100 so as to extend from the second deep layer 5 formed in the cell region Rc. In contrast, as shown in FIG. 11, the peripheral deep layer 5a may be arranged in a scattered manner only at the places where the extension line of the second deep layer 5 and the peripheral source wiring 20 intersect. In addition, the peripheral deep layer 5a does not necessarily have to be arranged on the extension line of the second deep layer 5, and may simply be arranged in a scattered manner so as to overlap with the peripheral source wiring 20. Of course, the peripheral deep layer 5a may be extended in the longitudinal direction of the second deep layer 5 so as to extend outside the peripheral source wiring 20.

[0076] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0077] (1) For example, in each of the above embodiments, the layout of the peripheral deep layer 5a is shown as merely one example. For example, in the first and second embodiments and their modifications, the peripheral deep layer 5a is provided in a straight line shape immediately below the straight portion of the peripheral source wiring 20 along the X direction, but the peripheral deep layer 5a may be in a dashed line shape instead of a straight line shape.

[0078] The peripheral deep layer 5a may be provided in other parts of the connection region Ra while being laid out in the layout shown in the first and second embodiments and their modified examples, or in the dashed line layout as described above. For example, the peripheral deep layer 5a may be laid out so as to intersect with the peripheral source wiring 20, in addition to the linear parts overlapping with the peripheral source wiring 20, on both the top and bottom sides of the semiconductor chip 100. In this case, holes generated in the connection region Ra pass through the parts of the peripheral deep layer 5a that intersect with the peripheral source wiring 20, reach the linear parts, and pass through to the peripheral source wiring 20, so that the holes can pass through more easily. This makes it possible to further suppress the decrease in avalanche resistance.

[0079] In each of the above embodiments, the peripheral contact portion 9a is formed in addition to the peripheral deep layer 5a, but when the peripheral deep layer 5a is formed up to the semiconductor surface, the peripheral deep layer 5a may be configured to directly contact the peripheral source wiring 20 without providing the peripheral contact portion 9a. In other words, the peripheral deep layer 5a may be configured to be connected to the peripheral source wiring 20 through the peripheral contact portion 9a, or may be configured to be directly connected to the peripheral source wiring 20 without providing the peripheral contact portion 9a.

[0080] In addition, the second deep layer 5, including the peripheral deep layer 5a, is formed from the surface of the p-type base region 7 to the first deep layer 4 deeper than the n-type layer 6, but it is sufficient that it is formed from at least the surface of the n-type layer 6 corresponding to the second layer. When the peripheral deep layer 5a is formed from the surface of the n-type layer 6, it may be either a configuration with or without the peripheral contact portion 9a, but if it is a structure without the peripheral contact portion 9a, it is sufficient that the p-type base region 7 is in direct contact with the peripheral source wiring 20. In addition, in the case of a structure with the peripheral contact portion 9a, it is preferable that the peripheral contact portion 9a is formed to the thickness of the p-type base region 7 and the peripheral contact portion 9a and the peripheral deep layer 5a are in contact with each other. Of course, the peripheral deep layer 5a and the peripheral contact portion 9a may be separated from each other with the p-type base region 7 in between. There may be a structure in which holes pass through the p-type base region 7 before passing through to the peripheral source wiring 20, but since the distance is short, the decrease in avalanche resistance can be limited.

[0081] In the second embodiment and its modified examples, the structure may be either with or without the peripheral contact portion 9a, but if the structure is with the peripheral contact portion 9a, it is preferable to use the same layout as the peripheral deep layer 5a. As a result, as described above, the effect of suppressing excessive etching of the SiC underlying layer during mask patterning for ion implantation of the peripheral contact portion 9a can be obtained.

[0082] (2) Although the outer shape of the cell region Rc is rectangular, other shapes are also acceptable. Even in such cases, the peripheral source wiring 20 is formed so as to follow each side of the outer shape of the cell region Rc.

[0083] Therefore, in the case of the first embodiment, the peripheral deep layer 5a may be formed in a line shape along the layout of the peripheral source wiring 20. In this case, the peripheral contact portion 9a may also be formed in a line shape along the peripheral source wiring 20.

[0084] In addition, in the case of the second embodiment or its modified example, the second deep layer 5 and the contact p in the cell region Rc of the peripheral source wiring 20 + The peripheral deep layer 5a and the peripheral contact portion 9a are arranged in a linear overlapping manner along the side along the mold layer 9. The second deep layer 5 and the contact p + In the portion intersecting with the extension line of the mold layer 9, the peripheral deep layer 5a and the peripheral contact portion 9a are arranged in a scattered manner. That is, as in the second embodiment, the peripheral deep layer 5a and the peripheral contact portion 9a may be formed in a line shape and may be arranged in a scattered state in the portion intersecting with the peripheral source wiring 20. Also, as in the modified example of the second embodiment, the peripheral deep layer 5a and the peripheral contact portion 9a may be arranged in a scattered manner only directly below the peripheral source wiring 20.

[0085] (3) In the above embodiment, the peripheral deep layer 5a and the peripheral source wiring 20 are provided to surround the pad 30 and the cell region Rc provided in the connection region Ra of the semiconductor chip 100 as shown in Fig. 3, but other layouts may be used. For example, a structure may be used in which the peripheral deep layer 5a and the peripheral source wiring 20 are arranged to pass between the cell region Rc and the pad 30 as shown in Fig. 12.

[0086] (4) In addition, in each of the above embodiments, the case where SiC is used as the semiconductor material has been described as an example, but the present invention can also be applied to semiconductor devices that use Si or other compound semiconductors as the semiconductor material.

[0087] (5) Furthermore, in the above embodiment, the semiconductor layer is + A mold substrate 1 is prepared. + A first conductive type layer corresponding to a first layer is formed on a substrate 1. - The structure in which the type layer 2 is epitaxially grown is given as an example. However, this is also just one example, and - A semiconductor substrate that constitutes the mold layer 2 is used, and ions are implanted on the back side of the substrate to form an n -A semiconductor layer having a higher impurity concentration than the mold layer 2 may be formed.

[0088] (6) In the above embodiments, an n-channel type MOSFET with an inversion type trench gate structure has been described as an example of a vertical power element. However, the above embodiments merely show one example of a vertical semiconductor element. For example, the above first embodiment and the like have been described as an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type, but a p-channel type MOSFET in which the conductivity types of each component are inverted may also be used. Also, in the above description, a MOSFET has been described as an example of a semiconductor element, but the present invention can also be applied to an IGBT with a similar structure. An IGBT is an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type. + The only difference is that the conductivity type of the substrate 1 is changed from n-type to p-type, and the other structures and manufacturing methods are the same as those of the above-mentioned embodiments. [Explanation of symbols]

[0089] 1...n + Mold substrate, 3...JFET section, 4...first deep layer, 5...second deep layer, 5a...periphery deep layer, 7...p-type base region, 8...n + Type source area, 9…Contact p + Mold layer, 9a...peripheral contact portion, 10...gate trench, 11...gate insulating film, 12...gate electrode, 13...interlayer insulating film, 13a, 13b...contact opening, 14...source electrode, 15...drain electrode, Rc: cell region, Ro: outer periphery region, Ra: connection region, Rb: voltage-resistance region

Claims

1. A semiconductor device comprising: A semiconductor layer (1) of a first or second conductivity type; a first layer (2) of a first conductivity type formed on the semiconductor layer and having a lower impurity concentration than the semiconductor layer; The semiconductor device has a cell region (Rc), a voltage-resistant region (Rb) having a peripheral voltage-resistant structure surrounding the outer periphery of the cell region, and an outer periphery region (Ro) including a connecting region (Ra) located between the voltage-resistant region and the cell region, The cell region includes: a saturation current suppression layer (3, 4) including a first deep layer (4) of a second conductivity type formed on the first layer, the first deep layer having a plurality of stripes arranged in one direction as a longitudinal direction, and a JFET portion (3) of a first conductivity type having a portion in which a plurality of stripes are arranged alternately with the first deep layer and the first deep layer in the longitudinal direction in the one direction; a second layer (6) of a first conductivity type formed on the saturation current suppression layer; a second deep layer (5) of a second conductivity type formed at least from the surface of the second layer to the first deep layer; a base region (7) of a second conductivity type formed on the second layer; a source region (8) of a first conductivity type formed on the base region and having a first conductivity type impurity concentration higher than that of the first layer; a contact region (9) formed on the base region at a position different from the source region and having a second conductive type impurity concentration higher than that of the base region; a trench gate structure including a gate insulating film (11) covering an inner wall surface of the gate trench (10) penetrating the source region and the base region, and a gate electrode (12) disposed on the gate insulating film, the trench gate structure including a plurality of gate insulating films arranged in a stripe shape with a direction intersecting the one direction as a longitudinal direction; an interlayer insulating film (13) in which a first contact opening (13a) is formed, the first contact opening covering the gate electrode and exposing the source region and the contact region; a source electrode (14) electrically connected to the source region through the first contact opening; A drain electrode (15) formed on the back surface side of the semiconductor layer, The connecting region includes: the first deep layer, the saturation current suppression layer including the JFET portion, the second layer, the base region, and the interlayer insulating film; A second contact opening (13b) surrounding the cell region is formed in the interlayer insulating film, a peripheral deep layer (5a) formed at least from the surface of the second layer to the first deep layer and having the same second conductivity type impurity concentration as the second deep layer; a peripheral source wiring (20) formed on the interlayer insulating film, arranged to surround the cell region, having a linear portion along the longitudinal direction of the trench gate structure, and connected to the peripheral deep layer through the second contact opening; the peripheral deep layer is disposed directly below the peripheral source wiring and extends along the linear portion of the peripheral source wiring.

2. 2. The semiconductor device according to claim 1, wherein a peripheral contact portion (9a) is formed at least on the base region at a position overlapping with the peripheral source wiring and the peripheral deep layer in a normal direction to the surface of the semiconductor layer, and having the same second conductivity type impurity concentration as the contact region.

3. 3. The semiconductor device according to claim 2, wherein said peripheral deep layer and said peripheral contact portion are formed so as to be continuous with each other.

4. 3. The semiconductor device according to claim 1, wherein a portion of said peripheral deep layer extending along said linear portion of said peripheral source wiring is linear.

5. The outer shape of the cell region is rectangular, the peripheral source wiring has a first side (L1) and a second side (L2) that are opposed to a side (H1) along a longitudinal direction of the trench gate structure and a side (H2) perpendicular to the side (H1) of the rectangle that constitutes the cell region, The outer circumferential deep layer is formed linearly along the first side immediately below the first side, 3. The semiconductor device according to claim 1, wherein the outer periphery deep layer is formed in a scattered manner immediately below the second side.

6. On both sides of the cell region in the longitudinal direction of the trench gate structure, The semiconductor device according to claim 5 , wherein the peripheral deep layer is formed in a straight line along the longitudinal direction of the trench gate structure formed in the cell region, so that the peripheral deep layer is arranged to intersect with the peripheral source wiring.

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