Semiconductor Device

Abstract

To provide a semiconductor device capable of avoiding erroneous determination while avoiding short-circuit tolerance in a main element from being decreased.SOLUTION: Gate electrodes 15 of a sense element Se and a main element Me are arranged to be connected to a common pad 1c which is connected to an external circuit. The sense element Se is configured so that whose sense saturation current density in a state in which a detection resistor R is not connected becomes higher than a main saturation current density of the main element Me, and whose sense saturation current density in a state in which the detection resistor R is connected becomes lower than the main saturation current density of the main element Me.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a main region in which a main element is formed and a sense region in which a sense element is formed. [Background technology]

[0002] Conventionally, a semiconductor device having a main region in which a main element is formed and a sense region in which a sense element is formed has been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, IGBT (short for Insulated Gate Bipolar Transistor) elements having the same configuration, including a gate structure, an emitter region, etc., are formed as the main element and the sense element. Furthermore, the main element and the sense element (i.e., the main region and the sense region) are formed to have a predetermined area ratio.

[0003] In such a semiconductor device, a sense resistor is connected in series to a sense element, and a main current flowing through the main element is generated using the voltage across the sense resistor as a sense voltage. That is, first, a sense current flowing through the sense element is derived based on the sense voltage. Furthermore, the current flowing through the main element and the current flowing through the sense element depend on the area ratio between the main element and the sense element. Therefore, the main current flowing through the main element is derived from the sense current flowing through the sense element (i.e., the sense voltage) and the area ratio between the main element and the sense element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4770119 Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device described above, the state of the semiconductor device is also determined based on the detected voltage. Specifically, the semiconductor device is determined to be operating normally when the detected voltage based on the current in the normal state is less than a predetermined normal threshold. Furthermore, the semiconductor device is determined to be operating short-circuited when the detected voltage based on the current in the transient state is equal to or greater than a predetermined transient threshold. Therefore, it is preferable that the semiconductor device described above suppresses erroneous determination of a transient state when a current in the normal state is flowing and prevents erroneous determination of a non-transient state when a current in the transient state is flowing. Therefore, it is preferable that the detected voltages in the normal state and the transient state are large in the semiconductor device described above.

[0006] In this case, in the semiconductor device described above, because a detection resistor is connected to the sense element, the actual gate-emitter voltage of the sense element is lower than the gate-emitter voltage of the main element. Therefore, it is conceivable to increase the detection voltage by increasing the saturation current density of the main element and the sense element. However, if the saturation current densities of both the main element and the sense element are increased to increase the detection voltage, the short-circuit resistance of the main element is likely to decrease.

[0007] In view of the above, the present invention provides a semiconductor device that can suppress a decrease in the short-circuit resistance of a main element and also suppress erroneous determination. [Means for solving the problem]

[0008] Claim 1 for achieving the above object provides a semiconductor device having a main region (Rm) in which a main element (Me) is formed and a sense region (Rs) in which a sense element (Se) is formed, wherein a detection resistor (R) is connected to the sense element and a main current flowing through the main element is detected based on a voltage generated in the detection resistor, and the main element and the sense element each include a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer, a first impurity region (16) of the first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a gate insulating film (14) arranged on the surface of the base layer sandwiched between the first impurity region and the drift layer, a gate electrode (15) arranged on the gate insulating film, a second impurity region (21) formed on the opposite side of the drift layer to the base layer, a first electrode (19) electrically connected to the first impurity region and the base layer, and a second electrode (22) electrically connected to the second impurity region. The gate electrodes of the sense element and the main element are connected to a common pad (1c) that is connected to an external circuit, and the sense element is configured so that the sense saturation current density when the detection resistor is not connected is higher than the main saturation current density of the main element, and so that the sense saturation current density when the detection resistor is connected is lower than the main saturation current density of the main element.

[0009] According to this, the sense saturation current density when the detection resistor is not connected is set higher than the main saturation current density. Therefore, the sense saturation current density can be increased without increasing the main saturation current density too much, and the range in which normal judgment and transient judgment are possible can be widened while suppressing a decrease in the short-circuit tolerance of the main element, thereby suppressing erroneous judgment. Furthermore, because the sense saturation current density when the detection resistor is connected is set lower than the main saturation current density, erroneous judgment can be suppressed under actual usage conditions.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 2 is a plan view of the main element. [Figure 5] FIG. 2 is a plan view of a sense element. [Figure 6] FIG. 10 is a diagram showing a circuit configuration when measuring a main current. [Figure 7] FIG. 10 is a diagram showing the relationship between a detected voltage in a steady state and a detected voltage in a transient state. [Figure 8] FIG. 10 is a diagram showing the relationship between the resistance value of a detection resistor and the saturation current density. [Figure 9] FIG. 10 is a graph showing the relationship between the gate-emitter voltage and the saturation current density. [Figure 10] FIG. 10 is a diagram showing the relationship between a detected voltage in a steady state and a detected voltage in a transient state. [Figure 11] FIG. 10 is a diagram showing the relationship between the resistance value of a detection resistor and the sense saturation current density. [Figure 12] FIG. 10 is a diagram showing the relationship between the detected voltage and the sense saturation current density in a transient state. [Figure 13] FIG. 10 is a graph showing the relationship between the gate-emitter voltage and the saturation current density. [Figure 14] FIG. 10 is a diagram showing the detected voltage in a transient state and the ratio of the main saturation current density to the sense saturation current density. [Figure 15] FIG. 10 is a cross-sectional view of a main element in a second embodiment. [Figure 16] FIG. 11 is a plan view of a sense element according to a third embodiment. [Figure 17] FIG. 10 is a cross-sectional view of a sense element according to a fourth embodiment. [Figure 18] FIG. 11 is a cross-sectional view of a sense element according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) The first embodiment will be described with reference to the drawings. The semiconductor device of the present embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

[0014] As shown in FIG. 1, the semiconductor device of this embodiment has a rectangular planar shape and includes a main region Rm where a main element Me is formed, a sense region Rs where a sense element Se is formed, and a peripheral region Rp. In the peripheral region Rp, a plurality of pads 1 are arranged along one side of the semiconductor device's outer shape. In this embodiment, as will be described later, the pad 1 includes a Kelvin emitter pad 1a, a sense emitter pad 1b, a gate pad 1c, and the like. The sense region Rs is arranged between the sense emitter pad 1b and the gate pad 1c. In other words, the sense region Rs is arranged near the gate pad 1c, and is located closer to the gate pad 1c than the main region Rm. The configurations of the main region Rm and the sense region Rs will be described below with reference to FIGS. 2 to 5.

[0015] The main element Me and the sense element Se of this embodiment have the same basic components, as will be described in detail later. The main element Me and the sense element Se are formed to have a predetermined area ratio (e.g., 5000:1). The semiconductor device of this embodiment detects (i.e., derives) the main current flowing through the main element Me based on the sense current flowing through the sense element Se and the area ratio.

[0016] The semiconductor device is constructed using a semiconductor substrate 10. The semiconductor substrate 10 is made of N - A P-type base layer 12 having a relatively low impurity concentration is disposed on the drift layer 11. In the following description, the surface of the semiconductor substrate 10 on the base layer 12 side will be referred to as one surface 10a of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 on the drift layer 11 side will be referred to as the other surface 10b.

[0017] A plurality of trenches 13 are formed in semiconductor substrate 10 so as to penetrate base layer 12 from one surface 10a side to reach drift layer 11, and base layer 12 is separated into a plurality of layers by these trenches 13. The plurality of trenches 13 are elongated in one direction of the planar direction of one surface 10a of semiconductor substrate 10 (i.e., the direction into the paper in FIGS. 2 and 3), and are arranged so as to form stripes at equal intervals.

[0018] Here, in this embodiment, if the distance between the centers of adjacent trenches 13 in a direction intersecting the longitudinal direction is defined as cell pitch dm, ds, the cell pitch ds of the sense element Se is narrower than the cell pitch dm of the main element Me.

[0019] Each trench 13 is filled with a gate insulating film 14 formed to cover the wall surface of the trench 13 and a gate electrode 15 made of polysilicon or the like formed on the gate insulating film 14. This forms a trench gate structure. In this embodiment, the gate electrode 15 of the main element Me and the gate electrode 15 of the sense element Se are connected to a common gate pad 1c via gate wiring formed in the peripheral region Rp, although details are omitted. The gate electrode 15 of the main element Me and the gate electrode 15 of the sense element Se are connected to a common drive circuit via the common gate pad 1c. In this embodiment, the portion of the wall surface of the trench 13 that exposes the base layer 12 corresponds to the surface of the base layer 12 arranged between the emitter region 16 and the drift layer 11, which will be described later.

[0020] As shown in FIGS. 2 to 5, the surface layer of the base layer 12 is + Type emitter region 16 and P + The emitter region 16 has a higher impurity concentration than the drift layer 11, and the contact region 17 has a higher impurity concentration than the base layer 12. In this embodiment, the emitter region 16 and the contact region 17 are alternately formed along the longitudinal direction of the trench 13.

[0021] 4 and 5, an interlayer insulating film 18 and an upper electrode 19, which will be described later, are omitted. In this embodiment, the emitter region 16 and the contact region 17 have the same length along the longitudinal direction of the trench 13. That is, the ratio of the emitter region 16 to the contact region 17 exposed from the surface 10a of the semiconductor substrate 10 is 1:1. In this embodiment, the emitter region 16 corresponds to a first impurity region.

[0022] An interlayer insulating film 18 made of BPSG (abbreviation of borophosphosilicate glass) or the like is formed on the base layer 12 (i.e., one surface 10a of the semiconductor substrate 10). In the interlayer insulating film 18, contact holes 18a that expose the emitter region 16 and the contact region 17 are formed.

[0023] An upper electrode 19 is formed on the interlayer insulating film 18. The upper electrode 19 is electrically connected to the emitter region 16 and the contact region 17 through a contact hole 18a. In this embodiment, the upper electrode 19 corresponds to a first electrode.

[0024] An N-type field stop layer (hereinafter simply referred to as an FS layer) 20 is formed on the side of the drift layer 11 opposite to the base layer 12 side (i.e., on the other surface 10b side of the semiconductor substrate 10). This FS layer 20 is not necessarily required, but it is provided to improve the breakdown voltage and steady-state loss performance by preventing the depletion layer from expanding, and to control the amount of holes injected from the other surface 10b side of the semiconductor substrate 10.

[0025] A p-type collector layer 21 is formed on the opposite side of the FS layer 20 from the drift layer 11. A lower electrode 22 is formed on the collector layer 21 (i.e., on the other surface 10b of the semiconductor substrate 10). In this embodiment, the collector layer 21 corresponds to a second impurity region, and the lower electrode 22 corresponds to a second electrode.

[0026] The above is the configuration of the semiconductor device in this embodiment. - Type, N + The first conductivity type corresponds to P type, P + In such a semiconductor device, the semiconductor substrate 10 includes the collector layer 21, the FS layer 20, the drift layer 11, the base layer 12, the emitter region 16, the contact region 17, and the like, as described above.

[0027] Next, the operation and effects of such a semiconductor device will be described.

[0028] In such a semiconductor device, when a voltage lower than that of lower electrode 22 is applied to upper electrode 19 and a voltage equal to or greater than the threshold voltage of the insulated gate structure is applied to gate electrode 15, an N-type inversion layer (i.e., a channel) is formed in the portion of base layer 12 that contacts trench 13. Then, electrons are supplied from emitter region 16 to drift layer 11 through the inversion layer, and holes are supplied from collector layer 21 to drift layer 11, and the resistance value of drift layer 11 is reduced by conductivity modulation, turning on the device.

[0029] The main current of the main element Me in such a semiconductor device is derived using a circuit configuration as shown in Fig. 6. Specifically, in this circuit configuration, a drive circuit 32 as an external circuit is connected to the gate pad 1c via an adjustment resistor 31. An external detection resistor R is connected between the sense emitter pad 1b connected to the upper electrode 19 of the sense element Se and the Kelvin emitter pad 1a. Resistors 33 and 34 in Fig. 6 represent parasitic resistances of the gate wiring, etc.

[0030] The main current flowing through the main element Me is detected as follows. That is, in the semiconductor device, the current flowing through the detection resistor R and the sense current flowing through the sense element Se are equal, so the sense current flowing through the sense element Se is detected based on the detection voltage Vse, which is the voltage across the detection resistor R. Furthermore, the main element Me and the sense element Se are formed with a predetermined area ratio, and the main current flowing through the main element Me and the sense current flowing through the sense element Se are proportional to the area ratio. Therefore, the main current flowing through the main element Me is derived based on the sense current (i.e., the detection voltage Vse) and the area ratio.

[0031] Furthermore, in such a semiconductor device, the normal operation and transient state of the semiconductor device are determined based on the detection voltage Vse. Specifically, the semiconductor device is determined to be operating normally if the detection voltage Vse is less than a predetermined normal threshold when a current in normal operation is flowing. Furthermore, the semiconductor device is determined to be in a short-circuit state if the detection voltage Vse is equal to or greater than a predetermined transient threshold when a current in transient operation is flowing. Therefore, as shown in FIG. 7, both the normal operation and transient operation can be determined appropriately when the detection voltage Vse is within validity region A. In this case, it is preferable to increase the portion of the detection voltage Vse that falls within validity region A to prevent erroneous determinations. The detection voltage Vse increases as the resistance value of the detection resistor R increases.

[0032] When the detection resistor R is disposed as described above, the gate-emitter voltage Vge of the sense element Se decreases by the detection voltage Vse. Specifically, as shown in FIG. 8, the detection voltage Vse of the sense element Se increases as the resistance value of the detection resistor R increases, and therefore the voltage Vge decreases. In other words, the sense saturation current density of the sense element Se decreases.

[0033] For this reason, in this embodiment, when the detection resistor R is not provided, the sense saturation current density of the sense element Se is set to be larger than the main saturation current density of the main element Me. Specifically, as shown in FIG. 9 , the saturation current density increases as the cell pitches dm and ds become smaller because current flows more easily. For this reason, in this embodiment, the cell pitch ds of the sense element Se is set narrower than the cell pitch dm of the main element Me. As a result, when the detection resistor R is not provided, the sense saturation current density of the sense element Se is larger than the main saturation current density of the main element Me. Therefore, as shown in FIG. 10 , the detection voltage Vse included in the range of the validity region A can be increased in the steady state and transient state. Note that the cell pitches in FIGS. 9 and 10 are shown as the reference cell pitch, with the cell pitch that is 2 / 3 times the reference cell pitch being referred to as the 2 / 3-times spacing and the cell pitch that is 1 / 2 times the reference cell pitch being referred to as the 1 / 2-times spacing.

[0034] However, as shown in Figures 11 and 12, when a detection resistor R is connected to the sense element Se to actually detect the detection voltage Vse, the sense saturation current density of the sense element Se may become higher than the main saturation current density of the main element Me, depending on the resistance value of the detection resistor R. If the main current is derived in a state in which the sense saturation current density of the sense element Se is higher than the main saturation current density of the main element Me, there is a high possibility of an erroneous determination being made that the main element Me is in a short-circuit state when it is not actually in a short-circuit state. Note that in Figures 11 and 12, the saturation current density of the main region Rm is set to 100 A / mm 29 and 10, the cell pitch in Fig. 11 and Fig. 12 is shown as follows: the reference interval is the reference cell pitch, the cell pitch that is 2 / 3 times the cell pitch of this reference interval is shown as 2 / 3 interval, and the cell pitch that is 1 / 2 times the cell pitch of this reference interval is shown as 1 / 2 interval.

[0035] For this reason, in this embodiment, when the detection resistor R is connected to the sense element Se, the sense saturation current density of the sense element Se is set to be lower than the main saturation current density of the main element Me.

[0036] Specifically, first, as shown in Fig. 13, the saturation current density increases as the gate-emitter voltage Vge increases. Then, because the detection resistor R is connected, the voltage Vge that serves as the operating voltage of the sense element Se is lower by the detection voltage Vse than the voltage Vge that serves as the operating voltage of the main element Me.

[0037] Furthermore, assuming that the sense element Se and the main element Me have the same configuration, if the reciprocal of the channel resistance is a, the gate-emitter voltage is Vge, the threshold voltage is Vth, the main saturation current density is Im, and the sense saturation current density is Is, the main saturation current density Im and the sense saturation current density Is can be expressed as follows:

[0038] (Equation 1) Im = a(Vge - Vth) 2 (Equation 2) Is = a(Vge - Vth - Vse) 2 If the ratio of the main saturation current density Im to the sense saturation current density Is is defined as the current density ratio Im / Is, the current density ratio Im / Is is in relation to the detection voltage Vse as shown in FIG. 14 and is expressed by the following equation 3.

[0039] (Equation 3) Im / Is = 0.0829 × (Vse) 2 +0.19×(Vse)+1.0055 Therefore, even if the sense saturation current density Is is increased, if the semiconductor device is configured so that the current density ratio Im / Is satisfies the following equation, it is possible to prevent the sense saturation current density Is from becoming larger than the main saturation current density Im when the detection resistor R is connected.

[0040] (Equation 4) Im / Is≦0.0829×(Vse) 2 +0.19×(Vse)+1.0055 As described above, in this embodiment, the sense element Se is formed so that the sense saturation current density Is is larger than the main saturation current density Im when the detection resistor R is not connected, and so that when the detection resistor R is connected, the formula 4 is satisfied.

[0041] 14 shows the results when the gate-emitter voltage Vge is 15 V and the threshold voltage Vth is 6.5 V, but similar results are obtained even when various conditions are changed. Furthermore, when the cell pitch ds of the sense element Se is shortened as in this embodiment, the channel resistance decreases, and therefore the reciprocal of the channel resistance, a, increases, thereby increasing the sense saturation current density Is.

[0042] According to the present embodiment described above, in the semiconductor device, the sense saturation current density Is is set higher than the main saturation current density Im when the detection resistor R is not connected. This makes it possible to increase the sense saturation current density Is without making the main saturation current density Im too high, thereby widening the range in which normal judgment and transient judgment are possible and suppressing erroneous judgments while suppressing a decrease in the short-circuit withstand capability of the main element Me.

[0043] Furthermore, in the semiconductor device, the sense saturation current density Is is set lower than the main saturation current density Im when the detection resistor R is connected, which makes it possible to prevent erroneous determinations under actual usage conditions.

[0044] (1) In this embodiment, the semiconductor device is configured to satisfy the above-mentioned formula 4. This makes it possible to easily prevent the sense saturation current density Is from becoming higher than the main saturation current density Im.

[0045] (2) In this embodiment, the semiconductor device has a cell pitch ds of the sense element Se narrower than the cell pitch dm of the main element Me. This makes it easy to increase the sense saturation current density of the sense element Se.

[0046] (3) In this embodiment, the sense region Rs is formed at a position where the distance from the gate pad 1c is shorter than that from the main region Rm. Therefore, the resistance 33 caused by the gate wiring connecting the sense element Se and the gate pad 1c is smaller than the resistance 34 caused by the gate wiring connecting the main element Me and the gate pad 1c. Therefore, the gate current of the sense element Se is promoted, making it easier to boost the gate electrode 15 of the sense element Se, and improving responsiveness.

[0047] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the main element Me is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0048] 15, in the semiconductor device of this embodiment, dummy electrodes 40 that are not connected to the gate electrodes 15 or the gate pad 1c are arranged in the trenches 13 of the main region Rm. That is, the main element Me has a thinned-out structure. In this embodiment, the gate electrodes 15 and the dummy electrodes 40 are arranged alternately in the trenches 13 of the main region Rm along the arrangement direction of the trenches 13 that intersects with the longitudinal direction of the trenches 13.

[0049] Similarly to the first embodiment, the sense element Se has a gate electrode 15 disposed in each trench 13. That is, in the semiconductor device of this embodiment, the proportion of the gate structure functioning as an IGBT element is higher in the sense element Se than in the main element Me. In other words, in the semiconductor device of this embodiment, the proportion of the gate electrodes 15 connected to the gate pad 1c among all the gate electrodes 15 of the sense element Se is higher than the proportion of the gate electrodes 15 connected to the gate pad 1c among all the gate electrodes 15 of the main element Me. This reduces the channel resistance, thereby increasing the sense saturation current density Is of the sense element Se. However, the sense saturation current density Is of the sense element Se is adjusted to be lower than the main saturation current density Im of the main element Me when the detection resistor R is connected.

[0050] According to the present embodiment described above, in the semiconductor device, the sense saturation current density Is is higher than the main saturation current density Im when the detection resistor R is not connected, and the sense saturation current density Is is lower than the main saturation current density Im when the detection resistor R is connected. Therefore, the same effects as those of the first embodiment can be obtained.

[0051] (1) In this embodiment, the proportion of the gate structure functioning as an IGBT element is configured to be higher in the sense element Se than in the main element Me. This makes it easy to increase the sense saturation current density Is of the sense element Se. Note that with this configuration, the sense saturation current density Is of the sense element Se can be increased by increasing the proportion of the gate structure. Therefore, the cell pitch dm of the main element Me and the cell pitch ds of the sense element Se may be the same.

[0052] (Third embodiment) A third embodiment will be described. In this embodiment, the configuration of the sense element Se is changed from that of the first embodiment. As the rest is the same as that of the first embodiment, a description thereof will be omitted here.

[0053] 16, in the semiconductor device of this embodiment, the emitter region 16 of the sense element Se is longer than the emitter region 16 of the main element Me in terms of the length of the emitter region 16 along the longitudinal direction of the trench 13. In other words, the ratio of the emitter region 16 to the contact region 17 exposed from one surface 10a of the semiconductor substrate 10 is higher in the sense element Se. Note that, in this embodiment, the length of the contact region 17 along the longitudinal direction of the trench 13 is the same for the main element Me and the sense element Se.

[0054] In such a semiconductor device, the ratio of the emitter region 16 connected to the upper electrode 19 to the total ratio of the emitter region 16 and the contact region 17 connected to the upper electrode 19 is such that the ratio of the emitter region 16 of the sense element Se connected to the upper electrode 19 is greater than the ratio of the emitter region 16 of the main element Me connected to the upper electrode 19. This reduces the channel resistance, thereby increasing the sense saturation current density Is of the sense element Se. However, the sense saturation current density Is of the sense element Se is adjusted to be lower than the main saturation current density Im of the main element Me when the detection resistor R is connected. The contact region 17 has the same conductivity type as the base layer 12, and the base layer 12 is electrically connected to the upper electrode 19 via the contact region 17. Therefore, connecting the contact region 17 to the upper electrode 19 can also be said to connect the base layer 12 to the upper electrode 19.

[0055] According to the present embodiment described above, in the semiconductor device, the sense saturation current density Is is higher than the main saturation current density Im when the detection resistor R is not connected, and the sense saturation current density Is is lower than the main saturation current density Im when the detection resistor R is connected. Therefore, the same effects as those of the first embodiment can be obtained.

[0056] (1) In this embodiment, with respect to the overall ratio of the emitter regions 16 and contact regions 17 connected to the upper electrode 19, the ratio of the emitter regions 16 of the sense element Se connected to the upper electrode 19 is set to be larger than the ratio of the emitter regions 16 of the main element Me connected to the upper electrode 19. This makes it easy to increase the sense saturation current density Is of the sense element Se. Note that in this embodiment, the sense saturation current density Is of the sense element Se can be increased by increasing the length of the emitter region 16 in the sense element Se. Therefore, the cell pitch dm of the main region Rm and the cell pitch ds of the sense region Rs may be the same.

[0057] (Modification of the third embodiment) In the third embodiment, an example has been described in which the contact region 17 of the sense element Se and the contact region 17 of the main element Me have the same length. However, the contact region 17 of the sense element Se may be made shorter than the contact region 17 of the main element Me, so that the emitter region 16 of the sense element Se has a longer length than the emitter region 16 of the main element Me.

[0058] (Fourth embodiment) A fourth embodiment will be described. In this embodiment, the configuration of the sense element Se is changed from that of the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0059] In the semiconductor device of this embodiment, as shown in FIG. 17, the base layer 12 of the sense element Se has a P - In such a semiconductor device, the threshold voltage Vth of the sense element Se is lower than the threshold voltage Vth of the main element Me. This allows the sense saturation current density Is of the sense element Se to be increased. However, the sense saturation current density Is of the sense element Se is adjusted to be lower than the main saturation current density Im of the main element Me when the detection resistor R is connected.

[0060] According to the present embodiment described above, in the semiconductor device, the sense saturation current density Is is higher than the main saturation current density Im when the detection resistor R is not connected, and the sense saturation current density Is is lower than the main saturation current density Im when the detection resistor R is connected. Therefore, the same effects as those of the first embodiment can be obtained.

[0061] (1) In this embodiment, the impurity concentration of the base layer 12 of the sense element Se is set lower than the impurity concentration of the base layer 12 of the main element Me. Therefore, the sense saturation current density Is of the sense element Se can be easily increased. In this configuration, the sense saturation current density Is of the sense element Se can be increased by lowering the impurity concentration of the base layer 12 of the sense element Se. Therefore, the cell pitch dm of the main element Me and the cell pitch ds of the sense element Se may be the same.

[0062] (Fifth embodiment) A fifth embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the sense element Se is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0063] In the semiconductor device of this embodiment, as shown in FIG. 18, the gate insulating film 14 of the sense element Se is thinner than the gate insulating film 14 of the main element Me. In such a semiconductor device, an inversion layer is more easily formed in the sense element Se than in the main element Me, resulting in a smaller channel resistance. This allows the sense saturation current density Is of the sense element Se to be increased. However, the sense saturation current density Is of the sense element Se is adjusted to be lower than the main saturation current density Im of the main element Me when the detection resistor R is connected.

[0064] According to the present embodiment described above, in the semiconductor device, the sense saturation current density Is is higher than the main saturation current density Im when the detection resistor R is not connected, and the sense saturation current density Is is lower than the main saturation current density Im when the detection resistor R is connected. Therefore, the same effects as those of the first embodiment can be obtained.

[0065] (1) In this embodiment, the gate insulating film 14 of the sense element Se is thinner than the gate insulating film 14 of the main element Me. Therefore, the sense saturation current density Is of the sense element Se can be easily increased. In this configuration, the sense saturation current density Is of the sense element Se can be increased by thinning the gate insulating film 14 of the sense element Se. Therefore, the cell pitch dm of the main element Me and the cell pitch ds of the sense element Se may be the same.

[0066] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0067] For example, in each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. + Alternatively, a MOSFET having a drain layer of the same type may be formed. Furthermore, in each of the above embodiments, a semiconductor element having a planar gate structure may be formed instead of a trench gate structure.

[0068] The above embodiments may also be combined. For example, the second embodiment may be combined with the third to fifth embodiments, so that the proportion of the gate structure functioning as an IGBT element is higher in the sense element Se than in the main element Me. The third embodiment may be combined with the fourth or fifth embodiment, so that the proportion of the emitter region 16 of the sense element Se that is connected to the upper electrode 19 is higher than the proportion of the emitter region 16 of the main element Me that is connected to the upper electrode 19. The fourth embodiment may be combined with the fifth embodiment, so that the impurity concentration of the base layer 12 of the sense element Se is lower than the impurity concentration of the base layer 12 of the main element Me. Combinations of the above embodiments may also be combined. [Explanation of symbols]

[0069] 11 Drift layer 12 Base Layer 14 Gate insulating film 15 gate electrode 16 Emitter region (first impurity region) 19 Upper electrode (1st electrode) 21 Collector layer (second impurity region) 22 Lower electrode (second electrode) Me main element Se sensing element Rm Main Area Rs sense region

Claims

1. A semiconductor device having a main region (Rm) in which a main element (Me) is formed and a sense region (Rs) in which a sense element (Se) is formed, a detection resistor (R) is connected to the sense element, and a main current flowing through the main element is detected based on a voltage generated in the detection resistor, The main element and the sense element are A drift layer (11) of a first conductivity type; a base layer (12) of a second conductivity type formed on the drift layer; a first impurity region (16) of a first conductivity type formed in a surface layer portion of the base layer and having a higher impurity concentration than the drift layer; a gate insulating film (14) disposed on a surface of the base layer sandwiched between the first impurity region and the drift layer; A gate electrode (15) disposed on the gate insulating film; a second impurity region (21) formed on the opposite side of the drift layer from the base layer; a first electrode (19) electrically connected to the first impurity region and the base layer; a second electrode (22) electrically connected to the second impurity region; The gate electrodes of the sense element and the main element are connected to a common pad (1c) that is connected to an external circuit, The semiconductor device is configured such that the sense element has a sense saturation current density higher than the main saturation current density of the main element when the detection resistor is not connected, and the sense saturation current density lower than the main saturation current density of the main element when the detection resistor is connected.

2. When the sense saturation current density of the sense element in a state in which the detection resistor is connected is Is, the main saturation current density of the main element is Im, and the voltage across the detection resistor is Vse, Im / Is≦0.0829×(Vse) ２ 2. The semiconductor device according to claim 1, which satisfies +0.191×Vse+1.

055.

3. the sense element and the main element each have a plurality of the gate electrodes; 3. The semiconductor device according to claim 1, wherein the distance (ds) between the centers of adjacent gate electrodes of the sense element is narrower than the distance (dm) between the centers of adjacent gate electrodes of the main element.

4. the sense element and the main element each have a plurality of the gate electrodes; 4. A semiconductor device according to claim 1, wherein the proportion of gate electrodes connected to the common pad among all gate electrodes formed in the sense element is higher than the proportion of gate electrodes connected to the common pad among all gate electrodes formed in the main element.

5. 5. A semiconductor device according to claim 1, wherein the ratio of the first impurity region of the sense element connected to the first electrode to the total ratio of the first impurity region and the base layer connected to the first electrode is higher than the ratio of the first impurity region of the main element connected to the first electrode.

6. 6. The semiconductor device according to claim 1, wherein the impurity concentration of the base layer of the sense element is lower than the impurity concentration of the base layer of the main element.

7. 7. The semiconductor device according to claim 1, wherein the thickness of the gate insulating film of the sense element is thinner than the thickness of the gate insulating film of the main element.

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